samsung_tty.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver core for Samsung SoC onboard UARTs.
   4 *
   5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6 *	http://armlinux.simtec.co.uk/
   7 */
   8
   9/* Note on 2410 error handling
  10 *
  11 * The s3c2410 manual has a love/hate affair with the contents of the
  12 * UERSTAT register in the UART blocks, and keeps marking some of the
  13 * error bits as reserved. Having checked with the s3c2410x01,
  14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15 * feature from the latter versions of the manual.
  16 *
  17 * If it becomes aparrent that latter versions of the 2410 remove these
  18 * bits, then action will have to be taken to differentiate the versions
  19 * and change the policy on BREAK
  20 *
  21 * BJD, 04-Nov-2004
  22 */
  23
  24#include <linux/console.h>
  25#include <linux/clk.h>
  26#include <linux/cpufreq.h>
  27#include <linux/delay.h>
  28#include <linux/dma-mapping.h>
  29#include <linux/dmaengine.h>
  30#include <linux/init.h>
  31#include <linux/io.h>
  32#include <linux/ioport.h>
  33#include <linux/math.h>
  34#include <linux/module.h>
  35#include <linux/of.h>
  36#include <linux/platform_device.h>
  37#include <linux/serial.h>
  38#include <linux/serial_core.h>
  39#include <linux/serial_s3c.h>
  40#include <linux/slab.h>
  41#include <linux/sysrq.h>
  42#include <linux/tty.h>
  43#include <linux/tty_flip.h>
  44#include <linux/types.h>
  45
  46#include <asm/irq.h>
  47
  48/* UART name and device definitions */
  49
  50#define S3C24XX_SERIAL_NAME	"ttySAC"
  51#define S3C24XX_SERIAL_MAJOR	204
  52#define S3C24XX_SERIAL_MINOR	64
  53
  54#ifdef CONFIG_ARM64
  55#define UART_NR			18
  56#else
  57#define UART_NR			CONFIG_SERIAL_SAMSUNG_UARTS
  58#endif
  59
  60#define S3C24XX_TX_PIO			1
  61#define S3C24XX_TX_DMA			2
  62#define S3C24XX_RX_PIO			1
  63#define S3C24XX_RX_DMA			2
  64
  65/* flag to ignore all characters coming in */
  66#define RXSTAT_DUMMY_READ (0x10000000)
  67
  68enum s3c24xx_port_type {
  69	TYPE_S3C6400,
  70	TYPE_APPLE_S5L,
  71};
  72
  73struct s3c24xx_uart_info {
  74	const char		*name;
  75	enum s3c24xx_port_type	type;
  76	unsigned int		port_type;
  77	unsigned int		fifosize;
  78	u32			rx_fifomask;
  79	u32			rx_fifoshift;
  80	u32			rx_fifofull;
  81	u32			tx_fifomask;
  82	u32			tx_fifoshift;
  83	u32			tx_fifofull;
  84	u32			clksel_mask;
  85	u32			clksel_shift;
  86	u32			ucon_mask;
  87	u8			def_clk_sel;
  88	u8			num_clks;
  89	u8			iotype;
  90
  91	/* uart port features */
  92	bool			has_divslot;
  93};
  94
  95struct s3c24xx_serial_drv_data {
  96	const struct s3c24xx_uart_info	info;
  97	const struct s3c2410_uartcfg	def_cfg;
  98	const unsigned int		fifosize[UART_NR];
  99};
 100
 101struct s3c24xx_uart_dma {
 102	unsigned int			rx_chan_id;
 103	unsigned int			tx_chan_id;
 104
 105	struct dma_slave_config		rx_conf;
 106	struct dma_slave_config		tx_conf;
 107
 108	struct dma_chan			*rx_chan;
 109	struct dma_chan			*tx_chan;
 110
 111	dma_addr_t			rx_addr;
 112	dma_addr_t			tx_addr;
 113
 114	dma_cookie_t			rx_cookie;
 115	dma_cookie_t			tx_cookie;
 116
 117	char				*rx_buf;
 118
 119	dma_addr_t			tx_transfer_addr;
 120
 121	size_t				rx_size;
 122	size_t				tx_size;
 123
 124	struct dma_async_tx_descriptor	*tx_desc;
 125	struct dma_async_tx_descriptor	*rx_desc;
 126
 127	int				tx_bytes_requested;
 128	int				rx_bytes_requested;
 129};
 130
 131struct s3c24xx_uart_port {
 132	unsigned char			rx_enabled;
 133	unsigned char			tx_enabled;
 134	unsigned int			pm_level;
 135	unsigned long			baudclk_rate;
 136	unsigned int			min_dma_size;
 137
 138	unsigned int			rx_irq;
 139	unsigned int			tx_irq;
 140
 141	unsigned int			tx_in_progress;
 142	unsigned int			tx_mode;
 143	unsigned int			rx_mode;
 144
 145	const struct s3c24xx_uart_info	*info;
 146	struct clk			*clk;
 147	struct clk			*baudclk;
 148	struct uart_port		port;
 149	const struct s3c24xx_serial_drv_data	*drv_data;
 150
 151	/* reference to platform data */
 152	const struct s3c2410_uartcfg	*cfg;
 153
 154	struct s3c24xx_uart_dma		*dma;
 155};
 156
 157static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 158
 159/* conversion functions */
 160
 161#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 162
 163/* register access controls */
 164
 165#define portaddr(port, reg) ((port)->membase + (reg))
 166#define portaddrl(port, reg) \
 167	((unsigned long *)(unsigned long)((port)->membase + (reg)))
 168
 169static u32 rd_reg(const struct uart_port *port, u32 reg)
 170{
 171	switch (port->iotype) {
 172	case UPIO_MEM:
 173		return readb_relaxed(portaddr(port, reg));
 174	case UPIO_MEM32:
 175		return readl_relaxed(portaddr(port, reg));
 176	default:
 177		return 0;
 178	}
 179	return 0;
 180}
 181
 182#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 183
 184static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
 185{
 186	switch (port->iotype) {
 187	case UPIO_MEM:
 188		writeb_relaxed(val, portaddr(port, reg));
 189		break;
 190	case UPIO_MEM32:
 191		writel_relaxed(val, portaddr(port, reg));
 192		break;
 193	default:
 194		break;
 195	}
 196}
 197
 198#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 199
 200/* Byte-order aware bit setting/clearing functions. */
 201
 202static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
 203				   u32 reg)
 204{
 205	unsigned long flags;
 206	u32 val;
 207
 208	local_irq_save(flags);
 209	val = rd_regl(port, reg);
 210	val |= (1 << idx);
 211	wr_regl(port, reg, val);
 212	local_irq_restore(flags);
 213}
 214
 215static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
 216				     u32 reg)
 217{
 218	unsigned long flags;
 219	u32 val;
 220
 221	local_irq_save(flags);
 222	val = rd_regl(port, reg);
 223	val &= ~(1 << idx);
 224	wr_regl(port, reg, val);
 225	local_irq_restore(flags);
 226}
 227
 228static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 229{
 230	return container_of(port, struct s3c24xx_uart_port, port);
 231}
 232
 233/* translate a port to the device name */
 234
 235static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
 236{
 237	return to_platform_device(port->dev)->name;
 238}
 239
 240static bool s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
 241{
 242	return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 243}
 244
 245static void s3c24xx_serial_rx_enable(struct uart_port *port)
 246{
 247	struct s3c24xx_uart_port *ourport = to_ourport(port);
 248	unsigned long flags;
 249	int count = 10000;
 250	u32 ucon, ufcon;
 251
 252	uart_port_lock_irqsave(port, &flags);
 253
 254	while (--count && !s3c24xx_serial_txempty_nofifo(port))
 255		udelay(100);
 256
 257	ufcon = rd_regl(port, S3C2410_UFCON);
 258	ufcon |= S3C2410_UFCON_RESETRX;
 259	wr_regl(port, S3C2410_UFCON, ufcon);
 260
 261	ucon = rd_regl(port, S3C2410_UCON);
 262	ucon |= S3C2410_UCON_RXIRQMODE;
 263	wr_regl(port, S3C2410_UCON, ucon);
 264
 265	ourport->rx_enabled = 1;
 266	uart_port_unlock_irqrestore(port, flags);
 267}
 268
 269static void s3c24xx_serial_rx_disable(struct uart_port *port)
 270{
 271	struct s3c24xx_uart_port *ourport = to_ourport(port);
 272	unsigned long flags;
 273	u32 ucon;
 274
 275	uart_port_lock_irqsave(port, &flags);
 276
 277	ucon = rd_regl(port, S3C2410_UCON);
 278	ucon &= ~S3C2410_UCON_RXIRQMODE;
 279	wr_regl(port, S3C2410_UCON, ucon);
 280
 281	ourport->rx_enabled = 0;
 282	uart_port_unlock_irqrestore(port, flags);
 283}
 284
 285static void s3c24xx_serial_stop_tx(struct uart_port *port)
 286{
 287	struct s3c24xx_uart_port *ourport = to_ourport(port);
 288	struct s3c24xx_uart_dma *dma = ourport->dma;
 289	struct dma_tx_state state;
 290	int count;
 291
 292	if (!ourport->tx_enabled)
 293		return;
 294
 295	switch (ourport->info->type) {
 296	case TYPE_S3C6400:
 297		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 298		break;
 299	case TYPE_APPLE_S5L:
 300		s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 301		break;
 302	default:
 303		disable_irq_nosync(ourport->tx_irq);
 304		break;
 305	}
 306
 307	if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 308		dmaengine_pause(dma->tx_chan);
 309		dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 310		dmaengine_terminate_all(dma->tx_chan);
 311		dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 312					dma->tx_transfer_addr, dma->tx_size,
 313					DMA_TO_DEVICE);
 314		async_tx_ack(dma->tx_desc);
 315		count = dma->tx_bytes_requested - state.residue;
 316		uart_xmit_advance(port, count);
 317	}
 318
 319	ourport->tx_enabled = 0;
 320	ourport->tx_in_progress = 0;
 321
 322	if (port->flags & UPF_CONS_FLOW)
 323		s3c24xx_serial_rx_enable(port);
 324
 325	ourport->tx_mode = 0;
 326}
 327
 328static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 329
 330static void s3c24xx_serial_tx_dma_complete(void *args)
 331{
 332	struct s3c24xx_uart_port *ourport = args;
 333	struct uart_port *port = &ourport->port;
 334	struct tty_port *tport = &port->state->port;
 335	struct s3c24xx_uart_dma *dma = ourport->dma;
 336	struct dma_tx_state state;
 337	unsigned long flags;
 338	int count;
 339
 340	dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 341	count = dma->tx_bytes_requested - state.residue;
 342	async_tx_ack(dma->tx_desc);
 343
 344	dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 345				dma->tx_transfer_addr, dma->tx_size,
 346				DMA_TO_DEVICE);
 347
 348	uart_port_lock_irqsave(port, &flags);
 349
 350	uart_xmit_advance(port, count);
 351	ourport->tx_in_progress = 0;
 352
 353	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
 354		uart_write_wakeup(port);
 355
 356	s3c24xx_serial_start_next_tx(ourport);
 357	uart_port_unlock_irqrestore(port, flags);
 358}
 359
 360static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 361{
 362	const struct uart_port *port = &ourport->port;
 363	u32 ucon;
 364
 365	/* Mask Tx interrupt */
 366	switch (ourport->info->type) {
 367	case TYPE_S3C6400:
 368		s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 369		break;
 370	case TYPE_APPLE_S5L:
 371		WARN_ON(1); // No DMA
 372		break;
 373	default:
 374		disable_irq_nosync(ourport->tx_irq);
 375		break;
 376	}
 377
 378	/* Enable tx dma mode */
 379	ucon = rd_regl(port, S3C2410_UCON);
 380	ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 381	ucon |= S3C64XX_UCON_TXBURST_1;
 382	ucon |= S3C64XX_UCON_TXMODE_DMA;
 383	wr_regl(port,  S3C2410_UCON, ucon);
 384
 385	ourport->tx_mode = S3C24XX_TX_DMA;
 386}
 387
 388static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 389{
 390	const struct uart_port *port = &ourport->port;
 391	u32 ucon, ufcon;
 392
 393	/* Set ufcon txtrig */
 394	ourport->tx_in_progress = S3C24XX_TX_PIO;
 395	ufcon = rd_regl(port, S3C2410_UFCON);
 396	wr_regl(port,  S3C2410_UFCON, ufcon);
 397
 398	/* Enable tx pio mode */
 399	ucon = rd_regl(port, S3C2410_UCON);
 400	ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 401	ucon |= S3C64XX_UCON_TXMODE_CPU;
 402	wr_regl(port,  S3C2410_UCON, ucon);
 403
 404	/* Unmask Tx interrupt */
 405	switch (ourport->info->type) {
 406	case TYPE_S3C6400:
 407		s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 408				  S3C64XX_UINTM);
 409		break;
 410	case TYPE_APPLE_S5L:
 411		ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 412		wr_regl(port, S3C2410_UCON, ucon);
 413		break;
 414	default:
 415		enable_irq(ourport->tx_irq);
 416		break;
 417	}
 418
 419	ourport->tx_mode = S3C24XX_TX_PIO;
 420
 421	/*
 422	 * The Apple version only has edge triggered TX IRQs, so we need
 423	 * to kick off the process by sending some characters here.
 424	 */
 425	if (ourport->info->type == TYPE_APPLE_S5L)
 426		s3c24xx_serial_tx_chars(ourport);
 427}
 428
 429static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 430{
 431	if (ourport->tx_mode != S3C24XX_TX_PIO)
 432		enable_tx_pio(ourport);
 433}
 434
 435static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 436				      unsigned int count, unsigned int tail)
 437{
 438	struct s3c24xx_uart_dma *dma = ourport->dma;
 439
 440	if (ourport->tx_mode != S3C24XX_TX_DMA)
 441		enable_tx_dma(ourport);
 442
 443	dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 444	dma->tx_transfer_addr = dma->tx_addr + tail;
 445
 446	dma_sync_single_for_device(dma->tx_chan->device->dev,
 447				   dma->tx_transfer_addr, dma->tx_size,
 448				   DMA_TO_DEVICE);
 449
 450	dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 451				dma->tx_transfer_addr, dma->tx_size,
 452				DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 453	if (!dma->tx_desc) {
 454		dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 455		return -EIO;
 456	}
 457
 458	dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 459	dma->tx_desc->callback_param = ourport;
 460	dma->tx_bytes_requested = dma->tx_size;
 461
 462	ourport->tx_in_progress = S3C24XX_TX_DMA;
 463	dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 464	dma_async_issue_pending(dma->tx_chan);
 465	return 0;
 466}
 467
 468static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 469{
 470	struct uart_port *port = &ourport->port;
 471	struct tty_port *tport = &port->state->port;
 472	unsigned int count, tail;
 473
 474	/* Get data size up to the end of buffer */
 475	count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE);
 476
 477	if (!count) {
 478		s3c24xx_serial_stop_tx(port);
 479		return;
 480	}
 481
 482	if (!ourport->dma || !ourport->dma->tx_chan ||
 483	    count < ourport->min_dma_size ||
 484	    tail & (dma_get_cache_alignment() - 1))
 485		s3c24xx_serial_start_tx_pio(ourport);
 486	else
 487		s3c24xx_serial_start_tx_dma(ourport, count, tail);
 488}
 489
 490static void s3c24xx_serial_start_tx(struct uart_port *port)
 491{
 492	struct s3c24xx_uart_port *ourport = to_ourport(port);
 493	struct tty_port *tport = &port->state->port;
 494
 495	if (!ourport->tx_enabled) {
 496		if (port->flags & UPF_CONS_FLOW)
 497			s3c24xx_serial_rx_disable(port);
 498
 499		ourport->tx_enabled = 1;
 500		if (!ourport->dma || !ourport->dma->tx_chan)
 501			s3c24xx_serial_start_tx_pio(ourport);
 502	}
 503
 504	if (ourport->dma && ourport->dma->tx_chan) {
 505		if (!kfifo_is_empty(&tport->xmit_fifo) &&
 506				!ourport->tx_in_progress)
 507			s3c24xx_serial_start_next_tx(ourport);
 508	}
 509}
 510
 511static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 512		struct tty_port *tty, int count)
 513{
 514	struct s3c24xx_uart_dma *dma = ourport->dma;
 515	int copied;
 516
 517	if (!count)
 518		return;
 519
 520	dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
 521				dma->rx_size, DMA_FROM_DEVICE);
 522
 523	ourport->port.icount.rx += count;
 524	if (!tty) {
 525		dev_err(ourport->port.dev, "No tty port\n");
 526		return;
 527	}
 528	copied = tty_insert_flip_string(tty,
 529			((unsigned char *)(ourport->dma->rx_buf)), count);
 530	if (copied != count) {
 531		WARN_ON(1);
 532		dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 533	}
 534}
 535
 536static void s3c24xx_serial_stop_rx(struct uart_port *port)
 537{
 538	struct s3c24xx_uart_port *ourport = to_ourport(port);
 539	struct s3c24xx_uart_dma *dma = ourport->dma;
 540	struct tty_port *t = &port->state->port;
 541	struct dma_tx_state state;
 542	enum dma_status dma_status;
 543	unsigned int received;
 544
 545	if (ourport->rx_enabled) {
 546		dev_dbg(port->dev, "stopping rx\n");
 547		switch (ourport->info->type) {
 548		case TYPE_S3C6400:
 549			s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 550					S3C64XX_UINTM);
 551			break;
 552		case TYPE_APPLE_S5L:
 553			s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 554			s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 555			s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
 556			break;
 557		default:
 558			disable_irq_nosync(ourport->rx_irq);
 559			break;
 560		}
 561		ourport->rx_enabled = 0;
 562	}
 563	if (dma && dma->rx_chan) {
 564		dmaengine_pause(dma->tx_chan);
 565		dma_status = dmaengine_tx_status(dma->rx_chan,
 566				dma->rx_cookie, &state);
 567		if (dma_status == DMA_IN_PROGRESS ||
 568			dma_status == DMA_PAUSED) {
 569			received = dma->rx_bytes_requested - state.residue;
 570			dmaengine_terminate_all(dma->rx_chan);
 571			s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 572		}
 573	}
 574}
 575
 576static inline const struct s3c24xx_uart_info
 577	*s3c24xx_port_to_info(struct uart_port *port)
 578{
 579	return to_ourport(port)->info;
 580}
 581
 582static inline const struct s3c2410_uartcfg
 583	*s3c24xx_port_to_cfg(const struct uart_port *port)
 584{
 585	const struct s3c24xx_uart_port *ourport;
 586
 587	if (port->dev == NULL)
 588		return NULL;
 589
 590	ourport = container_of(port, struct s3c24xx_uart_port, port);
 591	return ourport->cfg;
 592}
 593
 594static unsigned int
 595s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport, u32 ufstat)
 596{
 597	const struct s3c24xx_uart_info *info = ourport->info;
 598
 599	if (ufstat & info->rx_fifofull)
 600		return ourport->port.fifosize;
 601
 602	return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 603}
 604
 605static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 606static void s3c24xx_serial_rx_dma_complete(void *args)
 607{
 608	struct s3c24xx_uart_port *ourport = args;
 609	struct uart_port *port = &ourport->port;
 610
 611	struct s3c24xx_uart_dma *dma = ourport->dma;
 612	struct tty_port *t = &port->state->port;
 613	struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 614
 615	struct dma_tx_state state;
 616	unsigned long flags;
 617	int received;
 618
 619	dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 620	received  = dma->rx_bytes_requested - state.residue;
 621	async_tx_ack(dma->rx_desc);
 622
 623	uart_port_lock_irqsave(port, &flags);
 624
 625	if (received)
 626		s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 627
 628	if (tty) {
 629		tty_flip_buffer_push(t);
 630		tty_kref_put(tty);
 631	}
 632
 633	s3c64xx_start_rx_dma(ourport);
 634
 635	uart_port_unlock_irqrestore(port, flags);
 636}
 637
 638static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 639{
 640	struct s3c24xx_uart_dma *dma = ourport->dma;
 641
 642	dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
 643				   dma->rx_size, DMA_FROM_DEVICE);
 644
 645	dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 646				dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 647				DMA_PREP_INTERRUPT);
 648	if (!dma->rx_desc) {
 649		dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 650		return;
 651	}
 652
 653	dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 654	dma->rx_desc->callback_param = ourport;
 655	dma->rx_bytes_requested = dma->rx_size;
 656
 657	dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 658	dma_async_issue_pending(dma->rx_chan);
 659}
 660
 661/* ? - where has parity gone?? */
 662#define S3C2410_UERSTAT_PARITY (0x1000)
 663
 664static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 665{
 666	struct uart_port *port = &ourport->port;
 667	u32 ucon;
 668
 669	/* set Rx mode to DMA mode */
 670	ucon = rd_regl(port, S3C2410_UCON);
 671	ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 672			S3C64XX_UCON_TIMEOUT_MASK |
 673			S3C64XX_UCON_EMPTYINT_EN |
 674			S3C64XX_UCON_DMASUS_EN |
 675			S3C64XX_UCON_TIMEOUT_EN |
 676			S3C64XX_UCON_RXMODE_MASK);
 677	ucon |= S3C64XX_UCON_RXBURST_1 |
 678			0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 679			S3C64XX_UCON_EMPTYINT_EN |
 680			S3C64XX_UCON_TIMEOUT_EN |
 681			S3C64XX_UCON_RXMODE_DMA;
 682	wr_regl(port, S3C2410_UCON, ucon);
 683
 684	ourport->rx_mode = S3C24XX_RX_DMA;
 685}
 686
 687static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 688{
 689	struct uart_port *port = &ourport->port;
 690	u32 ucon;
 691
 692	/* set Rx mode to DMA mode */
 693	ucon = rd_regl(port, S3C2410_UCON);
 694	ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 695	ucon |= S3C64XX_UCON_RXMODE_CPU;
 696
 697	/* Apple types use these bits for IRQ masks */
 698	if (ourport->info->type != TYPE_APPLE_S5L) {
 699		ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 700				S3C64XX_UCON_EMPTYINT_EN |
 701				S3C64XX_UCON_DMASUS_EN |
 702				S3C64XX_UCON_TIMEOUT_EN);
 703		ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 704				S3C64XX_UCON_TIMEOUT_EN;
 705	}
 706	wr_regl(port, S3C2410_UCON, ucon);
 707
 708	ourport->rx_mode = S3C24XX_RX_PIO;
 709}
 710
 711static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 712
 713static irqreturn_t s3c24xx_serial_rx_chars_dma(struct s3c24xx_uart_port *ourport)
 714{
 715	struct uart_port *port = &ourport->port;
 716	struct s3c24xx_uart_dma *dma = ourport->dma;
 717	struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 718	struct tty_port *t = &port->state->port;
 719	struct dma_tx_state state;
 720	unsigned int received;
 721	u32 utrstat;
 722
 723	utrstat = rd_regl(port, S3C2410_UTRSTAT);
 724	rd_regl(port, S3C2410_UFSTAT);
 725
 726	uart_port_lock(port);
 727
 728	if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 729		s3c64xx_start_rx_dma(ourport);
 730		if (ourport->rx_mode == S3C24XX_RX_PIO)
 731			enable_rx_dma(ourport);
 732		goto finish;
 733	}
 734
 735	if (ourport->rx_mode == S3C24XX_RX_DMA) {
 736		dmaengine_pause(dma->rx_chan);
 737		dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 738		dmaengine_terminate_all(dma->rx_chan);
 739		received = dma->rx_bytes_requested - state.residue;
 740		s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 741
 742		enable_rx_pio(ourport);
 743	}
 744
 745	s3c24xx_serial_rx_drain_fifo(ourport);
 746
 747	if (tty) {
 748		tty_flip_buffer_push(t);
 749		tty_kref_put(tty);
 750	}
 751
 752	wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 753
 754finish:
 755	uart_port_unlock(port);
 756
 757	return IRQ_HANDLED;
 758}
 759
 760static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 761{
 762	struct uart_port *port = &ourport->port;
 763	unsigned int max_count = port->fifosize;
 764	unsigned int fifocnt = 0;
 765	u32 ufcon, ufstat, uerstat;
 766	u8 ch, flag;
 767
 768	while (max_count-- > 0) {
 769		/*
 770		 * Receive all characters known to be in FIFO
 771		 * before reading FIFO level again
 772		 */
 773		if (fifocnt == 0) {
 774			ufstat = rd_regl(port, S3C2410_UFSTAT);
 775			fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 776			if (fifocnt == 0)
 777				break;
 778		}
 779		fifocnt--;
 780
 781		uerstat = rd_regl(port, S3C2410_UERSTAT);
 782		ch = rd_reg(port, S3C2410_URXH);
 783
 784		if (port->flags & UPF_CONS_FLOW) {
 785			bool txe = s3c24xx_serial_txempty_nofifo(port);
 786
 787			if (ourport->rx_enabled) {
 788				if (!txe) {
 789					ourport->rx_enabled = 0;
 790					continue;
 791				}
 792			} else {
 793				if (txe) {
 794					ufcon = rd_regl(port, S3C2410_UFCON);
 795					ufcon |= S3C2410_UFCON_RESETRX;
 796					wr_regl(port, S3C2410_UFCON, ufcon);
 797					ourport->rx_enabled = 1;
 798					return;
 799				}
 800				continue;
 801			}
 802		}
 803
 804		/* insert the character into the buffer */
 805
 806		flag = TTY_NORMAL;
 807		port->icount.rx++;
 808
 809		if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 810			dev_dbg(port->dev,
 811				"rxerr: port ch=0x%02x, rxs=0x%08x\n",
 812				ch, uerstat);
 813
 814			/* check for break */
 815			if (uerstat & S3C2410_UERSTAT_BREAK) {
 816				dev_dbg(port->dev, "break!\n");
 817				port->icount.brk++;
 818				if (uart_handle_break(port))
 819					continue; /* Ignore character */
 820			}
 821
 822			if (uerstat & S3C2410_UERSTAT_FRAME)
 823				port->icount.frame++;
 824			if (uerstat & S3C2410_UERSTAT_OVERRUN)
 825				port->icount.overrun++;
 826
 827			uerstat &= port->read_status_mask;
 828
 829			if (uerstat & S3C2410_UERSTAT_BREAK)
 830				flag = TTY_BREAK;
 831			else if (uerstat & S3C2410_UERSTAT_PARITY)
 832				flag = TTY_PARITY;
 833			else if (uerstat & (S3C2410_UERSTAT_FRAME |
 834					    S3C2410_UERSTAT_OVERRUN))
 835				flag = TTY_FRAME;
 836		}
 837
 838		if (uart_handle_sysrq_char(port, ch))
 839			continue; /* Ignore character */
 840
 841		uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 842				 ch, flag);
 843	}
 844
 845	tty_flip_buffer_push(&port->state->port);
 846}
 847
 848static irqreturn_t s3c24xx_serial_rx_chars_pio(struct s3c24xx_uart_port *ourport)
 849{
 850	struct uart_port *port = &ourport->port;
 851
 852	uart_port_lock(port);
 853	s3c24xx_serial_rx_drain_fifo(ourport);
 854	uart_port_unlock(port);
 855
 856	return IRQ_HANDLED;
 857}
 858
 859static irqreturn_t s3c24xx_serial_rx_irq(struct s3c24xx_uart_port *ourport)
 860{
 861	if (ourport->dma && ourport->dma->rx_chan)
 862		return s3c24xx_serial_rx_chars_dma(ourport);
 863	return s3c24xx_serial_rx_chars_pio(ourport);
 864}
 865
 866static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 867{
 868	struct uart_port *port = &ourport->port;
 869	struct tty_port *tport = &port->state->port;
 870	unsigned int count, dma_count = 0, tail;
 871
 872	count = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE);
 873
 874	if (ourport->dma && ourport->dma->tx_chan &&
 875	    count >= ourport->min_dma_size) {
 876		int align = dma_get_cache_alignment() -
 877			(tail & (dma_get_cache_alignment() - 1));
 878		if (count - align >= ourport->min_dma_size) {
 879			dma_count = count - align;
 880			count = align;
 881			tail += align;
 882		}
 883	}
 884
 885	if (port->x_char) {
 886		wr_reg(port, S3C2410_UTXH, port->x_char);
 887		port->icount.tx++;
 888		port->x_char = 0;
 889		return;
 890	}
 891
 892	/* if there isn't anything more to transmit, or the uart is now
 893	 * stopped, disable the uart and exit
 894	 */
 895
 896	if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
 897		s3c24xx_serial_stop_tx(port);
 898		return;
 899	}
 900
 901	/* try and drain the buffer... */
 902
 903	if (count > port->fifosize) {
 904		count = port->fifosize;
 905		dma_count = 0;
 906	}
 907
 908	while (!(rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)) {
 909		unsigned char ch;
 910
 911		if (!uart_fifo_get(port, &ch))
 912			break;
 913
 914		wr_reg(port, S3C2410_UTXH, ch);
 915		count--;
 916	}
 917
 918	if (!count && dma_count) {
 919		s3c24xx_serial_start_tx_dma(ourport, dma_count, tail);
 920		return;
 921	}
 922
 923	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
 924		uart_write_wakeup(port);
 925
 926	if (kfifo_is_empty(&tport->xmit_fifo))
 927		s3c24xx_serial_stop_tx(port);
 928}
 929
 930static irqreturn_t s3c24xx_serial_tx_irq(struct s3c24xx_uart_port *ourport)
 931{
 932	struct uart_port *port = &ourport->port;
 933
 934	uart_port_lock(port);
 935
 936	s3c24xx_serial_tx_chars(ourport);
 937
 938	uart_port_unlock(port);
 939	return IRQ_HANDLED;
 940}
 941
 942/* interrupt handler for s3c64xx and later SoC's.*/
 943static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 944{
 945	struct s3c24xx_uart_port *ourport = id;
 946	const struct uart_port *port = &ourport->port;
 947	u32 pend = rd_regl(port, S3C64XX_UINTP);
 948	irqreturn_t ret = IRQ_HANDLED;
 949
 950	if (pend & S3C64XX_UINTM_RXD_MSK) {
 951		ret = s3c24xx_serial_rx_irq(ourport);
 952		wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 953	}
 954	if (pend & S3C64XX_UINTM_TXD_MSK) {
 955		ret = s3c24xx_serial_tx_irq(ourport);
 956		wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 957	}
 958	return ret;
 959}
 960
 961/* interrupt handler for Apple SoC's.*/
 962static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 963{
 964	struct s3c24xx_uart_port *ourport = id;
 965	const struct uart_port *port = &ourport->port;
 966	u32 pend = rd_regl(port, S3C2410_UTRSTAT);
 967	irqreturn_t ret = IRQ_NONE;
 968
 969	if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
 970		APPLE_S5L_UTRSTAT_RXTO_LEGACY)) {
 971		wr_regl(port, S3C2410_UTRSTAT,
 972			APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO |
 973			APPLE_S5L_UTRSTAT_RXTO_LEGACY);
 974		ret = s3c24xx_serial_rx_irq(ourport);
 975	}
 976	if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 977		wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 978		ret = s3c24xx_serial_tx_irq(ourport);
 979	}
 980
 981	return ret;
 982}
 983
 984static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 985{
 986	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 987	u32 ufstat = rd_regl(port, S3C2410_UFSTAT);
 988	u32 ufcon = rd_regl(port, S3C2410_UFCON);
 989
 990	if (ufcon & S3C2410_UFCON_FIFOMODE) {
 991		if ((ufstat & info->tx_fifomask) ||
 992		    (ufstat & info->tx_fifofull))
 993			return 0;
 994		return TIOCSER_TEMT;
 995	}
 996
 997	return s3c24xx_serial_txempty_nofifo(port) ? TIOCSER_TEMT : 0;
 998}
 999
1000/* no modem control lines */
1001static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1002{
1003	u32 umstat = rd_reg(port, S3C2410_UMSTAT);
1004
1005	if (umstat & S3C2410_UMSTAT_CTS)
1006		return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1007	else
1008		return TIOCM_CAR | TIOCM_DSR;
1009}
1010
1011static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1012{
1013	u32 umcon = rd_regl(port, S3C2410_UMCON);
1014	u32 ucon = rd_regl(port, S3C2410_UCON);
1015
1016	if (mctrl & TIOCM_RTS)
1017		umcon |= S3C2410_UMCOM_RTS_LOW;
1018	else
1019		umcon &= ~S3C2410_UMCOM_RTS_LOW;
1020
1021	wr_regl(port, S3C2410_UMCON, umcon);
1022
1023	if (mctrl & TIOCM_LOOP)
1024		ucon |= S3C2410_UCON_LOOPBACK;
1025	else
1026		ucon &= ~S3C2410_UCON_LOOPBACK;
1027
1028	wr_regl(port, S3C2410_UCON, ucon);
1029}
1030
1031static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1032{
1033	unsigned long flags;
1034	u32 ucon;
1035
1036	uart_port_lock_irqsave(port, &flags);
1037
1038	ucon = rd_regl(port, S3C2410_UCON);
1039
1040	if (break_state)
1041		ucon |= S3C2410_UCON_SBREAK;
1042	else
1043		ucon &= ~S3C2410_UCON_SBREAK;
1044
1045	wr_regl(port, S3C2410_UCON, ucon);
1046
1047	uart_port_unlock_irqrestore(port, flags);
1048}
1049
1050static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1051{
1052	struct s3c24xx_uart_dma	*dma = p->dma;
1053	struct dma_slave_caps dma_caps;
1054	const char *reason = NULL;
1055	int ret;
1056
1057	/* Default slave configuration parameters */
1058	dma->rx_conf.direction		= DMA_DEV_TO_MEM;
1059	dma->rx_conf.src_addr_width	= DMA_SLAVE_BUSWIDTH_1_BYTE;
1060	dma->rx_conf.src_addr		= p->port.mapbase + S3C2410_URXH;
1061	dma->rx_conf.src_maxburst	= 1;
1062
1063	dma->tx_conf.direction		= DMA_MEM_TO_DEV;
1064	dma->tx_conf.dst_addr_width	= DMA_SLAVE_BUSWIDTH_1_BYTE;
1065	dma->tx_conf.dst_addr		= p->port.mapbase + S3C2410_UTXH;
1066	dma->tx_conf.dst_maxburst	= 1;
1067
1068	dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1069
1070	if (IS_ERR(dma->rx_chan)) {
1071		reason = "DMA RX channel request failed";
1072		ret = PTR_ERR(dma->rx_chan);
1073		goto err_warn;
1074	}
1075
1076	ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1077	if (ret < 0 ||
1078	    dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1079		reason = "insufficient DMA RX engine capabilities";
1080		ret = -EOPNOTSUPP;
1081		goto err_release_rx;
1082	}
1083
1084	dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1085
1086	dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1087	if (IS_ERR(dma->tx_chan)) {
1088		reason = "DMA TX channel request failed";
1089		ret = PTR_ERR(dma->tx_chan);
1090		goto err_release_rx;
1091	}
1092
1093	ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1094	if (ret < 0 ||
1095	    dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1096		reason = "insufficient DMA TX engine capabilities";
1097		ret = -EOPNOTSUPP;
1098		goto err_release_tx;
1099	}
1100
1101	dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1102
1103	/* RX buffer */
1104	dma->rx_size = PAGE_SIZE;
1105
1106	dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1107	if (!dma->rx_buf) {
1108		ret = -ENOMEM;
1109		goto err_release_tx;
1110	}
1111
1112	dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1113				      dma->rx_size, DMA_FROM_DEVICE);
1114	if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1115		reason = "DMA mapping error for RX buffer";
1116		ret = -EIO;
1117		goto err_free_rx;
1118	}
1119
1120	/* TX buffer */
1121	dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1122				      p->port.state->port.xmit_buf,
1123				      UART_XMIT_SIZE,
1124				      DMA_TO_DEVICE);
1125	if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1126		reason = "DMA mapping error for TX buffer";
1127		ret = -EIO;
1128		goto err_unmap_rx;
1129	}
1130
1131	return 0;
1132
1133err_unmap_rx:
1134	dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1135			 dma->rx_size, DMA_FROM_DEVICE);
1136err_free_rx:
1137	kfree(dma->rx_buf);
1138err_release_tx:
1139	dma_release_channel(dma->tx_chan);
1140err_release_rx:
1141	dma_release_channel(dma->rx_chan);
1142err_warn:
1143	if (reason)
1144		dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1145	return ret;
1146}
1147
1148static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1149{
1150	struct s3c24xx_uart_dma	*dma = p->dma;
1151
1152	if (dma->rx_chan) {
1153		dmaengine_terminate_all(dma->rx_chan);
1154		dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1155				 dma->rx_size, DMA_FROM_DEVICE);
1156		kfree(dma->rx_buf);
1157		dma_release_channel(dma->rx_chan);
1158		dma->rx_chan = NULL;
1159	}
1160
1161	if (dma->tx_chan) {
1162		dmaengine_terminate_all(dma->tx_chan);
1163		dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1164				 UART_XMIT_SIZE, DMA_TO_DEVICE);
1165		dma_release_channel(dma->tx_chan);
1166		dma->tx_chan = NULL;
1167	}
1168}
1169
1170static void s3c64xx_serial_shutdown(struct uart_port *port)
1171{
1172	struct s3c24xx_uart_port *ourport = to_ourport(port);
1173
1174	ourport->tx_enabled = 0;
1175	ourport->tx_mode = 0;
1176	ourport->rx_enabled = 0;
1177
1178	free_irq(port->irq, ourport);
1179
1180	wr_regl(port, S3C64XX_UINTP, 0xf);
1181	wr_regl(port, S3C64XX_UINTM, 0xf);
1182
1183	if (ourport->dma)
1184		s3c24xx_serial_release_dma(ourport);
1185
1186	ourport->tx_in_progress = 0;
1187}
1188
1189static void apple_s5l_serial_shutdown(struct uart_port *port)
1190{
1191	struct s3c24xx_uart_port *ourport = to_ourport(port);
1192
1193	u32 ucon;
1194
1195	ucon = rd_regl(port, S3C2410_UCON);
1196	ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1197		  APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1198		  APPLE_S5L_UCON_RXTO_ENA_MSK |
1199		  APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
1200	wr_regl(port, S3C2410_UCON, ucon);
1201
1202	wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1203
1204	free_irq(port->irq, ourport);
1205
1206	ourport->tx_enabled = 0;
1207	ourport->tx_mode = 0;
1208	ourport->rx_enabled = 0;
1209
1210	if (ourport->dma)
1211		s3c24xx_serial_release_dma(ourport);
1212
1213	ourport->tx_in_progress = 0;
1214}
1215
1216static int s3c64xx_serial_startup(struct uart_port *port)
1217{
1218	struct s3c24xx_uart_port *ourport = to_ourport(port);
1219	unsigned long flags;
1220	u32 ufcon;
1221	int ret;
1222
1223	wr_regl(port, S3C64XX_UINTM, 0xf);
1224	if (ourport->dma) {
1225		ret = s3c24xx_serial_request_dma(ourport);
1226		if (ret < 0) {
1227			devm_kfree(port->dev, ourport->dma);
1228			ourport->dma = NULL;
1229		}
1230	}
1231
1232	ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1233			  s3c24xx_serial_portname(port), ourport);
1234	if (ret) {
1235		dev_err(port->dev, "cannot get irq %d\n", port->irq);
1236		return ret;
1237	}
1238
1239	/* For compatibility with s3c24xx Soc's */
1240	ourport->rx_enabled = 1;
1241	ourport->tx_enabled = 0;
1242
1243	uart_port_lock_irqsave(port, &flags);
1244
1245	ufcon = rd_regl(port, S3C2410_UFCON);
1246	ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1247	if (!uart_console(port))
1248		ufcon |= S3C2410_UFCON_RESETTX;
1249	wr_regl(port, S3C2410_UFCON, ufcon);
1250
1251	enable_rx_pio(ourport);
1252
1253	uart_port_unlock_irqrestore(port, flags);
1254
1255	/* Enable Rx Interrupt */
1256	s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1257
1258	return ret;
1259}
1260
1261static int apple_s5l_serial_startup(struct uart_port *port)
1262{
1263	struct s3c24xx_uart_port *ourport = to_ourport(port);
1264	unsigned long flags;
1265	u32 ufcon;
1266	int ret;
1267
1268	wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1269
1270	ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1271			  s3c24xx_serial_portname(port), ourport);
1272	if (ret) {
1273		dev_err(port->dev, "cannot get irq %d\n", port->irq);
1274		return ret;
1275	}
1276
1277	/* For compatibility with s3c24xx Soc's */
1278	ourport->rx_enabled = 1;
1279	ourport->tx_enabled = 0;
1280
1281	uart_port_lock_irqsave(port, &flags);
1282
1283	ufcon = rd_regl(port, S3C2410_UFCON);
1284	ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1285	if (!uart_console(port))
1286		ufcon |= S3C2410_UFCON_RESETTX;
1287	wr_regl(port, S3C2410_UFCON, ufcon);
1288
1289	enable_rx_pio(ourport);
1290
1291	uart_port_unlock_irqrestore(port, flags);
1292
1293	/* Enable Rx Interrupt */
1294	s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1295	s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1296	s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_LEGACY_ENA, S3C2410_UCON);
1297
1298	return ret;
1299}
1300
1301static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1302			      unsigned int old)
1303{
1304	struct s3c24xx_uart_port *ourport = to_ourport(port);
1305	int timeout = 10000;
1306
1307	ourport->pm_level = level;
1308
1309	switch (level) {
1310	case 3:
1311		while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1312			udelay(100);
1313
1314		if (!IS_ERR(ourport->baudclk))
1315			clk_disable_unprepare(ourport->baudclk);
1316
1317		clk_disable_unprepare(ourport->clk);
1318		break;
1319
1320	case 0:
1321		clk_prepare_enable(ourport->clk);
1322
1323		if (!IS_ERR(ourport->baudclk))
1324			clk_prepare_enable(ourport->baudclk);
1325		break;
1326	default:
1327		dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1328	}
1329}
1330
1331/* baud rate calculation
1332 *
1333 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1334 * of different sources, including the peripheral clock ("pclk") and an
1335 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1336 * with a programmable extra divisor.
1337 *
1338 * The following code goes through the clock sources, and calculates the
1339 * baud clocks (and the resultant actual baud rates) and then tries to
1340 * pick the closest one and select that.
1341 *
1342 */
1343
1344#define MAX_CLK_NAME_LENGTH 15
1345
1346static inline u8 s3c24xx_serial_getsource(struct uart_port *port)
1347{
1348	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1349	u32 ucon;
1350
1351	if (info->num_clks == 1)
1352		return 0;
1353
1354	ucon = rd_regl(port, S3C2410_UCON);
1355	ucon &= info->clksel_mask;
1356	return ucon >> info->clksel_shift;
1357}
1358
1359static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel)
1360{
1361	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1362	u32 ucon;
1363
1364	if (info->num_clks == 1)
1365		return;
1366
1367	ucon = rd_regl(port, S3C2410_UCON);
1368	if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1369		return;
1370
1371	ucon &= ~info->clksel_mask;
1372	ucon |= clk_sel << info->clksel_shift;
1373	wr_regl(port, S3C2410_UCON, ucon);
1374}
1375
1376static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1377			unsigned int req_baud, struct clk **best_clk,
1378			u8 *clk_num)
1379{
1380	const struct s3c24xx_uart_info *info = ourport->info;
1381	struct clk *clk;
1382	unsigned long rate;
1383	unsigned int baud, quot, best_quot = 0;
1384	char clkname[MAX_CLK_NAME_LENGTH];
1385	int calc_deviation, deviation = (1 << 30) - 1;
1386	u8 cnt;
1387
1388	for (cnt = 0; cnt < info->num_clks; cnt++) {
1389		/* Keep selected clock if provided */
1390		if (ourport->cfg->clk_sel &&
1391			!(ourport->cfg->clk_sel & (1 << cnt)))
1392			continue;
1393
1394		sprintf(clkname, "clk_uart_baud%d", cnt);
1395		clk = clk_get(ourport->port.dev, clkname);
1396		if (IS_ERR(clk))
1397			continue;
1398
1399		rate = clk_get_rate(clk);
1400		if (!rate) {
1401			dev_err(ourport->port.dev,
1402				"Failed to get clock rate for %s.\n", clkname);
1403			clk_put(clk);
1404			continue;
1405		}
1406
1407		if (ourport->info->has_divslot) {
1408			unsigned long div = rate / req_baud;
1409
1410			/* The UDIVSLOT register on the newer UARTs allows us to
1411			 * get a divisor adjustment of 1/16th on the baud clock.
1412			 *
1413			 * We don't keep the UDIVSLOT value (the 16ths we
1414			 * calculated by not multiplying the baud by 16) as it
1415			 * is easy enough to recalculate.
1416			 */
1417
1418			quot = div / 16;
1419			baud = rate / div;
1420		} else {
1421			quot = (rate + (8 * req_baud)) / (16 * req_baud);
1422			baud = rate / (quot * 16);
1423		}
1424		quot--;
1425
1426		calc_deviation = abs(req_baud - baud);
1427
1428		if (calc_deviation < deviation) {
1429			/*
1430			 * If we find a better clk, release the previous one, if
1431			 * any.
1432			 */
1433			if (!IS_ERR(*best_clk))
1434				clk_put(*best_clk);
1435			*best_clk = clk;
1436			best_quot = quot;
1437			*clk_num = cnt;
1438			deviation = calc_deviation;
1439		} else {
1440			clk_put(clk);
1441		}
1442	}
1443
1444	return best_quot;
1445}
1446
1447/* udivslot_table[]
1448 *
1449 * This table takes the fractional value of the baud divisor and gives
1450 * the recommended setting for the UDIVSLOT register.
1451 */
1452static const u16 udivslot_table[16] = {
1453	[0] = 0x0000,
1454	[1] = 0x0080,
1455	[2] = 0x0808,
1456	[3] = 0x0888,
1457	[4] = 0x2222,
1458	[5] = 0x4924,
1459	[6] = 0x4A52,
1460	[7] = 0x54AA,
1461	[8] = 0x5555,
1462	[9] = 0xD555,
1463	[10] = 0xD5D5,
1464	[11] = 0xDDD5,
1465	[12] = 0xDDDD,
1466	[13] = 0xDFDD,
1467	[14] = 0xDFDF,
1468	[15] = 0xFFDF,
1469};
1470
1471static void s3c24xx_serial_set_termios(struct uart_port *port,
1472				       struct ktermios *termios,
1473				       const struct ktermios *old)
1474{
1475	const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1476	struct s3c24xx_uart_port *ourport = to_ourport(port);
1477	struct clk *clk = ERR_PTR(-EINVAL);
1478	unsigned long flags;
1479	unsigned int baud, quot;
1480	unsigned int udivslot = 0;
1481	u32 ulcon, umcon;
1482	u8 clk_sel = 0;
1483
1484	/*
1485	 * We don't support modem control lines.
1486	 */
1487	termios->c_cflag &= ~(HUPCL | CMSPAR);
1488	termios->c_cflag |= CLOCAL;
1489
1490	/*
1491	 * Ask the core to calculate the divisor for us.
1492	 */
1493
1494	baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1495	quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1496	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1497		quot = port->custom_divisor;
1498	if (IS_ERR(clk))
1499		return;
1500
1501	/* check to see if we need  to change clock source */
1502
1503	if (ourport->baudclk != clk) {
1504		clk_prepare_enable(clk);
1505
1506		s3c24xx_serial_setsource(port, clk_sel);
1507
1508		if (!IS_ERR(ourport->baudclk)) {
1509			clk_disable_unprepare(ourport->baudclk);
1510			ourport->baudclk = ERR_PTR(-EINVAL);
1511		}
1512
1513		ourport->baudclk = clk;
1514		ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1515	}
1516
1517	if (ourport->info->has_divslot) {
1518		unsigned int div = ourport->baudclk_rate / baud;
1519
1520		if (cfg->has_fracval) {
1521			udivslot = (div & 15);
1522			dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1523		} else {
1524			udivslot = udivslot_table[div & 15];
1525			dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1526				udivslot, div & 15);
1527		}
1528	}
1529
1530	switch (termios->c_cflag & CSIZE) {
1531	case CS5:
1532		dev_dbg(port->dev, "config: 5bits/char\n");
1533		ulcon = S3C2410_LCON_CS5;
1534		break;
1535	case CS6:
1536		dev_dbg(port->dev, "config: 6bits/char\n");
1537		ulcon = S3C2410_LCON_CS6;
1538		break;
1539	case CS7:
1540		dev_dbg(port->dev, "config: 7bits/char\n");
1541		ulcon = S3C2410_LCON_CS7;
1542		break;
1543	case CS8:
1544	default:
1545		dev_dbg(port->dev, "config: 8bits/char\n");
1546		ulcon = S3C2410_LCON_CS8;
1547		break;
1548	}
1549
1550	/* preserve original lcon IR settings */
1551	ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1552
1553	if (termios->c_cflag & CSTOPB)
1554		ulcon |= S3C2410_LCON_STOPB;
1555
1556	if (termios->c_cflag & PARENB) {
1557		if (termios->c_cflag & PARODD)
1558			ulcon |= S3C2410_LCON_PODD;
1559		else
1560			ulcon |= S3C2410_LCON_PEVEN;
1561	} else {
1562		ulcon |= S3C2410_LCON_PNONE;
1563	}
1564
1565	uart_port_lock_irqsave(port, &flags);
1566
1567	dev_dbg(port->dev,
1568		"setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1569		ulcon, quot, udivslot);
1570
1571	wr_regl(port, S3C2410_ULCON, ulcon);
1572	wr_regl(port, S3C2410_UBRDIV, quot);
1573
1574	port->status &= ~UPSTAT_AUTOCTS;
1575
1576	umcon = rd_regl(port, S3C2410_UMCON);
1577	if (termios->c_cflag & CRTSCTS) {
1578		umcon |= S3C2410_UMCOM_AFC;
1579		/* Disable RTS when RX FIFO contains 63 bytes */
1580		umcon &= ~S3C2412_UMCON_AFC_8;
1581		port->status = UPSTAT_AUTOCTS;
1582	} else {
1583		umcon &= ~S3C2410_UMCOM_AFC;
1584	}
1585	wr_regl(port, S3C2410_UMCON, umcon);
1586
1587	if (ourport->info->has_divslot)
1588		wr_regl(port, S3C2443_DIVSLOT, udivslot);
1589
1590	dev_dbg(port->dev,
1591		"uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1592		rd_regl(port, S3C2410_ULCON),
1593		rd_regl(port, S3C2410_UCON),
1594		rd_regl(port, S3C2410_UFCON));
1595
1596	/*
1597	 * Update the per-port timeout.
1598	 */
1599	uart_update_timeout(port, termios->c_cflag, baud);
1600
1601	/*
1602	 * Which character status flags are we interested in?
1603	 */
1604	port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1605	if (termios->c_iflag & INPCK)
1606		port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1607			S3C2410_UERSTAT_PARITY;
1608	/*
1609	 * Which character status flags should we ignore?
1610	 */
1611	port->ignore_status_mask = 0;
1612	if (termios->c_iflag & IGNPAR)
1613		port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1614	if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1615		port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1616
1617	/*
1618	 * Ignore all characters if CREAD is not set.
1619	 */
1620	if ((termios->c_cflag & CREAD) == 0)
1621		port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1622
1623	uart_port_unlock_irqrestore(port, flags);
1624}
1625
1626static const char *s3c24xx_serial_type(struct uart_port *port)
1627{
1628	const struct s3c24xx_uart_port *ourport = to_ourport(port);
1629
1630	switch (ourport->info->type) {
1631	case TYPE_S3C6400:
1632		return "S3C6400/10";
1633	case TYPE_APPLE_S5L:
1634		return "APPLE S5L";
1635	default:
1636		return NULL;
1637	}
1638}
1639
1640static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1641{
1642	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1643
1644	if (flags & UART_CONFIG_TYPE)
1645		port->type = info->port_type;
1646}
1647
1648/*
1649 * verify the new serial_struct (for TIOCSSERIAL).
1650 */
1651static int
1652s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1653{
1654	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1655
1656	if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1657		return -EINVAL;
1658
1659	return 0;
1660}
1661
1662#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1663
1664static struct console s3c24xx_serial_console;
1665
1666static void __init s3c24xx_serial_register_console(void)
1667{
1668	register_console(&s3c24xx_serial_console);
1669}
1670
1671static void s3c24xx_serial_unregister_console(void)
1672{
1673	if (console_is_registered(&s3c24xx_serial_console))
1674		unregister_console(&s3c24xx_serial_console);
1675}
1676
1677#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1678#else
1679static inline void s3c24xx_serial_register_console(void) { }
1680static inline void s3c24xx_serial_unregister_console(void) { }
1681#define S3C24XX_SERIAL_CONSOLE NULL
1682#endif
1683
1684#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1685static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1686static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1687			 unsigned char c);
1688#endif
1689
1690static const struct uart_ops s3c64xx_serial_ops = {
1691	.pm		= s3c24xx_serial_pm,
1692	.tx_empty	= s3c24xx_serial_tx_empty,
1693	.get_mctrl	= s3c24xx_serial_get_mctrl,
1694	.set_mctrl	= s3c24xx_serial_set_mctrl,
1695	.stop_tx	= s3c24xx_serial_stop_tx,
1696	.start_tx	= s3c24xx_serial_start_tx,
1697	.stop_rx	= s3c24xx_serial_stop_rx,
1698	.break_ctl	= s3c24xx_serial_break_ctl,
1699	.startup	= s3c64xx_serial_startup,
1700	.shutdown	= s3c64xx_serial_shutdown,
1701	.set_termios	= s3c24xx_serial_set_termios,
1702	.type		= s3c24xx_serial_type,
1703	.config_port	= s3c24xx_serial_config_port,
1704	.verify_port	= s3c24xx_serial_verify_port,
1705#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1706	.poll_get_char = s3c24xx_serial_get_poll_char,
1707	.poll_put_char = s3c24xx_serial_put_poll_char,
1708#endif
1709};
1710
1711static const struct uart_ops apple_s5l_serial_ops = {
1712	.pm		= s3c24xx_serial_pm,
1713	.tx_empty	= s3c24xx_serial_tx_empty,
1714	.get_mctrl	= s3c24xx_serial_get_mctrl,
1715	.set_mctrl	= s3c24xx_serial_set_mctrl,
1716	.stop_tx	= s3c24xx_serial_stop_tx,
1717	.start_tx	= s3c24xx_serial_start_tx,
1718	.stop_rx	= s3c24xx_serial_stop_rx,
1719	.break_ctl	= s3c24xx_serial_break_ctl,
1720	.startup	= apple_s5l_serial_startup,
1721	.shutdown	= apple_s5l_serial_shutdown,
1722	.set_termios	= s3c24xx_serial_set_termios,
1723	.type		= s3c24xx_serial_type,
1724	.config_port	= s3c24xx_serial_config_port,
1725	.verify_port	= s3c24xx_serial_verify_port,
1726#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1727	.poll_get_char = s3c24xx_serial_get_poll_char,
1728	.poll_put_char = s3c24xx_serial_put_poll_char,
1729#endif
1730};
1731
1732static struct uart_driver s3c24xx_uart_drv = {
1733	.owner		= THIS_MODULE,
1734	.driver_name	= "s3c2410_serial",
1735	.nr		= UART_NR,
1736	.cons		= S3C24XX_SERIAL_CONSOLE,
1737	.dev_name	= S3C24XX_SERIAL_NAME,
1738	.major		= S3C24XX_SERIAL_MAJOR,
1739	.minor		= S3C24XX_SERIAL_MINOR,
1740};
1741
1742static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1743
1744static void s3c24xx_serial_init_port_default(int index)
1745{
1746	struct uart_port *port = &s3c24xx_serial_ports[index].port;
1747
1748	spin_lock_init(&port->lock);
1749
1750	port->uartclk = 0;
1751	port->fifosize = 16;
1752	port->flags = UPF_BOOT_AUTOCONF;
1753	port->line = index;
1754}
1755
1756/* s3c24xx_serial_resetport
1757 *
1758 * reset the fifos and other the settings.
1759 */
1760
1761static void s3c24xx_serial_resetport(struct uart_port *port,
1762				     const struct s3c2410_uartcfg *cfg)
1763{
1764	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1765	u32 ucon = rd_regl(port, S3C2410_UCON);
1766
1767	ucon &= (info->clksel_mask | info->ucon_mask);
1768	wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1769
1770	/* reset both fifos */
1771	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1772	wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1773
1774	/* some delay is required after fifo reset */
1775	udelay(1);
1776}
1777
1778static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1779{
1780	struct device *dev = ourport->port.dev;
1781	const struct s3c24xx_uart_info *info = ourport->info;
1782	char clk_name[MAX_CLK_NAME_LENGTH];
1783	struct clk *clk;
1784	int ret;
1785	u8 clk_sel, clk_num;
1786
1787	clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1788	for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1789		if (!(clk_sel & (1 << clk_num)))
1790			continue;
1791
1792		sprintf(clk_name, "clk_uart_baud%d", clk_num);
1793		clk = clk_get(dev, clk_name);
1794		if (IS_ERR(clk))
1795			continue;
1796
1797		ret = clk_prepare_enable(clk);
1798		if (ret) {
1799			clk_put(clk);
1800			continue;
1801		}
1802
1803		ourport->baudclk = clk;
1804		ourport->baudclk_rate = clk_get_rate(clk);
1805		s3c24xx_serial_setsource(&ourport->port, clk_num);
1806
1807		return 0;
1808	}
1809
1810	return -EINVAL;
1811}
1812
1813/* s3c24xx_serial_init_port
1814 *
1815 * initialise a single serial port from the platform device given
1816 */
1817
1818static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1819				    struct platform_device *platdev)
1820{
1821	struct uart_port *port = &ourport->port;
1822	const struct s3c2410_uartcfg *cfg = ourport->cfg;
1823	struct resource *res;
1824	int ret;
1825
1826	if (platdev == NULL)
1827		return -ENODEV;
1828
1829	if (port->mapbase != 0)
1830		return -EINVAL;
1831
1832	/* setup info for port */
1833	port->dev	= &platdev->dev;
1834
1835	port->uartclk = 1;
1836
1837	if (cfg->uart_flags & UPF_CONS_FLOW) {
1838		dev_dbg(port->dev, "enabling flow control\n");
1839		port->flags |= UPF_CONS_FLOW;
1840	}
1841
1842	/* sort our the physical and virtual addresses for each UART */
1843
1844	res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1845	if (res == NULL) {
1846		dev_err(port->dev, "failed to find memory resource for uart\n");
1847		return -EINVAL;
1848	}
1849
1850	dev_dbg(port->dev, "resource %pR)\n", res);
1851
1852	port->membase = devm_ioremap_resource(port->dev, res);
1853	if (IS_ERR(port->membase)) {
1854		dev_err(port->dev, "failed to remap controller address\n");
1855		return -EBUSY;
1856	}
1857
1858	port->mapbase = res->start;
1859	ret = platform_get_irq(platdev, 0);
1860	if (ret < 0) {
1861		port->irq = 0;
1862	} else {
1863		port->irq = ret;
1864		ourport->rx_irq = ret;
1865		ourport->tx_irq = ret + 1;
1866	}
1867
1868	/*
1869	 * DMA is currently supported only on DT platforms, if DMA properties
1870	 * are specified.
1871	 */
1872	if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1873						     "dmas", NULL)) {
1874		ourport->dma = devm_kzalloc(port->dev,
1875					    sizeof(*ourport->dma),
1876					    GFP_KERNEL);
1877		if (!ourport->dma) {
1878			ret = -ENOMEM;
1879			goto err;
1880		}
1881	}
1882
1883	ourport->clk	= clk_get(&platdev->dev, "uart");
1884	if (IS_ERR(ourport->clk)) {
1885		pr_err("%s: Controller clock not found\n",
1886				dev_name(&platdev->dev));
1887		ret = PTR_ERR(ourport->clk);
1888		goto err;
1889	}
1890
1891	ret = clk_prepare_enable(ourport->clk);
1892	if (ret) {
1893		pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1894		clk_put(ourport->clk);
1895		goto err;
1896	}
1897
1898	ret = s3c24xx_serial_enable_baudclk(ourport);
1899	if (ret)
1900		pr_warn("uart: failed to enable baudclk\n");
1901
1902	/* Keep all interrupts masked and cleared */
1903	switch (ourport->info->type) {
1904	case TYPE_S3C6400:
1905		wr_regl(port, S3C64XX_UINTM, 0xf);
1906		wr_regl(port, S3C64XX_UINTP, 0xf);
1907		wr_regl(port, S3C64XX_UINTSP, 0xf);
1908		break;
1909	case TYPE_APPLE_S5L: {
1910		u32 ucon;
1911
1912		ucon = rd_regl(port, S3C2410_UCON);
1913		ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1914			APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1915			APPLE_S5L_UCON_RXTO_ENA_MSK);
1916		wr_regl(port, S3C2410_UCON, ucon);
1917
1918		wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1919		break;
1920	}
1921	default:
1922		break;
1923	}
1924
1925	dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1926		&port->mapbase, port->membase, port->irq,
1927		ourport->rx_irq, ourport->tx_irq, port->uartclk);
1928
1929	/* reset the fifos (and setup the uart) */
1930	s3c24xx_serial_resetport(port, cfg);
1931
1932	return 0;
1933
1934err:
1935	port->mapbase = 0;
1936	return ret;
1937}
1938
1939/* Device driver serial port probe */
1940
1941static int probe_index;
1942
1943static inline const struct s3c24xx_serial_drv_data *
1944s3c24xx_get_driver_data(struct platform_device *pdev)
1945{
1946	if (dev_of_node(&pdev->dev))
1947		return of_device_get_match_data(&pdev->dev);
1948
1949	return (struct s3c24xx_serial_drv_data *)
1950			platform_get_device_id(pdev)->driver_data;
1951}
1952
1953static int s3c24xx_serial_probe(struct platform_device *pdev)
1954{
1955	struct device_node *np = pdev->dev.of_node;
1956	struct s3c24xx_uart_port *ourport;
1957	int index = probe_index;
1958	int ret, prop = 0, fifosize_prop = 1;
1959
1960	if (np) {
1961		ret = of_alias_get_id(np, "serial");
1962		if (ret >= 0)
1963			index = ret;
1964	}
1965
1966	if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1967		dev_err(&pdev->dev, "serial%d out of range\n", index);
1968		return -EINVAL;
1969	}
1970	ourport = &s3c24xx_serial_ports[index];
1971
1972	s3c24xx_serial_init_port_default(index);
1973
1974	ourport->drv_data = s3c24xx_get_driver_data(pdev);
1975	if (!ourport->drv_data) {
1976		dev_err(&pdev->dev, "could not find driver data\n");
1977		return -ENODEV;
1978	}
1979
1980	ourport->baudclk = ERR_PTR(-EINVAL);
1981	ourport->info = &ourport->drv_data->info;
1982	ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1983			dev_get_platdata(&pdev->dev) :
1984			&ourport->drv_data->def_cfg;
1985
1986	switch (ourport->info->type) {
1987	case TYPE_S3C6400:
1988		ourport->port.ops = &s3c64xx_serial_ops;
1989		break;
1990	case TYPE_APPLE_S5L:
1991		ourport->port.ops = &apple_s5l_serial_ops;
1992		break;
1993	}
1994
1995	ourport->port.iotype = ourport->info->iotype;
1996
1997	if (np) {
1998		fifosize_prop = of_property_read_u32(np, "samsung,uart-fifosize",
1999				&ourport->port.fifosize);
2000
2001		if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2002			switch (prop) {
2003			case 1:
2004				ourport->port.iotype = UPIO_MEM;
2005				break;
2006			case 4:
2007				ourport->port.iotype = UPIO_MEM32;
2008				break;
2009			default:
2010				dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2011						prop);
2012				return -EINVAL;
2013			}
2014		}
2015	}
2016
2017	if (fifosize_prop) {
2018		if (ourport->drv_data->fifosize[index])
2019			ourport->port.fifosize = ourport->drv_data->fifosize[index];
2020		else if (ourport->info->fifosize)
2021			ourport->port.fifosize = ourport->info->fifosize;
2022	}
2023
2024	ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2025
2026	/*
2027	 * DMA transfers must be aligned at least to cache line size,
2028	 * so find minimal transfer size suitable for DMA mode
2029	 */
2030	ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2031				    dma_get_cache_alignment());
2032
2033	dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2034
2035	ret = s3c24xx_serial_init_port(ourport, pdev);
2036	if (ret < 0)
2037		return ret;
2038
2039	if (!s3c24xx_uart_drv.state) {
2040		ret = uart_register_driver(&s3c24xx_uart_drv);
2041		if (ret < 0) {
2042			pr_err("Failed to register Samsung UART driver\n");
2043			return ret;
2044		}
2045	}
2046
2047	dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2048	uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2049	platform_set_drvdata(pdev, &ourport->port);
2050
2051	/*
2052	 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2053	 * so that a potential re-enablement through the pm-callback overlaps
2054	 * and keeps the clock enabled in this case.
2055	 */
2056	clk_disable_unprepare(ourport->clk);
2057	if (!IS_ERR(ourport->baudclk))
2058		clk_disable_unprepare(ourport->baudclk);
2059
2060	probe_index++;
2061
2062	return 0;
2063}
2064
2065static void s3c24xx_serial_remove(struct platform_device *dev)
2066{
2067	struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2068
2069	if (port)
2070		uart_remove_one_port(&s3c24xx_uart_drv, port);
2071
2072	uart_unregister_driver(&s3c24xx_uart_drv);
2073}
2074
2075/* UART power management code */
2076#ifdef CONFIG_PM_SLEEP
2077static int s3c24xx_serial_suspend(struct device *dev)
2078{
2079	struct uart_port *port = s3c24xx_dev_to_port(dev);
2080
2081	if (port)
2082		uart_suspend_port(&s3c24xx_uart_drv, port);
2083
2084	return 0;
2085}
2086
2087static int s3c24xx_serial_resume(struct device *dev)
2088{
2089	struct uart_port *port = s3c24xx_dev_to_port(dev);
2090	struct s3c24xx_uart_port *ourport = to_ourport(port);
2091
2092	if (port) {
2093		clk_prepare_enable(ourport->clk);
2094		if (!IS_ERR(ourport->baudclk))
2095			clk_prepare_enable(ourport->baudclk);
2096		s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2097		if (!IS_ERR(ourport->baudclk))
2098			clk_disable_unprepare(ourport->baudclk);
2099		clk_disable_unprepare(ourport->clk);
2100
2101		uart_resume_port(&s3c24xx_uart_drv, port);
2102	}
2103
2104	return 0;
2105}
2106
2107static int s3c24xx_serial_resume_noirq(struct device *dev)
2108{
2109	struct uart_port *port = s3c24xx_dev_to_port(dev);
2110	struct s3c24xx_uart_port *ourport = to_ourport(port);
2111
2112	if (port) {
2113		/* restore IRQ mask */
2114		switch (ourport->info->type) {
2115		case TYPE_S3C6400: {
2116			u32 uintm = 0xf;
2117
2118			if (ourport->tx_enabled)
2119				uintm &= ~S3C64XX_UINTM_TXD_MSK;
2120			if (ourport->rx_enabled)
2121				uintm &= ~S3C64XX_UINTM_RXD_MSK;
2122			clk_prepare_enable(ourport->clk);
2123			if (!IS_ERR(ourport->baudclk))
2124				clk_prepare_enable(ourport->baudclk);
2125			wr_regl(port, S3C64XX_UINTM, uintm);
2126			if (!IS_ERR(ourport->baudclk))
2127				clk_disable_unprepare(ourport->baudclk);
2128			clk_disable_unprepare(ourport->clk);
2129			break;
2130		}
2131		case TYPE_APPLE_S5L: {
2132			u32 ucon;
2133			int ret;
2134
2135			ret = clk_prepare_enable(ourport->clk);
2136			if (ret) {
2137				dev_err(dev, "clk_enable clk failed: %d\n", ret);
2138				return ret;
2139			}
2140			if (!IS_ERR(ourport->baudclk)) {
2141				ret = clk_prepare_enable(ourport->baudclk);
2142				if (ret) {
2143					dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2144					clk_disable_unprepare(ourport->clk);
2145					return ret;
2146				}
2147			}
2148
2149			ucon = rd_regl(port, S3C2410_UCON);
2150
2151			ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2152				  APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2153				  APPLE_S5L_UCON_RXTO_ENA_MSK |
2154				  APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK);
2155
2156			if (ourport->tx_enabled)
2157				ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2158			if (ourport->rx_enabled)
2159				ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2160					APPLE_S5L_UCON_RXTO_ENA_MSK |
2161					APPLE_S5L_UCON_RXTO_LEGACY_ENA_MSK;
2162
2163			wr_regl(port, S3C2410_UCON, ucon);
2164
2165			if (!IS_ERR(ourport->baudclk))
2166				clk_disable_unprepare(ourport->baudclk);
2167			clk_disable_unprepare(ourport->clk);
2168			break;
2169		}
2170		default:
2171			break;
2172		}
2173	}
2174
2175	return 0;
2176}
2177
2178static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2179	SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume)
2180	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq)
2181};
2182#define SERIAL_SAMSUNG_PM_OPS	(&s3c24xx_serial_pm_ops)
2183
2184#else /* !CONFIG_PM_SLEEP */
2185
2186#define SERIAL_SAMSUNG_PM_OPS	NULL
2187#endif /* CONFIG_PM_SLEEP */
2188
2189/* Console code */
2190
2191#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2192
2193static struct uart_port *cons_uart;
2194
2195static bool
2196s3c24xx_serial_console_txrdy(struct uart_port *port, u32 ufcon)
2197{
2198	const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2199	u32 ufstat, utrstat;
2200
2201	if (ufcon & S3C2410_UFCON_FIFOMODE) {
2202		/* fifo mode - check amount of data in fifo registers... */
2203
2204		ufstat = rd_regl(port, S3C2410_UFSTAT);
2205		return !(ufstat & info->tx_fifofull);
2206	}
2207
2208	/* in non-fifo mode, we go and use the tx buffer empty */
2209
2210	utrstat = rd_regl(port, S3C2410_UTRSTAT);
2211	return utrstat & S3C2410_UTRSTAT_TXE;
2212}
2213
2214static bool
2215s3c24xx_port_configured(u32 ucon)
2216{
2217	/* consider the serial port configured if the tx/rx mode set */
2218	return (ucon & 0xf) != 0;
2219}
2220
2221#ifdef CONFIG_CONSOLE_POLL
2222/*
2223 * Console polling routines for writing and reading from the uart while
2224 * in an interrupt or debug context.
2225 */
2226
2227static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2228{
2229	const struct s3c24xx_uart_port *ourport = to_ourport(port);
2230	u32 ufstat;
2231
2232	ufstat = rd_regl(port, S3C2410_UFSTAT);
2233	if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2234		return NO_POLL_CHAR;
2235
2236	return rd_reg(port, S3C2410_URXH);
2237}
2238
2239static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2240		unsigned char c)
2241{
2242	u32 ufcon = rd_regl(port, S3C2410_UFCON);
2243	u32 ucon = rd_regl(port, S3C2410_UCON);
2244
2245	/* not possible to xmit on unconfigured port */
2246	if (!s3c24xx_port_configured(ucon))
2247		return;
2248
2249	while (!s3c24xx_serial_console_txrdy(port, ufcon))
2250		cpu_relax();
2251	wr_reg(port, S3C2410_UTXH, c);
2252}
2253
2254#endif /* CONFIG_CONSOLE_POLL */
2255
2256static void
2257s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2258{
2259	u32 ufcon = rd_regl(port, S3C2410_UFCON);
2260
2261	while (!s3c24xx_serial_console_txrdy(port, ufcon))
2262		cpu_relax();
2263	wr_reg(port, S3C2410_UTXH, ch);
2264}
2265
2266static void
2267s3c24xx_serial_console_write(struct console *co, const char *s,
2268			     unsigned int count)
2269{
2270	u32 ucon = rd_regl(cons_uart, S3C2410_UCON);
2271	unsigned long flags;
2272	bool locked = true;
2273
2274	/* not possible to xmit on unconfigured port */
2275	if (!s3c24xx_port_configured(ucon))
2276		return;
2277
2278	if (cons_uart->sysrq)
2279		locked = false;
2280	else if (oops_in_progress)
2281		locked = uart_port_trylock_irqsave(cons_uart, &flags);
2282	else
2283		uart_port_lock_irqsave(cons_uart, &flags);
2284
2285	uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2286
2287	if (locked)
2288		uart_port_unlock_irqrestore(cons_uart, flags);
2289}
2290
2291/* Shouldn't be __init, as it can be instantiated from other module */
2292static void
2293s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2294			   int *parity, int *bits)
2295{
2296	struct clk *clk;
2297	unsigned long rate;
2298	u32 ulcon, ucon, ubrdiv;
2299	char clk_name[MAX_CLK_NAME_LENGTH];
2300	u8 clk_sel;
2301
2302	ulcon  = rd_regl(port, S3C2410_ULCON);
2303	ucon   = rd_regl(port, S3C2410_UCON);
2304	ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2305
2306	if (s3c24xx_port_configured(ucon)) {
2307		switch (ulcon & S3C2410_LCON_CSMASK) {
2308		case S3C2410_LCON_CS5:
2309			*bits = 5;
2310			break;
2311		case S3C2410_LCON_CS6:
2312			*bits = 6;
2313			break;
2314		case S3C2410_LCON_CS7:
2315			*bits = 7;
2316			break;
2317		case S3C2410_LCON_CS8:
2318		default:
2319			*bits = 8;
2320			break;
2321		}
2322
2323		switch (ulcon & S3C2410_LCON_PMASK) {
2324		case S3C2410_LCON_PEVEN:
2325			*parity = 'e';
2326			break;
2327
2328		case S3C2410_LCON_PODD:
2329			*parity = 'o';
2330			break;
2331
2332		case S3C2410_LCON_PNONE:
2333		default:
2334			*parity = 'n';
2335		}
2336
2337		/* now calculate the baud rate */
2338
2339		clk_sel = s3c24xx_serial_getsource(port);
2340		sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2341
2342		clk = clk_get(port->dev, clk_name);
2343		if (!IS_ERR(clk))
2344			rate = clk_get_rate(clk);
2345		else
2346			rate = 1;
2347
2348		*baud = rate / (16 * (ubrdiv + 1));
2349		dev_dbg(port->dev, "calculated baud %d\n", *baud);
2350	}
2351}
2352
2353/* Shouldn't be __init, as it can be instantiated from other module */
2354static int
2355s3c24xx_serial_console_setup(struct console *co, char *options)
2356{
2357	struct uart_port *port;
2358	int baud = 9600;
2359	int bits = 8;
2360	int parity = 'n';
2361	int flow = 'n';
2362
2363	/* is this a valid port */
2364
2365	if (co->index == -1 || co->index >= UART_NR)
2366		co->index = 0;
2367
2368	port = &s3c24xx_serial_ports[co->index].port;
2369
2370	/* is the port configured? */
2371
2372	if (port->mapbase == 0x0)
2373		return -ENODEV;
2374
2375	cons_uart = port;
2376
2377	/*
2378	 * Check whether an invalid uart number has been specified, and
2379	 * if so, search for the first available port that does have
2380	 * console support.
2381	 */
2382	if (options)
2383		uart_parse_options(options, &baud, &parity, &bits, &flow);
2384	else
2385		s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2386
2387	dev_dbg(port->dev, "baud %d\n", baud);
2388
2389	return uart_set_options(port, co, baud, parity, bits, flow);
2390}
2391
2392static struct console s3c24xx_serial_console = {
2393	.name		= S3C24XX_SERIAL_NAME,
2394	.device		= uart_console_device,
2395	.flags		= CON_PRINTBUFFER,
2396	.index		= -1,
2397	.write		= s3c24xx_serial_console_write,
2398	.setup		= s3c24xx_serial_console_setup,
2399	.data		= &s3c24xx_uart_drv,
2400};
2401#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2402
2403#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2404static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2405	.info = {
2406		.name		= "Samsung S3C6400 UART",
2407		.type		= TYPE_S3C6400,
2408		.port_type	= PORT_S3C6400,
2409		.iotype		= UPIO_MEM,
2410		.fifosize	= 64,
2411		.has_divslot	= true,
2412		.rx_fifomask	= S3C2440_UFSTAT_RXMASK,
2413		.rx_fifoshift	= S3C2440_UFSTAT_RXSHIFT,
2414		.rx_fifofull	= S3C2440_UFSTAT_RXFULL,
2415		.tx_fifofull	= S3C2440_UFSTAT_TXFULL,
2416		.tx_fifomask	= S3C2440_UFSTAT_TXMASK,
2417		.tx_fifoshift	= S3C2440_UFSTAT_TXSHIFT,
2418		.def_clk_sel	= S3C2410_UCON_CLKSEL2,
2419		.num_clks	= 4,
2420		.clksel_mask	= S3C6400_UCON_CLKMASK,
2421		.clksel_shift	= S3C6400_UCON_CLKSHIFT,
2422	},
2423	.def_cfg = {
2424		.ucon		= S3C2410_UCON_DEFAULT,
2425		.ufcon		= S3C2410_UFCON_DEFAULT,
2426	},
2427};
2428#define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2429#else
2430#define S3C6400_SERIAL_DRV_DATA NULL
2431#endif
2432
2433#ifdef CONFIG_CPU_S5PV210
2434static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2435	.info = {
2436		.name		= "Samsung S5PV210 UART",
2437		.type		= TYPE_S3C6400,
2438		.port_type	= PORT_S3C6400,
2439		.iotype		= UPIO_MEM,
2440		.has_divslot	= true,
2441		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,
2442		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,
2443		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,
2444		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,
2445		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,
2446		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,
2447		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2448		.num_clks	= 2,
2449		.clksel_mask	= S5PV210_UCON_CLKMASK,
2450		.clksel_shift	= S5PV210_UCON_CLKSHIFT,
2451	},
2452	.def_cfg = {
2453		.ucon		= S5PV210_UCON_DEFAULT,
2454		.ufcon		= S5PV210_UFCON_DEFAULT,
2455	},
2456	.fifosize = { 256, 64, 16, 16 },
2457};
2458#define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2459#else
2460#define S5PV210_SERIAL_DRV_DATA	NULL
2461#endif
2462
2463#if defined(CONFIG_ARCH_EXYNOS)
2464#define EXYNOS_COMMON_SERIAL_DRV_DATA				\
2465	.info = {						\
2466		.name		= "Samsung Exynos UART",	\
2467		.type		= TYPE_S3C6400,			\
2468		.port_type	= PORT_S3C6400,			\
2469		.iotype		= UPIO_MEM,			\
2470		.has_divslot	= true,				\
2471		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,	\
2472		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,	\
2473		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,	\
2474		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,	\
2475		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,	\
2476		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,	\
2477		.def_clk_sel	= S3C2410_UCON_CLKSEL0,		\
2478		.num_clks	= 1,				\
2479		.clksel_mask	= 0,				\
2480		.clksel_shift	= 0,				\
2481	},							\
2482	.def_cfg = {						\
2483		.ucon		= S5PV210_UCON_DEFAULT,		\
2484		.ufcon		= S5PV210_UFCON_DEFAULT,	\
2485		.has_fracval	= 1,				\
2486	}							\
2487
2488static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2489	EXYNOS_COMMON_SERIAL_DRV_DATA,
2490	.fifosize = { 256, 64, 16, 16 },
2491};
2492
2493static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2494	EXYNOS_COMMON_SERIAL_DRV_DATA,
2495	.fifosize = { 64, 256, 16, 256 },
2496};
2497
2498static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2499	EXYNOS_COMMON_SERIAL_DRV_DATA,
2500	.fifosize = { 256, 64, 64, 64 },
2501};
2502
2503static const struct s3c24xx_serial_drv_data exynos8895_serial_drv_data = {
2504	EXYNOS_COMMON_SERIAL_DRV_DATA,
2505	/* samsung,uart-fifosize must be specified in the device tree. */
2506	.fifosize = { 0 },
2507};
2508
2509static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
2510	.info = {
2511		.name		= "Google GS101 UART",
2512		.type		= TYPE_S3C6400,
2513		.port_type	= PORT_S3C6400,
2514		.iotype		= UPIO_MEM32,
2515		.has_divslot	= true,
2516		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,
2517		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,
2518		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,
2519		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,
2520		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,
2521		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,
2522		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2523		.num_clks	= 1,
2524		.clksel_mask	= 0,
2525		.clksel_shift	= 0,
2526	},
2527	.def_cfg = {
2528		.ucon		= S5PV210_UCON_DEFAULT,
2529		.ufcon		= S5PV210_UFCON_DEFAULT,
2530		.has_fracval	= 1,
2531	},
2532	/* samsung,uart-fifosize must be specified in the device tree. */
2533	.fifosize = { 0 },
2534};
2535
2536#define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2537#define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2538#define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2539#define EXYNOS8895_SERIAL_DRV_DATA (&exynos8895_serial_drv_data)
2540#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
2541
2542#else
2543#define EXYNOS4210_SERIAL_DRV_DATA NULL
2544#define EXYNOS5433_SERIAL_DRV_DATA NULL
2545#define EXYNOS850_SERIAL_DRV_DATA NULL
2546#define EXYNOS8895_SERIAL_DRV_DATA NULL
2547#define GS101_SERIAL_DRV_DATA NULL
2548#endif
2549
2550#ifdef CONFIG_ARCH_APPLE
2551static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2552	.info = {
2553		.name		= "Apple S5L UART",
2554		.type		= TYPE_APPLE_S5L,
2555		.port_type	= PORT_8250,
2556		.iotype		= UPIO_MEM32,
2557		.fifosize	= 16,
2558		.rx_fifomask	= S3C2410_UFSTAT_RXMASK,
2559		.rx_fifoshift	= S3C2410_UFSTAT_RXSHIFT,
2560		.rx_fifofull	= S3C2410_UFSTAT_RXFULL,
2561		.tx_fifofull	= S3C2410_UFSTAT_TXFULL,
2562		.tx_fifomask	= S3C2410_UFSTAT_TXMASK,
2563		.tx_fifoshift	= S3C2410_UFSTAT_TXSHIFT,
2564		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2565		.num_clks	= 1,
2566		.clksel_mask	= 0,
2567		.clksel_shift	= 0,
2568		.ucon_mask	= APPLE_S5L_UCON_MASK,
2569	},
2570	.def_cfg = {
2571		.ucon		= APPLE_S5L_UCON_DEFAULT,
2572		.ufcon		= S3C2410_UFCON_DEFAULT,
2573	},
2574};
2575#define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2576#else
2577#define S5L_SERIAL_DRV_DATA NULL
2578#endif
2579
2580#if defined(CONFIG_ARCH_ARTPEC)
2581static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2582	.info = {
2583		.name		= "Axis ARTPEC-8 UART",
2584		.type		= TYPE_S3C6400,
2585		.port_type	= PORT_S3C6400,
2586		.iotype		= UPIO_MEM,
2587		.fifosize	= 64,
2588		.has_divslot	= true,
2589		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,
2590		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,
2591		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,
2592		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,
2593		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,
2594		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,
2595		.def_clk_sel	= S3C2410_UCON_CLKSEL0,
2596		.num_clks	= 1,
2597		.clksel_mask	= 0,
2598		.clksel_shift	= 0,
2599	},
2600	.def_cfg = {
2601		.ucon		= S5PV210_UCON_DEFAULT,
2602		.ufcon		= S5PV210_UFCON_DEFAULT,
2603		.has_fracval	= 1,
2604	}
2605};
2606#define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2607#else
2608#define ARTPEC8_SERIAL_DRV_DATA (NULL)
2609#endif
2610
2611static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2612	{
2613		.name		= "s3c6400-uart",
2614		.driver_data	= (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2615	}, {
2616		.name		= "s5pv210-uart",
2617		.driver_data	= (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2618	}, {
2619		.name		= "exynos4210-uart",
2620		.driver_data	= (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2621	}, {
2622		.name		= "exynos5433-uart",
2623		.driver_data	= (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2624	}, {
2625		.name		= "s5l-uart",
2626		.driver_data	= (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2627	}, {
2628		.name		= "exynos850-uart",
2629		.driver_data	= (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2630	}, {
2631		.name		= "artpec8-uart",
2632		.driver_data	= (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2633	}, {
2634		.name		= "gs101-uart",
2635		.driver_data	= (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
2636	}, {
2637		.name		= "exynos8895-uart",
2638		.driver_data	= (kernel_ulong_t)EXYNOS8895_SERIAL_DRV_DATA,
2639	},
2640	{ },
2641};
2642MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2643
2644#ifdef CONFIG_OF
2645static const struct of_device_id s3c24xx_uart_dt_match[] = {
2646	{ .compatible = "samsung,s3c6400-uart",
2647		.data = S3C6400_SERIAL_DRV_DATA },
2648	{ .compatible = "samsung,s5pv210-uart",
2649		.data = S5PV210_SERIAL_DRV_DATA },
2650	{ .compatible = "samsung,exynos4210-uart",
2651		.data = EXYNOS4210_SERIAL_DRV_DATA },
2652	{ .compatible = "samsung,exynos5433-uart",
2653		.data = EXYNOS5433_SERIAL_DRV_DATA },
2654	{ .compatible = "apple,s5l-uart",
2655		.data = S5L_SERIAL_DRV_DATA },
2656	{ .compatible = "samsung,exynos850-uart",
2657		.data = EXYNOS850_SERIAL_DRV_DATA },
2658	{ .compatible = "axis,artpec8-uart",
2659		.data = ARTPEC8_SERIAL_DRV_DATA },
2660	{ .compatible = "google,gs101-uart",
2661		.data = GS101_SERIAL_DRV_DATA },
2662	{ .compatible = "samsung,exynos8895-uart",
2663		.data = EXYNOS8895_SERIAL_DRV_DATA },
2664	{},
2665};
2666MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2667#endif
2668
2669static struct platform_driver samsung_serial_driver = {
2670	.probe		= s3c24xx_serial_probe,
2671	.remove		= s3c24xx_serial_remove,
2672	.id_table	= s3c24xx_serial_driver_ids,
2673	.driver		= {
2674		.name	= "samsung-uart",
2675		.pm	= SERIAL_SAMSUNG_PM_OPS,
2676		.of_match_table	= of_match_ptr(s3c24xx_uart_dt_match),
2677	},
2678};
2679
2680static int __init samsung_serial_init(void)
2681{
2682	int ret;
2683
2684	s3c24xx_serial_register_console();
2685
2686	ret = platform_driver_register(&samsung_serial_driver);
2687	if (ret) {
2688		s3c24xx_serial_unregister_console();
2689		return ret;
2690	}
2691
2692	return 0;
2693}
2694
2695static void __exit samsung_serial_exit(void)
2696{
2697	platform_driver_unregister(&samsung_serial_driver);
2698	s3c24xx_serial_unregister_console();
2699}
2700
2701module_init(samsung_serial_init);
2702module_exit(samsung_serial_exit);
2703
2704#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2705/*
2706 * Early console.
2707 */
2708
2709static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2710{
2711	switch (port->iotype) {
2712	case UPIO_MEM:
2713		writeb(val, portaddr(port, reg));
2714		break;
2715	case UPIO_MEM32:
2716		writel(val, portaddr(port, reg));
2717		break;
2718	default:
2719		break;
2720	}
2721}
2722
2723struct samsung_early_console_data {
2724	u32 txfull_mask;
2725	u32 rxfifo_mask;
2726};
2727
2728static void samsung_early_busyuart(const struct uart_port *port)
2729{
2730	while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2731		;
2732}
2733
2734static void samsung_early_busyuart_fifo(const struct uart_port *port)
2735{
2736	const struct samsung_early_console_data *data = port->private_data;
2737
2738	while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2739		;
2740}
2741
2742static void samsung_early_putc(struct uart_port *port, unsigned char c)
2743{
2744	if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2745		samsung_early_busyuart_fifo(port);
2746	else
2747		samsung_early_busyuart(port);
2748
2749	wr_reg_barrier(port, S3C2410_UTXH, c);
2750}
2751
2752static void samsung_early_write(struct console *con, const char *s,
2753				unsigned int n)
2754{
2755	struct earlycon_device *dev = con->data;
2756
2757	uart_console_write(&dev->port, s, n, samsung_early_putc);
2758}
2759
2760static int samsung_early_read(struct console *con, char *s, unsigned int n)
2761{
2762	struct earlycon_device *dev = con->data;
2763	const struct samsung_early_console_data *data = dev->port.private_data;
2764	int num_read = 0;
2765	u32 ch, ufstat;
2766
2767	while (num_read < n) {
2768		ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2769		if (!(ufstat & data->rxfifo_mask))
2770			break;
2771		ch = rd_reg(&dev->port, S3C2410_URXH);
2772		if (ch == NO_POLL_CHAR)
2773			break;
2774
2775		s[num_read++] = ch;
2776	}
2777
2778	return num_read;
2779}
2780
2781static int __init samsung_early_console_setup(struct earlycon_device *device,
2782					      const char *opt)
2783{
2784	if (!device->port.membase)
2785		return -ENODEV;
2786
2787	device->con->write = samsung_early_write;
2788	device->con->read = samsung_early_read;
2789	return 0;
2790}
2791
2792/* S3C2410 */
2793static struct samsung_early_console_data s3c2410_early_console_data = {
2794	.txfull_mask = S3C2410_UFSTAT_TXFULL,
2795	.rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2796};
2797
2798/* S3C64xx */
2799static struct samsung_early_console_data s3c2440_early_console_data = {
2800	.txfull_mask = S3C2440_UFSTAT_TXFULL,
2801	.rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2802};
2803
2804static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2805					      const char *opt)
2806{
2807	device->port.private_data = &s3c2440_early_console_data;
2808	return samsung_early_console_setup(device, opt);
2809}
2810
2811OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2812			s3c2440_early_console_setup);
2813
2814/* S5PV210, Exynos */
2815static struct samsung_early_console_data s5pv210_early_console_data = {
2816	.txfull_mask = S5PV210_UFSTAT_TXFULL,
2817	.rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2818};
2819
2820static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2821					      const char *opt)
2822{
2823	device->port.private_data = &s5pv210_early_console_data;
2824	return samsung_early_console_setup(device, opt);
2825}
2826
2827OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2828			s5pv210_early_console_setup);
2829OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2830			s5pv210_early_console_setup);
2831OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2832			s5pv210_early_console_setup);
2833OF_EARLYCON_DECLARE(exynos850, "samsung,exynos850-uart",
2834			s5pv210_early_console_setup);
2835
2836static int __init gs101_early_console_setup(struct earlycon_device *device,
2837					    const char *opt)
2838{
2839	/* gs101 always expects MMIO32 register accesses. */
2840	device->port.iotype = UPIO_MEM32;
2841
2842	return s5pv210_early_console_setup(device, opt);
2843}
2844
2845OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup);
2846
2847/* Apple S5L */
2848static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2849						const char *opt)
2850{
2851	/* Apple A7-A11 requires MMIO32 register accesses. */
2852	device->port.iotype = UPIO_MEM32;
2853
2854	/* Close enough to S3C2410 for earlycon... */
2855	device->port.private_data = &s3c2410_early_console_data;
2856
2857#ifdef CONFIG_ARM64
2858	/* ... but we need to override the existing fixmap entry as nGnRnE */
2859	__set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2860		     __pgprot(PROT_DEVICE_nGnRnE));
2861#endif
2862	return samsung_early_console_setup(device, opt);
2863}
2864
2865OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2866#endif
2867
2868MODULE_ALIAS("platform:samsung-uart");
2869MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2870MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2871MODULE_LICENSE("GPL v2");