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jsm_neo.c
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linux-6.19.14/drivers/tty/serial/jsm/jsm_neo.c
1// SPDX-License-Identifier: GPL-2.0+ 2/************************************************************************ 3 * Copyright 2003 Digi International (www.digi.com) 4 * 5 * Copyright (C) 2004 IBM Corporation. All rights reserved. 6 * 7 * Contact Information: 8 * Scott H Kilau <Scott_Kilau@digi.com> 9 * Wendy Xiong <wendyx@us.ibm.com> 10 * 11 ***********************************************************************/ 12#include <linux/delay.h> /* For udelay */ 13#include <linux/serial_reg.h> /* For the various UART offsets */ 14#include <linux/tty.h> 15#include <linux/pci.h> 16#include <asm/io.h> 17 18#include "jsm.h" /* Driver main header file */ 19 20static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 21 22/* 23 * This function allows calls to ensure that all outstanding 24 * PCI writes have been completed, by doing a PCI read against 25 * a non-destructive, read-only location on the Neo card. 26 * 27 * In this case, we are reading the DVID (Read-only Device Identification) 28 * value of the Neo card. 29 */ 30static inline void neo_pci_posting_flush(struct jsm_board *bd) 31{ 32 readb(bd->re_map_membase + 0x8D); 33} 34 35static void neo_set_cts_flow_control(struct jsm_channel *ch) 36{ 37 u8 ier, efr; 38 ier = readb(&ch->ch_neo_uart->ier); 39 efr = readb(&ch->ch_neo_uart->efr); 40 41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); 42 43 /* Turn on auto CTS flow control */ 44 ier |= (UART_17158_IER_CTSDSR); 45 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 46 47 /* Turn off auto Xon flow control */ 48 efr &= ~(UART_17158_EFR_IXON); 49 50 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 51 writeb(0, &ch->ch_neo_uart->efr); 52 53 /* Turn on UART enhanced bits */ 54 writeb(efr, &ch->ch_neo_uart->efr); 55 56 /* Turn on table D, with 8 char hi/low watermarks */ 57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 58 59 /* Feed the UART our trigger levels */ 60 writeb(8, &ch->ch_neo_uart->tfifo); 61 ch->ch_t_tlevel = 8; 62 63 writeb(ier, &ch->ch_neo_uart->ier); 64} 65 66static void neo_set_rts_flow_control(struct jsm_channel *ch) 67{ 68 u8 ier, efr; 69 ier = readb(&ch->ch_neo_uart->ier); 70 efr = readb(&ch->ch_neo_uart->efr); 71 72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); 73 74 /* Turn on auto RTS flow control */ 75 ier |= (UART_17158_IER_RTSDTR); 76 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 77 78 /* Turn off auto Xoff flow control */ 79 ier &= ~(UART_17158_IER_XOFF); 80 efr &= ~(UART_17158_EFR_IXOFF); 81 82 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 83 writeb(0, &ch->ch_neo_uart->efr); 84 85 /* Turn on UART enhanced bits */ 86 writeb(efr, &ch->ch_neo_uart->efr); 87 88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 89 ch->ch_r_watermark = 4; 90 91 writeb(56, &ch->ch_neo_uart->rfifo); 92 ch->ch_r_tlevel = 56; 93 94 writeb(ier, &ch->ch_neo_uart->ier); 95 96 /* 97 * From the Neo UART spec sheet: 98 * The auto RTS/DTR function must be started by asserting 99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 100 * it is enabled. 101 */ 102 ch->ch_mostat |= (UART_MCR_RTS); 103} 104 105 106static void neo_set_ixon_flow_control(struct jsm_channel *ch) 107{ 108 u8 ier, efr; 109 ier = readb(&ch->ch_neo_uart->ier); 110 efr = readb(&ch->ch_neo_uart->efr); 111 112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); 113 114 /* Turn off auto CTS flow control */ 115 ier &= ~(UART_17158_IER_CTSDSR); 116 efr &= ~(UART_17158_EFR_CTSDSR); 117 118 /* Turn on auto Xon flow control */ 119 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 120 121 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 122 writeb(0, &ch->ch_neo_uart->efr); 123 124 /* Turn on UART enhanced bits */ 125 writeb(efr, &ch->ch_neo_uart->efr); 126 127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 128 ch->ch_r_watermark = 4; 129 130 writeb(32, &ch->ch_neo_uart->rfifo); 131 ch->ch_r_tlevel = 32; 132 133 /* Tell UART what start/stop chars it should be looking for */ 134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 135 writeb(0, &ch->ch_neo_uart->xonchar2); 136 137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 138 writeb(0, &ch->ch_neo_uart->xoffchar2); 139 140 writeb(ier, &ch->ch_neo_uart->ier); 141} 142 143static void neo_set_ixoff_flow_control(struct jsm_channel *ch) 144{ 145 u8 ier, efr; 146 ier = readb(&ch->ch_neo_uart->ier); 147 efr = readb(&ch->ch_neo_uart->efr); 148 149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); 150 151 /* Turn off auto RTS flow control */ 152 ier &= ~(UART_17158_IER_RTSDTR); 153 efr &= ~(UART_17158_EFR_RTSDTR); 154 155 /* Turn on auto Xoff flow control */ 156 ier |= (UART_17158_IER_XOFF); 157 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 158 159 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 160 writeb(0, &ch->ch_neo_uart->efr); 161 162 /* Turn on UART enhanced bits */ 163 writeb(efr, &ch->ch_neo_uart->efr); 164 165 /* Turn on table D, with 8 char hi/low watermarks */ 166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 167 168 writeb(8, &ch->ch_neo_uart->tfifo); 169 ch->ch_t_tlevel = 8; 170 171 /* Tell UART what start/stop chars it should be looking for */ 172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 173 writeb(0, &ch->ch_neo_uart->xonchar2); 174 175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 176 writeb(0, &ch->ch_neo_uart->xoffchar2); 177 178 writeb(ier, &ch->ch_neo_uart->ier); 179} 180 181static void neo_set_no_input_flow_control(struct jsm_channel *ch) 182{ 183 u8 ier, efr; 184 ier = readb(&ch->ch_neo_uart->ier); 185 efr = readb(&ch->ch_neo_uart->efr); 186 187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); 188 189 /* Turn off auto RTS flow control */ 190 ier &= ~(UART_17158_IER_RTSDTR); 191 efr &= ~(UART_17158_EFR_RTSDTR); 192 193 /* Turn off auto Xoff flow control */ 194 ier &= ~(UART_17158_IER_XOFF); 195 if (ch->ch_c_iflag & IXON) 196 efr &= ~(UART_17158_EFR_IXOFF); 197 else 198 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 199 200 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 201 writeb(0, &ch->ch_neo_uart->efr); 202 203 /* Turn on UART enhanced bits */ 204 writeb(efr, &ch->ch_neo_uart->efr); 205 206 /* Turn on table D, with 8 char hi/low watermarks */ 207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 208 209 ch->ch_r_watermark = 0; 210 211 writeb(16, &ch->ch_neo_uart->tfifo); 212 ch->ch_t_tlevel = 16; 213 214 writeb(16, &ch->ch_neo_uart->rfifo); 215 ch->ch_r_tlevel = 16; 216 217 writeb(ier, &ch->ch_neo_uart->ier); 218} 219 220static void neo_set_no_output_flow_control(struct jsm_channel *ch) 221{ 222 u8 ier, efr; 223 ier = readb(&ch->ch_neo_uart->ier); 224 efr = readb(&ch->ch_neo_uart->efr); 225 226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); 227 228 /* Turn off auto CTS flow control */ 229 ier &= ~(UART_17158_IER_CTSDSR); 230 efr &= ~(UART_17158_EFR_CTSDSR); 231 232 /* Turn off auto Xon flow control */ 233 if (ch->ch_c_iflag & IXOFF) 234 efr &= ~(UART_17158_EFR_IXON); 235 else 236 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 237 238 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 239 writeb(0, &ch->ch_neo_uart->efr); 240 241 /* Turn on UART enhanced bits */ 242 writeb(efr, &ch->ch_neo_uart->efr); 243 244 /* Turn on table D, with 8 char hi/low watermarks */ 245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 246 247 ch->ch_r_watermark = 0; 248 249 writeb(16, &ch->ch_neo_uart->tfifo); 250 ch->ch_t_tlevel = 16; 251 252 writeb(16, &ch->ch_neo_uart->rfifo); 253 ch->ch_r_tlevel = 16; 254 255 writeb(ier, &ch->ch_neo_uart->ier); 256} 257 258static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch) 259{ 260 261 /* if hardware flow control is set, then skip this whole thing */ 262 if (ch->ch_c_cflag & CRTSCTS) 263 return; 264 265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); 266 267 /* Tell UART what start/stop chars it should be looking for */ 268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 269 writeb(0, &ch->ch_neo_uart->xonchar2); 270 271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 272 writeb(0, &ch->ch_neo_uart->xoffchar2); 273} 274 275static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch) 276{ 277 int qleft = 0; 278 u8 linestatus = 0; 279 u8 error_mask = 0; 280 int n = 0; 281 int total = 0; 282 u16 head; 283 u16 tail; 284 285 /* cache head and tail of queue */ 286 head = ch->ch_r_head & RQUEUEMASK; 287 tail = ch->ch_r_tail & RQUEUEMASK; 288 289 /* Get our cached LSR */ 290 linestatus = ch->ch_cached_lsr; 291 ch->ch_cached_lsr = 0; 292 293 /* Store how much space we have left in the queue */ 294 qleft = tail - head - 1; 295 if (qleft < 0) 296 qleft += RQUEUEMASK + 1; 297 298 /* 299 * If the UART is not in FIFO mode, force the FIFO copy to 300 * NOT be run, by setting total to 0. 301 * 302 * On the other hand, if the UART IS in FIFO mode, then ask 303 * the UART to give us an approximation of data it has RX'ed. 304 */ 305 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 306 total = 0; 307 else { 308 total = readb(&ch->ch_neo_uart->rfifo); 309 310 /* 311 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 312 * 313 * This resolves a problem/bug with the Exar chip that sometimes 314 * returns a bogus value in the rfifo register. 315 * The count can be any where from 0-3 bytes "off". 316 * Bizarre, but true. 317 */ 318 total -= 3; 319 } 320 321 /* 322 * Finally, bound the copy to make sure we don't overflow 323 * our own queue... 324 * The byte by byte copy loop below this loop this will 325 * deal with the queue overflow possibility. 326 */ 327 total = min(total, qleft); 328 329 while (total > 0) { 330 /* 331 * Grab the linestatus register, we need to check 332 * to see if there are any errors in the FIFO. 333 */ 334 linestatus = readb(&ch->ch_neo_uart->lsr); 335 336 /* 337 * Break out if there is a FIFO error somewhere. 338 * This will allow us to go byte by byte down below, 339 * finding the exact location of the error. 340 */ 341 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 342 break; 343 344 /* Make sure we don't go over the end of our queue */ 345 n = min(((u32) total), (RQUEUESIZE - (u32) head)); 346 347 /* 348 * Cut down n even further if needed, this is to fix 349 * a problem with memcpy_fromio() with the Neo on the 350 * IBM pSeries platform. 351 * 15 bytes max appears to be the magic number. 352 */ 353 n = min((u32) n, (u32) 12); 354 355 /* 356 * Since we are grabbing the linestatus register, which 357 * will reset some bits after our read, we need to ensure 358 * we don't miss our TX FIFO emptys. 359 */ 360 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 361 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 362 363 linestatus = 0; 364 365 /* Copy data from uart to the queue */ 366 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 367 /* 368 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed 369 * that all the data currently in the FIFO is free of 370 * breaks and parity/frame/orun errors. 371 */ 372 memset(ch->ch_equeue + head, 0, n); 373 374 /* Add to and flip head if needed */ 375 head = (head + n) & RQUEUEMASK; 376 total -= n; 377 qleft -= n; 378 ch->ch_rxcount += n; 379 } 380 381 /* 382 * Create a mask to determine whether we should 383 * insert the character (if any) into our queue. 384 */ 385 if (ch->ch_c_iflag & IGNBRK) 386 error_mask |= UART_LSR_BI; 387 388 /* 389 * Now cleanup any leftover bytes still in the UART. 390 * Also deal with any possible queue overflow here as well. 391 */ 392 while (1) { 393 394 /* 395 * Its possible we have a linestatus from the loop above 396 * this, so we "OR" on any extra bits. 397 */ 398 linestatus |= readb(&ch->ch_neo_uart->lsr); 399 400 /* 401 * If the chip tells us there is no more data pending to 402 * be read, we can then leave. 403 * But before we do, cache the linestatus, just in case. 404 */ 405 if (!(linestatus & UART_LSR_DR)) { 406 ch->ch_cached_lsr = linestatus; 407 break; 408 } 409 410 /* No need to store this bit */ 411 linestatus &= ~UART_LSR_DR; 412 413 /* 414 * Since we are grabbing the linestatus register, which 415 * will reset some bits after our read, we need to ensure 416 * we don't miss our TX FIFO emptys. 417 */ 418 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 419 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 420 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 421 } 422 423 /* 424 * Discard character if we are ignoring the error mask. 425 */ 426 if (linestatus & error_mask) { 427 u8 discard; 428 linestatus = 0; 429 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 430 continue; 431 } 432 433 /* 434 * If our queue is full, we have no choice but to drop some data. 435 * The assumption is that HWFLOW or SWFLOW should have stopped 436 * things way way before we got to this point. 437 * 438 * I decided that I wanted to ditch the oldest data first, 439 * I hope thats okay with everyone? Yes? Good. 440 */ 441 while (qleft < 1) { 442 jsm_dbg(READ, &ch->ch_bd->pci_dev, 443 "Queue full, dropping DATA:%x LSR:%x\n", 444 ch->ch_rqueue[tail], ch->ch_equeue[tail]); 445 446 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; 447 ch->ch_err_overrun++; 448 qleft++; 449 } 450 451 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 452 ch->ch_equeue[head] = (u8) linestatus; 453 454 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", 455 ch->ch_rqueue[head], ch->ch_equeue[head]); 456 457 /* Ditch any remaining linestatus value. */ 458 linestatus = 0; 459 460 /* Add to and flip head if needed */ 461 head = (head + 1) & RQUEUEMASK; 462 463 qleft--; 464 ch->ch_rxcount++; 465 } 466 467 /* 468 * Write new final heads to channel structure. 469 */ 470 ch->ch_r_head = head & RQUEUEMASK; 471 ch->ch_e_head = head & EQUEUEMASK; 472 jsm_input(ch); 473} 474 475static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch) 476{ 477 struct tty_port *tport; 478 unsigned char *tail; 479 unsigned char c; 480 int n; 481 int s; 482 int qlen; 483 u32 len_written = 0; 484 485 if (!ch) 486 return; 487 488 tport = &ch->uart_port.state->port; 489 490 /* No data to write to the UART */ 491 if (kfifo_is_empty(&tport->xmit_fifo)) 492 return; 493 494 /* If port is "stopped", don't send any data to the UART */ 495 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) 496 return; 497 /* 498 * If FIFOs are disabled. Send data directly to txrx register 499 */ 500 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 501 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); 502 503 ch->ch_cached_lsr |= lsrbits; 504 if (ch->ch_cached_lsr & UART_LSR_THRE) { 505 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 506 507 WARN_ON_ONCE(!kfifo_get(&tport->xmit_fifo, &c)); 508 writeb(c, &ch->ch_neo_uart->txrx); 509 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, "Tx data: %x\n", c); 510 ch->ch_txcount++; 511 } 512 return; 513 } 514 515 /* 516 * We have to do it this way, because of the EXAR TXFIFO count bug. 517 */ 518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) 519 return; 520 521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 522 qlen = kfifo_len(&tport->xmit_fifo); 523 524 /* Find minimum of the FIFO space, versus queue length */ 525 n = min(n, qlen); 526 527 while (n > 0) { 528 s = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, n); 529 if (s <= 0) 530 break; 531 532 memcpy_toio(&ch->ch_neo_uart->txrxburst, tail, s); 533 kfifo_skip_count(&tport->xmit_fifo, s); 534 n -= s; 535 ch->ch_txcount += s; 536 len_written += s; 537 } 538 539 if (len_written >= ch->ch_t_tlevel) 540 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 541 542 if (kfifo_is_empty(&tport->xmit_fifo)) 543 uart_write_wakeup(&ch->uart_port); 544} 545 546static void neo_parse_modem(struct jsm_channel *ch, u8 signals) 547{ 548 u8 msignals = signals; 549 550 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 551 "neo_parse_modem: port: %d msignals: %x\n", 552 ch->ch_portnum, msignals); 553 554 /* Scrub off lower bits. They signify delta's, which I don't care about */ 555 /* Keep DDCD and DDSR though */ 556 msignals &= 0xf8; 557 558 if (msignals & UART_MSR_DDCD) 559 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); 560 if (msignals & UART_MSR_DDSR) 561 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); 562 if (msignals & UART_MSR_DCD) 563 ch->ch_mistat |= UART_MSR_DCD; 564 else 565 ch->ch_mistat &= ~UART_MSR_DCD; 566 567 if (msignals & UART_MSR_DSR) 568 ch->ch_mistat |= UART_MSR_DSR; 569 else 570 ch->ch_mistat &= ~UART_MSR_DSR; 571 572 if (msignals & UART_MSR_RI) 573 ch->ch_mistat |= UART_MSR_RI; 574 else 575 ch->ch_mistat &= ~UART_MSR_RI; 576 577 if (msignals & UART_MSR_CTS) 578 ch->ch_mistat |= UART_MSR_CTS; 579 else 580 ch->ch_mistat &= ~UART_MSR_CTS; 581 582 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, 583 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n", 584 ch->ch_portnum, 585 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), 586 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), 587 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), 588 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), 589 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), 590 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); 591} 592 593/* Make the UART raise any of the output signals we want up */ 594static void neo_assert_modem_signals(struct jsm_channel *ch) 595{ 596 if (!ch) 597 return; 598 599 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 600 601 /* flush write operation */ 602 neo_pci_posting_flush(ch->ch_bd); 603} 604 605/* 606 * Flush the WRITE FIFO on the Neo. 607 * 608 * NOTE: Channel lock MUST be held before calling this function! 609 */ 610static void neo_flush_uart_write(struct jsm_channel *ch) 611{ 612 u8 tmp = 0; 613 int i = 0; 614 615 if (!ch) 616 return; 617 618 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 619 620 for (i = 0; i < 10; i++) { 621 622 /* Check to see if the UART feels it completely flushed the FIFO. */ 623 tmp = readb(&ch->ch_neo_uart->isr_fcr); 624 if (tmp & UART_FCR_CLEAR_XMIT) { 625 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 626 "Still flushing TX UART... i: %d\n", i); 627 udelay(10); 628 } 629 else 630 break; 631 } 632 633 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 634} 635 636 637/* 638 * Flush the READ FIFO on the Neo. 639 * 640 * NOTE: Channel lock MUST be held before calling this function! 641 */ 642static void neo_flush_uart_read(struct jsm_channel *ch) 643{ 644 u8 tmp = 0; 645 int i = 0; 646 647 if (!ch) 648 return; 649 650 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 651 652 for (i = 0; i < 10; i++) { 653 654 /* Check to see if the UART feels it completely flushed the FIFO. */ 655 tmp = readb(&ch->ch_neo_uart->isr_fcr); 656 if (tmp & 2) { 657 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 658 "Still flushing RX UART... i: %d\n", i); 659 udelay(10); 660 } 661 else 662 break; 663 } 664} 665 666/* 667 * No locks are assumed to be held when calling this function. 668 */ 669static void neo_clear_break(struct jsm_channel *ch) 670{ 671 unsigned long lock_flags; 672 673 spin_lock_irqsave(&ch->ch_lock, lock_flags); 674 675 /* Turn break off, and unset some variables */ 676 if (ch->ch_flags & CH_BREAK_SENDING) { 677 u8 temp = readb(&ch->ch_neo_uart->lcr); 678 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 679 680 ch->ch_flags &= ~(CH_BREAK_SENDING); 681 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, 682 "clear break Finishing UART_LCR_SBC! finished: %lx\n", 683 jiffies); 684 685 /* flush write operation */ 686 neo_pci_posting_flush(ch->ch_bd); 687 } 688 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 689} 690 691/* 692 * Parse the ISR register. 693 */ 694static void neo_parse_isr(struct jsm_board *brd, u32 port) 695{ 696 struct jsm_channel *ch; 697 u8 isr; 698 u8 cause; 699 unsigned long lock_flags; 700 701 if (!brd) 702 return; 703 704 if (port >= brd->maxports) 705 return; 706 707 ch = brd->channels[port]; 708 if (!ch) 709 return; 710 711 /* Here we try to figure out what caused the interrupt to happen */ 712 while (1) { 713 714 isr = readb(&ch->ch_neo_uart->isr_fcr); 715 716 /* Bail if no pending interrupt */ 717 if (isr & UART_IIR_NO_INT) 718 break; 719 720 /* 721 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 722 */ 723 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 724 725 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", 726 __FILE__, __LINE__, isr); 727 728 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 729 /* Read data from uart -> queue */ 730 neo_copy_data_from_uart_to_queue(ch); 731 732 /* Call our tty layer to enforce queue flow control if needed. */ 733 spin_lock_irqsave(&ch->ch_lock, lock_flags); 734 jsm_check_queue_flow_control(ch); 735 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 736 } 737 738 if (isr & UART_IIR_THRI) { 739 /* Transfer data (if any) from Write Queue -> UART. */ 740 spin_lock_irqsave(&ch->ch_lock, lock_flags); 741 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 742 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 743 neo_copy_data_from_queue_to_uart(ch); 744 } 745 746 if (isr & UART_17158_IIR_XONXOFF) { 747 cause = readb(&ch->ch_neo_uart->xoffchar1); 748 749 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 750 "Port %d. Got ISR_XONXOFF: cause:%x\n", 751 port, cause); 752 753 /* 754 * Since the UART detected either an XON or 755 * XOFF match, we need to figure out which 756 * one it was, so we can suspend or resume data flow. 757 */ 758 spin_lock_irqsave(&ch->ch_lock, lock_flags); 759 if (cause == UART_17158_XON_DETECT) { 760 /* Is output stopped right now, if so, resume it */ 761 if (brd->channels[port]->ch_flags & CH_STOP) { 762 ch->ch_flags &= ~(CH_STOP); 763 } 764 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 765 "Port %d. XON detected in incoming data\n", 766 port); 767 } 768 else if (cause == UART_17158_XOFF_DETECT) { 769 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 770 ch->ch_flags |= CH_STOP; 771 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 772 "Setting CH_STOP\n"); 773 } 774 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 775 "Port: %d. XOFF detected in incoming data\n", 776 port); 777 } 778 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 779 } 780 781 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 782 /* 783 * If we get here, this means the hardware is doing auto flow control. 784 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 785 */ 786 cause = readb(&ch->ch_neo_uart->mcr); 787 788 /* Which pin is doing auto flow? RTS or DTR? */ 789 spin_lock_irqsave(&ch->ch_lock, lock_flags); 790 if ((cause & 0x4) == 0) { 791 if (cause & UART_MCR_RTS) 792 ch->ch_mostat |= UART_MCR_RTS; 793 else 794 ch->ch_mostat &= ~(UART_MCR_RTS); 795 } else { 796 if (cause & UART_MCR_DTR) 797 ch->ch_mostat |= UART_MCR_DTR; 798 else 799 ch->ch_mostat &= ~(UART_MCR_DTR); 800 } 801 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 802 } 803 804 /* Parse any modem signal changes */ 805 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 806 "MOD_STAT: sending to parse_modem_sigs\n"); 807 uart_port_lock_irqsave(&ch->uart_port, &lock_flags); 808 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 809 uart_port_unlock_irqrestore(&ch->uart_port, lock_flags); 810 } 811} 812 813static inline void neo_parse_lsr(struct jsm_board *brd, u32 port) 814{ 815 struct jsm_channel *ch; 816 int linestatus; 817 unsigned long lock_flags; 818 819 if (!brd) 820 return; 821 822 if (port >= brd->maxports) 823 return; 824 825 ch = brd->channels[port]; 826 if (!ch) 827 return; 828 829 linestatus = readb(&ch->ch_neo_uart->lsr); 830 831 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", 832 __FILE__, __LINE__, port, linestatus); 833 834 ch->ch_cached_lsr |= linestatus; 835 836 if (ch->ch_cached_lsr & UART_LSR_DR) { 837 /* Read data from uart -> queue */ 838 neo_copy_data_from_uart_to_queue(ch); 839 spin_lock_irqsave(&ch->ch_lock, lock_flags); 840 jsm_check_queue_flow_control(ch); 841 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 842 } 843 844 /* 845 * This is a special flag. It indicates that at least 1 846 * RX error (parity, framing, or break) has happened. 847 * Mark this in our struct, which will tell me that I have 848 *to do the special RX+LSR read for this FIFO load. 849 */ 850 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 851 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 852 "%s:%d Port: %d Got an RX error, need to parse LSR\n", 853 __FILE__, __LINE__, port); 854 855 /* 856 * The next 3 tests should *NOT* happen, as the above test 857 * should encapsulate all 3... At least, thats what Exar says. 858 */ 859 860 if (linestatus & UART_LSR_PE) { 861 ch->ch_err_parity++; 862 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", 863 __FILE__, __LINE__, port); 864 } 865 866 if (linestatus & UART_LSR_FE) { 867 ch->ch_err_frame++; 868 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", 869 __FILE__, __LINE__, port); 870 } 871 872 if (linestatus & UART_LSR_BI) { 873 ch->ch_err_break++; 874 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 875 "%s:%d Port: %d. BRK INTR!\n", 876 __FILE__, __LINE__, port); 877 } 878 879 if (linestatus & UART_LSR_OE) { 880 /* 881 * Rx Oruns. Exar says that an orun will NOT corrupt 882 * the FIFO. It will just replace the holding register 883 * with this new data byte. So basically just ignore this. 884 * Probably we should eventually have an orun stat in our driver... 885 */ 886 ch->ch_err_overrun++; 887 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 888 "%s:%d Port: %d. Rx Overrun!\n", 889 __FILE__, __LINE__, port); 890 } 891 892 if (linestatus & UART_LSR_THRE) { 893 spin_lock_irqsave(&ch->ch_lock, lock_flags); 894 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 895 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 896 897 /* Transfer data (if any) from Write Queue -> UART. */ 898 neo_copy_data_from_queue_to_uart(ch); 899 } 900 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 901 spin_lock_irqsave(&ch->ch_lock, lock_flags); 902 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 903 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); 904 905 /* Transfer data (if any) from Write Queue -> UART. */ 906 neo_copy_data_from_queue_to_uart(ch); 907 } 908} 909 910/* 911 * neo_param() 912 * Send any/all changes to the line to the UART. 913 */ 914static void neo_param(struct jsm_channel *ch) 915{ 916 u8 lcr = 0; 917 u8 uart_lcr, ier; 918 u32 baud; 919 int quot; 920 struct jsm_board *bd; 921 922 bd = ch->ch_bd; 923 if (!bd) 924 return; 925 926 /* 927 * If baud rate is zero, flush queues, and set mval to drop DTR. 928 */ 929 if ((ch->ch_c_cflag & CBAUD) == B0) { 930 ch->ch_r_head = ch->ch_r_tail = 0; 931 ch->ch_e_head = ch->ch_e_tail = 0; 932 933 neo_flush_uart_write(ch); 934 neo_flush_uart_read(ch); 935 936 ch->ch_flags |= (CH_BAUD0); 937 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 938 neo_assert_modem_signals(ch); 939 return; 940 941 } else { 942 int i; 943 unsigned int cflag; 944 static struct { 945 unsigned int rate; 946 unsigned int cflag; 947 } baud_rates[] = { 948 { 921600, B921600 }, 949 { 460800, B460800 }, 950 { 230400, B230400 }, 951 { 115200, B115200 }, 952 { 57600, B57600 }, 953 { 38400, B38400 }, 954 { 19200, B19200 }, 955 { 9600, B9600 }, 956 { 4800, B4800 }, 957 { 2400, B2400 }, 958 { 1200, B1200 }, 959 { 600, B600 }, 960 { 300, B300 }, 961 { 200, B200 }, 962 { 150, B150 }, 963 { 134, B134 }, 964 { 110, B110 }, 965 { 75, B75 }, 966 { 50, B50 }, 967 }; 968 969 cflag = C_BAUD(ch->uart_port.state->port.tty); 970 baud = 9600; 971 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) { 972 if (baud_rates[i].cflag == cflag) { 973 baud = baud_rates[i].rate; 974 break; 975 } 976 } 977 978 if (ch->ch_flags & CH_BAUD0) 979 ch->ch_flags &= ~(CH_BAUD0); 980 } 981 982 if (ch->ch_c_cflag & PARENB) 983 lcr |= UART_LCR_PARITY; 984 985 if (!(ch->ch_c_cflag & PARODD)) 986 lcr |= UART_LCR_EPAR; 987 988 if (ch->ch_c_cflag & CMSPAR) 989 lcr |= UART_LCR_SPAR; 990 991 if (ch->ch_c_cflag & CSTOPB) 992 lcr |= UART_LCR_STOP; 993 994 lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag)); 995 996 ier = readb(&ch->ch_neo_uart->ier); 997 uart_lcr = readb(&ch->ch_neo_uart->lcr); 998 999 quot = ch->ch_bd->bd_dividend / baud; 1000 1001 if (quot != 0) { 1002 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 1003 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 1004 writeb((quot >> 8), &ch->ch_neo_uart->ier); 1005 writeb(lcr, &ch->ch_neo_uart->lcr); 1006 } 1007 1008 if (uart_lcr != lcr) 1009 writeb(lcr, &ch->ch_neo_uart->lcr); 1010 1011 if (ch->ch_c_cflag & CREAD) 1012 ier |= (UART_IER_RDI | UART_IER_RLSI); 1013 1014 ier |= (UART_IER_THRI | UART_IER_MSI); 1015 1016 writeb(ier, &ch->ch_neo_uart->ier); 1017 1018 /* Set new start/stop chars */ 1019 neo_set_new_start_stop_chars(ch); 1020 1021 if (ch->ch_c_cflag & CRTSCTS) 1022 neo_set_cts_flow_control(ch); 1023 else if (ch->ch_c_iflag & IXON) { 1024 /* If start/stop is set to disable, then we should disable flow control */ 1025 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1026 neo_set_no_output_flow_control(ch); 1027 else 1028 neo_set_ixon_flow_control(ch); 1029 } 1030 else 1031 neo_set_no_output_flow_control(ch); 1032 1033 if (ch->ch_c_cflag & CRTSCTS) 1034 neo_set_rts_flow_control(ch); 1035 else if (ch->ch_c_iflag & IXOFF) { 1036 /* If start/stop is set to disable, then we should disable flow control */ 1037 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) 1038 neo_set_no_input_flow_control(ch); 1039 else 1040 neo_set_ixoff_flow_control(ch); 1041 } 1042 else 1043 neo_set_no_input_flow_control(ch); 1044 /* 1045 * Adjust the RX FIFO Trigger level if baud is less than 9600. 1046 * Not exactly elegant, but this is needed because of the Exar chip's 1047 * delay on firing off the RX FIFO interrupt on slower baud rates. 1048 */ 1049 if (baud < 9600) { 1050 writeb(1, &ch->ch_neo_uart->rfifo); 1051 ch->ch_r_tlevel = 1; 1052 } 1053 1054 neo_assert_modem_signals(ch); 1055 1056 /* Get current status of the modem signals now */ 1057 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 1058 return; 1059} 1060 1061/* 1062 * jsm_neo_intr() 1063 * 1064 * Neo specific interrupt handler. 1065 */ 1066static irqreturn_t neo_intr(int irq, void *voidbrd) 1067{ 1068 struct jsm_board *brd = voidbrd; 1069 struct jsm_channel *ch; 1070 int port = 0; 1071 int type = 0; 1072 int current_port; 1073 u32 tmp; 1074 u32 uart_poll; 1075 unsigned long lock_flags; 1076 unsigned long lock_flags2; 1077 int outofloop_count = 0; 1078 1079 /* Lock out the slow poller from running on this board. */ 1080 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); 1081 1082 /* 1083 * Read in "extended" IRQ information from the 32bit Neo register. 1084 * Bits 0-7: What port triggered the interrupt. 1085 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 1086 */ 1087 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 1088 1089 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", 1090 __FILE__, __LINE__, uart_poll); 1091 1092 if (!uart_poll) { 1093 jsm_dbg(INTR, &brd->pci_dev, 1094 "Kernel interrupted to me, but no pending interrupts...\n"); 1095 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1096 return IRQ_NONE; 1097 } 1098 1099 /* At this point, we have at least SOMETHING to service, dig further... */ 1100 1101 current_port = 0; 1102 1103 /* Loop on each port */ 1104 while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){ 1105 1106 tmp = uart_poll; 1107 outofloop_count++; 1108 1109 /* Check current port to see if it has interrupt pending */ 1110 if ((tmp & jsm_offset_table[current_port]) != 0) { 1111 port = current_port; 1112 type = tmp >> (8 + (port * 3)); 1113 type &= 0x7; 1114 } else { 1115 current_port++; 1116 continue; 1117 } 1118 1119 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", 1120 __FILE__, __LINE__, port, type); 1121 1122 /* Remove this port + type from uart_poll */ 1123 uart_poll &= ~(jsm_offset_table[port]); 1124 1125 if (!type) { 1126 /* If no type, just ignore it, and move onto next port */ 1127 jsm_dbg(INTR, &brd->pci_dev, 1128 "Interrupt with no type! port: %d\n", port); 1129 continue; 1130 } 1131 1132 /* Switch on type of interrupt we have */ 1133 switch (type) { 1134 1135 case UART_17158_RXRDY_TIMEOUT: 1136 /* 1137 * RXRDY Time-out is cleared by reading data in the 1138 * RX FIFO until it falls below the trigger level. 1139 */ 1140 1141 /* Verify the port is in range. */ 1142 if (port >= brd->nasync) 1143 continue; 1144 1145 ch = brd->channels[port]; 1146 if (!ch) 1147 continue; 1148 1149 neo_copy_data_from_uart_to_queue(ch); 1150 1151 /* Call our tty layer to enforce queue flow control if needed. */ 1152 spin_lock_irqsave(&ch->ch_lock, lock_flags2); 1153 jsm_check_queue_flow_control(ch); 1154 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); 1155 1156 continue; 1157 1158 case UART_17158_RX_LINE_STATUS: 1159 /* 1160 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1161 */ 1162 neo_parse_lsr(brd, port); 1163 continue; 1164 1165 case UART_17158_TXRDY: 1166 /* 1167 * TXRDY interrupt clears after reading ISR register for the UART channel. 1168 */ 1169 1170 /* 1171 * Yes, this is odd... 1172 * Why would I check EVERY possibility of type of 1173 * interrupt, when we know its TXRDY??? 1174 * Becuz for some reason, even tho we got triggered for TXRDY, 1175 * it seems to be occasionally wrong. Instead of TX, which 1176 * it should be, I was getting things like RXDY too. Weird. 1177 */ 1178 neo_parse_isr(brd, port); 1179 continue; 1180 1181 case UART_17158_MSR: 1182 /* 1183 * MSR or flow control was seen. 1184 */ 1185 neo_parse_isr(brd, port); 1186 continue; 1187 1188 default: 1189 /* 1190 * The UART triggered us with a bogus interrupt type. 1191 * It appears the Exar chip, when REALLY bogged down, will throw 1192 * these once and awhile. 1193 * Its harmless, just ignore it and move on. 1194 */ 1195 jsm_dbg(INTR, &brd->pci_dev, 1196 "%s:%d Unknown Interrupt type: %x\n", 1197 __FILE__, __LINE__, type); 1198 continue; 1199 } 1200 } 1201 1202 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); 1203 1204 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); 1205 return IRQ_HANDLED; 1206} 1207 1208/* 1209 * Neo specific way of turning off the receiver. 1210 * Used as a way to enforce queue flow control when in 1211 * hardware flow control mode. 1212 */ 1213static void neo_disable_receiver(struct jsm_channel *ch) 1214{ 1215 u8 tmp = readb(&ch->ch_neo_uart->ier); 1216 tmp &= ~(UART_IER_RDI); 1217 writeb(tmp, &ch->ch_neo_uart->ier); 1218 1219 /* flush write operation */ 1220 neo_pci_posting_flush(ch->ch_bd); 1221} 1222 1223 1224/* 1225 * Neo specific way of turning on the receiver. 1226 * Used as a way to un-enforce queue flow control when in 1227 * hardware flow control mode. 1228 */ 1229static void neo_enable_receiver(struct jsm_channel *ch) 1230{ 1231 u8 tmp = readb(&ch->ch_neo_uart->ier); 1232 tmp |= (UART_IER_RDI); 1233 writeb(tmp, &ch->ch_neo_uart->ier); 1234 1235 /* flush write operation */ 1236 neo_pci_posting_flush(ch->ch_bd); 1237} 1238 1239static void neo_send_start_character(struct jsm_channel *ch) 1240{ 1241 if (!ch) 1242 return; 1243 1244 if (ch->ch_startc != __DISABLED_CHAR) { 1245 ch->ch_xon_sends++; 1246 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1247 1248 /* flush write operation */ 1249 neo_pci_posting_flush(ch->ch_bd); 1250 } 1251} 1252 1253static void neo_send_stop_character(struct jsm_channel *ch) 1254{ 1255 if (!ch) 1256 return; 1257 1258 if (ch->ch_stopc != __DISABLED_CHAR) { 1259 ch->ch_xoff_sends++; 1260 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1261 1262 /* flush write operation */ 1263 neo_pci_posting_flush(ch->ch_bd); 1264 } 1265} 1266 1267/* 1268 * neo_uart_init 1269 */ 1270static void neo_uart_init(struct jsm_channel *ch) 1271{ 1272 writeb(0, &ch->ch_neo_uart->ier); 1273 writeb(0, &ch->ch_neo_uart->efr); 1274 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1275 1276 /* Clear out UART and FIFO */ 1277 readb(&ch->ch_neo_uart->txrx); 1278 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1279 readb(&ch->ch_neo_uart->lsr); 1280 readb(&ch->ch_neo_uart->msr); 1281 1282 ch->ch_flags |= CH_FIFO_ENABLED; 1283 1284 /* Assert any signals we want up */ 1285 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1286} 1287 1288/* 1289 * Make the UART completely turn off. 1290 */ 1291static void neo_uart_off(struct jsm_channel *ch) 1292{ 1293 /* Turn off UART enhanced bits */ 1294 writeb(0, &ch->ch_neo_uart->efr); 1295 1296 /* Stop all interrupts from occurring. */ 1297 writeb(0, &ch->ch_neo_uart->ier); 1298} 1299 1300/* Channel lock MUST be held by the calling function! */ 1301static void neo_send_break(struct jsm_channel *ch) 1302{ 1303 /* 1304 * Set the time we should stop sending the break. 1305 * If we are already sending a break, toss away the existing 1306 * time to stop, and use this new value instead. 1307 */ 1308 1309 /* Tell the UART to start sending the break */ 1310 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1311 u8 temp = readb(&ch->ch_neo_uart->lcr); 1312 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1313 ch->ch_flags |= (CH_BREAK_SENDING); 1314 1315 /* flush write operation */ 1316 neo_pci_posting_flush(ch->ch_bd); 1317 } 1318} 1319 1320struct board_ops jsm_neo_ops = { 1321 .intr = neo_intr, 1322 .uart_init = neo_uart_init, 1323 .uart_off = neo_uart_off, 1324 .param = neo_param, 1325 .assert_modem_signals = neo_assert_modem_signals, 1326 .flush_uart_write = neo_flush_uart_write, 1327 .flush_uart_read = neo_flush_uart_read, 1328 .disable_receiver = neo_disable_receiver, 1329 .enable_receiver = neo_enable_receiver, 1330 .send_break = neo_send_break, 1331 .clear_break = neo_clear_break, 1332 .send_start_character = neo_send_start_character, 1333 .send_stop_character = neo_send_stop_character, 1334 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 1335};
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