ip22zilog.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for Zilog serial chips found on SGI workstations and
   4 * servers.  This driver could actually be made more generic.
   5 *
   6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
   7 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
   8 * drivers/sbus/char/zs.c code.  A lot of code has been simply moved over
   9 * directly from there but much has been rewritten.  Credits therefore go out
  10 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
  11 * for their work there.
  12 *
  13 *  Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
  14 *  Copyright (C) 2002 David S. Miller (davem@redhat.com)
  15 */
  16#include <linux/module.h>
  17#include <linux/kernel.h>
  18#include <linux/errno.h>
  19#include <linux/delay.h>
  20#include <linux/tty.h>
  21#include <linux/tty_flip.h>
  22#include <linux/major.h>
  23#include <linux/string.h>
  24#include <linux/ptrace.h>
  25#include <linux/ioport.h>
  26#include <linux/slab.h>
  27#include <linux/circ_buf.h>
  28#include <linux/serial.h>
  29#include <linux/sysrq.h>
  30#include <linux/console.h>
  31#include <linux/spinlock.h>
  32#include <linux/init.h>
  33#include <linux/platform_device.h>
  34
  35#include <linux/io.h>
  36#include <asm/irq.h>
  37#include <asm/sgialib.h>
  38#include <asm/sgi/ioc.h>
  39#include <asm/sgi/hpc3.h>
  40#include <asm/sgi/ip22.h>
  41
  42#include <linux/serial_core.h>
  43
  44#include "ip22zilog.h"
  45
  46/*
  47 * On IP22 we need to delay after register accesses but we do not need to
  48 * flush writes.
  49 */
  50#define ZSDELAY()		udelay(5)
  51#define ZSDELAY_LONG()		udelay(20)
  52#define ZS_WSYNC(channel)	do { } while (0)
  53
  54#define NUM_CHANNELS		2
  55#define CHANNEL_B		0
  56#define CHANNEL_A		1
  57
  58#define ZS_CLOCK		3672000	/* Zilog input clock rate. */
  59#define ZS_CLOCK_DIVISOR	16      /* Divisor this driver uses. */
  60
  61/*
  62 * We wrap our port structure around the generic uart_port.
  63 */
  64struct uart_ip22zilog_port {
  65	struct uart_port		port;
  66
  67	/* Current values of Zilog write registers.  */
  68	unsigned char			curregs[NUM_ZSREGS];
  69
  70	unsigned int			flags;
  71#define IP22ZILOG_FLAG_IS_CONS		0x00000004
  72#define IP22ZILOG_FLAG_IS_KGDB		0x00000008
  73#define IP22ZILOG_FLAG_MODEM_STATUS	0x00000010
  74#define IP22ZILOG_FLAG_REGS_HELD	0x00000040
  75#define IP22ZILOG_FLAG_TX_STOPPED	0x00000080
  76#define IP22ZILOG_FLAG_TX_ACTIVE	0x00000100
  77#define IP22ZILOG_FLAG_RESET_DONE	0x00000200
  78
  79	unsigned int			tty_break;
  80
  81	unsigned char			parity_mask;
  82	unsigned char			prev_status;
  83};
  84
  85static struct uart_ip22zilog_port ip22zilog_port_table[NUM_CHANNELS];
  86
  87#define ZILOG_CHANNEL_FROM_PORT(PORT)	((struct zilog_channel *)((PORT)->membase))
  88#define UART_ZILOG(PORT)		((struct uart_ip22zilog_port *)(PORT))
  89#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM)		\
  90	(UART_ZILOG(PORT)->curregs[REGNUM])
  91#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL)	\
  92	((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
  93#define ZS_IS_CONS(UP)	((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
  94#define ZS_IS_KGDB(UP)	((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
  95#define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
  96#define ZS_REGS_HELD(UP)	((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
  97#define ZS_TX_STOPPED(UP)	((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
  98#define ZS_TX_ACTIVE(UP)	((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
  99
 100/* Reading and writing Zilog8530 registers.  The delays are to make this
 101 * driver work on the IP22 which needs a settling delay after each chip
 102 * register access, other machines handle this in hardware via auxiliary
 103 * flip-flops which implement the settle time we do in software.
 104 *
 105 * The port lock must be held and local IRQs must be disabled
 106 * when {read,write}_zsreg is invoked.
 107 */
 108static unsigned char read_zsreg(struct zilog_channel *channel,
 109				unsigned char reg)
 110{
 111	unsigned char retval;
 112
 113	writeb(reg, &channel->control);
 114	ZSDELAY();
 115	retval = readb(&channel->control);
 116	ZSDELAY();
 117
 118	return retval;
 119}
 120
 121static void write_zsreg(struct zilog_channel *channel,
 122			unsigned char reg, unsigned char value)
 123{
 124	writeb(reg, &channel->control);
 125	ZSDELAY();
 126	writeb(value, &channel->control);
 127	ZSDELAY();
 128}
 129
 130static void ip22zilog_clear_fifo(struct zilog_channel *channel)
 131{
 132	int i;
 133
 134	for (i = 0; i < 32; i++) {
 135		unsigned char regval;
 136
 137		regval = readb(&channel->control);
 138		ZSDELAY();
 139		if (regval & Rx_CH_AV)
 140			break;
 141
 142		regval = read_zsreg(channel, R1);
 143		readb(&channel->data);
 144		ZSDELAY();
 145
 146		if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 147			writeb(ERR_RES, &channel->control);
 148			ZSDELAY();
 149			ZS_WSYNC(channel);
 150		}
 151	}
 152}
 153
 154/* This function must only be called when the TX is not busy.  The UART
 155 * port lock must be held and local interrupts disabled.
 156 */
 157static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
 158{
 159	int i;
 160
 161	/* Let pending transmits finish.  */
 162	for (i = 0; i < 1000; i++) {
 163		unsigned char stat = read_zsreg(channel, R1);
 164		if (stat & ALL_SNT)
 165			break;
 166		udelay(100);
 167	}
 168
 169	writeb(ERR_RES, &channel->control);
 170	ZSDELAY();
 171	ZS_WSYNC(channel);
 172
 173	ip22zilog_clear_fifo(channel);
 174
 175	/* Disable all interrupts.  */
 176	write_zsreg(channel, R1,
 177		    regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
 178
 179	/* Set parity, sync config, stop bits, and clock divisor.  */
 180	write_zsreg(channel, R4, regs[R4]);
 181
 182	/* Set misc. TX/RX control bits.  */
 183	write_zsreg(channel, R10, regs[R10]);
 184
 185	/* Set TX/RX controls sans the enable bits.  */
 186	write_zsreg(channel, R3, regs[R3] & ~RxENAB);
 187	write_zsreg(channel, R5, regs[R5] & ~TxENAB);
 188
 189	/* Synchronous mode config.  */
 190	write_zsreg(channel, R6, regs[R6]);
 191	write_zsreg(channel, R7, regs[R7]);
 192
 193	/* Don't mess with the interrupt vector (R2, unused by us) and
 194	 * master interrupt control (R9).  We make sure this is setup
 195	 * properly at probe time then never touch it again.
 196	 */
 197
 198	/* Disable baud generator.  */
 199	write_zsreg(channel, R14, regs[R14] & ~BRENAB);
 200
 201	/* Clock mode control.  */
 202	write_zsreg(channel, R11, regs[R11]);
 203
 204	/* Lower and upper byte of baud rate generator divisor.  */
 205	write_zsreg(channel, R12, regs[R12]);
 206	write_zsreg(channel, R13, regs[R13]);
 207
 208	/* Now rewrite R14, with BRENAB (if set).  */
 209	write_zsreg(channel, R14, regs[R14]);
 210
 211	/* External status interrupt control.  */
 212	write_zsreg(channel, R15, regs[R15]);
 213
 214	/* Reset external status interrupts.  */
 215	write_zsreg(channel, R0, RES_EXT_INT);
 216	write_zsreg(channel, R0, RES_EXT_INT);
 217
 218	/* Rewrite R3/R5, this time without enables masked.  */
 219	write_zsreg(channel, R3, regs[R3]);
 220	write_zsreg(channel, R5, regs[R5]);
 221
 222	/* Rewrite R1, this time without IRQ enabled masked.  */
 223	write_zsreg(channel, R1, regs[R1]);
 224}
 225
 226/* Reprogram the Zilog channel HW registers with the copies found in the
 227 * software state struct.  If the transmitter is busy, we defer this update
 228 * until the next TX complete interrupt.  Else, we do it right now.
 229 *
 230 * The UART port lock must be held and local interrupts disabled.
 231 */
 232static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
 233				       struct zilog_channel *channel)
 234{
 235	if (!ZS_REGS_HELD(up)) {
 236		if (ZS_TX_ACTIVE(up)) {
 237			up->flags |= IP22ZILOG_FLAG_REGS_HELD;
 238		} else {
 239			__load_zsregs(channel, up->curregs);
 240		}
 241	}
 242}
 243
 244#define Rx_BRK 0x0100                   /* BREAK event software flag.  */
 245#define Rx_SYS 0x0200                   /* SysRq event software flag.  */
 246
 247static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
 248						  struct zilog_channel *channel)
 249{
 250	unsigned int r1;
 251	u8 ch, flag;
 252	bool push = up->port.state != NULL;
 253
 254	for (;;) {
 255		ch = readb(&channel->control);
 256		ZSDELAY();
 257		if (!(ch & Rx_CH_AV))
 258			break;
 259
 260		r1 = read_zsreg(channel, R1);
 261		if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 262			writeb(ERR_RES, &channel->control);
 263			ZSDELAY();
 264			ZS_WSYNC(channel);
 265		}
 266
 267		ch = readb(&channel->data);
 268		ZSDELAY();
 269
 270		ch &= up->parity_mask;
 271
 272		/* Handle the null char got when BREAK is removed.  */
 273		if (!ch)
 274			r1 |= up->tty_break;
 275
 276		/* A real serial line, record the character and status.  */
 277		flag = TTY_NORMAL;
 278		up->port.icount.rx++;
 279		if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) {
 280			up->tty_break = 0;
 281
 282			if (r1 & (Rx_SYS | Rx_BRK)) {
 283				up->port.icount.brk++;
 284				if (r1 & Rx_SYS)
 285					continue;
 286				r1 &= ~(PAR_ERR | CRC_ERR);
 287			}
 288			else if (r1 & PAR_ERR)
 289				up->port.icount.parity++;
 290			else if (r1 & CRC_ERR)
 291				up->port.icount.frame++;
 292			if (r1 & Rx_OVR)
 293				up->port.icount.overrun++;
 294			r1 &= up->port.read_status_mask;
 295			if (r1 & Rx_BRK)
 296				flag = TTY_BREAK;
 297			else if (r1 & PAR_ERR)
 298				flag = TTY_PARITY;
 299			else if (r1 & CRC_ERR)
 300				flag = TTY_FRAME;
 301		}
 302
 303		if (uart_handle_sysrq_char(&up->port, ch))
 304			continue;
 305
 306		if (push)
 307			uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
 308	}
 309	return push;
 310}
 311
 312static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
 313				   struct zilog_channel *channel)
 314{
 315	unsigned char status;
 316
 317	status = readb(&channel->control);
 318	ZSDELAY();
 319
 320	writeb(RES_EXT_INT, &channel->control);
 321	ZSDELAY();
 322	ZS_WSYNC(channel);
 323
 324	if (up->curregs[R15] & BRKIE) {
 325		if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
 326			if (uart_handle_break(&up->port))
 327				up->tty_break = Rx_SYS;
 328			else
 329				up->tty_break = Rx_BRK;
 330		}
 331	}
 332
 333	if (ZS_WANTS_MODEM_STATUS(up)) {
 334		if (status & SYNC)
 335			up->port.icount.dsr++;
 336
 337		/* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
 338		 * But it does not tell us which bit has changed, we have to keep
 339		 * track of this ourselves.
 340		 */
 341		if ((status ^ up->prev_status) ^ DCD)
 342			uart_handle_dcd_change(&up->port,
 343					       (status & DCD));
 344		if ((status ^ up->prev_status) ^ CTS)
 345			uart_handle_cts_change(&up->port,
 346					       (status & CTS));
 347
 348		wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 349	}
 350
 351	up->prev_status = status;
 352}
 353
 354static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
 355				    struct zilog_channel *channel)
 356{
 357	struct tty_port *tport;
 358	unsigned char c;
 359
 360	if (ZS_IS_CONS(up)) {
 361		unsigned char status = readb(&channel->control);
 362		ZSDELAY();
 363
 364		/* TX still busy?  Just wait for the next TX done interrupt.
 365		 *
 366		 * It can occur because of how we do serial console writes.  It would
 367		 * be nice to transmit console writes just like we normally would for
 368		 * a TTY line. (ie. buffered and TX interrupt driven).  That is not
 369		 * easy because console writes cannot sleep.  One solution might be
 370		 * to poll on enough port->xmit space becoming free.  -DaveM
 371		 */
 372		if (!(status & Tx_BUF_EMP))
 373			return;
 374	}
 375
 376	up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
 377
 378	if (ZS_REGS_HELD(up)) {
 379		__load_zsregs(channel, up->curregs);
 380		up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
 381	}
 382
 383	if (ZS_TX_STOPPED(up)) {
 384		up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
 385		goto ack_tx_int;
 386	}
 387
 388	if (up->port.x_char) {
 389		up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
 390		writeb(up->port.x_char, &channel->data);
 391		ZSDELAY();
 392		ZS_WSYNC(channel);
 393
 394		up->port.icount.tx++;
 395		up->port.x_char = 0;
 396		return;
 397	}
 398
 399	if (up->port.state == NULL)
 400		goto ack_tx_int;
 401	tport = &up->port.state->port;
 402	if (uart_tx_stopped(&up->port))
 403		goto ack_tx_int;
 404	if (!uart_fifo_get(&up->port, &c))
 405		goto ack_tx_int;
 406
 407	up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
 408	writeb(c, &channel->data);
 409	ZSDELAY();
 410	ZS_WSYNC(channel);
 411
 412	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
 413		uart_write_wakeup(&up->port);
 414
 415	return;
 416
 417ack_tx_int:
 418	writeb(RES_Tx_P, &channel->control);
 419	ZSDELAY();
 420	ZS_WSYNC(channel);
 421}
 422
 423static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
 424{
 425	struct uart_ip22zilog_port *up;
 426	struct zilog_channel *channel;
 427	unsigned char r3;
 428	bool push = false;
 429
 430	up = &ip22zilog_port_table[CHANNEL_A];
 431	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 432
 433	uart_port_lock(&up->port);
 434	r3 = read_zsreg(channel, R3);
 435
 436	/* Channel A */
 437	if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
 438		writeb(RES_H_IUS, &channel->control);
 439		ZSDELAY();
 440		ZS_WSYNC(channel);
 441
 442		if (r3 & CHARxIP)
 443			push = ip22zilog_receive_chars(up, channel);
 444		if (r3 & CHAEXT)
 445			ip22zilog_status_handle(up, channel);
 446		if (r3 & CHATxIP)
 447			ip22zilog_transmit_chars(up, channel);
 448	}
 449	uart_port_unlock(&up->port);
 450
 451	if (push)
 452		tty_flip_buffer_push(&up->port.state->port);
 453
 454	/* Channel B */
 455	up = &ip22zilog_port_table[CHANNEL_B];
 456	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 457	push = false;
 458
 459	uart_port_lock(&up->port);
 460	if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
 461		writeb(RES_H_IUS, &channel->control);
 462		ZSDELAY();
 463		ZS_WSYNC(channel);
 464
 465		if (r3 & CHBRxIP)
 466			push = ip22zilog_receive_chars(up, channel);
 467		if (r3 & CHBEXT)
 468			ip22zilog_status_handle(up, channel);
 469		if (r3 & CHBTxIP)
 470			ip22zilog_transmit_chars(up, channel);
 471	}
 472	uart_port_unlock(&up->port);
 473
 474	if (push)
 475		tty_flip_buffer_push(&up->port.state->port);
 476
 477	return IRQ_HANDLED;
 478}
 479
 480/* A convenient way to quickly get R0 status.  The caller must _not_ hold the
 481 * port lock, it is acquired here.
 482 */
 483static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
 484{
 485	struct zilog_channel *channel;
 486	unsigned char status;
 487
 488	channel = ZILOG_CHANNEL_FROM_PORT(port);
 489	status = readb(&channel->control);
 490	ZSDELAY();
 491
 492	return status;
 493}
 494
 495/* The port lock is not held.  */
 496static unsigned int ip22zilog_tx_empty(struct uart_port *port)
 497{
 498	unsigned long flags;
 499	unsigned char status;
 500	unsigned int ret;
 501
 502	uart_port_lock_irqsave(port, &flags);
 503
 504	status = ip22zilog_read_channel_status(port);
 505
 506	uart_port_unlock_irqrestore(port, flags);
 507
 508	if (status & Tx_BUF_EMP)
 509		ret = TIOCSER_TEMT;
 510	else
 511		ret = 0;
 512
 513	return ret;
 514}
 515
 516/* The port lock is held and interrupts are disabled.  */
 517static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
 518{
 519	unsigned char status;
 520	unsigned int ret;
 521
 522	status = ip22zilog_read_channel_status(port);
 523
 524	ret = 0;
 525	if (status & DCD)
 526		ret |= TIOCM_CAR;
 527	if (status & SYNC)
 528		ret |= TIOCM_DSR;
 529	if (status & CTS)
 530		ret |= TIOCM_CTS;
 531
 532	return ret;
 533}
 534
 535/* The port lock is held and interrupts are disabled.  */
 536static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
 537{
 538	struct uart_ip22zilog_port *up =
 539		container_of(port, struct uart_ip22zilog_port, port);
 540	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 541	unsigned char set_bits, clear_bits;
 542
 543	set_bits = clear_bits = 0;
 544
 545	if (mctrl & TIOCM_RTS)
 546		set_bits |= RTS;
 547	else
 548		clear_bits |= RTS;
 549	if (mctrl & TIOCM_DTR)
 550		set_bits |= DTR;
 551	else
 552		clear_bits |= DTR;
 553
 554	/* NOTE: Not subject to 'transmitter active' rule.  */
 555	up->curregs[R5] |= set_bits;
 556	up->curregs[R5] &= ~clear_bits;
 557	write_zsreg(channel, R5, up->curregs[R5]);
 558}
 559
 560/* The port lock is held and interrupts are disabled.  */
 561static void ip22zilog_stop_tx(struct uart_port *port)
 562{
 563	struct uart_ip22zilog_port *up =
 564		container_of(port, struct uart_ip22zilog_port, port);
 565
 566	up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
 567}
 568
 569/* The port lock is held and interrupts are disabled.  */
 570static void ip22zilog_start_tx(struct uart_port *port)
 571{
 572	struct uart_ip22zilog_port *up =
 573		container_of(port, struct uart_ip22zilog_port, port);
 574	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 575	unsigned char status;
 576
 577	up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
 578	up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
 579
 580	status = readb(&channel->control);
 581	ZSDELAY();
 582
 583	/* TX busy?  Just wait for the TX done interrupt.  */
 584	if (!(status & Tx_BUF_EMP))
 585		return;
 586
 587	/* Send the first character to jump-start the TX done
 588	 * IRQ sending engine.
 589	 */
 590	if (port->x_char) {
 591		writeb(port->x_char, &channel->data);
 592		ZSDELAY();
 593		ZS_WSYNC(channel);
 594
 595		port->icount.tx++;
 596		port->x_char = 0;
 597	} else {
 598		struct tty_port *tport = &port->state->port;
 599		unsigned char c;
 600
 601		if (!uart_fifo_get(port, &c))
 602			return;
 603		writeb(c, &channel->data);
 604		ZSDELAY();
 605		ZS_WSYNC(channel);
 606
 607		if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
 608			uart_write_wakeup(&up->port);
 609	}
 610}
 611
 612/* The port lock is held and interrupts are disabled.  */
 613static void ip22zilog_stop_rx(struct uart_port *port)
 614{
 615	struct uart_ip22zilog_port *up = UART_ZILOG(port);
 616	struct zilog_channel *channel;
 617
 618	if (ZS_IS_CONS(up))
 619		return;
 620
 621	channel = ZILOG_CHANNEL_FROM_PORT(port);
 622
 623	/* Disable all RX interrupts.  */
 624	up->curregs[R1] &= ~RxINT_MASK;
 625	ip22zilog_maybe_update_regs(up, channel);
 626}
 627
 628/* The port lock is held.  */
 629static void ip22zilog_enable_ms(struct uart_port *port)
 630{
 631	struct uart_ip22zilog_port *up =
 632		container_of(port, struct uart_ip22zilog_port, port);
 633	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 634	unsigned char new_reg;
 635
 636	new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
 637	if (new_reg != up->curregs[R15]) {
 638		up->curregs[R15] = new_reg;
 639
 640		/* NOTE: Not subject to 'transmitter active' rule.  */
 641		write_zsreg(channel, R15, up->curregs[R15]);
 642	}
 643}
 644
 645/* The port lock is not held.  */
 646static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
 647{
 648	struct uart_ip22zilog_port *up =
 649		container_of(port, struct uart_ip22zilog_port, port);
 650	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 651	unsigned char set_bits, clear_bits, new_reg;
 652	unsigned long flags;
 653
 654	set_bits = clear_bits = 0;
 655
 656	if (break_state)
 657		set_bits |= SND_BRK;
 658	else
 659		clear_bits |= SND_BRK;
 660
 661	uart_port_lock_irqsave(port, &flags);
 662
 663	new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
 664	if (new_reg != up->curregs[R5]) {
 665		up->curregs[R5] = new_reg;
 666
 667		/* NOTE: Not subject to 'transmitter active' rule.  */
 668		write_zsreg(channel, R5, up->curregs[R5]);
 669	}
 670
 671	uart_port_unlock_irqrestore(port, flags);
 672}
 673
 674static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
 675{
 676	struct zilog_channel *channel;
 677	int i;
 678
 679	if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
 680		return;
 681
 682	/* Let pending transmits finish.  */
 683	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 684	for (i = 0; i < 1000; i++) {
 685		unsigned char stat = read_zsreg(channel, R1);
 686		if (stat & ALL_SNT)
 687			break;
 688		udelay(100);
 689	}
 690
 691	up = &ip22zilog_port_table[CHANNEL_A];
 692	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 693
 694	write_zsreg(channel, R9, FHWRES);
 695	ZSDELAY_LONG();
 696	(void) read_zsreg(channel, R0);
 697
 698	up->flags |= IP22ZILOG_FLAG_RESET_DONE;
 699	up = &ip22zilog_port_table[CHANNEL_B];
 700	up->flags |= IP22ZILOG_FLAG_RESET_DONE;
 701}
 702
 703static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
 704{
 705	struct zilog_channel *channel;
 706
 707	channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 708
 709	__ip22zilog_reset(up);
 710
 711	__load_zsregs(channel, up->curregs);
 712	/* set master interrupt enable */
 713	write_zsreg(channel, R9, up->curregs[R9]);
 714	up->prev_status = readb(&channel->control);
 715
 716	/* Enable receiver and transmitter.  */
 717	up->curregs[R3] |= RxENAB;
 718	up->curregs[R5] |= TxENAB;
 719
 720	up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
 721	ip22zilog_maybe_update_regs(up, channel);
 722}
 723
 724static int ip22zilog_startup(struct uart_port *port)
 725{
 726	struct uart_ip22zilog_port *up = UART_ZILOG(port);
 727	unsigned long flags;
 728
 729	if (ZS_IS_CONS(up))
 730		return 0;
 731
 732	uart_port_lock_irqsave(port, &flags);
 733	__ip22zilog_startup(up);
 734	uart_port_unlock_irqrestore(port, flags);
 735	return 0;
 736}
 737
 738/*
 739 * The test for ZS_IS_CONS is explained by the following e-mail:
 740 *****
 741 * From: Russell King <rmk@arm.linux.org.uk>
 742 * Date: Sun, 8 Dec 2002 10:18:38 +0000
 743 *
 744 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
 745 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
 746 * > and I noticed that something is not right with reference
 747 * > counting in this case. It seems that when the console
 748 * > is open by kernel initially, this is not accounted
 749 * > as an open, and uart_startup is not called.
 750 *
 751 * That is correct.  We are unable to call uart_startup when the serial
 752 * console is initialised because it may need to allocate memory (as
 753 * request_irq does) and the memory allocators may not have been
 754 * initialised.
 755 *
 756 * 1. initialise the port into a state where it can send characters in the
 757 *    console write method.
 758 *
 759 * 2. don't do the actual hardware shutdown in your shutdown() method (but
 760 *    do the normal software shutdown - ie, free irqs etc)
 761 *****
 762 */
 763static void ip22zilog_shutdown(struct uart_port *port)
 764{
 765	struct uart_ip22zilog_port *up = UART_ZILOG(port);
 766	struct zilog_channel *channel;
 767	unsigned long flags;
 768
 769	if (ZS_IS_CONS(up))
 770		return;
 771
 772	uart_port_lock_irqsave(port, &flags);
 773
 774	channel = ZILOG_CHANNEL_FROM_PORT(port);
 775
 776	/* Disable receiver and transmitter.  */
 777	up->curregs[R3] &= ~RxENAB;
 778	up->curregs[R5] &= ~TxENAB;
 779
 780	/* Disable all interrupts and BRK assertion.  */
 781	up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
 782	up->curregs[R5] &= ~SND_BRK;
 783	ip22zilog_maybe_update_regs(up, channel);
 784
 785	uart_port_unlock_irqrestore(port, flags);
 786}
 787
 788/* Shared by TTY driver and serial console setup.  The port lock is held
 789 * and local interrupts are disabled.
 790 */
 791static void
 792ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
 793		       unsigned int iflag, int brg)
 794{
 795
 796	up->curregs[R10] = NRZ;
 797	up->curregs[R11] = TCBR | RCBR;
 798
 799	/* Program BAUD and clock source. */
 800	up->curregs[R4] &= ~XCLK_MASK;
 801	up->curregs[R4] |= X16CLK;
 802	up->curregs[R12] = brg & 0xff;
 803	up->curregs[R13] = (brg >> 8) & 0xff;
 804	up->curregs[R14] = BRENAB;
 805
 806	/* Character size, stop bits, and parity. */
 807	up->curregs[3] &= ~RxN_MASK;
 808	up->curregs[5] &= ~TxN_MASK;
 809	switch (cflag & CSIZE) {
 810	case CS5:
 811		up->curregs[3] |= Rx5;
 812		up->curregs[5] |= Tx5;
 813		up->parity_mask = 0x1f;
 814		break;
 815	case CS6:
 816		up->curregs[3] |= Rx6;
 817		up->curregs[5] |= Tx6;
 818		up->parity_mask = 0x3f;
 819		break;
 820	case CS7:
 821		up->curregs[3] |= Rx7;
 822		up->curregs[5] |= Tx7;
 823		up->parity_mask = 0x7f;
 824		break;
 825	case CS8:
 826	default:
 827		up->curregs[3] |= Rx8;
 828		up->curregs[5] |= Tx8;
 829		up->parity_mask = 0xff;
 830		break;
 831	}
 832	up->curregs[4] &= ~0x0c;
 833	if (cflag & CSTOPB)
 834		up->curregs[4] |= SB2;
 835	else
 836		up->curregs[4] |= SB1;
 837	if (cflag & PARENB)
 838		up->curregs[4] |= PAR_ENAB;
 839	else
 840		up->curregs[4] &= ~PAR_ENAB;
 841	if (!(cflag & PARODD))
 842		up->curregs[4] |= PAR_EVEN;
 843	else
 844		up->curregs[4] &= ~PAR_EVEN;
 845
 846	up->port.read_status_mask = Rx_OVR;
 847	if (iflag & INPCK)
 848		up->port.read_status_mask |= CRC_ERR | PAR_ERR;
 849	if (iflag & (IGNBRK | BRKINT | PARMRK))
 850		up->port.read_status_mask |= BRK_ABRT;
 851
 852	up->port.ignore_status_mask = 0;
 853	if (iflag & IGNPAR)
 854		up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
 855	if (iflag & IGNBRK) {
 856		up->port.ignore_status_mask |= BRK_ABRT;
 857		if (iflag & IGNPAR)
 858			up->port.ignore_status_mask |= Rx_OVR;
 859	}
 860
 861	if ((cflag & CREAD) == 0)
 862		up->port.ignore_status_mask = 0xff;
 863}
 864
 865/* The port lock is not held.  */
 866static void
 867ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
 868		      const struct ktermios *old)
 869{
 870	struct uart_ip22zilog_port *up =
 871		container_of(port, struct uart_ip22zilog_port, port);
 872	unsigned long flags;
 873	int baud, brg;
 874
 875	baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
 876
 877	uart_port_lock_irqsave(&up->port, &flags);
 878
 879	brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 880
 881	ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
 882
 883	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 884		up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
 885	else
 886		up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
 887
 888	ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
 889	uart_update_timeout(port, termios->c_cflag, baud);
 890
 891	uart_port_unlock_irqrestore(&up->port, flags);
 892}
 893
 894static const char *ip22zilog_type(struct uart_port *port)
 895{
 896	return "IP22-Zilog";
 897}
 898
 899/* We do not request/release mappings of the registers here, this
 900 * happens at early serial probe time.
 901 */
 902static void ip22zilog_release_port(struct uart_port *port)
 903{
 904}
 905
 906static int ip22zilog_request_port(struct uart_port *port)
 907{
 908	return 0;
 909}
 910
 911/* These do not need to do anything interesting either.  */
 912static void ip22zilog_config_port(struct uart_port *port, int flags)
 913{
 914}
 915
 916/* We do not support letting the user mess with the divisor, IRQ, etc. */
 917static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
 918{
 919	return -EINVAL;
 920}
 921
 922static const struct uart_ops ip22zilog_pops = {
 923	.tx_empty	=	ip22zilog_tx_empty,
 924	.set_mctrl	=	ip22zilog_set_mctrl,
 925	.get_mctrl	=	ip22zilog_get_mctrl,
 926	.stop_tx	=	ip22zilog_stop_tx,
 927	.start_tx	=	ip22zilog_start_tx,
 928	.stop_rx	=	ip22zilog_stop_rx,
 929	.enable_ms	=	ip22zilog_enable_ms,
 930	.break_ctl	=	ip22zilog_break_ctl,
 931	.startup	=	ip22zilog_startup,
 932	.shutdown	=	ip22zilog_shutdown,
 933	.set_termios	=	ip22zilog_set_termios,
 934	.type		=	ip22zilog_type,
 935	.release_port	=	ip22zilog_release_port,
 936	.request_port	=	ip22zilog_request_port,
 937	.config_port	=	ip22zilog_config_port,
 938	.verify_port	=	ip22zilog_verify_port,
 939};
 940
 941#define ZS_PUT_CHAR_MAX_DELAY	2000	/* 10 ms */
 942
 943#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
 944static void ip22zilog_put_char(struct uart_port *port, unsigned char ch)
 945{
 946	struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
 947	int loops = ZS_PUT_CHAR_MAX_DELAY;
 948
 949	/* This is a timed polling loop so do not switch the explicit
 950	 * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
 951	 */
 952	do {
 953		unsigned char val = readb(&channel->control);
 954		if (val & Tx_BUF_EMP) {
 955			ZSDELAY();
 956			break;
 957		}
 958		udelay(5);
 959	} while (--loops);
 960
 961	writeb(ch, &channel->data);
 962	ZSDELAY();
 963	ZS_WSYNC(channel);
 964}
 965
 966static void
 967ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
 968{
 969	struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
 970	unsigned long flags;
 971
 972	uart_port_lock_irqsave(&up->port, &flags);
 973	uart_console_write(&up->port, s, count, ip22zilog_put_char);
 974	udelay(2);
 975	uart_port_unlock_irqrestore(&up->port, flags);
 976}
 977
 978static int __init ip22zilog_console_setup(struct console *con, char *options)
 979{
 980	struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
 981	unsigned long flags;
 982	int baud = 9600, bits = 8;
 983	int parity = 'n';
 984	int flow = 'n';
 985
 986	up->flags |= IP22ZILOG_FLAG_IS_CONS;
 987
 988	printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);
 989
 990	uart_port_lock_irqsave(&up->port, &flags);
 991
 992	up->curregs[R15] |= BRKIE;
 993
 994	__ip22zilog_startup(up);
 995
 996	uart_port_unlock_irqrestore(&up->port, flags);
 997
 998	if (options)
 999		uart_parse_options(options, &baud, &parity, &bits, &flow);
1000	return uart_set_options(&up->port, con, baud, parity, bits, flow);
1001}
1002
1003static struct uart_driver ip22zilog_reg;
1004
1005static struct console ip22zilog_console = {
1006	.name	=	"ttyS",
1007	.write	=	ip22zilog_console_write,
1008	.device	=	uart_console_device,
1009	.setup	=	ip22zilog_console_setup,
1010	.flags	=	CON_PRINTBUFFER,
1011	.index	=	-1,
1012	.data	=	&ip22zilog_reg,
1013};
1014#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1015
1016static struct uart_driver ip22zilog_reg = {
1017	.owner		= THIS_MODULE,
1018	.driver_name	= "serial",
1019	.dev_name	= "ttyS",
1020	.major		= TTY_MAJOR,
1021	.minor		= 64,
1022	.nr		= NUM_CHANNELS,
1023#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1024	.cons		= &ip22zilog_console,
1025#endif
1026};
1027
1028static void __init ip22zilog_prepare(struct uart_ip22zilog_port *up)
1029{
1030	unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE);
1031	int brg;
1032
1033	spin_lock_init(&up->port.lock);
1034
1035	up->port.iotype = UPIO_MEM;
1036	up->port.uartclk = ZS_CLOCK;
1037	up->port.fifosize = 1;
1038	up->port.has_sysrq = sysrq_on;
1039	up->port.ops = &ip22zilog_pops;
1040	up->port.type = PORT_IP22ZILOG;
1041
1042	/* Normal serial TTY. */
1043	up->parity_mask = 0xff;
1044	up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1045	up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1046	up->curregs[R3] = RxENAB | Rx8;
1047	up->curregs[R5] = TxENAB | Tx8;
1048	up->curregs[R9] = NV | MIE;
1049	up->curregs[R10] = NRZ;
1050	up->curregs[R11] = TCBR | RCBR;
1051	brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1052	up->curregs[R12] = (brg & 0xff);
1053	up->curregs[R13] = (brg >> 8) & 0xff;
1054	up->curregs[R14] = BRENAB;
1055}
1056
1057static int ip22zilog_probe(struct platform_device *pdev)
1058{
1059	struct uart_ip22zilog_port *up;
1060	char __iomem *membase;
1061	struct resource *res;
1062	int irq;
1063	int i;
1064
1065	up = &ip22zilog_port_table[CHANNEL_B];
1066	if (up->port.dev)
1067		return -ENOSPC;
1068
1069	irq = platform_get_irq(pdev, 0);
1070	if (irq < 0)
1071		return irq;
1072
1073	membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1074	if (IS_ERR(membase))
1075		return PTR_ERR(membase);
1076
1077	ip22zilog_prepare(up);
1078
1079	up->port.mapbase = res->start + offsetof(struct zilog_layout, channelB);
1080	up->port.membase = membase + offsetof(struct zilog_layout, channelB);
1081	up->port.line = 0;
1082	up->port.dev = &pdev->dev;
1083	up->port.irq = irq;
1084
1085	up = &ip22zilog_port_table[CHANNEL_A];
1086	ip22zilog_prepare(up);
1087
1088	up->port.mapbase = res->start + offsetof(struct zilog_layout, channelA);
1089	up->port.membase = membase + offsetof(struct zilog_layout, channelA);
1090	up->port.line = 1;
1091	up->port.dev = &pdev->dev;
1092	up->port.irq = irq;
1093
1094	if (request_irq(irq, ip22zilog_interrupt, 0,
1095			"IP22-Zilog", NULL)) {
1096		panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1097	}
1098
1099	for (i = 0; i < NUM_CHANNELS; i++)
1100		uart_add_one_port(&ip22zilog_reg,
1101				  &ip22zilog_port_table[i].port);
1102
1103	return 0;
1104}
1105
1106static void ip22zilog_remove(struct platform_device *pdev)
1107{
1108	int i;
1109
1110	for (i = 0; i < NUM_CHANNELS; i++) {
1111		uart_remove_one_port(&ip22zilog_reg,
1112				     &ip22zilog_port_table[i].port);
1113		ip22zilog_port_table[i].port.dev = NULL;
1114	}
1115}
1116
1117static struct platform_driver ip22zilog_driver = {
1118	.probe	= ip22zilog_probe,
1119	.remove	= ip22zilog_remove,
1120	.driver	= {
1121		.name = "ip22zilog"
1122	}
1123};
1124
1125static int __init ip22zilog_init(void)
1126{
1127	int ret;
1128
1129	ret = uart_register_driver(&ip22zilog_reg);
1130	if (ret)
1131		return ret;
1132
1133	ret = platform_driver_register(&ip22zilog_driver);
1134	if (ret)
1135		uart_unregister_driver(&ip22zilog_reg);
1136
1137	return ret;
1138
1139}
1140
1141static void __exit ip22zilog_exit(void)
1142{
1143	uart_unregister_driver(&ip22zilog_reg);
1144	platform_driver_unregister(&ip22zilog_driver);
1145}
1146
1147module_init(ip22zilog_init);
1148module_exit(ip22zilog_exit);
1149
1150/* David wrote it but I'm to blame for the bugs ...  */
1151MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1152MODULE_DESCRIPTION("SGI Zilog serial port driver");
1153MODULE_LICENSE("GPL");