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8250_port.c
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linux-6.19.14/drivers/tty/serial/8250/8250_port.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Base port operations for 8250/16550-type serial ports 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * Split from 8250_core.c, Copyright (C) 2001 Russell King. 7 * 8 * A note about mapbase / membase 9 * 10 * mapbase is the physical address of the IO port. 11 * membase is an 'ioremapped' cookie. 12 */ 13 14#include <linux/module.h> 15#include <linux/moduleparam.h> 16#include <linux/ioport.h> 17#include <linux/init.h> 18#include <linux/irq.h> 19#include <linux/console.h> 20#include <linux/gpio/consumer.h> 21#include <linux/lockdep.h> 22#include <linux/sysrq.h> 23#include <linux/delay.h> 24#include <linux/platform_device.h> 25#include <linux/tty.h> 26#include <linux/ratelimit.h> 27#include <linux/tty_flip.h> 28#include <linux/serial.h> 29#include <linux/serial_8250.h> 30#include <linux/nmi.h> 31#include <linux/mutex.h> 32#include <linux/slab.h> 33#include <linux/uaccess.h> 34#include <linux/pm_runtime.h> 35#include <linux/ktime.h> 36 37#include <asm/io.h> 38#include <asm/irq.h> 39 40#include "8250.h" 41 42/* 43 * Here we define the default xmit fifo size used for each type of UART. 44 */ 45static const struct serial8250_config uart_config[] = { 46 [PORT_UNKNOWN] = { 47 .name = "unknown", 48 .fifo_size = 1, 49 .tx_loadsz = 1, 50 }, 51 [PORT_8250] = { 52 .name = "8250", 53 .fifo_size = 1, 54 .tx_loadsz = 1, 55 }, 56 [PORT_16450] = { 57 .name = "16450", 58 .fifo_size = 1, 59 .tx_loadsz = 1, 60 }, 61 [PORT_16550] = { 62 .name = "16550", 63 .fifo_size = 1, 64 .tx_loadsz = 1, 65 }, 66 [PORT_16550A] = { 67 .name = "16550A", 68 .fifo_size = 16, 69 .tx_loadsz = 16, 70 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 71 .rxtrig_bytes = {1, 4, 8, 14}, 72 .flags = UART_CAP_FIFO, 73 }, 74 [PORT_CIRRUS] = { 75 .name = "Cirrus", 76 .fifo_size = 1, 77 .tx_loadsz = 1, 78 }, 79 [PORT_16650] = { 80 .name = "ST16650", 81 .fifo_size = 1, 82 .tx_loadsz = 1, 83 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 84 }, 85 [PORT_16650V2] = { 86 .name = "ST16650V2", 87 .fifo_size = 32, 88 .tx_loadsz = 16, 89 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 90 UART_FCR_T_TRIG_00, 91 .rxtrig_bytes = {8, 16, 24, 28}, 92 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 93 }, 94 [PORT_16750] = { 95 .name = "TI16750", 96 .fifo_size = 64, 97 .tx_loadsz = 64, 98 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 99 UART_FCR7_64BYTE, 100 .rxtrig_bytes = {1, 16, 32, 56}, 101 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, 102 }, 103 [PORT_STARTECH] = { 104 .name = "Startech", 105 .fifo_size = 1, 106 .tx_loadsz = 1, 107 }, 108 [PORT_16C950] = { 109 .name = "16C950/954", 110 .fifo_size = 128, 111 .tx_loadsz = 128, 112 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, 113 .rxtrig_bytes = {16, 32, 112, 120}, 114 /* UART_CAP_EFR breaks billionon CF bluetooth card. */ 115 .flags = UART_CAP_FIFO | UART_CAP_SLEEP, 116 }, 117 [PORT_16654] = { 118 .name = "ST16654", 119 .fifo_size = 64, 120 .tx_loadsz = 32, 121 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 122 UART_FCR_T_TRIG_10, 123 .rxtrig_bytes = {8, 16, 56, 60}, 124 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 125 }, 126 [PORT_16850] = { 127 .name = "XR16850", 128 .fifo_size = 128, 129 .tx_loadsz = 128, 130 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 131 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 132 }, 133 [PORT_RSA] = { 134 .name = "RSA", 135 .fifo_size = 2048, 136 .tx_loadsz = 2048, 137 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, 138 .flags = UART_CAP_FIFO, 139 }, 140 [PORT_NS16550A] = { 141 .name = "NS16550A", 142 .fifo_size = 16, 143 .tx_loadsz = 16, 144 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 145 .flags = UART_CAP_FIFO | UART_NATSEMI, 146 }, 147 [PORT_XSCALE] = { 148 .name = "XScale", 149 .fifo_size = 32, 150 .tx_loadsz = 32, 151 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 152 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, 153 }, 154 [PORT_OCTEON] = { 155 .name = "OCTEON", 156 .fifo_size = 64, 157 .tx_loadsz = 64, 158 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 159 .flags = UART_CAP_FIFO, 160 }, 161 [PORT_U6_16550A] = { 162 .name = "U6_16550A", 163 .fifo_size = 64, 164 .tx_loadsz = 64, 165 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 166 .flags = UART_CAP_FIFO | UART_CAP_AFE, 167 }, 168 [PORT_TEGRA] = { 169 .name = "Tegra", 170 .fifo_size = 32, 171 .tx_loadsz = 8, 172 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 173 UART_FCR_T_TRIG_01, 174 .rxtrig_bytes = {1, 4, 8, 14}, 175 .flags = UART_CAP_FIFO | UART_CAP_RTOIE, 176 }, 177 [PORT_XR17D15X] = { 178 .name = "XR17D15X", 179 .fifo_size = 64, 180 .tx_loadsz = 64, 181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 182 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 183 UART_CAP_SLEEP, 184 }, 185 [PORT_XR17V35X] = { 186 .name = "XR17V35X", 187 .fifo_size = 256, 188 .tx_loadsz = 256, 189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | 190 UART_FCR_T_TRIG_11, 191 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 192 UART_CAP_SLEEP, 193 }, 194 [PORT_LPC3220] = { 195 .name = "LPC3220", 196 .fifo_size = 64, 197 .tx_loadsz = 32, 198 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | 199 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, 200 .flags = UART_CAP_FIFO, 201 }, 202 [PORT_BRCM_TRUMANAGE] = { 203 .name = "TruManage", 204 .fifo_size = 1, 205 .tx_loadsz = 1024, 206 .flags = UART_CAP_HFIFO, 207 }, 208 [PORT_8250_CIR] = { 209 .name = "CIR port" 210 }, 211 [PORT_ALTR_16550_F32] = { 212 .name = "Altera 16550 FIFO32", 213 .fifo_size = 32, 214 .tx_loadsz = 32, 215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 216 .rxtrig_bytes = {1, 8, 16, 30}, 217 .flags = UART_CAP_FIFO | UART_CAP_AFE, 218 }, 219 [PORT_ALTR_16550_F64] = { 220 .name = "Altera 16550 FIFO64", 221 .fifo_size = 64, 222 .tx_loadsz = 64, 223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 224 .rxtrig_bytes = {1, 16, 32, 62}, 225 .flags = UART_CAP_FIFO | UART_CAP_AFE, 226 }, 227 [PORT_ALTR_16550_F128] = { 228 .name = "Altera 16550 FIFO128", 229 .fifo_size = 128, 230 .tx_loadsz = 128, 231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 232 .rxtrig_bytes = {1, 32, 64, 126}, 233 .flags = UART_CAP_FIFO | UART_CAP_AFE, 234 }, 235 /* 236 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement 237 * workaround of errata A-008006 which states that tx_loadsz should 238 * be configured less than Maximum supported fifo bytes. 239 */ 240 [PORT_16550A_FSL64] = { 241 .name = "16550A_FSL64", 242 .fifo_size = 64, 243 .tx_loadsz = 63, 244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 245 UART_FCR7_64BYTE, 246 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT, 247 }, 248 [PORT_RT2880] = { 249 .name = "Palmchip BK-3103", 250 .fifo_size = 16, 251 .tx_loadsz = 16, 252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 253 .rxtrig_bytes = {1, 4, 8, 14}, 254 .flags = UART_CAP_FIFO, 255 }, 256 [PORT_DA830] = { 257 .name = "TI DA8xx/66AK2x", 258 .fifo_size = 16, 259 .tx_loadsz = 16, 260 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | 261 UART_FCR_R_TRIG_10, 262 .rxtrig_bytes = {1, 4, 8, 14}, 263 .flags = UART_CAP_FIFO | UART_CAP_AFE, 264 }, 265 [PORT_MTK_BTIF] = { 266 .name = "MediaTek BTIF", 267 .fifo_size = 16, 268 .tx_loadsz = 16, 269 .fcr = UART_FCR_ENABLE_FIFO | 270 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 271 .flags = UART_CAP_FIFO, 272 }, 273 [PORT_NPCM] = { 274 .name = "Nuvoton 16550", 275 .fifo_size = 16, 276 .tx_loadsz = 16, 277 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 278 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 279 .rxtrig_bytes = {1, 4, 8, 14}, 280 .flags = UART_CAP_FIFO, 281 }, 282 [PORT_SUNIX] = { 283 .name = "Sunix", 284 .fifo_size = 128, 285 .tx_loadsz = 128, 286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 287 .rxtrig_bytes = {1, 32, 64, 112}, 288 .flags = UART_CAP_FIFO | UART_CAP_SLEEP, 289 }, 290 [PORT_ASPEED_VUART] = { 291 .name = "ASPEED VUART", 292 .fifo_size = 16, 293 .tx_loadsz = 16, 294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, 295 .rxtrig_bytes = {1, 4, 8, 14}, 296 .flags = UART_CAP_FIFO, 297 }, 298 [PORT_MCHP16550A] = { 299 .name = "MCHP16550A", 300 .fifo_size = 256, 301 .tx_loadsz = 256, 302 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, 303 .rxtrig_bytes = {2, 66, 130, 194}, 304 .flags = UART_CAP_FIFO, 305 }, 306 [PORT_BCM7271] = { 307 .name = "Broadcom BCM7271 UART", 308 .fifo_size = 32, 309 .tx_loadsz = 32, 310 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, 311 .rxtrig_bytes = {1, 8, 16, 30}, 312 .flags = UART_CAP_FIFO | UART_CAP_AFE, 313 }, 314}; 315 316/* Uart divisor latch read */ 317static u32 default_serial_dl_read(struct uart_8250_port *up) 318{ 319 /* Assign these in pieces to truncate any bits above 7. */ 320 unsigned char dll = serial_in(up, UART_DLL); 321 unsigned char dlm = serial_in(up, UART_DLM); 322 323 return dll | dlm << 8; 324} 325 326/* Uart divisor latch write */ 327static void default_serial_dl_write(struct uart_8250_port *up, u32 value) 328{ 329 serial_out(up, UART_DLL, value & 0xff); 330 serial_out(up, UART_DLM, value >> 8 & 0xff); 331} 332 333#ifdef CONFIG_HAS_IOPORT 334static u32 hub6_serial_in(struct uart_port *p, unsigned int offset) 335{ 336 offset = offset << p->regshift; 337 outb(p->hub6 - 1 + offset, p->iobase); 338 return inb(p->iobase + 1); 339} 340 341static void hub6_serial_out(struct uart_port *p, unsigned int offset, u32 value) 342{ 343 offset = offset << p->regshift; 344 outb(p->hub6 - 1 + offset, p->iobase); 345 outb(value, p->iobase + 1); 346} 347#endif /* CONFIG_HAS_IOPORT */ 348 349static u32 mem_serial_in(struct uart_port *p, unsigned int offset) 350{ 351 offset = offset << p->regshift; 352 return readb(p->membase + offset); 353} 354 355static void mem_serial_out(struct uart_port *p, unsigned int offset, u32 value) 356{ 357 offset = offset << p->regshift; 358 writeb(value, p->membase + offset); 359} 360 361static void mem16_serial_out(struct uart_port *p, unsigned int offset, u32 value) 362{ 363 offset = offset << p->regshift; 364 writew(value, p->membase + offset); 365} 366 367static u32 mem16_serial_in(struct uart_port *p, unsigned int offset) 368{ 369 offset = offset << p->regshift; 370 return readw(p->membase + offset); 371} 372 373static void mem32_serial_out(struct uart_port *p, unsigned int offset, u32 value) 374{ 375 offset = offset << p->regshift; 376 writel(value, p->membase + offset); 377} 378 379static u32 mem32_serial_in(struct uart_port *p, unsigned int offset) 380{ 381 offset = offset << p->regshift; 382 return readl(p->membase + offset); 383} 384 385static void mem32be_serial_out(struct uart_port *p, unsigned int offset, u32 value) 386{ 387 offset = offset << p->regshift; 388 iowrite32be(value, p->membase + offset); 389} 390 391static u32 mem32be_serial_in(struct uart_port *p, unsigned int offset) 392{ 393 offset = offset << p->regshift; 394 return ioread32be(p->membase + offset); 395} 396 397#ifdef CONFIG_HAS_IOPORT 398static u32 io_serial_in(struct uart_port *p, unsigned int offset) 399{ 400 offset = offset << p->regshift; 401 return inb(p->iobase + offset); 402} 403 404static void io_serial_out(struct uart_port *p, unsigned int offset, u32 value) 405{ 406 offset = offset << p->regshift; 407 outb(value, p->iobase + offset); 408} 409#endif 410static u32 no_serial_in(struct uart_port *p, unsigned int offset) 411{ 412 return ~0U; 413} 414 415static void no_serial_out(struct uart_port *p, unsigned int offset, u32 value) 416{ 417} 418 419static int serial8250_default_handle_irq(struct uart_port *port); 420 421static void set_io_from_upio(struct uart_port *p) 422{ 423 struct uart_8250_port *up = up_to_u8250p(p); 424 425 up->dl_read = default_serial_dl_read; 426 up->dl_write = default_serial_dl_write; 427 428 switch (p->iotype) { 429#ifdef CONFIG_HAS_IOPORT 430 case UPIO_HUB6: 431 p->serial_in = hub6_serial_in; 432 p->serial_out = hub6_serial_out; 433 break; 434#endif 435 436 case UPIO_MEM: 437 p->serial_in = mem_serial_in; 438 p->serial_out = mem_serial_out; 439 break; 440 441 case UPIO_MEM16: 442 p->serial_in = mem16_serial_in; 443 p->serial_out = mem16_serial_out; 444 break; 445 446 case UPIO_MEM32: 447 p->serial_in = mem32_serial_in; 448 p->serial_out = mem32_serial_out; 449 break; 450 451 case UPIO_MEM32BE: 452 p->serial_in = mem32be_serial_in; 453 p->serial_out = mem32be_serial_out; 454 break; 455#ifdef CONFIG_HAS_IOPORT 456 case UPIO_PORT: 457 p->serial_in = io_serial_in; 458 p->serial_out = io_serial_out; 459 break; 460#endif 461 default: 462 WARN(p->iotype != UPIO_PORT || p->iobase, 463 "Unsupported UART type %x\n", p->iotype); 464 p->serial_in = no_serial_in; 465 p->serial_out = no_serial_out; 466 } 467 /* Remember loaded iotype */ 468 up->cur_iotype = p->iotype; 469 p->handle_irq = serial8250_default_handle_irq; 470} 471 472static void 473serial_port_out_sync(struct uart_port *p, int offset, int value) 474{ 475 switch (p->iotype) { 476 case UPIO_MEM: 477 case UPIO_MEM16: 478 case UPIO_MEM32: 479 case UPIO_MEM32BE: 480 case UPIO_AU: 481 p->serial_out(p, offset, value); 482 p->serial_in(p, UART_LCR); /* safe, no side-effects */ 483 break; 484 default: 485 p->serial_out(p, offset, value); 486 } 487} 488 489/* 490 * FIFO support. 491 */ 492void serial8250_clear_fifos(struct uart_8250_port *p) 493{ 494 if (p->capabilities & UART_CAP_FIFO) { 495 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); 496 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | 497 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 498 serial_out(p, UART_FCR, 0); 499 } 500} 501EXPORT_SYMBOL_NS_GPL(serial8250_clear_fifos, "SERIAL_8250"); 502 503static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t); 504static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t); 505 506void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) 507{ 508 serial8250_clear_fifos(p); 509 serial_out(p, UART_FCR, p->fcr); 510} 511EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); 512 513void serial8250_rpm_get(struct uart_8250_port *p) 514{ 515 if (!(p->capabilities & UART_CAP_RPM)) 516 return; 517 pm_runtime_get_sync(p->port.dev); 518} 519EXPORT_SYMBOL_GPL(serial8250_rpm_get); 520 521void serial8250_rpm_put(struct uart_8250_port *p) 522{ 523 if (!(p->capabilities & UART_CAP_RPM)) 524 return; 525 pm_runtime_mark_last_busy(p->port.dev); 526 pm_runtime_put_autosuspend(p->port.dev); 527} 528EXPORT_SYMBOL_GPL(serial8250_rpm_put); 529 530/** 531 * serial8250_em485_init() - put uart_8250_port into rs485 emulating 532 * @p: uart_8250_port port instance 533 * 534 * The function is used to start rs485 software emulating on the 535 * &struct uart_8250_port* @p. Namely, RTS is switched before/after 536 * transmission. The function is idempotent, so it is safe to call it 537 * multiple times. 538 * 539 * The caller MUST enable interrupt on empty shift register before 540 * calling serial8250_em485_init(). This interrupt is not a part of 541 * 8250 standard, but implementation defined. 542 * 543 * The function is supposed to be called from .rs485_config callback 544 * or from any other callback protected with p->port.lock spinlock. 545 * 546 * See also serial8250_em485_destroy() 547 * 548 * Return 0 - success, -errno - otherwise 549 */ 550static int serial8250_em485_init(struct uart_8250_port *p) 551{ 552 /* Port locked to synchronize UART_IER access against the console. */ 553 lockdep_assert_held_once(&p->port.lock); 554 555 if (p->em485) 556 goto deassert_rts; 557 558 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC); 559 if (!p->em485) 560 return -ENOMEM; 561 562 hrtimer_setup(&p->em485->stop_tx_timer, &serial8250_em485_handle_stop_tx, CLOCK_MONOTONIC, 563 HRTIMER_MODE_REL); 564 hrtimer_setup(&p->em485->start_tx_timer, &serial8250_em485_handle_start_tx, CLOCK_MONOTONIC, 565 HRTIMER_MODE_REL); 566 p->em485->port = p; 567 p->em485->active_timer = NULL; 568 p->em485->tx_stopped = true; 569 570deassert_rts: 571 if (p->em485->tx_stopped) 572 p->rs485_stop_tx(p, true); 573 574 return 0; 575} 576 577/** 578 * serial8250_em485_destroy() - put uart_8250_port into normal state 579 * @p: uart_8250_port port instance 580 * 581 * The function is used to stop rs485 software emulating on the 582 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to 583 * call it multiple times. 584 * 585 * The function is supposed to be called from .rs485_config callback 586 * or from any other callback protected with p->port.lock spinlock. 587 * 588 * See also serial8250_em485_init() 589 */ 590void serial8250_em485_destroy(struct uart_8250_port *p) 591{ 592 if (!p->em485) 593 return; 594 595 hrtimer_cancel(&p->em485->start_tx_timer); 596 hrtimer_cancel(&p->em485->stop_tx_timer); 597 598 kfree(p->em485); 599 p->em485 = NULL; 600} 601EXPORT_SYMBOL_GPL(serial8250_em485_destroy); 602 603struct serial_rs485 serial8250_em485_supported = { 604 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 605 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX, 606 .delay_rts_before_send = 1, 607 .delay_rts_after_send = 1, 608}; 609EXPORT_SYMBOL_GPL(serial8250_em485_supported); 610 611/** 612 * serial8250_em485_config() - generic ->rs485_config() callback 613 * @port: uart port 614 * @termios: termios structure 615 * @rs485: rs485 settings 616 * 617 * Generic callback usable by 8250 uart drivers to activate rs485 settings 618 * if the uart is incapable of driving RTS as a Transmit Enable signal in 619 * hardware, relying on software emulation instead. 620 */ 621int serial8250_em485_config(struct uart_port *port, struct ktermios *termios, 622 struct serial_rs485 *rs485) 623{ 624 struct uart_8250_port *up = up_to_u8250p(port); 625 626 /* 627 * Both serial8250_em485_init() and serial8250_em485_destroy() 628 * are idempotent. 629 */ 630 if (rs485->flags & SER_RS485_ENABLED) 631 return serial8250_em485_init(up); 632 633 serial8250_em485_destroy(up); 634 return 0; 635} 636EXPORT_SYMBOL_GPL(serial8250_em485_config); 637 638/* 639 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than 640 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is 641 * empty and the HW can idle again. 642 */ 643static void serial8250_rpm_get_tx(struct uart_8250_port *p) 644{ 645 unsigned char rpm_active; 646 647 if (!(p->capabilities & UART_CAP_RPM)) 648 return; 649 650 rpm_active = xchg(&p->rpm_tx_active, 1); 651 if (rpm_active) 652 return; 653 pm_runtime_get_sync(p->port.dev); 654} 655 656static void serial8250_rpm_put_tx(struct uart_8250_port *p) 657{ 658 unsigned char rpm_active; 659 660 if (!(p->capabilities & UART_CAP_RPM)) 661 return; 662 663 rpm_active = xchg(&p->rpm_tx_active, 0); 664 if (!rpm_active) 665 return; 666 pm_runtime_mark_last_busy(p->port.dev); 667 pm_runtime_put_autosuspend(p->port.dev); 668} 669 670/* 671 * IER sleep support. UARTs which have EFRs need the "extended 672 * capability" bit enabled. Note that on XR16C850s, we need to 673 * reset LCR to write to IER. 674 */ 675static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) 676{ 677 unsigned char lcr = 0, efr = 0; 678 679 guard(serial8250_rpm)(p); 680 681 if (!(p->capabilities & UART_CAP_SLEEP)) 682 return; 683 684 /* Synchronize UART_IER access against the console. */ 685 guard(uart_port_lock_irq)(&p->port); 686 687 if (p->capabilities & UART_CAP_EFR) { 688 lcr = serial_in(p, UART_LCR); 689 efr = serial_in(p, UART_EFR); 690 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 691 serial_out(p, UART_EFR, UART_EFR_ECB); 692 serial_out(p, UART_LCR, 0); 693 } 694 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); 695 if (p->capabilities & UART_CAP_EFR) { 696 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 697 serial_out(p, UART_EFR, efr); 698 serial_out(p, UART_LCR, lcr); 699 } 700} 701 702/* Clear the interrupt registers. */ 703static void serial8250_clear_interrupts(struct uart_port *port) 704{ 705 serial_port_in(port, UART_LSR); 706 serial_port_in(port, UART_RX); 707 serial_port_in(port, UART_IIR); 708 serial_port_in(port, UART_MSR); 709} 710 711static void serial8250_clear_IER(struct uart_8250_port *up) 712{ 713 if (up->capabilities & UART_CAP_UUE) 714 serial_out(up, UART_IER, UART_IER_UUE); 715 else 716 serial_out(up, UART_IER, 0); 717} 718 719/* 720 * This is a quickie test to see how big the FIFO is. 721 * It doesn't work at all the time, more's the pity. 722 */ 723static int size_fifo(struct uart_8250_port *up) 724{ 725 unsigned char old_fcr, old_mcr, old_lcr; 726 u32 old_dl; 727 int count; 728 729 old_lcr = serial_in(up, UART_LCR); 730 serial_out(up, UART_LCR, 0); 731 old_fcr = serial_in(up, UART_FCR); 732 old_mcr = serial8250_in_MCR(up); 733 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 734 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 735 serial8250_out_MCR(up, UART_MCR_LOOP); 736 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 737 old_dl = serial_dl_read(up); 738 serial_dl_write(up, 0x0001); 739 serial_out(up, UART_LCR, UART_LCR_WLEN8); 740 for (count = 0; count < 256; count++) 741 serial_out(up, UART_TX, count); 742 mdelay(20);/* FIXME - schedule_timeout */ 743 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && 744 (count < 256); count++) 745 serial_in(up, UART_RX); 746 serial_out(up, UART_FCR, old_fcr); 747 serial8250_out_MCR(up, old_mcr); 748 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 749 serial_dl_write(up, old_dl); 750 serial_out(up, UART_LCR, old_lcr); 751 752 return count; 753} 754 755/* 756 * Read UART ID using the divisor method - set DLL and DLM to zero 757 * and the revision will be in DLL and device type in DLM. We 758 * preserve the device state across this. 759 */ 760static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) 761{ 762 unsigned char old_lcr; 763 unsigned int id, old_dl; 764 765 old_lcr = serial_in(p, UART_LCR); 766 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); 767 old_dl = serial_dl_read(p); 768 serial_dl_write(p, 0); 769 id = serial_dl_read(p); 770 serial_dl_write(p, old_dl); 771 772 serial_out(p, UART_LCR, old_lcr); 773 774 return id; 775} 776 777/* 778 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. 779 * When this function is called we know it is at least a StarTech 780 * 16650 V2, but it might be one of several StarTech UARTs, or one of 781 * its clones. (We treat the broken original StarTech 16650 V1 as a 782 * 16550, and why not? Startech doesn't seem to even acknowledge its 783 * existence.) 784 * 785 * What evil have men's minds wrought... 786 */ 787static void autoconfig_has_efr(struct uart_8250_port *up) 788{ 789 unsigned int id1, id2, id3, rev; 790 791 /* 792 * Everything with an EFR has SLEEP 793 */ 794 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 795 796 /* 797 * First we check to see if it's an Oxford Semiconductor UART. 798 * 799 * If we have to do this here because some non-National 800 * Semiconductor clone chips lock up if you try writing to the 801 * LSR register (which serial_icr_read does) 802 */ 803 804 /* 805 * Check for Oxford Semiconductor 16C950. 806 * 807 * EFR [4] must be set else this test fails. 808 * 809 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) 810 * claims that it's needed for 952 dual UART's (which are not 811 * recommended for new designs). 812 */ 813 up->acr = 0; 814 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 815 serial_out(up, UART_EFR, UART_EFR_ECB); 816 serial_out(up, UART_LCR, 0x00); 817 id1 = serial_icr_read(up, UART_ID1); 818 id2 = serial_icr_read(up, UART_ID2); 819 id3 = serial_icr_read(up, UART_ID3); 820 rev = serial_icr_read(up, UART_REV); 821 822 if (id1 == 0x16 && id2 == 0xC9 && 823 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { 824 up->port.type = PORT_16C950; 825 826 /* 827 * Enable work around for the Oxford Semiconductor 952 rev B 828 * chip which causes it to seriously miscalculate baud rates 829 * when DLL is 0. 830 */ 831 if (id3 == 0x52 && rev == 0x01) 832 up->bugs |= UART_BUG_QUOT; 833 return; 834 } 835 836 /* 837 * We check for a XR16C850 by setting DLL and DLM to 0, and then 838 * reading back DLL and DLM. The chip type depends on the DLM 839 * value read back: 840 * 0x10 - XR16C850 and the DLL contains the chip revision. 841 * 0x12 - XR16C2850. 842 * 0x14 - XR16C854. 843 */ 844 id1 = autoconfig_read_divisor_id(up); 845 846 id2 = id1 >> 8; 847 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { 848 up->port.type = PORT_16850; 849 return; 850 } 851 852 /* 853 * It wasn't an XR16C850. 854 * 855 * We distinguish between the '654 and the '650 by counting 856 * how many bytes are in the FIFO. I'm using this for now, 857 * since that's the technique that was sent to me in the 858 * serial driver update, but I'm not convinced this works. 859 * I've had problems doing this in the past. -TYT 860 */ 861 if (size_fifo(up) == 64) 862 up->port.type = PORT_16654; 863 else 864 up->port.type = PORT_16650V2; 865} 866 867/* 868 * We detected a chip without a FIFO. Only two fall into 869 * this category - the original 8250 and the 16450. The 870 * 16450 has a scratch register (accessible with LCR=0) 871 */ 872static void autoconfig_8250(struct uart_8250_port *up) 873{ 874 unsigned char scratch, status1, status2; 875 876 up->port.type = PORT_8250; 877 878 scratch = serial_in(up, UART_SCR); 879 serial_out(up, UART_SCR, 0xa5); 880 status1 = serial_in(up, UART_SCR); 881 serial_out(up, UART_SCR, 0x5a); 882 status2 = serial_in(up, UART_SCR); 883 serial_out(up, UART_SCR, scratch); 884 885 if (status1 == 0xa5 && status2 == 0x5a) 886 up->port.type = PORT_16450; 887} 888 889static int broken_efr(struct uart_8250_port *up) 890{ 891 /* 892 * Exar ST16C2550 "A2" devices incorrectly detect as 893 * having an EFR, and report an ID of 0x0201. See 894 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 895 */ 896 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) 897 return 1; 898 899 return 0; 900} 901 902/* 903 * We know that the chip has FIFOs. Does it have an EFR? The 904 * EFR is located in the same register position as the IIR and 905 * we know the top two bits of the IIR are currently set. The 906 * EFR should contain zero. Try to read the EFR. 907 */ 908static void autoconfig_16550a(struct uart_8250_port *up) 909{ 910 unsigned char status1, status2; 911 unsigned int iersave; 912 913 /* Port locked to synchronize UART_IER access against the console. */ 914 lockdep_assert_held_once(&up->port.lock); 915 916 up->port.type = PORT_16550A; 917 up->capabilities |= UART_CAP_FIFO; 918 919 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) && 920 !(up->port.flags & UPF_FULL_PROBE)) 921 return; 922 923 /* 924 * Check for presence of the EFR when DLAB is set. 925 * Only ST16C650V1 UARTs pass this test. 926 */ 927 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 928 if (serial_in(up, UART_EFR) == 0) { 929 serial_out(up, UART_EFR, 0xA8); 930 if (serial_in(up, UART_EFR) != 0) { 931 up->port.type = PORT_16650; 932 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 933 } else { 934 serial_out(up, UART_LCR, 0); 935 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 936 UART_FCR7_64BYTE); 937 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 938 serial_out(up, UART_FCR, 0); 939 serial_out(up, UART_LCR, 0); 940 941 if (status1 == UART_IIR_FIFO_ENABLED_16750) 942 up->port.type = PORT_16550A_FSL64; 943 } 944 serial_out(up, UART_EFR, 0); 945 return; 946 } 947 948 /* 949 * Maybe it requires 0xbf to be written to the LCR. 950 * (other ST16C650V2 UARTs, TI16C752A, etc) 951 */ 952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 953 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { 954 autoconfig_has_efr(up); 955 return; 956 } 957 958 /* 959 * Check for a National Semiconductor SuperIO chip. 960 * Attempt to switch to bank 2, read the value of the LOOP bit 961 * from EXCR1. Switch back to bank 0, change it in MCR. Then 962 * switch back to bank 2, read it from EXCR1 again and check 963 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 964 */ 965 serial_out(up, UART_LCR, 0); 966 status1 = serial8250_in_MCR(up); 967 serial_out(up, UART_LCR, 0xE0); 968 status2 = serial_in(up, 0x02); /* EXCR1 */ 969 970 if (!((status2 ^ status1) & UART_MCR_LOOP)) { 971 serial_out(up, UART_LCR, 0); 972 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP); 973 serial_out(up, UART_LCR, 0xE0); 974 status2 = serial_in(up, 0x02); /* EXCR1 */ 975 serial_out(up, UART_LCR, 0); 976 serial8250_out_MCR(up, status1); 977 978 if ((status2 ^ status1) & UART_MCR_LOOP) { 979 unsigned short quot; 980 981 serial_out(up, UART_LCR, 0xE0); 982 983 quot = serial_dl_read(up); 984 quot <<= 3; 985 986 if (ns16550a_goto_highspeed(up)) 987 serial_dl_write(up, quot); 988 989 serial_out(up, UART_LCR, 0); 990 991 up->port.uartclk = 921600*16; 992 up->port.type = PORT_NS16550A; 993 up->capabilities |= UART_NATSEMI; 994 return; 995 } 996 } 997 998 /* 999 * No EFR. Try to detect a TI16750, which only sets bit 5 of 1000 * the IIR when 64 byte FIFO mode is enabled when DLAB is set. 1001 * Try setting it with and without DLAB set. Cheap clones 1002 * set bit 5 without DLAB set. 1003 */ 1004 serial_out(up, UART_LCR, 0); 1005 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1006 status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 1007 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1008 1009 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1010 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1011 status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 1012 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1013 1014 serial_out(up, UART_LCR, 0); 1015 1016 if (status1 == UART_IIR_FIFO_ENABLED_16550A && 1017 status2 == UART_IIR_FIFO_ENABLED_16750) { 1018 up->port.type = PORT_16750; 1019 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; 1020 return; 1021 } 1022 1023 /* 1024 * Try writing and reading the UART_IER_UUE bit (b6). 1025 * If it works, this is probably one of the Xscale platform's 1026 * internal UARTs. 1027 * We're going to explicitly set the UUE bit to 0 before 1028 * trying to write and read a 1 just to make sure it's not 1029 * already a 1 and maybe locked there before we even start. 1030 */ 1031 iersave = serial_in(up, UART_IER); 1032 serial_out(up, UART_IER, iersave & ~UART_IER_UUE); 1033 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { 1034 /* 1035 * OK it's in a known zero state, try writing and reading 1036 * without disturbing the current state of the other bits. 1037 */ 1038 serial_out(up, UART_IER, iersave | UART_IER_UUE); 1039 if (serial_in(up, UART_IER) & UART_IER_UUE) { 1040 /* 1041 * It's an Xscale. 1042 * We'll leave the UART_IER_UUE bit set to 1 (enabled). 1043 */ 1044 up->port.type = PORT_XSCALE; 1045 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; 1046 return; 1047 } 1048 } 1049 serial_out(up, UART_IER, iersave); 1050 1051 /* 1052 * We distinguish between 16550A and U6 16550A by counting 1053 * how many bytes are in the FIFO. 1054 */ 1055 if (up->port.type == PORT_16550A && size_fifo(up) == 64) { 1056 up->port.type = PORT_U6_16550A; 1057 up->capabilities |= UART_CAP_AFE; 1058 } 1059} 1060 1061/* 1062 * This routine is called by rs_init() to initialize a specific serial 1063 * port. It determines what type of UART chip this serial port is 1064 * using: 8250, 16450, 16550, 16550A. The important question is 1065 * whether or not this UART is a 16550A or not, since this will 1066 * determine whether or not we can use its FIFO features or not. 1067 */ 1068static void autoconfig(struct uart_8250_port *up) 1069{ 1070 unsigned char status1, scratch, scratch2, scratch3; 1071 unsigned char save_lcr, save_mcr; 1072 struct uart_port *port = &up->port; 1073 unsigned long flags; 1074 unsigned int old_capabilities; 1075 1076 if (!port->iobase && !port->mapbase && !port->membase) 1077 return; 1078 1079 /* 1080 * We really do need global IRQs disabled here - we're going to 1081 * be frobbing the chips IRQ enable register to see if it exists. 1082 * 1083 * Synchronize UART_IER access against the console. 1084 */ 1085 uart_port_lock_irqsave(port, &flags); 1086 1087 up->capabilities = 0; 1088 up->bugs = 0; 1089 1090 if (!(port->flags & UPF_BUGGY_UART)) { 1091 /* 1092 * Do a simple existence test first; if we fail this, 1093 * there's no point trying anything else. 1094 * 1095 * 0x80 is used as a nonsense port to prevent against 1096 * false positives due to ISA bus float. The 1097 * assumption is that 0x80 is a non-existent port; 1098 * which should be safe since include/asm/io.h also 1099 * makes this assumption. 1100 * 1101 * Note: this is safe as long as MCR bit 4 is clear 1102 * and the device is in "PC" mode. 1103 */ 1104 scratch = serial_in(up, UART_IER); 1105 serial_out(up, UART_IER, 0); 1106#if defined(__i386__) && defined(CONFIG_HAS_IOPORT) 1107 outb(0xff, 0x080); 1108#endif 1109 /* 1110 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL 1111 * 16C754B) allow only to modify them if an EFR bit is set. 1112 */ 1113 scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR; 1114 serial_out(up, UART_IER, UART_IER_ALL_INTR); 1115#if defined(__i386__) && defined(CONFIG_HAS_IOPORT) 1116 outb(0, 0x080); 1117#endif 1118 scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR; 1119 serial_out(up, UART_IER, scratch); 1120 if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) { 1121 /* 1122 * We failed; there's nothing here 1123 */ 1124 uart_port_unlock_irqrestore(port, flags); 1125 return; 1126 } 1127 } 1128 1129 save_mcr = serial8250_in_MCR(up); 1130 save_lcr = serial_in(up, UART_LCR); 1131 1132 /* 1133 * Check to see if a UART is really there. Certain broken 1134 * internal modems based on the Rockwell chipset fail this 1135 * test, because they apparently don't implement the loopback 1136 * test mode. So this test is skipped on the COM 1 through 1137 * COM 4 ports. This *should* be safe, since no board 1138 * manufacturer would be stupid enough to design a board 1139 * that conflicts with COM 1-4 --- we hope! 1140 */ 1141 if (!(port->flags & UPF_SKIP_TEST)) { 1142 serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS); 1143 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS; 1144 serial8250_out_MCR(up, save_mcr); 1145 if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) { 1146 uart_port_unlock_irqrestore(port, flags); 1147 return; 1148 } 1149 } 1150 1151 /* 1152 * We're pretty sure there's a port here. Lets find out what 1153 * type of port it is. The IIR top two bits allows us to find 1154 * out if it's 8250 or 16450, 16550, 16550A or later. This 1155 * determines what we test for next. 1156 * 1157 * We also initialise the EFR (if any) to zero for later. The 1158 * EFR occupies the same register location as the FCR and IIR. 1159 */ 1160 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1161 serial_out(up, UART_EFR, 0); 1162 serial_out(up, UART_LCR, 0); 1163 1164 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1165 1166 switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) { 1167 case UART_IIR_FIFO_ENABLED_8250: 1168 autoconfig_8250(up); 1169 break; 1170 case UART_IIR_FIFO_ENABLED_16550: 1171 port->type = PORT_16550; 1172 break; 1173 case UART_IIR_FIFO_ENABLED_16550A: 1174 autoconfig_16550a(up); 1175 break; 1176 default: 1177 port->type = PORT_UNKNOWN; 1178 break; 1179 } 1180 1181 rsa_autoconfig(up); 1182 1183 serial_out(up, UART_LCR, save_lcr); 1184 1185 port->fifosize = uart_config[up->port.type].fifo_size; 1186 old_capabilities = up->capabilities; 1187 up->capabilities = uart_config[port->type].flags; 1188 up->tx_loadsz = uart_config[port->type].tx_loadsz; 1189 1190 if (port->type != PORT_UNKNOWN) { 1191 /* 1192 * Reset the UART. 1193 */ 1194 rsa_reset(up); 1195 serial8250_out_MCR(up, save_mcr); 1196 serial8250_clear_fifos(up); 1197 serial_in(up, UART_RX); 1198 serial8250_clear_IER(up); 1199 } 1200 1201 uart_port_unlock_irqrestore(port, flags); 1202 1203 /* 1204 * Check if the device is a Fintek F81216A 1205 */ 1206 if (port->type == PORT_16550A && port->iotype == UPIO_PORT) 1207 fintek_8250_probe(up); 1208 1209 if (up->capabilities != old_capabilities) { 1210 dev_warn(port->dev, "detected caps %08x should be %08x\n", 1211 old_capabilities, up->capabilities); 1212 } 1213} 1214 1215static void autoconfig_irq(struct uart_8250_port *up) 1216{ 1217 struct uart_port *port = &up->port; 1218 unsigned char save_mcr, save_ier; 1219 unsigned char save_ICP = 0; 1220 unsigned int ICP = 0; 1221 unsigned long irqs; 1222 int irq; 1223 1224 if (port->flags & UPF_FOURPORT) { 1225 ICP = (port->iobase & 0xfe0) | 0x1f; 1226 save_ICP = inb_p(ICP); 1227 outb_p(0x80, ICP); 1228 inb_p(ICP); 1229 } 1230 1231 /* forget possible initially masked and pending IRQ */ 1232 probe_irq_off(probe_irq_on()); 1233 save_mcr = serial8250_in_MCR(up); 1234 /* Synchronize UART_IER access against the console. */ 1235 scoped_guard(uart_port_lock_irq, port) 1236 save_ier = serial_in(up, UART_IER); 1237 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2); 1238 1239 irqs = probe_irq_on(); 1240 serial8250_out_MCR(up, 0); 1241 udelay(10); 1242 if (port->flags & UPF_FOURPORT) { 1243 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS); 1244 } else { 1245 serial8250_out_MCR(up, 1246 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1247 } 1248 /* Synchronize UART_IER access against the console. */ 1249 scoped_guard(uart_port_lock_irq, port) 1250 serial_out(up, UART_IER, UART_IER_ALL_INTR); 1251 serial8250_clear_interrupts(port); 1252 serial_out(up, UART_TX, 0xFF); 1253 udelay(20); 1254 irq = probe_irq_off(irqs); 1255 1256 serial8250_out_MCR(up, save_mcr); 1257 /* Synchronize UART_IER access against the console. */ 1258 scoped_guard(uart_port_lock_irq, port) 1259 serial_out(up, UART_IER, save_ier); 1260 1261 if (port->flags & UPF_FOURPORT) 1262 outb_p(save_ICP, ICP); 1263 1264 port->irq = (irq > 0) ? irq : 0; 1265} 1266 1267static void serial8250_stop_rx(struct uart_port *port) 1268{ 1269 struct uart_8250_port *up = up_to_u8250p(port); 1270 1271 /* Port locked to synchronize UART_IER access against the console. */ 1272 lockdep_assert_held_once(&port->lock); 1273 1274 guard(serial8250_rpm)(up); 1275 1276 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1277 serial_port_out(port, UART_IER, up->ier); 1278} 1279 1280/** 1281 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback 1282 * @p: uart 8250 port 1283 * @toggle_ier: true to allow enabling receive interrupts 1284 * 1285 * Generic callback usable by 8250 uart drivers to stop rs485 transmission. 1286 */ 1287void serial8250_em485_stop_tx(struct uart_8250_port *p, bool toggle_ier) 1288{ 1289 unsigned char mcr = serial8250_in_MCR(p); 1290 1291 /* Port locked to synchronize UART_IER access against the console. */ 1292 lockdep_assert_held_once(&p->port.lock); 1293 1294 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND) 1295 mcr |= UART_MCR_RTS; 1296 else 1297 mcr &= ~UART_MCR_RTS; 1298 serial8250_out_MCR(p, mcr); 1299 1300 /* 1301 * Empty the RX FIFO, we are not interested in anything 1302 * received during the half-duplex transmission. 1303 * Enable previously disabled RX interrupts. 1304 */ 1305 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) { 1306 serial8250_clear_and_reinit_fifos(p); 1307 1308 if (toggle_ier) { 1309 p->ier |= UART_IER_RLSI | UART_IER_RDI; 1310 serial_port_out(&p->port, UART_IER, p->ier); 1311 } 1312 } 1313} 1314EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx); 1315 1316static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t) 1317{ 1318 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485, 1319 stop_tx_timer); 1320 struct uart_8250_port *p = em485->port; 1321 1322 guard(serial8250_rpm)(p); 1323 guard(uart_port_lock_irqsave)(&p->port); 1324 1325 if (em485->active_timer == &em485->stop_tx_timer) { 1326 p->rs485_stop_tx(p, true); 1327 em485->active_timer = NULL; 1328 em485->tx_stopped = true; 1329 } 1330 1331 return HRTIMER_NORESTART; 1332} 1333 1334static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) 1335{ 1336 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); 1337} 1338 1339static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay) 1340{ 1341 struct uart_8250_em485 *em485 = p->em485; 1342 1343 /* Port locked to synchronize UART_IER access against the console. */ 1344 lockdep_assert_held_once(&p->port.lock); 1345 1346 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC; 1347 1348 /* 1349 * rs485_stop_tx() is going to set RTS according to config 1350 * AND flush RX FIFO if required. 1351 */ 1352 if (stop_delay > 0) { 1353 em485->active_timer = &em485->stop_tx_timer; 1354 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL); 1355 } else { 1356 p->rs485_stop_tx(p, true); 1357 em485->active_timer = NULL; 1358 em485->tx_stopped = true; 1359 } 1360} 1361 1362static inline void __stop_tx(struct uart_8250_port *p) 1363{ 1364 struct uart_8250_em485 *em485 = p->em485; 1365 1366 if (em485) { 1367 u16 lsr = serial_lsr_in(p); 1368 u64 stop_delay = 0; 1369 1370 if (!(lsr & UART_LSR_THRE)) 1371 return; 1372 /* 1373 * To provide required timing and allow FIFO transfer, 1374 * __stop_tx_rs485() must be called only when both FIFO and 1375 * shift register are empty. The device driver should either 1376 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will 1377 * enlarge stop_tx_timer by the tx time of one frame to cover 1378 * for emptying of the shift register. 1379 */ 1380 if (!(lsr & UART_LSR_TEMT)) { 1381 if (!(p->capabilities & UART_CAP_NOTEMT)) 1382 return; 1383 /* 1384 * RTS might get deasserted too early with the normal 1385 * frame timing formula. It seems to suggest THRE might 1386 * get asserted already during tx of the stop bit 1387 * rather than after it is fully sent. 1388 * Roughly estimate 1 extra bit here with / 7. 1389 */ 1390 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7); 1391 } 1392 1393 __stop_tx_rs485(p, stop_delay); 1394 } 1395 1396 if (serial8250_clear_THRI(p)) 1397 serial8250_rpm_put_tx(p); 1398} 1399 1400static void serial8250_stop_tx(struct uart_port *port) 1401{ 1402 struct uart_8250_port *up = up_to_u8250p(port); 1403 1404 guard(serial8250_rpm)(up); 1405 __stop_tx(up); 1406 1407 /* 1408 * We really want to stop the transmitter from sending. 1409 */ 1410 if (port->type == PORT_16C950) { 1411 up->acr |= UART_ACR_TXDIS; 1412 serial_icr_write(up, UART_ACR, up->acr); 1413 } 1414} 1415 1416static inline void __start_tx(struct uart_port *port) 1417{ 1418 struct uart_8250_port *up = up_to_u8250p(port); 1419 1420 if (up->dma && !up->dma->tx_dma(up)) 1421 return; 1422 1423 if (serial8250_set_THRI(up)) { 1424 if (up->bugs & UART_BUG_TXEN) { 1425 u16 lsr = serial_lsr_in(up); 1426 1427 if (lsr & UART_LSR_THRE) 1428 serial8250_tx_chars(up); 1429 } 1430 } 1431 1432 /* 1433 * Re-enable the transmitter if we disabled it. 1434 */ 1435 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 1436 up->acr &= ~UART_ACR_TXDIS; 1437 serial_icr_write(up, UART_ACR, up->acr); 1438 } 1439} 1440 1441/** 1442 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback 1443 * @up: uart 8250 port 1444 * @toggle_ier: true to allow disabling receive interrupts 1445 * 1446 * Generic callback usable by 8250 uart drivers to start rs485 transmission. 1447 * Assumes that setting the RTS bit in the MCR register means RTS is high. 1448 * (Some chips use inverse semantics.) Further assumes that reception is 1449 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the 1450 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.) 1451 */ 1452void serial8250_em485_start_tx(struct uart_8250_port *up, bool toggle_ier) 1453{ 1454 unsigned char mcr = serial8250_in_MCR(up); 1455 1456 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && toggle_ier) 1457 serial8250_stop_rx(&up->port); 1458 1459 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) 1460 mcr |= UART_MCR_RTS; 1461 else 1462 mcr &= ~UART_MCR_RTS; 1463 serial8250_out_MCR(up, mcr); 1464} 1465EXPORT_SYMBOL_GPL(serial8250_em485_start_tx); 1466 1467/* Returns false, if start_tx_timer was setup to defer TX start */ 1468static bool start_tx_rs485(struct uart_port *port) 1469{ 1470 struct uart_8250_port *up = up_to_u8250p(port); 1471 struct uart_8250_em485 *em485 = up->em485; 1472 1473 /* 1474 * While serial8250_em485_handle_stop_tx() is a noop if 1475 * em485->active_timer != &em485->stop_tx_timer, it might happen that 1476 * the timer is still armed and triggers only after the current bunch of 1477 * chars is send and em485->active_timer == &em485->stop_tx_timer again. 1478 * So cancel the timer. There is still a theoretical race condition if 1479 * the timer is already running and only comes around to check for 1480 * em485->active_timer when &em485->stop_tx_timer is armed again. 1481 */ 1482 if (em485->active_timer == &em485->stop_tx_timer) 1483 hrtimer_try_to_cancel(&em485->stop_tx_timer); 1484 1485 em485->active_timer = NULL; 1486 1487 if (em485->tx_stopped) { 1488 em485->tx_stopped = false; 1489 1490 up->rs485_start_tx(up, true); 1491 1492 if (up->port.rs485.delay_rts_before_send > 0) { 1493 em485->active_timer = &em485->start_tx_timer; 1494 start_hrtimer_ms(&em485->start_tx_timer, 1495 up->port.rs485.delay_rts_before_send); 1496 return false; 1497 } 1498 } 1499 1500 return true; 1501} 1502 1503static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t) 1504{ 1505 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485, 1506 start_tx_timer); 1507 struct uart_8250_port *p = em485->port; 1508 1509 guard(uart_port_lock_irqsave)(&p->port); 1510 1511 if (em485->active_timer == &em485->start_tx_timer) { 1512 __start_tx(&p->port); 1513 em485->active_timer = NULL; 1514 } 1515 1516 return HRTIMER_NORESTART; 1517} 1518 1519static void serial8250_start_tx(struct uart_port *port) 1520{ 1521 struct uart_8250_port *up = up_to_u8250p(port); 1522 struct uart_8250_em485 *em485 = up->em485; 1523 1524 /* Port locked to synchronize UART_IER access against the console. */ 1525 lockdep_assert_held_once(&port->lock); 1526 1527 if (!port->x_char && kfifo_is_empty(&port->state->port.xmit_fifo)) 1528 return; 1529 1530 serial8250_rpm_get_tx(up); 1531 1532 if (em485) { 1533 if ((em485->active_timer == &em485->start_tx_timer) || 1534 !start_tx_rs485(port)) 1535 return; 1536 } 1537 __start_tx(port); 1538} 1539 1540static void serial8250_throttle(struct uart_port *port) 1541{ 1542 port->throttle(port); 1543} 1544 1545static void serial8250_unthrottle(struct uart_port *port) 1546{ 1547 port->unthrottle(port); 1548} 1549 1550static void serial8250_disable_ms(struct uart_port *port) 1551{ 1552 struct uart_8250_port *up = up_to_u8250p(port); 1553 1554 /* Port locked to synchronize UART_IER access against the console. */ 1555 lockdep_assert_held_once(&port->lock); 1556 1557 /* no MSR capabilities */ 1558 if (up->bugs & UART_BUG_NOMSR) 1559 return; 1560 1561 mctrl_gpio_disable_ms_no_sync(up->gpios); 1562 1563 up->ier &= ~UART_IER_MSI; 1564 serial_port_out(port, UART_IER, up->ier); 1565} 1566 1567static void serial8250_enable_ms(struct uart_port *port) 1568{ 1569 struct uart_8250_port *up = up_to_u8250p(port); 1570 1571 /* Port locked to synchronize UART_IER access against the console. */ 1572 lockdep_assert_held_once(&port->lock); 1573 1574 /* no MSR capabilities */ 1575 if (up->bugs & UART_BUG_NOMSR) 1576 return; 1577 1578 mctrl_gpio_enable_ms(up->gpios); 1579 1580 up->ier |= UART_IER_MSI; 1581 1582 guard(serial8250_rpm)(up); 1583 serial_port_out(port, UART_IER, up->ier); 1584} 1585 1586void serial8250_read_char(struct uart_8250_port *up, u16 lsr) 1587{ 1588 struct uart_port *port = &up->port; 1589 u8 ch, flag = TTY_NORMAL; 1590 1591 if (likely(lsr & UART_LSR_DR)) 1592 ch = serial_in(up, UART_RX); 1593 else 1594 /* 1595 * Intel 82571 has a Serial Over Lan device that will 1596 * set UART_LSR_BI without setting UART_LSR_DR when 1597 * it receives a break. To avoid reading from the 1598 * receive buffer without UART_LSR_DR bit set, we 1599 * just force the read character to be 0 1600 */ 1601 ch = 0; 1602 1603 port->icount.rx++; 1604 1605 lsr |= up->lsr_saved_flags; 1606 up->lsr_saved_flags = 0; 1607 1608 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 1609 if (lsr & UART_LSR_BI) { 1610 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 1611 port->icount.brk++; 1612 /* 1613 * We do the SysRQ and SAK checking 1614 * here because otherwise the break 1615 * may get masked by ignore_status_mask 1616 * or read_status_mask. 1617 */ 1618 if (uart_handle_break(port)) 1619 return; 1620 } else if (lsr & UART_LSR_PE) 1621 port->icount.parity++; 1622 else if (lsr & UART_LSR_FE) 1623 port->icount.frame++; 1624 if (lsr & UART_LSR_OE) 1625 port->icount.overrun++; 1626 1627 /* 1628 * Mask off conditions which should be ignored. 1629 */ 1630 lsr &= port->read_status_mask; 1631 1632 if (lsr & UART_LSR_BI) { 1633 dev_dbg(port->dev, "handling break\n"); 1634 flag = TTY_BREAK; 1635 } else if (lsr & UART_LSR_PE) 1636 flag = TTY_PARITY; 1637 else if (lsr & UART_LSR_FE) 1638 flag = TTY_FRAME; 1639 } 1640 if (uart_prepare_sysrq_char(port, ch)) 1641 return; 1642 1643 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); 1644} 1645EXPORT_SYMBOL_GPL(serial8250_read_char); 1646 1647/* 1648 * serial8250_rx_chars - Read characters. The first LSR value must be passed in. 1649 * 1650 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits 1651 * (such as THRE) because the LSR value might come from an already consumed 1652 * character. 1653 */ 1654u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr) 1655{ 1656 struct uart_port *port = &up->port; 1657 int max_count = 256; 1658 1659 do { 1660 serial8250_read_char(up, lsr); 1661 if (--max_count == 0) 1662 break; 1663 lsr = serial_in(up, UART_LSR); 1664 } while (lsr & (UART_LSR_DR | UART_LSR_BI)); 1665 1666 tty_flip_buffer_push(&port->state->port); 1667 return lsr; 1668} 1669EXPORT_SYMBOL_GPL(serial8250_rx_chars); 1670 1671void serial8250_tx_chars(struct uart_8250_port *up) 1672{ 1673 struct uart_port *port = &up->port; 1674 struct tty_port *tport = &port->state->port; 1675 int count; 1676 1677 if (port->x_char) { 1678 uart_xchar_out(port, UART_TX); 1679 return; 1680 } 1681 if (uart_tx_stopped(port)) { 1682 serial8250_stop_tx(port); 1683 return; 1684 } 1685 if (kfifo_is_empty(&tport->xmit_fifo)) { 1686 __stop_tx(up); 1687 return; 1688 } 1689 1690 count = up->tx_loadsz; 1691 do { 1692 unsigned char c; 1693 1694 if (!uart_fifo_get(port, &c)) 1695 break; 1696 1697 serial_out(up, UART_TX, c); 1698 if (up->bugs & UART_BUG_TXRACE) { 1699 /* 1700 * The Aspeed BMC virtual UARTs have a bug where data 1701 * may get stuck in the BMC's Tx FIFO from bursts of 1702 * writes on the APB interface. 1703 * 1704 * Delay back-to-back writes by a read cycle to avoid 1705 * stalling the VUART. Read a register that won't have 1706 * side-effects and discard the result. 1707 */ 1708 serial_in(up, UART_SCR); 1709 } 1710 1711 if ((up->capabilities & UART_CAP_HFIFO) && 1712 !uart_lsr_tx_empty(serial_in(up, UART_LSR))) 1713 break; 1714 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */ 1715 if ((up->capabilities & UART_CAP_MINI) && 1716 !(serial_in(up, UART_LSR) & UART_LSR_THRE)) 1717 break; 1718 } while (--count > 0); 1719 1720 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1721 uart_write_wakeup(port); 1722 1723 /* 1724 * With RPM enabled, we have to wait until the FIFO is empty before the 1725 * HW can go idle. So we get here once again with empty FIFO and disable 1726 * the interrupt and RPM in __stop_tx() 1727 */ 1728 if (kfifo_is_empty(&tport->xmit_fifo) && 1729 !(up->capabilities & UART_CAP_RPM)) 1730 __stop_tx(up); 1731} 1732EXPORT_SYMBOL_GPL(serial8250_tx_chars); 1733 1734/* Caller holds uart port lock */ 1735unsigned int serial8250_modem_status(struct uart_8250_port *up) 1736{ 1737 struct uart_port *port = &up->port; 1738 unsigned int status = serial_in(up, UART_MSR); 1739 1740 status |= up->msr_saved_flags; 1741 up->msr_saved_flags = 0; 1742 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 1743 port->state != NULL) { 1744 if (status & UART_MSR_TERI) 1745 port->icount.rng++; 1746 if (status & UART_MSR_DDSR) 1747 port->icount.dsr++; 1748 if (status & UART_MSR_DDCD) 1749 uart_handle_dcd_change(port, status & UART_MSR_DCD); 1750 if (status & UART_MSR_DCTS) 1751 uart_handle_cts_change(port, status & UART_MSR_CTS); 1752 1753 wake_up_interruptible(&port->state->port.delta_msr_wait); 1754 } 1755 1756 return status; 1757} 1758EXPORT_SYMBOL_GPL(serial8250_modem_status); 1759 1760static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1761{ 1762 switch (iir & 0x3f) { 1763 case UART_IIR_THRI: 1764 /* 1765 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT 1766 * because it's impossible to do an informed decision about 1767 * that with IIR_THRI. 1768 * 1769 * This also fixes one known DMA Rx corruption issue where 1770 * DR is asserted but DMA Rx only gets a corrupted zero byte 1771 * (too early DR?). 1772 */ 1773 return false; 1774 case UART_IIR_RDI: 1775 if (!up->dma->rx_running) 1776 break; 1777 fallthrough; 1778 case UART_IIR_RLSI: 1779 case UART_IIR_RX_TIMEOUT: 1780 serial8250_rx_dma_flush(up); 1781 return true; 1782 } 1783 return up->dma->rx_dma(up); 1784} 1785 1786/* 1787 * Context: port's lock must be held by the caller. 1788 */ 1789void serial8250_handle_irq_locked(struct uart_port *port, unsigned int iir) 1790{ 1791 struct uart_8250_port *up = up_to_u8250p(port); 1792 struct tty_port *tport = &port->state->port; 1793 bool skip_rx = false; 1794 u16 status; 1795 1796 lockdep_assert_held_once(&port->lock); 1797 1798 status = serial_lsr_in(up); 1799 1800 /* 1801 * If port is stopped and there are no error conditions in the 1802 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer 1803 * overflow. Not servicing, RX FIFO would trigger auto HW flow 1804 * control when FIFO occupancy reaches preset threshold, thus 1805 * halting RX. This only works when auto HW flow control is 1806 * available. 1807 */ 1808 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) && 1809 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) && 1810 !(up->ier & (UART_IER_RLSI | UART_IER_RDI))) 1811 skip_rx = true; 1812 1813 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) { 1814 struct irq_data *d; 1815 1816 d = irq_get_irq_data(port->irq); 1817 if (d && irqd_is_wakeup_set(d)) 1818 pm_wakeup_event(tport->tty->dev, 0); 1819 if (!up->dma || handle_rx_dma(up, iir)) 1820 status = serial8250_rx_chars(up, status); 1821 } 1822 serial8250_modem_status(up); 1823 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) { 1824 if (!up->dma || up->dma->tx_err) 1825 serial8250_tx_chars(up); 1826 else if (!up->dma->tx_running) 1827 __stop_tx(up); 1828 } 1829} 1830EXPORT_SYMBOL_NS_GPL(serial8250_handle_irq_locked, "SERIAL_8250"); 1831 1832/* 1833 * This handles the interrupt from one port. 1834 */ 1835int serial8250_handle_irq(struct uart_port *port, unsigned int iir) 1836{ 1837 if (iir & UART_IIR_NO_INT) 1838 return 0; 1839 1840 guard(uart_port_lock_irqsave)(port); 1841 serial8250_handle_irq_locked(port, iir); 1842 1843 return 1; 1844} 1845EXPORT_SYMBOL_GPL(serial8250_handle_irq); 1846 1847static int serial8250_default_handle_irq(struct uart_port *port) 1848{ 1849 struct uart_8250_port *up = up_to_u8250p(port); 1850 unsigned int iir; 1851 1852 guard(serial8250_rpm)(up); 1853 1854 iir = serial_port_in(port, UART_IIR); 1855 return serial8250_handle_irq(port, iir); 1856} 1857 1858/* 1859 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP 1860 * have a programmable TX threshold that triggers the THRE interrupt in 1861 * the IIR register. In this case, the THRE interrupt indicates the FIFO 1862 * has space available. Load it up with tx_loadsz bytes. 1863 */ 1864static int serial8250_tx_threshold_handle_irq(struct uart_port *port) 1865{ 1866 unsigned int iir = serial_port_in(port, UART_IIR); 1867 1868 /* TX Threshold IRQ triggered so load up FIFO */ 1869 if ((iir & UART_IIR_ID) == UART_IIR_THRI) { 1870 struct uart_8250_port *up = up_to_u8250p(port); 1871 1872 guard(uart_port_lock_irqsave)(port); 1873 serial8250_tx_chars(up); 1874 } 1875 1876 iir = serial_port_in(port, UART_IIR); 1877 return serial8250_handle_irq(port, iir); 1878} 1879 1880static unsigned int serial8250_tx_empty(struct uart_port *port) 1881{ 1882 struct uart_8250_port *up = up_to_u8250p(port); 1883 1884 guard(serial8250_rpm)(up); 1885 guard(uart_port_lock_irqsave)(port); 1886 1887 if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up))) 1888 return TIOCSER_TEMT; 1889 1890 return 0; 1891} 1892 1893unsigned int serial8250_do_get_mctrl(struct uart_port *port) 1894{ 1895 struct uart_8250_port *up = up_to_u8250p(port); 1896 unsigned int status; 1897 unsigned int val; 1898 1899 scoped_guard(serial8250_rpm, up) 1900 status = serial8250_modem_status(up); 1901 1902 val = serial8250_MSR_to_TIOCM(status); 1903 if (up->gpios) 1904 return mctrl_gpio_get(up->gpios, &val); 1905 1906 return val; 1907} 1908EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl); 1909 1910static unsigned int serial8250_get_mctrl(struct uart_port *port) 1911{ 1912 if (port->get_mctrl) 1913 return port->get_mctrl(port); 1914 return serial8250_do_get_mctrl(port); 1915} 1916 1917void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl) 1918{ 1919 struct uart_8250_port *up = up_to_u8250p(port); 1920 unsigned char mcr; 1921 1922 mcr = serial8250_TIOCM_to_MCR(mctrl); 1923 1924 mcr |= up->mcr; 1925 1926 serial8250_out_MCR(up, mcr); 1927} 1928EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl); 1929 1930static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 1931{ 1932 if (port->rs485.flags & SER_RS485_ENABLED) 1933 return; 1934 1935 if (port->set_mctrl) 1936 port->set_mctrl(port, mctrl); 1937 else 1938 serial8250_do_set_mctrl(port, mctrl); 1939} 1940 1941static void serial8250_break_ctl(struct uart_port *port, int break_state) 1942{ 1943 struct uart_8250_port *up = up_to_u8250p(port); 1944 1945 guard(serial8250_rpm)(up); 1946 guard(uart_port_lock_irqsave)(port); 1947 1948 if (break_state == -1) 1949 up->lcr |= UART_LCR_SBC; 1950 else 1951 up->lcr &= ~UART_LCR_SBC; 1952 serial_port_out(port, UART_LCR, up->lcr); 1953} 1954 1955/* Returns true if @bits were set, false on timeout */ 1956static bool wait_for_lsr(struct uart_8250_port *up, int bits) 1957{ 1958 unsigned int status, tmout; 1959 1960 /* 1961 * Wait for a character to be sent. Fallback to a safe default 1962 * timeout value if @frame_time is not available. 1963 */ 1964 if (up->port.frame_time) 1965 tmout = up->port.frame_time * 2 / NSEC_PER_USEC; 1966 else 1967 tmout = 10000; 1968 1969 for (;;) { 1970 status = serial_lsr_in(up); 1971 1972 if ((status & bits) == bits) 1973 break; 1974 if (--tmout == 0) 1975 break; 1976 udelay(1); 1977 touch_nmi_watchdog(); 1978 } 1979 1980 return (tmout != 0); 1981} 1982 1983/* Wait for transmitter and holding register to empty with timeout */ 1984static void wait_for_xmitr(struct uart_8250_port *up, int bits) 1985{ 1986 unsigned int tmout; 1987 1988 wait_for_lsr(up, bits); 1989 1990 /* Wait up to 1s for flow control if necessary */ 1991 if (up->port.flags & UPF_CONS_FLOW) { 1992 for (tmout = 1000000; tmout; tmout--) { 1993 unsigned int msr = serial_in(up, UART_MSR); 1994 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1995 if (msr & UART_MSR_CTS) 1996 break; 1997 udelay(1); 1998 touch_nmi_watchdog(); 1999 } 2000 } 2001} 2002 2003#ifdef CONFIG_CONSOLE_POLL 2004/* 2005 * Console polling routines for writing and reading from the uart while 2006 * in an interrupt or debug context. 2007 */ 2008 2009static int serial8250_get_poll_char(struct uart_port *port) 2010{ 2011 struct uart_8250_port *up = up_to_u8250p(port); 2012 u16 lsr; 2013 2014 guard(serial8250_rpm)(up); 2015 2016 lsr = serial_port_in(port, UART_LSR); 2017 if (!(lsr & UART_LSR_DR)) 2018 return NO_POLL_CHAR; 2019 2020 return serial_port_in(port, UART_RX); 2021} 2022 2023 2024static void serial8250_put_poll_char(struct uart_port *port, 2025 unsigned char c) 2026{ 2027 unsigned int ier; 2028 struct uart_8250_port *up = up_to_u8250p(port); 2029 2030 /* 2031 * Normally the port is locked to synchronize UART_IER access 2032 * against the console. However, this function is only used by 2033 * KDB/KGDB, where it may not be possible to acquire the port 2034 * lock because all other CPUs are quiesced. The quiescence 2035 * should allow safe lockless usage here. 2036 */ 2037 2038 guard(serial8250_rpm)(up); 2039 /* 2040 * First save the IER then disable the interrupts 2041 */ 2042 ier = serial_port_in(port, UART_IER); 2043 serial8250_clear_IER(up); 2044 2045 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY); 2046 /* 2047 * Send the character out. 2048 */ 2049 serial_port_out(port, UART_TX, c); 2050 2051 /* 2052 * Finally, wait for transmitter to become empty 2053 * and restore the IER 2054 */ 2055 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY); 2056 serial_port_out(port, UART_IER, ier); 2057} 2058 2059#endif /* CONFIG_CONSOLE_POLL */ 2060 2061static void serial8250_startup_special(struct uart_port *port) 2062{ 2063 struct uart_8250_port *up = up_to_u8250p(port); 2064 2065 switch (port->type) { 2066 case PORT_16C950: { 2067 /* 2068 * Wake up and initialize UART 2069 * 2070 * Synchronize UART_IER access against the console. 2071 */ 2072 guard(uart_port_lock_irqsave)(port); 2073 up->acr = 0; 2074 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2075 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2076 serial_port_out(port, UART_IER, 0); 2077 serial_port_out(port, UART_LCR, 0); 2078 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 2079 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2080 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2081 serial_port_out(port, UART_LCR, 0); 2082 break; 2083 } 2084 case PORT_DA830: 2085 /* 2086 * Reset the port 2087 * 2088 * Synchronize UART_IER access against the console. 2089 */ 2090 scoped_guard(uart_port_lock_irqsave, port) { 2091 serial_port_out(port, UART_IER, 0); 2092 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0); 2093 } 2094 mdelay(10); 2095 2096 /* Enable Tx, Rx and free run mode */ 2097 serial_port_out(port, UART_DA830_PWREMU_MGMT, 2098 UART_DA830_PWREMU_MGMT_UTRST | 2099 UART_DA830_PWREMU_MGMT_URRST | 2100 UART_DA830_PWREMU_MGMT_FREE); 2101 break; 2102 case PORT_RSA: 2103 rsa_enable(up); 2104 break; 2105 } 2106} 2107 2108static void serial8250_set_TRG_levels(struct uart_port *port) 2109{ 2110 struct uart_8250_port *up = up_to_u8250p(port); 2111 2112 switch (port->type) { 2113 /* For a XR16C850, we need to set the trigger levels */ 2114 case PORT_16850: { 2115 u8 fctr; 2116 2117 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 2118 2119 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); 2120 fctr |= UART_FCTR_TRGD; 2121 serial_port_out(port, UART_FCTR, fctr | UART_FCTR_RX); 2122 serial_port_out(port, UART_TRG, UART_TRG_96); 2123 serial_port_out(port, UART_FCTR, fctr | UART_FCTR_TX); 2124 serial_port_out(port, UART_TRG, UART_TRG_96); 2125 2126 serial_port_out(port, UART_LCR, 0); 2127 break; 2128 } 2129 /* For the Altera 16550 variants, set TX threshold trigger level. */ 2130 case PORT_ALTR_16550_F32: 2131 case PORT_ALTR_16550_F64: 2132 case PORT_ALTR_16550_F128: 2133 if (port->fifosize <= 1) 2134 return; 2135 2136 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */ 2137 if (up->tx_loadsz < 2 || up->tx_loadsz > port->fifosize) { 2138 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n"); 2139 return; 2140 } 2141 serial_port_out(port, UART_ALTR_AFR, UART_ALTR_EN_TXFIFO_LW); 2142 serial_port_out(port, UART_ALTR_TX_LOW, port->fifosize - up->tx_loadsz); 2143 port->handle_irq = serial8250_tx_threshold_handle_irq; 2144 break; 2145 } 2146} 2147 2148static void serial8250_THRE_test(struct uart_port *port) 2149{ 2150 struct uart_8250_port *up = up_to_u8250p(port); 2151 bool iir_noint1, iir_noint2; 2152 2153 if (!port->irq) 2154 return; 2155 2156 if (up->port.flags & UPF_NO_THRE_TEST) 2157 return; 2158 2159 disable_irq(port->irq); 2160 2161 /* 2162 * Test for UARTs that do not reassert THRE when the transmitter is idle and the interrupt 2163 * has already been cleared. Real 16550s should always reassert this interrupt whenever the 2164 * transmitter is idle and the interrupt is enabled. Delays are necessary to allow register 2165 * changes to become visible. 2166 * 2167 * Synchronize UART_IER access against the console. 2168 */ 2169 scoped_guard(uart_port_lock_irqsave, port) { 2170 wait_for_xmitr(up, UART_LSR_THRE); 2171 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 2172 udelay(1); /* allow THRE to set */ 2173 iir_noint1 = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT; 2174 serial_port_out(port, UART_IER, 0); 2175 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 2176 udelay(1); /* allow a working UART time to re-assert THRE */ 2177 iir_noint2 = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT; 2178 serial_port_out(port, UART_IER, 0); 2179 } 2180 2181 enable_irq(port->irq); 2182 2183 /* 2184 * If the interrupt is not reasserted, or we otherwise don't trust the iir, setup a timer to 2185 * kick the UART on a regular basis. 2186 */ 2187 if ((!iir_noint1 && iir_noint2) || up->port.flags & UPF_BUG_THRE) 2188 up->bugs |= UART_BUG_THRE; 2189} 2190 2191static void serial8250_init_mctrl(struct uart_port *port) 2192{ 2193 if (port->flags & UPF_FOURPORT) { 2194 if (!port->irq) 2195 port->mctrl |= TIOCM_OUT1; 2196 } else { 2197 /* Most PC uarts need OUT2 raised to enable interrupts. */ 2198 if (port->irq) 2199 port->mctrl |= TIOCM_OUT2; 2200 } 2201 2202 serial8250_set_mctrl(port, port->mctrl); 2203} 2204 2205static void serial8250_iir_txen_test(struct uart_port *port) 2206{ 2207 struct uart_8250_port *up = up_to_u8250p(port); 2208 bool lsr_temt, iir_noint; 2209 2210 if (port->quirks & UPQ_NO_TXEN_TEST) 2211 return; 2212 2213 /* Do a quick test to see if we receive an interrupt when we enable the TX irq. */ 2214 serial_port_out(port, UART_IER, UART_IER_THRI); 2215 lsr_temt = serial_port_in(port, UART_LSR) & UART_LSR_TEMT; 2216 iir_noint = serial_port_in(port, UART_IIR) & UART_IIR_NO_INT; 2217 serial_port_out(port, UART_IER, 0); 2218 2219 /* 2220 * Serial over Lan (SoL) hack: 2221 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be used for Serial Over 2222 * Lan. Those chips take a longer time than a normal serial device to signalize that a 2223 * transmission data was queued. Due to that, the above test generally fails. One solution 2224 * would be to delay the reading of iir. However, this is not reliable, since the timeout is 2225 * variable. So, in case of UPQ_NO_TXEN_TEST, let's just don't test if we receive TX irq. 2226 * This way, we'll never enable UART_BUG_TXEN. 2227 */ 2228 if (lsr_temt && iir_noint) { 2229 if (!(up->bugs & UART_BUG_TXEN)) { 2230 up->bugs |= UART_BUG_TXEN; 2231 dev_dbg(port->dev, "enabling bad tx status workarounds\n"); 2232 } 2233 return; 2234 } 2235 2236 /* FIXME: why is this needed? */ 2237 up->bugs &= ~UART_BUG_TXEN; 2238} 2239 2240static void serial8250_initialize(struct uart_port *port) 2241{ 2242 guard(uart_port_lock_irqsave)(port); 2243 serial_port_out(port, UART_LCR, UART_LCR_WLEN8); 2244 2245 serial8250_init_mctrl(port); 2246 serial8250_iir_txen_test(port); 2247} 2248 2249int serial8250_do_startup(struct uart_port *port) 2250{ 2251 struct uart_8250_port *up = up_to_u8250p(port); 2252 int retval; 2253 2254 if (!port->fifosize) 2255 port->fifosize = uart_config[port->type].fifo_size; 2256 if (!up->tx_loadsz) 2257 up->tx_loadsz = uart_config[port->type].tx_loadsz; 2258 if (!up->capabilities) 2259 up->capabilities = uart_config[port->type].flags; 2260 up->mcr = 0; 2261 2262 if (port->iotype != up->cur_iotype) 2263 set_io_from_upio(port); 2264 2265 guard(serial8250_rpm)(up); 2266 2267 serial8250_startup_special(port); 2268 2269 /* 2270 * Clear the FIFO buffers and disable them. 2271 * (they will be reenabled in set_termios()) 2272 */ 2273 serial8250_clear_fifos(up); 2274 2275 serial8250_clear_interrupts(port); 2276 2277 /* 2278 * At this point, there's no way the LSR could still be 0xff; 2279 * if it is, then bail out, because there's likely no UART 2280 * here. 2281 */ 2282 if (!(port->flags & UPF_BUGGY_UART) && 2283 (serial_port_in(port, UART_LSR) == 0xff)) { 2284 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n"); 2285 return -ENODEV; 2286 } 2287 2288 serial8250_set_TRG_levels(port); 2289 2290 /* Check if we need to have shared IRQs */ 2291 if (port->irq && (up->port.flags & UPF_SHARE_IRQ)) 2292 up->port.irqflags |= IRQF_SHARED; 2293 2294 retval = up->ops->setup_irq(up); 2295 if (retval) 2296 return retval; 2297 2298 serial8250_THRE_test(port); 2299 2300 up->ops->setup_timer(up); 2301 2302 serial8250_initialize(port); 2303 2304 /* 2305 * Clear the interrupt registers again for luck, and clear the 2306 * saved flags to avoid getting false values from polling 2307 * routines or the previous session. 2308 */ 2309 serial8250_clear_interrupts(port); 2310 up->lsr_saved_flags = 0; 2311 up->msr_saved_flags = 0; 2312 2313 /* 2314 * Request DMA channels for both RX and TX. 2315 */ 2316 if (up->dma) { 2317 const char *msg = NULL; 2318 2319 if (uart_console(port)) 2320 msg = "forbid DMA for kernel console"; 2321 else if (serial8250_request_dma(up)) 2322 msg = "failed to request DMA"; 2323 if (msg) { 2324 dev_warn_ratelimited(port->dev, "%s\n", msg); 2325 up->dma = NULL; 2326 } 2327 } 2328 2329 /* 2330 * Set the IER shadow for rx interrupts but defer actual interrupt 2331 * enable until after the FIFOs are enabled; otherwise, an already- 2332 * active sender can swamp the interrupt handler with "too much work". 2333 */ 2334 up->ier = UART_IER_RLSI | UART_IER_RDI; 2335 2336 if (port->flags & UPF_FOURPORT) { 2337 unsigned int icp; 2338 /* 2339 * Enable interrupts on the AST Fourport board 2340 */ 2341 icp = (port->iobase & 0xfe0) | 0x01f; 2342 outb_p(0x80, icp); 2343 inb_p(icp); 2344 } 2345 2346 return 0; 2347} 2348EXPORT_SYMBOL_GPL(serial8250_do_startup); 2349 2350static int serial8250_startup(struct uart_port *port) 2351{ 2352 if (port->startup) 2353 return port->startup(port); 2354 return serial8250_do_startup(port); 2355} 2356 2357void serial8250_do_shutdown(struct uart_port *port) 2358{ 2359 struct uart_8250_port *up = up_to_u8250p(port); 2360 u32 lcr; 2361 2362 serial8250_rpm_get(up); 2363 /* 2364 * Disable interrupts from this port 2365 * 2366 * Synchronize UART_IER access against the console. 2367 */ 2368 scoped_guard(uart_port_lock_irqsave, port) { 2369 up->ier = 0; 2370 serial_port_out(port, UART_IER, 0); 2371 } 2372 2373 synchronize_irq(port->irq); 2374 2375 if (up->dma) 2376 serial8250_release_dma(up); 2377 2378 scoped_guard(uart_port_lock_irqsave, port) { 2379 if (port->flags & UPF_FOURPORT) { 2380 /* reset interrupts on the AST Fourport board */ 2381 inb((port->iobase & 0xfe0) | 0x1f); 2382 port->mctrl |= TIOCM_OUT1; 2383 } else 2384 port->mctrl &= ~TIOCM_OUT2; 2385 2386 serial8250_set_mctrl(port, port->mctrl); 2387 2388 /* Disable break condition */ 2389 lcr = serial_port_in(port, UART_LCR); 2390 lcr &= ~UART_LCR_SBC; 2391 serial_port_out(port, UART_LCR, lcr); 2392 } 2393 2394 serial8250_clear_fifos(up); 2395 2396 rsa_disable(up); 2397 2398 /* 2399 * Read data port to reset things, and then unlink from 2400 * the IRQ chain. 2401 */ 2402 serial_port_in(port, UART_RX); 2403 /* 2404 * LCR writes on DW UART can trigger late (unmaskable) IRQs. 2405 * Handle them before releasing the handler. 2406 */ 2407 synchronize_irq(port->irq); 2408 2409 serial8250_rpm_put(up); 2410 2411 up->ops->release_irq(up); 2412} 2413EXPORT_SYMBOL_GPL(serial8250_do_shutdown); 2414 2415static void serial8250_shutdown(struct uart_port *port) 2416{ 2417 if (port->shutdown) 2418 port->shutdown(port); 2419 else 2420 serial8250_do_shutdown(port); 2421} 2422 2423static void serial8250_flush_buffer(struct uart_port *port) 2424{ 2425 struct uart_8250_port *up = up_to_u8250p(port); 2426 2427 if (up->dma) 2428 serial8250_tx_dma_flush(up); 2429} 2430 2431static unsigned int serial8250_do_get_divisor(struct uart_port *port, unsigned int baud) 2432{ 2433 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER; 2434 struct uart_8250_port *up = up_to_u8250p(port); 2435 unsigned int quot; 2436 2437 /* 2438 * Handle magic divisors for baud rates above baud_base on SMSC 2439 * Super I/O chips. We clamp custom rates from clk/6 and clk/12 2440 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These 2441 * magic divisors actually reprogram the baud rate generator's 2442 * reference clock derived from chips's 14.318MHz clock input. 2443 * 2444 * Documentation claims that with these magic divisors the base 2445 * frequencies of 7.3728MHz and 3.6864MHz are used respectively 2446 * for the extra baud rates of 460800bps and 230400bps rather 2447 * than the usual base frequency of 1.8462MHz. However empirical 2448 * evidence contradicts that. 2449 * 2450 * Instead bit 7 of the DLM register (bit 15 of the divisor) is 2451 * effectively used as a clock prescaler selection bit for the 2452 * base frequency of 7.3728MHz, always used. If set to 0, then 2453 * the base frequency is divided by 4 for use by the Baud Rate 2454 * Generator, for the usual arrangement where the value of 1 of 2455 * the divisor produces the baud rate of 115200bps. Conversely, 2456 * if set to 1 and high-speed operation has been enabled with the 2457 * Serial Port Mode Register in the Device Configuration Space, 2458 * then the base frequency is supplied directly to the Baud Rate 2459 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003, 2460 * 0x8004, etc. the respective baud rates produced are 460800bps, 2461 * 230400bps, 153600bps, 115200bps, etc. 2462 * 2463 * In all cases only low 15 bits of the divisor are used to divide 2464 * the baud base and therefore 32767 is the maximum divisor value 2465 * possible, even though documentation says that the programmable 2466 * Baud Rate Generator is capable of dividing the internal PLL 2467 * clock by any divisor from 1 to 65535. 2468 */ 2469 if (magic_multiplier && baud >= port->uartclk / 6) 2470 quot = 0x8001; 2471 else if (magic_multiplier && baud >= port->uartclk / 12) 2472 quot = 0x8002; 2473 else 2474 quot = uart_get_divisor(port, baud); 2475 2476 /* 2477 * Oxford Semi 952 rev B workaround 2478 */ 2479 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) 2480 quot++; 2481 2482 return quot; 2483} 2484 2485static unsigned int serial8250_get_divisor(struct uart_port *port, 2486 unsigned int baud, 2487 unsigned int *frac) 2488{ 2489 if (port->get_divisor) 2490 return port->get_divisor(port, baud, frac); 2491 2492 return serial8250_do_get_divisor(port, baud); 2493} 2494 2495static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, tcflag_t c_cflag) 2496{ 2497 u8 lcr = UART_LCR_WLEN(tty_get_char_size(c_cflag)); 2498 2499 if (c_cflag & CSTOPB) 2500 lcr |= UART_LCR_STOP; 2501 if (c_cflag & PARENB) 2502 lcr |= UART_LCR_PARITY; 2503 if (!(c_cflag & PARODD)) 2504 lcr |= UART_LCR_EPAR; 2505 if (c_cflag & CMSPAR) 2506 lcr |= UART_LCR_SPAR; 2507 2508 return lcr; 2509} 2510 2511void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud, 2512 unsigned int quot) 2513{ 2514 struct uart_8250_port *up = up_to_u8250p(port); 2515 2516 /* Workaround to enable 115200 baud on OMAP1510 internal ports */ 2517 if (is_omap1510_8250(up)) { 2518 if (baud == 115200) { 2519 quot = 1; 2520 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); 2521 } else 2522 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); 2523 } 2524 2525 /* 2526 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, 2527 * otherwise just set DLAB 2528 */ 2529 if (up->capabilities & UART_NATSEMI) 2530 serial_port_out(port, UART_LCR, 0xe0); 2531 else 2532 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); 2533 2534 serial_dl_write(up, quot); 2535} 2536EXPORT_SYMBOL_GPL(serial8250_do_set_divisor); 2537 2538static void serial8250_set_divisor(struct uart_port *port, unsigned int baud, 2539 unsigned int quot, unsigned int quot_frac) 2540{ 2541 if (port->set_divisor) 2542 port->set_divisor(port, baud, quot, quot_frac); 2543 else 2544 serial8250_do_set_divisor(port, baud, quot); 2545} 2546 2547static unsigned int serial8250_get_baud_rate(struct uart_port *port, 2548 struct ktermios *termios, 2549 const struct ktermios *old) 2550{ 2551 unsigned int tolerance = port->uartclk / 100; 2552 unsigned int min; 2553 unsigned int max; 2554 2555 /* 2556 * Handle magic divisors for baud rates above baud_base on SMSC 2557 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but 2558 * disable divisor values beyond 32767, which are unavailable. 2559 */ 2560 if (port->flags & UPF_MAGIC_MULTIPLIER) { 2561 min = port->uartclk / 16 / UART_DIV_MAX >> 1; 2562 max = (port->uartclk + tolerance) / 4; 2563 } else { 2564 min = port->uartclk / 16 / UART_DIV_MAX; 2565 max = (port->uartclk + tolerance) / 16; 2566 } 2567 2568 /* 2569 * Ask the core to calculate the divisor for us. 2570 * Allow 1% tolerance at the upper limit so uart clks marginally 2571 * slower than nominal still match standard baud rates without 2572 * causing transmission errors. 2573 */ 2574 return uart_get_baud_rate(port, termios, old, min, max); 2575} 2576 2577/* 2578 * Note in order to avoid the tty port mutex deadlock don't use the next method 2579 * within the uart port callbacks. Primarily it's supposed to be utilized to 2580 * handle a sudden reference clock rate change. 2581 */ 2582void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk) 2583{ 2584 struct tty_port *tport = &port->state->port; 2585 2586 scoped_guard(tty_port_tty, tport) { 2587 struct tty_struct *tty = scoped_tty(); 2588 2589 guard(rwsem_write)(&tty->termios_rwsem); 2590 guard(mutex)(&tport->mutex); 2591 2592 if (port->uartclk == uartclk) 2593 return; 2594 2595 port->uartclk = uartclk; 2596 2597 if (!tty_port_initialized(tport)) 2598 return; 2599 2600 serial8250_do_set_termios(port, &tty->termios, NULL); 2601 2602 return; 2603 } 2604 guard(mutex)(&tport->mutex); 2605 port->uartclk = uartclk; 2606} 2607EXPORT_SYMBOL_GPL(serial8250_update_uartclk); 2608 2609static void serial8250_set_mini(struct uart_port *port, struct ktermios *termios) 2610{ 2611 struct uart_8250_port *up = up_to_u8250p(port); 2612 2613 if (!(up->capabilities & UART_CAP_MINI)) 2614 return; 2615 2616 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); 2617 2618 tcflag_t csize = termios->c_cflag & CSIZE; 2619 if (csize == CS5 || csize == CS6) { 2620 termios->c_cflag &= ~CSIZE; 2621 termios->c_cflag |= CS7; 2622 } 2623} 2624 2625static void serial8250_set_trigger_for_slow_speed(struct uart_port *port, struct ktermios *termios, 2626 unsigned int baud) 2627{ 2628 struct uart_8250_port *up = up_to_u8250p(port); 2629 2630 if (!(up->capabilities & UART_CAP_FIFO)) 2631 return; 2632 if (port->fifosize <= 1) 2633 return; 2634 if (baud >= 2400) 2635 return; 2636 if (up->dma) 2637 return; 2638 2639 up->fcr &= ~UART_FCR_TRIGGER_MASK; 2640 up->fcr |= UART_FCR_TRIGGER_1; 2641} 2642 2643/* 2644 * MCR-based auto flow control. When AFE is enabled, RTS will be deasserted when the receive FIFO 2645 * contains more characters than the trigger, or the MCR RTS bit is cleared. 2646 */ 2647static void serial8250_set_afe(struct uart_port *port, struct ktermios *termios) 2648{ 2649 struct uart_8250_port *up = up_to_u8250p(port); 2650 2651 if (!(up->capabilities & UART_CAP_AFE)) 2652 return; 2653 2654 up->mcr &= ~UART_MCR_AFE; 2655 if (termios->c_cflag & CRTSCTS) 2656 up->mcr |= UART_MCR_AFE; 2657} 2658 2659static void serial8250_set_errors_and_ignores(struct uart_port *port, struct ktermios *termios) 2660{ 2661 /* 2662 * Specify which conditions may be considered for error handling and the ignoring of 2663 * characters. The actual ignoring of characters only occurs if the bit is set in 2664 * @ignore_status_mask as well. 2665 */ 2666 port->read_status_mask = UART_LSR_OE | UART_LSR_DR; 2667 if (termios->c_iflag & INPCK) 2668 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 2669 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2670 port->read_status_mask |= UART_LSR_BI; 2671 2672 /* Characters to ignore */ 2673 port->ignore_status_mask = 0; 2674 if (termios->c_iflag & IGNPAR) 2675 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 2676 if (termios->c_iflag & IGNBRK) { 2677 port->ignore_status_mask |= UART_LSR_BI; 2678 /* 2679 * If we're ignoring parity and break indicators, ignore overruns too (for real raw 2680 * support). 2681 */ 2682 if (termios->c_iflag & IGNPAR) 2683 port->ignore_status_mask |= UART_LSR_OE; 2684 } 2685 2686 /* ignore all characters if CREAD is not set */ 2687 if ((termios->c_cflag & CREAD) == 0) 2688 port->ignore_status_mask |= UART_LSR_DR; 2689} 2690 2691static void serial8250_set_ier(struct uart_port *port, struct ktermios *termios) 2692{ 2693 struct uart_8250_port *up = up_to_u8250p(port); 2694 2695 /* CTS flow control flag and modem status interrupts */ 2696 up->ier &= ~UART_IER_MSI; 2697 if (!(up->bugs & UART_BUG_NOMSR) && UART_ENABLE_MS(&up->port, termios->c_cflag)) 2698 up->ier |= UART_IER_MSI; 2699 if (up->capabilities & UART_CAP_UUE) 2700 up->ier |= UART_IER_UUE; 2701 if (up->capabilities & UART_CAP_RTOIE) 2702 up->ier |= UART_IER_RTOIE; 2703 2704 serial_port_out(port, UART_IER, up->ier); 2705} 2706 2707static void serial8250_set_efr(struct uart_port *port, struct ktermios *termios) 2708{ 2709 struct uart_8250_port *up = up_to_u8250p(port); 2710 u8 efr_reg = UART_EFR; 2711 u8 efr = 0; 2712 2713 if (!(up->capabilities & UART_CAP_EFR)) 2714 return; 2715 2716 /* 2717 * TI16C752/Startech hardware flow control. FIXME: 2718 * - TI16C752 requires control thresholds to be set. 2719 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. 2720 */ 2721 if (termios->c_cflag & CRTSCTS) 2722 efr |= UART_EFR_CTS; 2723 2724 if (port->flags & UPF_EXAR_EFR) 2725 efr_reg = UART_XR_EFR; 2726 2727 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2728 serial_port_out(port, efr_reg, efr); 2729} 2730 2731static void serial8250_set_fcr(struct uart_port *port, struct ktermios *termios) 2732{ 2733 struct uart_8250_port *up = up_to_u8250p(port); 2734 bool is_16750 = port->type == PORT_16750; 2735 2736 if (is_16750) 2737 serial_port_out(port, UART_FCR, up->fcr); 2738 2739 /* 2740 * LCR DLAB must be reset to enable 64-byte FIFO mode. If the FCR is written without DLAB 2741 * set, this mode will be disabled. 2742 */ 2743 serial_port_out(port, UART_LCR, up->lcr); 2744 2745 if (is_16750) 2746 return; 2747 2748 /* emulated UARTs (Lucent Venus 167x) need two steps */ 2749 if (up->fcr & UART_FCR_ENABLE_FIFO) 2750 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); 2751 2752 serial_port_out(port, UART_FCR, up->fcr); 2753} 2754 2755void 2756serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, 2757 const struct ktermios *old) 2758{ 2759 struct uart_8250_port *up = up_to_u8250p(port); 2760 unsigned int baud, quot, frac = 0; 2761 u8 lcr; 2762 2763 serial8250_set_mini(port, termios); 2764 lcr = serial8250_compute_lcr(up, termios->c_cflag); 2765 baud = serial8250_get_baud_rate(port, termios, old); 2766 quot = serial8250_get_divisor(port, baud, &frac); 2767 2768 /* 2769 * Ok, we're now changing the port state. Do it with interrupts disabled. 2770 * 2771 * Synchronize UART_IER access against the console. 2772 */ 2773 scoped_guard(serial8250_rpm, up) { 2774 guard(uart_port_lock_irqsave)(port); 2775 2776 up->lcr = lcr; 2777 serial8250_set_trigger_for_slow_speed(port, termios, baud); 2778 serial8250_set_afe(port, termios); 2779 uart_update_timeout(port, termios->c_cflag, baud); 2780 serial8250_set_errors_and_ignores(port, termios); 2781 serial8250_set_ier(port, termios); 2782 serial8250_set_efr(port, termios); 2783 serial8250_set_divisor(port, baud, quot, frac); 2784 serial8250_set_fcr(port, termios); 2785 serial8250_set_mctrl(port, port->mctrl); 2786 } 2787 2788 /* Don't rewrite B0 */ 2789 if (tty_termios_baud_rate(termios)) 2790 tty_termios_encode_baud_rate(termios, baud, baud); 2791} 2792EXPORT_SYMBOL(serial8250_do_set_termios); 2793 2794static void 2795serial8250_set_termios(struct uart_port *port, struct ktermios *termios, 2796 const struct ktermios *old) 2797{ 2798 if (port->set_termios) 2799 port->set_termios(port, termios, old); 2800 else 2801 serial8250_do_set_termios(port, termios, old); 2802} 2803 2804void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios) 2805{ 2806 if (termios->c_line == N_PPS) { 2807 port->flags |= UPF_HARDPPS_CD; 2808 guard(uart_port_lock_irq)(port); 2809 serial8250_enable_ms(port); 2810 } else { 2811 port->flags &= ~UPF_HARDPPS_CD; 2812 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2813 guard(uart_port_lock_irq)(port); 2814 serial8250_disable_ms(port); 2815 } 2816 } 2817} 2818EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc); 2819 2820static void 2821serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios) 2822{ 2823 if (port->set_ldisc) 2824 port->set_ldisc(port, termios); 2825 else 2826 serial8250_do_set_ldisc(port, termios); 2827} 2828 2829void serial8250_do_pm(struct uart_port *port, unsigned int state, 2830 unsigned int oldstate) 2831{ 2832 struct uart_8250_port *p = up_to_u8250p(port); 2833 2834 serial8250_set_sleep(p, state != 0); 2835} 2836EXPORT_SYMBOL(serial8250_do_pm); 2837 2838static void 2839serial8250_pm(struct uart_port *port, unsigned int state, 2840 unsigned int oldstate) 2841{ 2842 if (port->pm) 2843 port->pm(port, state, oldstate); 2844 else 2845 serial8250_do_pm(port, state, oldstate); 2846} 2847 2848static unsigned int serial8250_port_size(struct uart_8250_port *pt) 2849{ 2850 if (pt->port.mapsize) 2851 return pt->port.mapsize; 2852 if (is_omap1_8250(pt)) 2853 return 0x16 << pt->port.regshift; 2854 2855 return 8 << pt->port.regshift; 2856} 2857 2858/* 2859 * Resource handling. 2860 */ 2861static int serial8250_request_std_resource(struct uart_8250_port *up) 2862{ 2863 unsigned int size = serial8250_port_size(up); 2864 struct uart_port *port = &up->port; 2865 2866 switch (port->iotype) { 2867 case UPIO_AU: 2868 case UPIO_TSI: 2869 case UPIO_MEM32: 2870 case UPIO_MEM32BE: 2871 case UPIO_MEM16: 2872 case UPIO_MEM: 2873 if (!port->mapbase) 2874 return -EINVAL; 2875 2876 if (!request_mem_region(port->mapbase, size, "serial")) 2877 return -EBUSY; 2878 2879 if (port->flags & UPF_IOREMAP) { 2880 port->membase = ioremap(port->mapbase, size); 2881 if (!port->membase) { 2882 release_mem_region(port->mapbase, size); 2883 return -ENOMEM; 2884 } 2885 } 2886 return 0; 2887 case UPIO_HUB6: 2888 case UPIO_PORT: 2889 if (!request_region(port->iobase, size, "serial")) 2890 return -EBUSY; 2891 return 0; 2892 case UPIO_UNKNOWN: 2893 break; 2894 } 2895 2896 return 0; 2897} 2898 2899static void serial8250_release_std_resource(struct uart_8250_port *up) 2900{ 2901 unsigned int size = serial8250_port_size(up); 2902 struct uart_port *port = &up->port; 2903 2904 switch (port->iotype) { 2905 case UPIO_AU: 2906 case UPIO_TSI: 2907 case UPIO_MEM32: 2908 case UPIO_MEM32BE: 2909 case UPIO_MEM16: 2910 case UPIO_MEM: 2911 if (!port->mapbase) 2912 break; 2913 2914 if (port->flags & UPF_IOREMAP) { 2915 iounmap(port->membase); 2916 port->membase = NULL; 2917 } 2918 2919 release_mem_region(port->mapbase, size); 2920 break; 2921 2922 case UPIO_HUB6: 2923 case UPIO_PORT: 2924 release_region(port->iobase, size); 2925 break; 2926 case UPIO_UNKNOWN: 2927 break; 2928 } 2929} 2930 2931static void serial8250_release_port(struct uart_port *port) 2932{ 2933 struct uart_8250_port *up = up_to_u8250p(port); 2934 2935 serial8250_release_std_resource(up); 2936} 2937 2938static int serial8250_request_port(struct uart_port *port) 2939{ 2940 struct uart_8250_port *up = up_to_u8250p(port); 2941 2942 return serial8250_request_std_resource(up); 2943} 2944 2945static int fcr_get_rxtrig_bytes(struct uart_8250_port *up) 2946{ 2947 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 2948 unsigned char bytes; 2949 2950 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; 2951 2952 return bytes ? bytes : -EOPNOTSUPP; 2953} 2954 2955static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes) 2956{ 2957 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 2958 int i; 2959 2960 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)]) 2961 return -EOPNOTSUPP; 2962 2963 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) { 2964 if (bytes < conf_type->rxtrig_bytes[i]) 2965 /* Use the nearest lower value */ 2966 return (--i) << UART_FCR_R_TRIG_SHIFT; 2967 } 2968 2969 return UART_FCR_R_TRIG_11; 2970} 2971 2972static int do_get_rxtrig(struct tty_port *port) 2973{ 2974 struct uart_state *state = container_of(port, struct uart_state, port); 2975 struct uart_port *uport = state->uart_port; 2976 struct uart_8250_port *up = up_to_u8250p(uport); 2977 2978 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) 2979 return -EINVAL; 2980 2981 return fcr_get_rxtrig_bytes(up); 2982} 2983 2984static int do_serial8250_get_rxtrig(struct tty_port *port) 2985{ 2986 int rxtrig_bytes; 2987 2988 mutex_lock(&port->mutex); 2989 rxtrig_bytes = do_get_rxtrig(port); 2990 mutex_unlock(&port->mutex); 2991 2992 return rxtrig_bytes; 2993} 2994 2995static ssize_t rx_trig_bytes_show(struct device *dev, 2996 struct device_attribute *attr, char *buf) 2997{ 2998 struct tty_port *port = dev_get_drvdata(dev); 2999 int rxtrig_bytes; 3000 3001 rxtrig_bytes = do_serial8250_get_rxtrig(port); 3002 if (rxtrig_bytes < 0) 3003 return rxtrig_bytes; 3004 3005 return sysfs_emit(buf, "%d\n", rxtrig_bytes); 3006} 3007 3008static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) 3009{ 3010 struct uart_state *state = container_of(port, struct uart_state, port); 3011 struct uart_port *uport = state->uart_port; 3012 struct uart_8250_port *up = up_to_u8250p(uport); 3013 int rxtrig; 3014 3015 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) 3016 return -EINVAL; 3017 3018 rxtrig = bytes_to_fcr_rxtrig(up, bytes); 3019 if (rxtrig < 0) 3020 return rxtrig; 3021 3022 serial8250_clear_fifos(up); 3023 up->fcr &= ~UART_FCR_TRIGGER_MASK; 3024 up->fcr |= (unsigned char)rxtrig; 3025 serial_out(up, UART_FCR, up->fcr); 3026 return 0; 3027} 3028 3029static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes) 3030{ 3031 int ret; 3032 3033 mutex_lock(&port->mutex); 3034 ret = do_set_rxtrig(port, bytes); 3035 mutex_unlock(&port->mutex); 3036 3037 return ret; 3038} 3039 3040static ssize_t rx_trig_bytes_store(struct device *dev, 3041 struct device_attribute *attr, const char *buf, size_t count) 3042{ 3043 struct tty_port *port = dev_get_drvdata(dev); 3044 unsigned char bytes; 3045 int ret; 3046 3047 if (!count) 3048 return -EINVAL; 3049 3050 ret = kstrtou8(buf, 10, &bytes); 3051 if (ret < 0) 3052 return ret; 3053 3054 ret = do_serial8250_set_rxtrig(port, bytes); 3055 if (ret < 0) 3056 return ret; 3057 3058 return count; 3059} 3060 3061static DEVICE_ATTR_RW(rx_trig_bytes); 3062 3063static struct attribute *serial8250_dev_attrs[] = { 3064 &dev_attr_rx_trig_bytes.attr, 3065 NULL 3066}; 3067 3068static struct attribute_group serial8250_dev_attr_group = { 3069 .attrs = serial8250_dev_attrs, 3070}; 3071 3072static void register_dev_spec_attr_grp(struct uart_8250_port *up) 3073{ 3074 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 3075 3076 if (conf_type->rxtrig_bytes[0]) 3077 up->port.attr_group = &serial8250_dev_attr_group; 3078} 3079 3080static void serial8250_config_port(struct uart_port *port, int flags) 3081{ 3082 struct uart_8250_port *up = up_to_u8250p(port); 3083 int ret; 3084 3085 /* 3086 * Find the region that we can probe for. This in turn 3087 * tells us whether we can probe for the type of port. 3088 */ 3089 ret = serial8250_request_std_resource(up); 3090 if (ret < 0) 3091 return; 3092 3093 if (port->iotype != up->cur_iotype) 3094 set_io_from_upio(port); 3095 3096 if (flags & UART_CONFIG_TYPE) 3097 autoconfig(up); 3098 3099 /* HW bugs may trigger IRQ while IIR == NO_INT */ 3100 if (port->type == PORT_TEGRA) 3101 up->bugs |= UART_BUG_NOMSR; 3102 3103 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) 3104 autoconfig_irq(up); 3105 3106 if (port->type == PORT_UNKNOWN) 3107 serial8250_release_std_resource(up); 3108 3109 register_dev_spec_attr_grp(up); 3110 up->fcr = uart_config[up->port.type].fcr; 3111} 3112 3113static int 3114serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) 3115{ 3116 if (ser->irq >= irq_get_nr_irqs() || ser->irq < 0 || 3117 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || 3118 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || 3119 ser->type == PORT_STARTECH) 3120 return -EINVAL; 3121 return 0; 3122} 3123 3124static const char *serial8250_type(struct uart_port *port) 3125{ 3126 int type = port->type; 3127 3128 if (type >= ARRAY_SIZE(uart_config)) 3129 type = 0; 3130 return uart_config[type].name; 3131} 3132 3133static const struct uart_ops serial8250_pops = { 3134 .tx_empty = serial8250_tx_empty, 3135 .set_mctrl = serial8250_set_mctrl, 3136 .get_mctrl = serial8250_get_mctrl, 3137 .stop_tx = serial8250_stop_tx, 3138 .start_tx = serial8250_start_tx, 3139 .throttle = serial8250_throttle, 3140 .unthrottle = serial8250_unthrottle, 3141 .stop_rx = serial8250_stop_rx, 3142 .enable_ms = serial8250_enable_ms, 3143 .break_ctl = serial8250_break_ctl, 3144 .startup = serial8250_startup, 3145 .shutdown = serial8250_shutdown, 3146 .flush_buffer = serial8250_flush_buffer, 3147 .set_termios = serial8250_set_termios, 3148 .set_ldisc = serial8250_set_ldisc, 3149 .pm = serial8250_pm, 3150 .type = serial8250_type, 3151 .release_port = serial8250_release_port, 3152 .request_port = serial8250_request_port, 3153 .config_port = serial8250_config_port, 3154 .verify_port = serial8250_verify_port, 3155#ifdef CONFIG_CONSOLE_POLL 3156 .poll_get_char = serial8250_get_poll_char, 3157 .poll_put_char = serial8250_put_poll_char, 3158#endif 3159}; 3160 3161void serial8250_init_port(struct uart_8250_port *up) 3162{ 3163 struct uart_port *port = &up->port; 3164 3165 spin_lock_init(&port->lock); 3166 port->ctrl_id = 0; 3167 port->pm = NULL; 3168 port->ops = &serial8250_pops; 3169 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 3170 3171 up->cur_iotype = UPIO_UNKNOWN; 3172} 3173EXPORT_SYMBOL_GPL(serial8250_init_port); 3174 3175void serial8250_set_defaults(struct uart_8250_port *up) 3176{ 3177 struct uart_port *port = &up->port; 3178 3179 if (up->port.flags & UPF_FIXED_TYPE) { 3180 unsigned int type = up->port.type; 3181 3182 if (!up->port.fifosize) 3183 up->port.fifosize = uart_config[type].fifo_size; 3184 if (!up->tx_loadsz) 3185 up->tx_loadsz = uart_config[type].tx_loadsz; 3186 if (!up->capabilities) 3187 up->capabilities = uart_config[type].flags; 3188 } 3189 3190 set_io_from_upio(port); 3191 3192 /* default dma handlers */ 3193 if (up->dma) { 3194 if (!up->dma->tx_dma) 3195 up->dma->tx_dma = serial8250_tx_dma; 3196 if (!up->dma->rx_dma) 3197 up->dma->rx_dma = serial8250_rx_dma; 3198 } 3199} 3200EXPORT_SYMBOL_GPL(serial8250_set_defaults); 3201 3202void serial8250_fifo_wait_for_lsr_thre(struct uart_8250_port *up, unsigned int count) 3203{ 3204 unsigned int i; 3205 3206 for (i = 0; i < count; i++) { 3207 if (wait_for_lsr(up, UART_LSR_THRE)) 3208 return; 3209 } 3210} 3211EXPORT_SYMBOL_NS_GPL(serial8250_fifo_wait_for_lsr_thre, "SERIAL_8250"); 3212 3213#ifdef CONFIG_SERIAL_8250_CONSOLE 3214 3215static void serial8250_console_putchar(struct uart_port *port, unsigned char ch) 3216{ 3217 serial_port_out(port, UART_TX, ch); 3218} 3219 3220static void serial8250_console_wait_putchar(struct uart_port *port, unsigned char ch) 3221{ 3222 struct uart_8250_port *up = up_to_u8250p(port); 3223 3224 wait_for_xmitr(up, UART_LSR_THRE); 3225 serial8250_console_putchar(port, ch); 3226} 3227 3228/* 3229 * Restore serial console when h/w power-off detected 3230 */ 3231static void serial8250_console_restore(struct uart_8250_port *up) 3232{ 3233 struct uart_port *port = &up->port; 3234 struct ktermios termios; 3235 unsigned int baud, quot, frac = 0; 3236 3237 termios.c_cflag = port->cons->cflag; 3238 termios.c_ispeed = port->cons->ispeed; 3239 termios.c_ospeed = port->cons->ospeed; 3240 if (port->state->port.tty && termios.c_cflag == 0) { 3241 termios.c_cflag = port->state->port.tty->termios.c_cflag; 3242 termios.c_ispeed = port->state->port.tty->termios.c_ispeed; 3243 termios.c_ospeed = port->state->port.tty->termios.c_ospeed; 3244 } 3245 3246 baud = serial8250_get_baud_rate(port, &termios, NULL); 3247 quot = serial8250_get_divisor(port, baud, &frac); 3248 3249 serial8250_set_divisor(port, baud, quot, frac); 3250 serial_port_out(port, UART_LCR, up->lcr); 3251 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS); 3252} 3253 3254/* 3255 * Print a string to the serial port using the device FIFO 3256 * 3257 * It sends fifosize bytes and then waits for the fifo 3258 * to get empty. 3259 */ 3260static void serial8250_console_fifo_write(struct uart_8250_port *up, 3261 const char *s, unsigned int count) 3262{ 3263 const char *end = s + count; 3264 unsigned int fifosize = up->tx_loadsz; 3265 struct uart_port *port = &up->port; 3266 unsigned int tx_count = 0; 3267 bool cr_sent = false; 3268 unsigned int i; 3269 3270 while (s != end) { 3271 /* Allow timeout for each byte of a possibly full FIFO */ 3272 serial8250_fifo_wait_for_lsr_thre(up, fifosize); 3273 3274 for (i = 0; i < fifosize && s != end; ++i) { 3275 if (*s == '\n' && !cr_sent) { 3276 serial8250_console_putchar(port, '\r'); 3277 cr_sent = true; 3278 } else { 3279 serial8250_console_putchar(port, *s++); 3280 cr_sent = false; 3281 } 3282 } 3283 tx_count = i; 3284 } 3285 3286 /* 3287 * Allow timeout for each byte written since the caller will only wait 3288 * for UART_LSR_BOTH_EMPTY using the timeout of a single character 3289 */ 3290 serial8250_fifo_wait_for_lsr_thre(up, tx_count); 3291} 3292 3293/* 3294 * Print a string to the serial port trying not to disturb 3295 * any possible real use of the port... 3296 * 3297 * The console_lock must be held when we get here. 3298 * 3299 * Doing runtime PM is really a bad idea for the kernel console. 3300 * Thus, we assume the function is called when device is powered up. 3301 */ 3302void serial8250_console_write(struct uart_8250_port *up, const char *s, 3303 unsigned int count) 3304{ 3305 struct uart_8250_em485 *em485 = up->em485; 3306 struct uart_port *port = &up->port; 3307 unsigned long flags; 3308 unsigned int ier, use_fifo; 3309 int locked = 1; 3310 3311 touch_nmi_watchdog(); 3312 3313 if (oops_in_progress) 3314 locked = uart_port_trylock_irqsave(port, &flags); 3315 else 3316 uart_port_lock_irqsave(port, &flags); 3317 3318 /* 3319 * First save the IER then disable the interrupts 3320 */ 3321 ier = serial_port_in(port, UART_IER); 3322 serial8250_clear_IER(up); 3323 3324 /* check scratch reg to see if port powered off during system sleep */ 3325 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) { 3326 serial8250_console_restore(up); 3327 up->canary = 0; 3328 } 3329 3330 if (em485) { 3331 if (em485->tx_stopped) 3332 up->rs485_start_tx(up, false); 3333 mdelay(port->rs485.delay_rts_before_send); 3334 } 3335 3336 use_fifo = (up->capabilities & UART_CAP_FIFO) && 3337 /* 3338 * BCM283x requires to check the fifo 3339 * after each byte. 3340 */ 3341 !(up->capabilities & UART_CAP_MINI) && 3342 /* 3343 * tx_loadsz contains the transmit fifo size 3344 */ 3345 up->tx_loadsz > 1 && 3346 (up->fcr & UART_FCR_ENABLE_FIFO) && 3347 port->state && 3348 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) && 3349 /* 3350 * After we put a data in the fifo, the controller will send 3351 * it regardless of the CTS state. Therefore, only use fifo 3352 * if we don't use control flow. 3353 */ 3354 !(up->port.flags & UPF_CONS_FLOW); 3355 3356 if (likely(use_fifo)) 3357 serial8250_console_fifo_write(up, s, count); 3358 else 3359 uart_console_write(port, s, count, serial8250_console_wait_putchar); 3360 3361 /* 3362 * Finally, wait for transmitter to become empty 3363 * and restore the IER 3364 */ 3365 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY); 3366 3367 if (em485) { 3368 mdelay(port->rs485.delay_rts_after_send); 3369 if (em485->tx_stopped) 3370 up->rs485_stop_tx(up, false); 3371 } 3372 3373 serial_port_out(port, UART_IER, ier); 3374 3375 /* 3376 * The receive handling will happen properly because the 3377 * receive ready bit will still be set; it is not cleared 3378 * on read. However, modem control will not, we must 3379 * call it if we have saved something in the saved flags 3380 * while processing with interrupts off. 3381 */ 3382 if (up->msr_saved_flags) 3383 serial8250_modem_status(up); 3384 3385 if (locked) 3386 uart_port_unlock_irqrestore(port, flags); 3387} 3388 3389static unsigned int probe_baud(struct uart_port *port) 3390{ 3391 unsigned char lcr, dll, dlm; 3392 unsigned int quot; 3393 3394 lcr = serial_port_in(port, UART_LCR); 3395 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB); 3396 dll = serial_port_in(port, UART_DLL); 3397 dlm = serial_port_in(port, UART_DLM); 3398 serial_port_out(port, UART_LCR, lcr); 3399 3400 quot = (dlm << 8) | dll; 3401 return (port->uartclk / 16) / quot; 3402} 3403 3404int serial8250_console_setup(struct uart_port *port, char *options, bool probe) 3405{ 3406 int baud = 9600; 3407 int bits = 8; 3408 int parity = 'n'; 3409 int flow = 'n'; 3410 int ret; 3411 3412 if (!port->iobase && !port->membase) 3413 return -ENODEV; 3414 3415 if (options) 3416 uart_parse_options(options, &baud, &parity, &bits, &flow); 3417 else if (probe) 3418 baud = probe_baud(port); 3419 3420 ret = uart_set_options(port, port->cons, baud, parity, bits, flow); 3421 if (ret) 3422 return ret; 3423 3424 if (port->dev) 3425 pm_runtime_get_sync(port->dev); 3426 3427 return 0; 3428} 3429 3430int serial8250_console_exit(struct uart_port *port) 3431{ 3432 if (port->dev) 3433 pm_runtime_put_sync(port->dev); 3434 3435 return 0; 3436} 3437 3438#endif /* CONFIG_SERIAL_8250_CONSOLE */ 3439 3440MODULE_DESCRIPTION("Base port operations for 8250/16550-type serial ports"); 3441MODULE_LICENSE("GPL");
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