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8250_pci1xxxx.c
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linux-6.19.14/drivers/tty/serial/8250/8250_pci1xxxx.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Probe module for 8250/16550-type MCHP PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. 8 */ 9 10#include <linux/array_size.h> 11#include <linux/bitfield.h> 12#include <linux/bits.h> 13#include <linux/circ_buf.h> 14#include <linux/device.h> 15#include <linux/errno.h> 16#include <linux/gfp_types.h> 17#include <linux/io.h> 18#include <linux/iopoll.h> 19#include <linux/minmax.h> 20#include <linux/module.h> 21#include <linux/mutex.h> 22#include <linux/overflow.h> 23#include <linux/pci.h> 24#include <linux/pm.h> 25#include <linux/serial_core.h> 26#include <linux/serial_reg.h> 27#include <linux/serial_8250.h> 28#include <linux/spinlock.h> 29#include <linux/string.h> 30#include <linux/time.h> 31#include <linux/tty.h> 32#include <linux/tty_flip.h> 33#include <linux/types.h> 34#include <linux/units.h> 35 36#include <asm/byteorder.h> 37 38#include "8250.h" 39#include "8250_pcilib.h" 40 41#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 42#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 43#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 44#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 45#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 46 47#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 48#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 49#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 50#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 51#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 52#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 53#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 54#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 55#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 56#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a 57#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b 58#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c 59#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d 60#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e 61#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f 62 63#define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000 64#define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010 65#define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101 66#define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400 67#define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414 68 69#define UART_SYSTEM_ADDR_BASE 0x1000 70#define UART_DEV_REV_REG (UART_SYSTEM_ADDR_BASE + 0x00) 71#define UART_DEV_REV_MASK GENMASK(7, 0) 72#define UART_SYSLOCK_REG (UART_SYSTEM_ADDR_BASE + 0xA0) 73#define UART_SYSLOCK BIT(2) 74#define SYSLOCK_SLEEP_TIMEOUT 100 75#define SYSLOCK_RETRY_CNT 1000 76 77#define UART_RX_BYTE_FIFO 0x00 78#define UART_TX_BYTE_FIFO 0x00 79#define UART_FIFO_CTL 0x02 80 81#define UART_MODEM_CTL_REG 0x04 82#define UART_MODEM_CTL_RTS_SET BIT(1) 83 84#define UART_LINE_STAT_REG 0x05 85#define UART_LINE_XMIT_CHECK_MASK GENMASK(6, 5) 86 87#define UART_ACTV_REG 0x11 88#define UART_BLOCK_SET_ACTIVE BIT(0) 89 90#define UART_PCI_CTRL_REG 0x80 91#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) 92#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) 93 94#define ADCL_CFG_REG 0x40 95#define ADCL_CFG_POL_SEL BIT(2) 96#define ADCL_CFG_PIN_SEL BIT(1) 97#define ADCL_CFG_EN BIT(0) 98 99#define UART_BIT_SAMPLE_CNT_8 8 100#define UART_BIT_SAMPLE_CNT_16 16 101#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) 102#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) 103#define FRAC_DIV_TX_END_POINT_MASK GENMASK(23, 20) 104 105#define UART_WAKE_REG 0x8C 106#define UART_WAKE_MASK_REG 0x90 107#define UART_WAKE_N_PIN BIT(2) 108#define UART_WAKE_NCTS BIT(1) 109#define UART_WAKE_INT BIT(0) 110#define UART_WAKE_SRCS \ 111 (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) 112 113#define UART_BAUD_CLK_DIVISOR_REG 0x54 114#define FRAC_DIV_CFG_REG 0x58 115 116#define UART_RESET_REG 0x94 117#define UART_RESET_D3_RESET_DISABLE BIT(16) 118#define UART_RESET_HOT_RESET_DISABLE BIT(17) 119 120#define UART_BURST_STATUS_REG 0x9C 121#define UART_TX_BURST_FIFO 0xA0 122#define UART_RX_BURST_FIFO 0xA4 123 124#define UART_BIT_DIVISOR_8 0x26731000 125#define UART_BIT_DIVISOR_16 0x6ef71000 126#define UART_BAUD_4MBPS 4000000 127 128#define MAX_PORTS 4 129#define PORT_OFFSET 0x100 130#define RX_BUF_SIZE 512 131#define UART_BYTE_SIZE 1 132#define UART_BURST_SIZE 4 133 134#define UART_BST_STAT_RX_COUNT_MASK 0x00FF 135#define UART_BST_STAT_TX_COUNT_MASK 0xFF00 136#define UART_BST_STAT_IIR_INT_PEND 0x100000 137#define UART_LSR_OVERRUN_ERR_CLR 0x43 138#define UART_BST_STAT_LSR_RX_MASK 0x9F000000 139#define UART_BST_STAT_LSR_RX_ERR_MASK 0x9E000000 140#define UART_BST_STAT_LSR_OVERRUN_ERR 0x2000000 141#define UART_BST_STAT_LSR_PARITY_ERR 0x4000000 142#define UART_BST_STAT_LSR_FRAME_ERR 0x8000000 143#define UART_BST_STAT_LSR_THRE 0x20000000 144 145#define GET_MODEM_CTL_RTS_STATUS(reg) ((reg) & UART_MODEM_CTL_RTS_SET) 146#define GET_RTS_PIN_STATUS(val) (((val) & TIOCM_RTS) >> 1) 147#define RTS_TOGGLE_STATUS_MASK(val, reg) (GET_MODEM_CTL_RTS_STATUS(reg) \ 148 != GET_RTS_PIN_STATUS(val)) 149 150struct pci1xxxx_8250 { 151 unsigned int nr; 152 u8 dev_rev; 153 u8 pad[3]; 154 void __iomem *membase; 155 int line[] __counted_by(nr); 156}; 157 158static const struct serial_rs485 pci1xxxx_rs485_supported = { 159 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | 160 SER_RS485_RTS_AFTER_SEND, 161 .delay_rts_after_send = 1, 162 /* Delay RTS before send is not supported */ 163}; 164 165static int pci1xxxx_set_sys_lock(struct pci1xxxx_8250 *port) 166{ 167 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); 168 return readl(port->membase + UART_SYSLOCK_REG); 169} 170 171static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_8250 *port) 172{ 173 u32 regval; 174 175 return readx_poll_timeout(pci1xxxx_set_sys_lock, port, regval, 176 (regval & UART_SYSLOCK), 177 SYSLOCK_SLEEP_TIMEOUT, 178 SYSLOCK_RETRY_CNT * SYSLOCK_SLEEP_TIMEOUT); 179} 180 181static void pci1xxxx_release_sys_lock(struct pci1xxxx_8250 *port) 182{ 183 writel(0x0, port->membase + UART_SYSLOCK_REG); 184} 185 186static const int logical_to_physical_port_idx[][MAX_PORTS] = { 187 {0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */ 188 {0, 1, 2, 3}, /* PCI4p */ 189 {0, 1, 2, -1}, /* PCI3p012 */ 190 {0, 1, 3, -1}, /* PCI3p013 */ 191 {0, 2, 3, -1}, /* PCI3p023 */ 192 {1, 2, 3, -1}, /* PCI3p123 */ 193 {0, 1, -1, -1}, /* PCI2p01 */ 194 {0, 2, -1, -1}, /* PCI2p02 */ 195 {0, 3, -1, -1}, /* PCI2p03 */ 196 {1, 2, -1, -1}, /* PCI2p12 */ 197 {1, 3, -1, -1}, /* PCI2p13 */ 198 {2, 3, -1, -1}, /* PCI2p23 */ 199 {0, -1, -1, -1}, /* PCI1p0 */ 200 {1, -1, -1, -1}, /* PCI1p1 */ 201 {2, -1, -1, -1}, /* PCI1p2 */ 202 {3, -1, -1, -1}, /* PCI1p3 */ 203}; 204 205static int pci1xxxx_get_num_ports(struct pci_dev *dev) 206{ 207 switch (dev->subsystem_device) { 208 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: 209 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: 210 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: 211 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: 212 case PCI_SUBDEVICE_ID_EFAR_PCI12000: 213 case PCI_SUBDEVICE_ID_EFAR_PCI11010: 214 case PCI_SUBDEVICE_ID_EFAR_PCI11101: 215 case PCI_SUBDEVICE_ID_EFAR_PCI11400: 216 default: 217 return 1; 218 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: 219 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: 220 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: 221 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: 222 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: 223 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: 224 return 2; 225 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: 226 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: 227 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: 228 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: 229 return 3; 230 case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: 231 case PCI_SUBDEVICE_ID_EFAR_PCI11414: 232 return 4; 233 } 234} 235 236static unsigned int pci1xxxx_get_divisor(struct uart_port *port, 237 unsigned int baud, unsigned int *frac) 238{ 239 unsigned int uart_sample_cnt; 240 unsigned int quot; 241 242 if (baud >= UART_BAUD_4MBPS) 243 uart_sample_cnt = UART_BIT_SAMPLE_CNT_8; 244 else 245 uart_sample_cnt = UART_BIT_SAMPLE_CNT_16; 246 247 /* 248 * Calculate baud rate sampling period in nanoseconds. 249 * Fractional part x denotes x/255 parts of a nanosecond. 250 */ 251 quot = NSEC_PER_SEC / (baud * uart_sample_cnt); 252 *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) * 253 255 / uart_sample_cnt / baud; 254 255 return quot; 256} 257 258static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, 259 unsigned int quot, unsigned int frac) 260{ 261 if (baud >= UART_BAUD_4MBPS) 262 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); 263 else 264 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); 265 266 writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, 267 port->membase + UART_BAUD_CLK_DIVISOR_REG); 268} 269 270static void pci1xxxx_set_mctrl(struct uart_port *port, unsigned int mctrl) 271{ 272 u32 fract_div_cfg_reg; 273 u32 line_stat_reg; 274 u32 modem_ctl_reg; 275 u32 adcl_cfg_reg; 276 277 adcl_cfg_reg = readl(port->membase + ADCL_CFG_REG); 278 279 /* HW is responsible in ADCL_EN case */ 280 if ((adcl_cfg_reg & (ADCL_CFG_EN | ADCL_CFG_PIN_SEL))) 281 return; 282 283 modem_ctl_reg = readl(port->membase + UART_MODEM_CTL_REG); 284 285 serial8250_do_set_mctrl(port, mctrl); 286 287 if (RTS_TOGGLE_STATUS_MASK(mctrl, modem_ctl_reg)) { 288 line_stat_reg = readl(port->membase + UART_LINE_STAT_REG); 289 if (line_stat_reg & UART_LINE_XMIT_CHECK_MASK) { 290 fract_div_cfg_reg = readl(port->membase + 291 FRAC_DIV_CFG_REG); 292 293 writel((fract_div_cfg_reg & 294 ~(FRAC_DIV_TX_END_POINT_MASK)), 295 port->membase + FRAC_DIV_CFG_REG); 296 297 /* Enable ADC and set the nRTS pin */ 298 writel((adcl_cfg_reg | (ADCL_CFG_EN | 299 ADCL_CFG_PIN_SEL)), 300 port->membase + ADCL_CFG_REG); 301 302 /* Revert to the original settings */ 303 writel(adcl_cfg_reg, port->membase + ADCL_CFG_REG); 304 305 writel(fract_div_cfg_reg, port->membase + 306 FRAC_DIV_CFG_REG); 307 } 308 } 309} 310 311static int pci1xxxx_rs485_config(struct uart_port *port, 312 struct ktermios *termios, 313 struct serial_rs485 *rs485) 314{ 315 u32 delay_in_baud_periods; 316 u32 baud_period_in_ns; 317 u32 mode_cfg = 0; 318 u32 sample_cnt; 319 u32 clock_div; 320 u32 frac_div; 321 322 frac_div = readl(port->membase + FRAC_DIV_CFG_REG); 323 324 if (frac_div == UART_BIT_DIVISOR_16) 325 sample_cnt = UART_BIT_SAMPLE_CNT_16; 326 else 327 sample_cnt = UART_BIT_SAMPLE_CNT_8; 328 329 /* 330 * pci1xxxx's uart hardware supports only RTS delay after 331 * Tx and in units of bit times to a maximum of 15 332 */ 333 if (rs485->flags & SER_RS485_ENABLED) { 334 mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; 335 336 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) 337 mode_cfg |= ADCL_CFG_POL_SEL; 338 339 if (rs485->delay_rts_after_send) { 340 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); 341 baud_period_in_ns = 342 FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * 343 sample_cnt; 344 delay_in_baud_periods = 345 rs485->delay_rts_after_send * NSEC_PER_MSEC / 346 baud_period_in_ns; 347 delay_in_baud_periods = 348 min_t(u32, delay_in_baud_periods, 349 FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); 350 mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, 351 delay_in_baud_periods); 352 rs485->delay_rts_after_send = 353 baud_period_in_ns * delay_in_baud_periods / 354 NSEC_PER_MSEC; 355 } 356 } 357 writel(mode_cfg, port->membase + ADCL_CFG_REG); 358 return 0; 359} 360 361static u32 pci1xxxx_read_burst_status(struct uart_port *port) 362{ 363 u32 status; 364 365 status = readl(port->membase + UART_BURST_STATUS_REG); 366 if (status & UART_BST_STAT_LSR_RX_ERR_MASK) { 367 if (status & UART_BST_STAT_LSR_OVERRUN_ERR) { 368 writeb(UART_LSR_OVERRUN_ERR_CLR, 369 port->membase + UART_FIFO_CTL); 370 port->icount.overrun++; 371 } 372 373 if (status & UART_BST_STAT_LSR_FRAME_ERR) 374 port->icount.frame++; 375 376 if (status & UART_BST_STAT_LSR_PARITY_ERR) 377 port->icount.parity++; 378 } 379 return status; 380} 381 382static void pci1xxxx_process_read_data(struct uart_port *port, 383 unsigned char *rx_buff, u32 *buff_index, 384 u32 *valid_byte_count) 385{ 386 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; 387 u32 *burst_buf; 388 389 /* 390 * Depending on the RX Trigger Level the number of bytes that can be 391 * stored in RX FIFO at a time varies. Each transaction reads data 392 * in DWORDs. If there are less than four remaining valid_byte_count 393 * to read, the data is received one byte at a time. 394 */ 395 while (valid_burst_count--) { 396 if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE)) 397 break; 398 burst_buf = (u32 *)&rx_buff[*buff_index]; 399 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO); 400 *buff_index += UART_BURST_SIZE; 401 *valid_byte_count -= UART_BURST_SIZE; 402 } 403 404 while (*valid_byte_count) { 405 if (*buff_index >= RX_BUF_SIZE) 406 break; 407 rx_buff[*buff_index] = readb(port->membase + 408 UART_RX_BYTE_FIFO); 409 *buff_index += UART_BYTE_SIZE; 410 *valid_byte_count -= UART_BYTE_SIZE; 411 } 412} 413 414static void pci1xxxx_rx_burst(struct uart_port *port, u32 uart_status) 415{ 416 u32 valid_byte_count = uart_status & UART_BST_STAT_RX_COUNT_MASK; 417 struct tty_port *tty_port = &port->state->port; 418 unsigned char rx_buff[RX_BUF_SIZE]; 419 u32 buff_index = 0; 420 u32 copied_len; 421 422 if (valid_byte_count != 0 && 423 valid_byte_count < RX_BUF_SIZE) { 424 pci1xxxx_process_read_data(port, rx_buff, &buff_index, 425 &valid_byte_count); 426 427 copied_len = (u32)tty_insert_flip_string(tty_port, rx_buff, 428 buff_index); 429 430 if (copied_len != buff_index) 431 port->icount.overrun += buff_index - copied_len; 432 433 port->icount.rx += buff_index; 434 tty_flip_buffer_push(tty_port); 435 } 436} 437 438static void pci1xxxx_process_write_data(struct uart_port *port, 439 int *data_empty_count, 440 u32 *valid_byte_count) 441{ 442 struct tty_port *tport = &port->state->port; 443 u32 valid_burst_count = *valid_byte_count / UART_BURST_SIZE; 444 445 /* 446 * Each transaction transfers data in DWORDs. If there are less than 447 * four remaining valid_byte_count to transfer or if the circular 448 * buffer has insufficient space for a DWORD, the data is transferred 449 * one byte at a time. 450 */ 451 while (valid_burst_count) { 452 u32 c; 453 454 if (*data_empty_count - UART_BURST_SIZE < 0) 455 break; 456 if (kfifo_len(&tport->xmit_fifo) < UART_BURST_SIZE) 457 break; 458 if (WARN_ON(kfifo_out(&tport->xmit_fifo, (u8 *)&c, sizeof(c)) != 459 sizeof(c))) 460 break; 461 writel(c, port->membase + UART_TX_BURST_FIFO); 462 *valid_byte_count -= UART_BURST_SIZE; 463 *data_empty_count -= UART_BURST_SIZE; 464 valid_burst_count -= UART_BYTE_SIZE; 465 } 466 467 while (*valid_byte_count) { 468 u8 c; 469 470 if (!kfifo_get(&tport->xmit_fifo, &c)) 471 break; 472 writeb(c, port->membase + UART_TX_BYTE_FIFO); 473 *data_empty_count -= UART_BYTE_SIZE; 474 *valid_byte_count -= UART_BYTE_SIZE; 475 476 /* 477 * If there are any pending burst count, data is handled by 478 * transmitting DWORDs at a time. 479 */ 480 if (valid_burst_count && 481 kfifo_len(&tport->xmit_fifo) >= UART_BURST_SIZE) 482 break; 483 } 484} 485 486static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) 487{ 488 struct uart_8250_port *up = up_to_u8250p(port); 489 struct tty_port *tport = &port->state->port; 490 u32 valid_byte_count; 491 int data_empty_count; 492 493 if (port->x_char) { 494 writeb(port->x_char, port->membase + UART_TX); 495 port->icount.tx++; 496 port->x_char = 0; 497 return; 498 } 499 500 if ((uart_tx_stopped(port)) || kfifo_is_empty(&tport->xmit_fifo)) { 501 port->ops->stop_tx(port); 502 } else { 503 data_empty_count = (pci1xxxx_read_burst_status(port) & 504 UART_BST_STAT_TX_COUNT_MASK) >> 8; 505 do { 506 valid_byte_count = kfifo_len(&tport->xmit_fifo); 507 508 pci1xxxx_process_write_data(port, 509 &data_empty_count, 510 &valid_byte_count); 511 512 port->icount.tx++; 513 if (kfifo_is_empty(&tport->xmit_fifo)) 514 break; 515 } while (data_empty_count && valid_byte_count); 516 } 517 518 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 519 uart_write_wakeup(port); 520 521 /* 522 * With RPM enabled, we have to wait until the FIFO is empty before 523 * the HW can go idle. So we get here once again with empty FIFO and 524 * disable the interrupt and RPM in __stop_tx() 525 */ 526 if (kfifo_is_empty(&tport->xmit_fifo) && 527 !(up->capabilities & UART_CAP_RPM)) 528 port->ops->stop_tx(port); 529} 530 531static int pci1xxxx_handle_irq(struct uart_port *port) 532{ 533 unsigned long flags; 534 u32 status; 535 536 status = pci1xxxx_read_burst_status(port); 537 538 if (status & UART_BST_STAT_IIR_INT_PEND) 539 return 0; 540 541 spin_lock_irqsave(&port->lock, flags); 542 543 if (status & UART_BST_STAT_LSR_RX_MASK) 544 pci1xxxx_rx_burst(port, status); 545 546 if (status & UART_BST_STAT_LSR_THRE) 547 pci1xxxx_tx_burst(port, status); 548 549 spin_unlock_irqrestore(&port->lock, flags); 550 551 return 1; 552} 553 554static bool pci1xxxx_port_suspend(int line) 555{ 556 struct uart_8250_port *up = serial8250_get_port(line); 557 struct uart_port *port = &up->port; 558 struct tty_port *tport = &port->state->port; 559 unsigned long flags; 560 bool ret = false; 561 u8 wakeup_mask; 562 563 mutex_lock(&tport->mutex); 564 if (port->suspended == 0 && port->dev) { 565 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); 566 567 uart_port_lock_irqsave(port, &flags); 568 port->mctrl &= ~TIOCM_OUT2; 569 port->ops->set_mctrl(port, port->mctrl); 570 uart_port_unlock_irqrestore(port, flags); 571 572 ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; 573 } 574 575 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 576 mutex_unlock(&tport->mutex); 577 578 return ret; 579} 580 581static void pci1xxxx_port_resume(int line) 582{ 583 struct uart_8250_port *up = serial8250_get_port(line); 584 struct uart_port *port = &up->port; 585 struct tty_port *tport = &port->state->port; 586 unsigned long flags; 587 588 mutex_lock(&tport->mutex); 589 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); 590 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 591 592 if (port->suspended == 0) { 593 uart_port_lock_irqsave(port, &flags); 594 port->mctrl |= TIOCM_OUT2; 595 port->ops->set_mctrl(port, port->mctrl); 596 uart_port_unlock_irqrestore(port, flags); 597 } 598 mutex_unlock(&tport->mutex); 599} 600 601static int pci1xxxx_suspend(struct device *dev) 602{ 603 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 604 struct pci_dev *pcidev = to_pci_dev(dev); 605 bool wakeup = false; 606 unsigned int data; 607 void __iomem *p; 608 int i; 609 610 for (i = 0; i < priv->nr; i++) { 611 if (priv->line[i] >= 0) { 612 serial8250_suspend_port(priv->line[i]); 613 wakeup |= pci1xxxx_port_suspend(priv->line[i]); 614 } 615 } 616 617 p = pci_ioremap_bar(pcidev, 0); 618 if (!p) { 619 dev_err(dev, "remapping of bar 0 memory failed"); 620 return -ENOMEM; 621 } 622 623 data = readl(p + UART_RESET_REG); 624 625 if (priv->dev_rev >= 0xC0) 626 data |= UART_RESET_HOT_RESET_DISABLE; 627 628 writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 629 630 if (wakeup) 631 writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); 632 633 iounmap(p); 634 device_set_wakeup_enable(dev, true); 635 pci_wake_from_d3(pcidev, true); 636 637 return 0; 638} 639 640static int pci1xxxx_resume(struct device *dev) 641{ 642 struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); 643 struct pci_dev *pcidev = to_pci_dev(dev); 644 unsigned int data; 645 void __iomem *p; 646 int i; 647 648 p = pci_ioremap_bar(pcidev, 0); 649 if (!p) { 650 dev_err(dev, "remapping of bar 0 memory failed"); 651 return -ENOMEM; 652 } 653 654 data = readl(p + UART_RESET_REG); 655 656 if (priv->dev_rev >= 0xC0) 657 data &= ~UART_RESET_HOT_RESET_DISABLE; 658 659 writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); 660 661 iounmap(p); 662 663 for (i = 0; i < priv->nr; i++) { 664 if (priv->line[i] >= 0) { 665 pci1xxxx_port_resume(priv->line[i]); 666 serial8250_resume_port(priv->line[i]); 667 } 668 } 669 670 return 0; 671} 672 673static int pci1xxxx_setup(struct pci_dev *pdev, 674 struct uart_8250_port *port, int port_idx, struct pci1xxxx_8250 *priv) 675{ 676 int ret; 677 678 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; 679 port->port.type = PORT_MCHP16550A; 680 /* 681 * 8250 core considers prescaller value to be always 16. 682 * The MCHP ports support downscaled mode and hence the 683 * functional UART clock can be lower, i.e. 62.5MHz, than 684 * software expects in order to support higher baud rates. 685 * Assign here 64MHz to support 4Mbps. 686 * 687 * The value itself is not really used anywhere except baud 688 * rate calculations, so we can mangle it as we wish. 689 */ 690 port->port.uartclk = 64 * HZ_PER_MHZ; 691 port->port.set_termios = serial8250_do_set_termios; 692 port->port.get_divisor = pci1xxxx_get_divisor; 693 port->port.set_divisor = pci1xxxx_set_divisor; 694 port->port.rs485_config = pci1xxxx_rs485_config; 695 port->port.rs485_supported = pci1xxxx_rs485_supported; 696 697 /* 698 * C0 and later revisions support Burst operation. 699 * RTS workaround in mctrl is applicable only to B0. 700 */ 701 if (priv->dev_rev >= 0xC0) 702 port->port.handle_irq = pci1xxxx_handle_irq; 703 else if (priv->dev_rev == 0xB0) 704 port->port.set_mctrl = pci1xxxx_set_mctrl; 705 706 ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0, priv->membase); 707 if (ret < 0) 708 return ret; 709 710 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); 711 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); 712 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); 713 714 return 0; 715} 716 717static unsigned int pci1xxxx_get_max_port(int subsys_dev) 718{ 719 unsigned int i = MAX_PORTS; 720 721 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 722 while (i--) { 723 if (logical_to_physical_port_idx[subsys_dev][i] != -1) 724 return logical_to_physical_port_idx[subsys_dev][i] + 1; 725 } 726 727 if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414) 728 return 4; 729 730 return 1; 731} 732 733static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) 734{ 735 if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) 736 return logical_to_physical_port_idx[subsys_dev][port]; 737 738 return logical_to_physical_port_idx[0][port]; 739} 740 741static int pci1xxxx_get_device_revision(struct pci1xxxx_8250 *priv) 742{ 743 u32 regval; 744 int ret; 745 746 /* 747 * DEV REV is a system register, HW Syslock bit 748 * should be acquired before accessing the register 749 */ 750 ret = pci1xxxx_acquire_sys_lock(priv); 751 if (ret) 752 return ret; 753 754 regval = readl(priv->membase + UART_DEV_REV_REG); 755 priv->dev_rev = regval & UART_DEV_REV_MASK; 756 757 pci1xxxx_release_sys_lock(priv); 758 759 return 0; 760} 761 762static int pci1xxxx_serial_probe(struct pci_dev *pdev, 763 const struct pci_device_id *id) 764{ 765 struct device *dev = &pdev->dev; 766 struct pci1xxxx_8250 *priv; 767 struct uart_8250_port uart; 768 unsigned int max_vec_reqd; 769 unsigned int nr_ports, i; 770 int num_vectors; 771 int subsys_dev; 772 int port_idx; 773 int ret; 774 int rc; 775 776 rc = pcim_enable_device(pdev); 777 if (rc) 778 return rc; 779 780 nr_ports = pci1xxxx_get_num_ports(pdev); 781 782 priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 783 if (!priv) 784 return -ENOMEM; 785 786 priv->membase = pci_ioremap_bar(pdev, 0); 787 if (!priv->membase) 788 return -ENOMEM; 789 790 ret = pci1xxxx_get_device_revision(priv); 791 if (ret) 792 return ret; 793 794 pci_set_master(pdev); 795 796 priv->nr = nr_ports; 797 798 subsys_dev = pdev->subsystem_device; 799 max_vec_reqd = pci1xxxx_get_max_port(subsys_dev); 800 801 num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES); 802 if (num_vectors < 0) { 803 pci_iounmap(pdev, priv->membase); 804 return num_vectors; 805 } 806 807 memset(&uart, 0, sizeof(uart)); 808 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 809 uart.port.dev = dev; 810 811 if (num_vectors == max_vec_reqd) 812 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); 813 814 for (i = 0; i < nr_ports; i++) { 815 priv->line[i] = -ENODEV; 816 817 port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i); 818 819 if (num_vectors == max_vec_reqd) 820 uart.port.irq = pci_irq_vector(pdev, port_idx); 821 else 822 uart.port.irq = pci_irq_vector(pdev, 0); 823 824 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv); 825 if (rc) { 826 dev_warn(dev, "Failed to setup port %u\n", i); 827 continue; 828 } 829 830 priv->line[i] = serial8250_register_8250_port(&uart); 831 if (priv->line[i] < 0) { 832 dev_warn(dev, 833 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 834 uart.port.iobase, uart.port.irq, uart.port.iotype, 835 priv->line[i]); 836 } 837 } 838 839 pci_set_drvdata(pdev, priv); 840 841 return 0; 842} 843 844static void pci1xxxx_serial_remove(struct pci_dev *dev) 845{ 846 struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); 847 unsigned int i; 848 849 for (i = 0; i < priv->nr; i++) { 850 if (priv->line[i] >= 0) 851 serial8250_unregister_port(priv->line[i]); 852 } 853 854 pci_free_irq_vectors(dev); 855 pci_iounmap(dev, priv->membase); 856} 857 858static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume); 859 860static const struct pci_device_id pci1xxxx_pci_tbl[] = { 861 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, 862 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, 863 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, 864 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, 865 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, 866 {} 867}; 868MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); 869 870static struct pci_driver pci1xxxx_pci_driver = { 871 .name = "pci1xxxx serial", 872 .probe = pci1xxxx_serial_probe, 873 .remove = pci1xxxx_serial_remove, 874 .driver = { 875 .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), 876 }, 877 .id_table = pci1xxxx_pci_tbl, 878}; 879module_pci_driver(pci1xxxx_pci_driver); 880 881static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1)); 882 883MODULE_IMPORT_NS("SERIAL_8250_PCI"); 884MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); 885MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>"); 886MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>"); 887MODULE_LICENSE("GPL");
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