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8250_pci.c
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linux-6.19.14/drivers/tty/serial/8250/8250_pci.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9#undef DEBUG 10#include <linux/module.h> 11#include <linux/pci.h> 12#include <linux/string.h> 13#include <linux/kernel.h> 14#include <linux/math.h> 15#include <linux/slab.h> 16#include <linux/delay.h> 17#include <linux/tty.h> 18#include <linux/serial_reg.h> 19#include <linux/serial_core.h> 20#include <linux/8250_pci.h> 21#include <linux/bitops.h> 22#include <linux/bitfield.h> 23 24#include <asm/byteorder.h> 25#include <asm/io.h> 26 27#include "8250.h" 28#include "8250_pcilib.h" 29 30#define PCI_VENDOR_ID_SBSMODULARIO 0x124B 31#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 32#define PCI_DEVICE_ID_OCTPRO 0x0001 33#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 34#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 35#define PCI_SUBDEVICE_ID_POCTAL232 0x0308 36#define PCI_SUBDEVICE_ID_POCTAL422 0x0408 37#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 38#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 39#define PCI_VENDOR_ID_ADVANTECH 0x13fe 40#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 41#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 42#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 43#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 44#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 45#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 46#define PCI_DEVICE_ID_TITAN_200I 0x8028 47#define PCI_DEVICE_ID_TITAN_400I 0x8048 48#define PCI_DEVICE_ID_TITAN_800I 0x8088 49#define PCI_DEVICE_ID_TITAN_800EH 0xA007 50#define PCI_DEVICE_ID_TITAN_800EHB 0xA008 51#define PCI_DEVICE_ID_TITAN_400EH 0xA009 52#define PCI_DEVICE_ID_TITAN_100E 0xA010 53#define PCI_DEVICE_ID_TITAN_200E 0xA012 54#define PCI_DEVICE_ID_TITAN_400E 0xA013 55#define PCI_DEVICE_ID_TITAN_800E 0xA014 56#define PCI_DEVICE_ID_TITAN_200EI 0xA016 57#define PCI_DEVICE_ID_TITAN_200EISI 0xA017 58#define PCI_DEVICE_ID_TITAN_200V3 0xA306 59#define PCI_DEVICE_ID_TITAN_400V3 0xA310 60#define PCI_DEVICE_ID_TITAN_410V3 0xA312 61#define PCI_DEVICE_ID_TITAN_800V3 0xA314 62#define PCI_DEVICE_ID_TITAN_800V3B 0xA315 63#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 64#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 65#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 66#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 67 68#define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253 69#define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173 70 71#define PCI_VENDOR_ID_AGESTAR 0x5372 72#define PCI_DEVICE_ID_AGESTAR_9375 0x6872 73#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 74#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 75 76#define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470 77#define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853 78 79#define PCI_DEVICE_ID_MOXA_CP102E 0x1024 80#define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 81#define PCI_DEVICE_ID_MOXA_CP102N 0x1027 82#define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 83#define PCI_DEVICE_ID_MOXA_CP104N 0x1046 84#define PCI_DEVICE_ID_MOXA_CP112N 0x1121 85#define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 86#define PCI_DEVICE_ID_MOXA_CP114N 0x1145 87#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 88#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 89#define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 90#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 91#define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 92#define PCI_DEVICE_ID_MOXA_CP132N 0x1323 93#define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 94#define PCI_DEVICE_ID_MOXA_CP134N 0x1343 95#define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 96#define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 97 98#define PCI_DEVICE_ID_ADDIDATA_CPCI7500 0x7003 99#define PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG 0x7024 100#define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025 101#define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026 102 103/* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 104#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 105#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 106 107/* 108 * init function returns: 109 * > 0 - number of ports 110 * = 0 - use board->num_ports 111 * < 0 - error 112 */ 113struct pci_serial_quirk { 114 u32 vendor; 115 u32 device; 116 u32 subvendor; 117 u32 subdevice; 118 int (*probe)(struct pci_dev *dev); 119 int (*init)(struct pci_dev *dev); 120 int (*setup)(struct serial_private *, 121 const struct pciserial_board *, 122 struct uart_8250_port *, int); 123 void (*exit)(struct pci_dev *dev); 124}; 125 126struct f815xxa_data { 127 spinlock_t lock; 128 int idx; 129}; 130 131struct serial_private { 132 struct pci_dev *dev; 133 unsigned int nr; 134 struct pci_serial_quirk *quirk; 135 const struct pciserial_board *board; 136 int line[]; 137}; 138 139#define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 140#define PCIE_VENDOR_ID_ASIX 0x125B 141#define PCIE_DEVICE_ID_AX99100 0x9100 142 143static const struct pci_device_id pci_use_msi[] = { 144 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 145 0xA000, 0x1000) }, 146 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 147 0xA000, 0x1000) }, 148 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 149 0xA000, 0x1000) }, 150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 151 0xA000, 0x1000) }, 152 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 153 PCI_ANY_ID, PCI_ANY_ID) }, 154 { PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100, 155 0xA000, 0x1000) }, 156 { } 157}; 158 159static int pci_default_setup(struct serial_private*, 160 const struct pciserial_board*, struct uart_8250_port *, int); 161 162static void moan_device(const char *str, struct pci_dev *dev) 163{ 164 pci_err(dev, "%s\n" 165 "Please send the output of lspci -vv, this\n" 166 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 167 "manufacturer and name of serial board or\n" 168 "modem board to <linux-serial@vger.kernel.org>.\n", 169 str, dev->vendor, dev->device, 170 dev->subsystem_vendor, dev->subsystem_device); 171} 172 173static int 174setup_port(struct serial_private *priv, struct uart_8250_port *port, 175 u8 bar, unsigned int offset, int regshift) 176{ 177 void __iomem *iomem = NULL; 178 179 if (pci_resource_flags(priv->dev, bar) & IORESOURCE_MEM) { 180 iomem = pcim_iomap(priv->dev, bar, 0); 181 if (!iomem) 182 return -ENOMEM; 183 } 184 185 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift, iomem); 186} 187 188/* 189 * ADDI-DATA GmbH communication cards <info@addi-data.com> 190 */ 191static int addidata_apci7800_setup(struct serial_private *priv, 192 const struct pciserial_board *board, 193 struct uart_8250_port *port, int idx) 194{ 195 unsigned int bar = 0, offset = board->first_offset; 196 bar = FL_GET_BASE(board->flags); 197 198 if (idx < 2) { 199 offset += idx * board->uart_offset; 200 } else if ((idx >= 2) && (idx < 4)) { 201 bar += 1; 202 offset += ((idx - 2) * board->uart_offset); 203 } else if ((idx >= 4) && (idx < 6)) { 204 bar += 2; 205 offset += ((idx - 4) * board->uart_offset); 206 } else if (idx >= 6) { 207 bar += 3; 208 offset += ((idx - 6) * board->uart_offset); 209 } 210 211 return setup_port(priv, port, bar, offset, board->reg_shift); 212} 213 214/* 215 * AFAVLAB uses a different mixture of BARs and offsets 216 * Not that ugly ;) -- HW 217 */ 218static int 219afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 220 struct uart_8250_port *port, int idx) 221{ 222 unsigned int bar, offset = board->first_offset; 223 224 bar = FL_GET_BASE(board->flags); 225 if (idx < 4) 226 bar += idx; 227 else { 228 bar = 4; 229 offset += (idx - 4) * board->uart_offset; 230 } 231 232 return setup_port(priv, port, bar, offset, board->reg_shift); 233} 234 235/* 236 * HP's Remote Management Console. The Diva chip came in several 237 * different versions. N-class, L2000 and A500 have two Diva chips, each 238 * with 3 UARTs (the third UART on the second chip is unused). Superdome 239 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 240 * one Diva chip, but it has been expanded to 5 UARTs. 241 */ 242static int pci_hp_diva_init(struct pci_dev *dev) 243{ 244 int rc = 0; 245 246 switch (dev->subsystem_device) { 247 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 248 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 249 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 250 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 251 rc = 3; 252 break; 253 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 254 rc = 2; 255 break; 256 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 257 rc = 4; 258 break; 259 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 260 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 261 rc = 1; 262 break; 263 } 264 265 return rc; 266} 267 268/* 269 * HP's Diva chip puts the 4th/5th serial port further out, and 270 * some serial ports are supposed to be hidden on certain models. 271 */ 272static int 273pci_hp_diva_setup(struct serial_private *priv, 274 const struct pciserial_board *board, 275 struct uart_8250_port *port, int idx) 276{ 277 unsigned int offset = board->first_offset; 278 unsigned int bar = FL_GET_BASE(board->flags); 279 280 switch (priv->dev->subsystem_device) { 281 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 282 if (idx == 3) 283 idx++; 284 break; 285 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 286 if (idx > 0) 287 idx++; 288 if (idx > 2) 289 idx++; 290 break; 291 } 292 if (idx > 2) 293 offset = 0x18; 294 295 offset += idx * board->uart_offset; 296 297 return setup_port(priv, port, bar, offset, board->reg_shift); 298} 299 300/* 301 * Added for EKF Intel i960 serial boards 302 */ 303static int pci_inteli960ni_init(struct pci_dev *dev) 304{ 305 u32 oldval; 306 307 if (!(dev->subsystem_device & 0x1000)) 308 return -ENODEV; 309 310 /* is firmware started? */ 311 pci_read_config_dword(dev, 0x44, &oldval); 312 if (oldval == 0x00001000L) { /* RESET value */ 313 pci_dbg(dev, "Local i960 firmware missing\n"); 314 return -ENODEV; 315 } 316 return 0; 317} 318 319/* 320 * Some PCI serial cards using the PLX 9050 PCI interface chip require 321 * that the card interrupt be explicitly enabled or disabled. This 322 * seems to be mainly needed on card using the PLX which also use I/O 323 * mapped memory. 324 */ 325static int pci_plx9050_init(struct pci_dev *dev) 326{ 327 u8 irq_config; 328 void __iomem *p; 329 330 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 331 moan_device("no memory in bar 0", dev); 332 return 0; 333 } 334 335 irq_config = 0x41; 336 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 337 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 338 irq_config = 0x43; 339 340 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 341 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 342 /* 343 * As the megawolf cards have the int pins active 344 * high, and have 2 UART chips, both ints must be 345 * enabled on the 9050. Also, the UARTS are set in 346 * 16450 mode by default, so we have to enable the 347 * 16C950 'enhanced' mode so that we can use the 348 * deep FIFOs 349 */ 350 irq_config = 0x5b; 351 /* 352 * enable/disable interrupts 353 */ 354 p = ioremap(pci_resource_start(dev, 0), 0x80); 355 if (p == NULL) 356 return -ENOMEM; 357 writel(irq_config, p + 0x4c); 358 359 /* 360 * Read the register back to ensure that it took effect. 361 */ 362 readl(p + 0x4c); 363 iounmap(p); 364 365 return 0; 366} 367 368static void pci_plx9050_exit(struct pci_dev *dev) 369{ 370 u8 __iomem *p; 371 372 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 373 return; 374 375 /* 376 * disable interrupts 377 */ 378 p = ioremap(pci_resource_start(dev, 0), 0x80); 379 if (p != NULL) { 380 writel(0, p + 0x4c); 381 382 /* 383 * Read the register back to ensure that it took effect. 384 */ 385 readl(p + 0x4c); 386 iounmap(p); 387 } 388} 389 390#define NI8420_INT_ENABLE_REG 0x38 391#define NI8420_INT_ENABLE_BIT 0x2000 392 393static void pci_ni8420_exit(struct pci_dev *dev) 394{ 395 void __iomem *p; 396 unsigned int bar = 0; 397 398 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 399 moan_device("no memory in bar", dev); 400 return; 401 } 402 403 p = pci_ioremap_bar(dev, bar); 404 if (p == NULL) 405 return; 406 407 /* Disable the CPU Interrupt */ 408 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 409 p + NI8420_INT_ENABLE_REG); 410 iounmap(p); 411} 412 413 414/* MITE registers */ 415#define MITE_IOWBSR1 0xc4 416#define MITE_IOWCR1 0xf4 417#define MITE_LCIMR1 0x08 418#define MITE_LCIMR2 0x10 419 420#define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 421 422static void pci_ni8430_exit(struct pci_dev *dev) 423{ 424 void __iomem *p; 425 unsigned int bar = 0; 426 427 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 428 moan_device("no memory in bar", dev); 429 return; 430 } 431 432 p = pci_ioremap_bar(dev, bar); 433 if (p == NULL) 434 return; 435 436 /* Disable the CPU Interrupt */ 437 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 438 iounmap(p); 439} 440 441/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 442static int 443sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 444 struct uart_8250_port *port, int idx) 445{ 446 unsigned int bar, offset = board->first_offset; 447 448 bar = 0; 449 450 if (idx < 4) { 451 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 452 offset += idx * board->uart_offset; 453 } else if (idx < 8) { 454 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 455 offset += idx * board->uart_offset + 0xC00; 456 } else /* we have only 8 ports on PMC-OCTALPRO */ 457 return 1; 458 459 return setup_port(priv, port, bar, offset, board->reg_shift); 460} 461 462/* 463* This does initialization for PMC OCTALPRO cards: 464* maps the device memory, resets the UARTs (needed, bc 465* if the module is removed and inserted again, the card 466* is in the sleep mode) and enables global interrupt. 467*/ 468 469/* global control register offset for SBS PMC-OctalPro */ 470#define OCT_REG_CR_OFF 0x500 471 472static int sbs_init(struct pci_dev *dev) 473{ 474 u8 __iomem *p; 475 476 p = pci_ioremap_bar(dev, 0); 477 478 if (p == NULL) 479 return -ENOMEM; 480 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 481 writeb(0x10, p + OCT_REG_CR_OFF); 482 udelay(50); 483 writeb(0x0, p + OCT_REG_CR_OFF); 484 485 /* Set bit-2 (INTENABLE) of Control Register */ 486 writeb(0x4, p + OCT_REG_CR_OFF); 487 iounmap(p); 488 489 return 0; 490} 491 492/* 493 * Disables the global interrupt of PMC-OctalPro 494 */ 495 496static void sbs_exit(struct pci_dev *dev) 497{ 498 u8 __iomem *p; 499 500 p = pci_ioremap_bar(dev, 0); 501 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 502 if (p != NULL) 503 writeb(0, p + OCT_REG_CR_OFF); 504 iounmap(p); 505} 506 507/* 508 * SIIG serial cards have an PCI interface chip which also controls 509 * the UART clocking frequency. Each UART can be clocked independently 510 * (except cards equipped with 4 UARTs) and initial clocking settings 511 * are stored in the EEPROM chip. It can cause problems because this 512 * version of serial driver doesn't support differently clocked UART's 513 * on single PCI card. To prevent this, initialization functions set 514 * high frequency clocking for all UART's on given card. It is safe (I 515 * hope) because it doesn't touch EEPROM settings to prevent conflicts 516 * with other OSes (like M$ DOS). 517 * 518 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 519 * 520 * There is two family of SIIG serial cards with different PCI 521 * interface chip and different configuration methods: 522 * - 10x cards have control registers in IO and/or memory space; 523 * - 20x cards have control registers in standard PCI configuration space. 524 * 525 * Note: all 10x cards have PCI device ids 0x10.. 526 * all 20x cards have PCI device ids 0x20.. 527 * 528 * There are also Quartet Serial cards which use Oxford Semiconductor 529 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 530 * 531 * Note: some SIIG cards are probed by the parport_serial object. 532 */ 533 534#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 535#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 536 537static int pci_siig10x_init(struct pci_dev *dev) 538{ 539 u16 data; 540 void __iomem *p; 541 542 switch (dev->device & 0xfff8) { 543 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 544 data = 0xffdf; 545 break; 546 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 547 data = 0xf7ff; 548 break; 549 default: /* 1S1P, 4S */ 550 data = 0xfffb; 551 break; 552 } 553 554 p = ioremap(pci_resource_start(dev, 0), 0x80); 555 if (p == NULL) 556 return -ENOMEM; 557 558 writew(readw(p + 0x28) & data, p + 0x28); 559 readw(p + 0x28); 560 iounmap(p); 561 return 0; 562} 563 564#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 565#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 566 567static int pci_siig20x_init(struct pci_dev *dev) 568{ 569 u8 data; 570 571 /* Change clock frequency for the first UART. */ 572 pci_read_config_byte(dev, 0x6f, &data); 573 pci_write_config_byte(dev, 0x6f, data & 0xef); 574 575 /* If this card has 2 UART, we have to do the same with second UART. */ 576 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 577 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 578 pci_read_config_byte(dev, 0x73, &data); 579 pci_write_config_byte(dev, 0x73, data & 0xef); 580 } 581 return 0; 582} 583 584static int pci_siig_init(struct pci_dev *dev) 585{ 586 unsigned int type = dev->device & 0xff00; 587 588 if (type == 0x1000) 589 return pci_siig10x_init(dev); 590 if (type == 0x2000) 591 return pci_siig20x_init(dev); 592 593 moan_device("Unknown SIIG card", dev); 594 return -ENODEV; 595} 596 597static int pci_siig_setup(struct serial_private *priv, 598 const struct pciserial_board *board, 599 struct uart_8250_port *port, int idx) 600{ 601 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 602 603 if (idx > 3) { 604 bar = 4; 605 offset = (idx - 4) * 8; 606 } 607 608 return setup_port(priv, port, bar, offset, 0); 609} 610 611/* 612 * Timedia has an explosion of boards, and to avoid the PCI table from 613 * growing *huge*, we use this function to collapse some 70 entries 614 * in the PCI table into one, for sanity's and compactness's sake. 615 */ 616static const unsigned short timedia_single_port[] = { 617 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 618}; 619 620static const unsigned short timedia_dual_port[] = { 621 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 622 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 623 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 624 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 625 0xD079, 0 626}; 627 628static const unsigned short timedia_quad_port[] = { 629 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 630 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 631 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 632 0xB157, 0 633}; 634 635static const unsigned short timedia_eight_port[] = { 636 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 637 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 638}; 639 640static const struct timedia_struct { 641 int num; 642 const unsigned short *ids; 643} timedia_data[] = { 644 { 1, timedia_single_port }, 645 { 2, timedia_dual_port }, 646 { 4, timedia_quad_port }, 647 { 8, timedia_eight_port } 648}; 649 650/* 651 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 652 * listing them individually, this driver merely grabs them all with 653 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 654 * and should be left free to be claimed by parport_serial instead. 655 */ 656static int pci_timedia_probe(struct pci_dev *dev) 657{ 658 /* 659 * Check the third digit of the subdevice ID 660 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 661 */ 662 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 663 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 664 dev->subsystem_device); 665 return -ENODEV; 666 } 667 668 return 0; 669} 670 671static int pci_timedia_init(struct pci_dev *dev) 672{ 673 const unsigned short *ids; 674 int i, j; 675 676 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 677 ids = timedia_data[i].ids; 678 for (j = 0; ids[j]; j++) 679 if (dev->subsystem_device == ids[j]) 680 return timedia_data[i].num; 681 } 682 return 0; 683} 684 685/* 686 * Timedia/SUNIX uses a mixture of BARs and offsets 687 * Ugh, this is ugly as all hell --- TYT 688 */ 689static int 690pci_timedia_setup(struct serial_private *priv, 691 const struct pciserial_board *board, 692 struct uart_8250_port *port, int idx) 693{ 694 unsigned int bar = 0, offset = board->first_offset; 695 696 switch (idx) { 697 case 0: 698 bar = 0; 699 break; 700 case 1: 701 offset = board->uart_offset; 702 bar = 0; 703 break; 704 case 2: 705 bar = 1; 706 break; 707 case 3: 708 offset = board->uart_offset; 709 fallthrough; 710 case 4: /* BAR 2 */ 711 case 5: /* BAR 3 */ 712 case 6: /* BAR 4 */ 713 case 7: /* BAR 5 */ 714 bar = idx - 2; 715 } 716 717 return setup_port(priv, port, bar, offset, board->reg_shift); 718} 719 720/* 721 * Some Titan cards are also a little weird 722 */ 723static int 724titan_400l_800l_setup(struct serial_private *priv, 725 const struct pciserial_board *board, 726 struct uart_8250_port *port, int idx) 727{ 728 unsigned int bar, offset = board->first_offset; 729 730 switch (idx) { 731 case 0: 732 bar = 1; 733 break; 734 case 1: 735 bar = 2; 736 break; 737 default: 738 bar = 4; 739 offset = (idx - 2) * board->uart_offset; 740 } 741 742 return setup_port(priv, port, bar, offset, board->reg_shift); 743} 744 745static int pci_xircom_init(struct pci_dev *dev) 746{ 747 msleep(100); 748 return 0; 749} 750 751static int pci_ni8420_init(struct pci_dev *dev) 752{ 753 void __iomem *p; 754 unsigned int bar = 0; 755 756 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 757 moan_device("no memory in bar", dev); 758 return 0; 759 } 760 761 p = pci_ioremap_bar(dev, bar); 762 if (p == NULL) 763 return -ENOMEM; 764 765 /* Enable CPU Interrupt */ 766 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 767 p + NI8420_INT_ENABLE_REG); 768 769 iounmap(p); 770 return 0; 771} 772 773#define MITE_IOWBSR1_WSIZE 0xa 774#define MITE_IOWBSR1_WIN_OFFSET 0x800 775#define MITE_IOWBSR1_WENAB (1 << 7) 776#define MITE_LCIMR1_IO_IE_0 (1 << 24) 777#define MITE_LCIMR2_SET_CPU_IE (1 << 31) 778#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 779 780static int pci_ni8430_init(struct pci_dev *dev) 781{ 782 void __iomem *p; 783 struct pci_bus_region region; 784 u32 device_window; 785 unsigned int bar = 0; 786 787 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 788 moan_device("no memory in bar", dev); 789 return 0; 790 } 791 792 p = pci_ioremap_bar(dev, bar); 793 if (p == NULL) 794 return -ENOMEM; 795 796 /* 797 * Set device window address and size in BAR0, while acknowledging that 798 * the resource structure may contain a translated address that differs 799 * from the address the device responds to. 800 */ 801 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 802 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 803 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 804 writel(device_window, p + MITE_IOWBSR1); 805 806 /* Set window access to go to RAMSEL IO address space */ 807 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 808 p + MITE_IOWCR1); 809 810 /* Enable IO Bus Interrupt 0 */ 811 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 812 813 /* Enable CPU Interrupt */ 814 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 815 816 iounmap(p); 817 return 0; 818} 819 820/* UART Port Control Register */ 821#define NI8430_PORTCON 0x0f 822#define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 823 824static int 825pci_ni8430_setup(struct serial_private *priv, 826 const struct pciserial_board *board, 827 struct uart_8250_port *port, int idx) 828{ 829 struct pci_dev *dev = priv->dev; 830 void __iomem *p; 831 unsigned int bar, offset = board->first_offset; 832 833 if (idx >= board->num_ports) 834 return 1; 835 836 bar = FL_GET_BASE(board->flags); 837 offset += idx * board->uart_offset; 838 839 p = pci_ioremap_bar(dev, bar); 840 if (!p) 841 return -ENOMEM; 842 843 /* enable the transceiver */ 844 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 845 p + offset + NI8430_PORTCON); 846 847 iounmap(p); 848 849 return setup_port(priv, port, bar, offset, board->reg_shift); 850} 851 852static int pci_netmos_9900_setup(struct serial_private *priv, 853 const struct pciserial_board *board, 854 struct uart_8250_port *port, int idx) 855{ 856 unsigned int bar; 857 858 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 859 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 860 /* netmos apparently orders BARs by datasheet layout, so serial 861 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 862 */ 863 bar = 3 * idx; 864 865 return setup_port(priv, port, bar, 0, board->reg_shift); 866 } 867 868 return pci_default_setup(priv, board, port, idx); 869} 870 871/* the 99xx series comes with a range of device IDs and a variety 872 * of capabilities: 873 * 874 * 9900 has varying capabilities and can cascade to sub-controllers 875 * (cascading should be purely internal) 876 * 9904 is hardwired with 4 serial ports 877 * 9912 and 9922 are hardwired with 2 serial ports 878 */ 879static int pci_netmos_9900_numports(struct pci_dev *dev) 880{ 881 unsigned int c = dev->class; 882 unsigned int pi; 883 unsigned short sub_serports; 884 885 pi = c & 0xff; 886 887 if (pi == 2) 888 return 1; 889 890 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 891 /* two possibilities: 0x30ps encodes number of parallel and 892 * serial ports, or 0x1000 indicates *something*. This is not 893 * immediately obvious, since the 2s1p+4s configuration seems 894 * to offer all functionality on functions 0..2, while still 895 * advertising the same function 3 as the 4s+2s1p config. 896 */ 897 sub_serports = dev->subsystem_device & 0xf; 898 if (sub_serports > 0) 899 return sub_serports; 900 901 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 902 return 0; 903 } 904 905 moan_device("unknown NetMos/Mostech program interface", dev); 906 return 0; 907} 908 909static int pci_netmos_init(struct pci_dev *dev) 910{ 911 /* subdevice 0x00PS means <P> parallel, <S> serial */ 912 unsigned int num_serial = dev->subsystem_device & 0xf; 913 914 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 915 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 916 return 0; 917 918 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 919 dev->subsystem_device == 0x0299) 920 return 0; 921 922 switch (dev->device) { /* FALLTHROUGH on all */ 923 case PCI_DEVICE_ID_NETMOS_9904: 924 case PCI_DEVICE_ID_NETMOS_9912: 925 case PCI_DEVICE_ID_NETMOS_9922: 926 case PCI_DEVICE_ID_NETMOS_9900: 927 case PCIE_DEVICE_ID_AX99100: 928 num_serial = pci_netmos_9900_numports(dev); 929 break; 930 931 default: 932 break; 933 } 934 935 if (num_serial == 0) { 936 moan_device("unknown NetMos/Mostech device", dev); 937 return -ENODEV; 938 } 939 940 return num_serial; 941} 942 943/* 944 * These chips are available with optionally one parallel port and up to 945 * two serial ports. Unfortunately they all have the same product id. 946 * 947 * Basic configuration is done over a region of 32 I/O ports. The base 948 * ioport is called INTA or INTC, depending on docs/other drivers. 949 * 950 * The region of the 32 I/O ports is configured in POSIO0R... 951 */ 952 953/* registers */ 954#define ITE_887x_MISCR 0x9c 955#define ITE_887x_INTCBAR 0x78 956#define ITE_887x_UARTBAR 0x7c 957#define ITE_887x_PS0BAR 0x10 958#define ITE_887x_POSIO0 0x60 959 960/* I/O space size */ 961#define ITE_887x_IOSIZE 32 962/* I/O space size (bits 26-24; 8 bytes = 011b) */ 963#define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 964/* I/O space size (bits 26-24; 32 bytes = 101b) */ 965#define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 966/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 967#define ITE_887x_POSIO_SPEED (3 << 29) 968/* enable IO_Space bit */ 969#define ITE_887x_POSIO_ENABLE (1 << 31) 970 971/* inta_addr are the configuration addresses of the ITE */ 972static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 973static int pci_ite887x_init(struct pci_dev *dev) 974{ 975 int ret, i, type; 976 struct resource *iobase = NULL; 977 u32 miscr, uartbar, ioport; 978 979 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 980 return serial_8250_warn_need_ioport(dev); 981 982 /* search for the base-ioport */ 983 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 984 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 985 "ite887x"); 986 if (iobase != NULL) { 987 /* write POSIO0R - speed | size | ioport */ 988 pci_write_config_dword(dev, ITE_887x_POSIO0, 989 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 990 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 991 /* write INTCBAR - ioport */ 992 pci_write_config_dword(dev, ITE_887x_INTCBAR, 993 inta_addr[i]); 994 ret = inb(inta_addr[i]); 995 if (ret != 0xff) { 996 /* ioport connected */ 997 break; 998 } 999 release_region(iobase->start, ITE_887x_IOSIZE); 1000 } 1001 } 1002 1003 if (i == ARRAY_SIZE(inta_addr)) { 1004 pci_err(dev, "could not find iobase\n"); 1005 return -ENODEV; 1006 } 1007 1008 /* start of undocumented type checking (see parport_pc.c) */ 1009 type = inb(iobase->start + 0x18) & 0x0f; 1010 1011 switch (type) { 1012 case 0x2: /* ITE8871 (1P) */ 1013 case 0xa: /* ITE8875 (1P) */ 1014 ret = 0; 1015 break; 1016 case 0xe: /* ITE8872 (2S1P) */ 1017 ret = 2; 1018 break; 1019 case 0x6: /* ITE8873 (1S) */ 1020 ret = 1; 1021 break; 1022 case 0x8: /* ITE8874 (2S) */ 1023 ret = 2; 1024 break; 1025 default: 1026 moan_device("Unknown ITE887x", dev); 1027 ret = -ENODEV; 1028 } 1029 1030 /* configure all serial ports */ 1031 for (i = 0; i < ret; i++) { 1032 /* read the I/O port from the device */ 1033 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 1034 &ioport); 1035 ioport &= 0x0000FF00; /* the actual base address */ 1036 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 1037 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 1038 ITE_887x_POSIO_IOSIZE_8 | ioport); 1039 1040 /* write the ioport to the UARTBAR */ 1041 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 1042 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 1043 uartbar |= (ioport << (16 * i)); /* set the ioport */ 1044 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 1045 1046 /* get current config */ 1047 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 1048 /* disable interrupts (UARTx_Routing[3:0]) */ 1049 miscr &= ~(0xf << (12 - 4 * i)); 1050 /* activate the UART (UARTx_En) */ 1051 miscr |= 1 << (23 - i); 1052 /* write new config with activated UART */ 1053 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 1054 } 1055 1056 if (ret <= 0) { 1057 /* the device has no UARTs if we get here */ 1058 release_region(iobase->start, ITE_887x_IOSIZE); 1059 } 1060 1061 return ret; 1062} 1063 1064static void pci_ite887x_exit(struct pci_dev *dev) 1065{ 1066 u32 ioport; 1067 /* the ioport is bit 0-15 in POSIO0R */ 1068 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 1069 ioport &= 0xffff; 1070 release_region(ioport, ITE_887x_IOSIZE); 1071} 1072 1073/* 1074 * Oxford Semiconductor Inc. 1075 * Check if an OxSemi device is part of the Tornado range of devices. 1076 */ 1077#define PCI_VENDOR_ID_ENDRUN 0x7401 1078#define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1079 1080static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1081{ 1082 /* OxSemi Tornado devices are all 0xCxxx */ 1083 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1084 (dev->device & 0xf000) != 0xc000) 1085 return false; 1086 1087 /* EndRun devices are all 0xExxx */ 1088 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1089 (dev->device & 0xf000) != 0xe000) 1090 return false; 1091 1092 return true; 1093} 1094 1095/* 1096 * Determine the number of ports available on a Tornado device. 1097 */ 1098static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1099{ 1100 u8 __iomem *p; 1101 unsigned long deviceID; 1102 unsigned int number_uarts = 0; 1103 1104 if (!pci_oxsemi_tornado_p(dev)) 1105 return 0; 1106 1107 p = pci_iomap(dev, 0, 5); 1108 if (p == NULL) 1109 return -ENOMEM; 1110 1111 deviceID = ioread32(p); 1112 /* Tornado device */ 1113 if (deviceID == 0x07000200) { 1114 number_uarts = ioread8(p + 4); 1115 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1116 number_uarts, 1117 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1118 "EndRun" : "Oxford"); 1119 } 1120 pci_iounmap(dev, p); 1121 return number_uarts; 1122} 1123 1124/* Tornado-specific constants for the TCR and CPR registers; see below. */ 1125#define OXSEMI_TORNADO_TCR_MASK 0xf 1126#define OXSEMI_TORNADO_CPR_MASK 0x1ff 1127#define OXSEMI_TORNADO_CPR_MIN 0x008 1128#define OXSEMI_TORNADO_CPR_DEF 0x10f 1129 1130/* 1131 * Determine the oversampling rate, the clock prescaler, and the clock 1132 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1133 * which is four times the baud base, and the prescaler increments in 1134 * steps of 1/8. Therefore to make calculations on integers we need 1135 * to use a scaled clock rate, which is the baud base multiplied by 32 1136 * (or our assumed UART clock rate multiplied by 2). 1137 * 1138 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1139 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1140 * values between 1.000 and 63.875 inclusive (operation for values from 1141 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1142 * unsigned 16-bit integer. 1143 * 1144 * For the most accurate baud rate we use a table of predetermined 1145 * oversampling rates and clock prescalers that records all possible 1146 * products of the two parameters in the range from 4 up to 255 inclusive, 1147 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1148 * by 8. The table is sorted by the decreasing value of the oversampling 1149 * rate and ties are resolved by sorting by the decreasing value of the 1150 * product. This way preference is given to higher oversampling rates. 1151 * 1152 * We iterate over the table and choose the product of an oversampling 1153 * rate and a clock prescaler that gives the lowest integer division 1154 * result deviation, or if an exact integer divider is found we stop 1155 * looking for it right away. We do some fixup if the resulting clock 1156 * divisor required would be out of its unsigned 16-bit integer range. 1157 * 1158 * Finally we abuse the supposed fractional part returned to encode the 1159 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1160 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1161 */ 1162static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1163 unsigned int baud, 1164 unsigned int *frac) 1165{ 1166 static u8 p[][2] = { 1167 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1168 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1169 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1170 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1171 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1172 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1173 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1174 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1175 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1176 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1177 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1178 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1179 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1180 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1181 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1182 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1183 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1184 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1185 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1186 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1187 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1188 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1189 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1190 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1191 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1192 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1193 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1194 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1195 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1196 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1197 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1198 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1199 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1200 { 4, 9, }, { 4, 8, }, 1201 }; 1202 /* Scale the quotient for comparison to get the fractional part. */ 1203 const unsigned int quot_scale = 65536; 1204 unsigned int sclk = port->uartclk * 2; 1205 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1206 unsigned int best_squot; 1207 unsigned int squot; 1208 unsigned int quot; 1209 u16 cpr; 1210 u8 tcr; 1211 int i; 1212 1213 /* Old custom speed handling. */ 1214 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1215 unsigned int cust_div = port->custom_divisor; 1216 1217 quot = cust_div & UART_DIV_MAX; 1218 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1219 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1220 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1221 cpr = OXSEMI_TORNADO_CPR_DEF; 1222 } else { 1223 best_squot = quot_scale; 1224 for (i = 0; i < ARRAY_SIZE(p); i++) { 1225 unsigned int spre; 1226 unsigned int srem; 1227 u8 cp; 1228 u8 tc; 1229 1230 tc = p[i][0]; 1231 cp = p[i][1]; 1232 spre = tc * cp; 1233 1234 srem = sdiv % spre; 1235 if (srem > spre / 2) 1236 srem = spre - srem; 1237 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1238 1239 if (srem == 0) { 1240 tcr = tc; 1241 cpr = cp; 1242 quot = sdiv / spre; 1243 break; 1244 } else if (squot < best_squot) { 1245 best_squot = squot; 1246 tcr = tc; 1247 cpr = cp; 1248 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1249 } 1250 } 1251 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1252 quot % 2 == 0) { 1253 quot >>= 1; 1254 tcr <<= 1; 1255 } 1256 while (quot > UART_DIV_MAX) { 1257 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1258 quot >>= 1; 1259 tcr <<= 1; 1260 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1261 quot >>= 1; 1262 cpr <<= 1; 1263 } else { 1264 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1265 cpr = OXSEMI_TORNADO_CPR_MASK; 1266 } 1267 } 1268 } 1269 1270 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1271 return quot; 1272} 1273 1274/* 1275 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1276 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1277 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1278 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1279 * has to be written first, followed by CPR2, which occupies the location 1280 * of CKS used with earlier UART designs. 1281 */ 1282static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1283 unsigned int baud, 1284 unsigned int quot, 1285 unsigned int quot_frac) 1286{ 1287 struct uart_8250_port *up = up_to_u8250p(port); 1288 u8 cpr2 = quot_frac >> 16; 1289 u8 cpr = quot_frac >> 8; 1290 u8 tcr = quot_frac; 1291 1292 serial_icr_write(up, UART_TCR, tcr); 1293 serial_icr_write(up, UART_CPR, cpr); 1294 serial_icr_write(up, UART_CKS, cpr2); 1295 serial8250_do_set_divisor(port, baud, quot); 1296} 1297 1298/* 1299 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1300 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1301 */ 1302static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1303 unsigned int mctrl) 1304{ 1305 struct uart_8250_port *up = up_to_u8250p(port); 1306 1307 up->mcr |= UART_MCR_CLKSEL; 1308 serial8250_do_set_mctrl(port, mctrl); 1309} 1310 1311/* 1312 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1313 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1314 */ 1315static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1316 const struct pciserial_board *board, 1317 struct uart_8250_port *up, int idx) 1318{ 1319 struct pci_dev *dev = priv->dev; 1320 1321 if (pci_oxsemi_tornado_p(dev)) { 1322 up->port.flags |= UPF_FULL_PROBE; 1323 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1324 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1325 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1326 } 1327 1328 return pci_default_setup(priv, board, up, idx); 1329} 1330 1331#define QPCR_TEST_FOR1 0x3F 1332#define QPCR_TEST_GET1 0x00 1333#define QPCR_TEST_FOR2 0x40 1334#define QPCR_TEST_GET2 0x40 1335#define QPCR_TEST_FOR3 0x80 1336#define QPCR_TEST_GET3 0x40 1337#define QPCR_TEST_FOR4 0xC0 1338#define QPCR_TEST_GET4 0x80 1339 1340#define QOPR_CLOCK_X1 0x0000 1341#define QOPR_CLOCK_X2 0x0001 1342#define QOPR_CLOCK_X4 0x0002 1343#define QOPR_CLOCK_X8 0x0003 1344#define QOPR_CLOCK_RATE_MASK 0x0003 1345 1346/* Quatech devices have their own extra interface features */ 1347static struct pci_device_id quatech_cards[] = { 1348 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1349 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1350 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1351 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1352 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1353 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1354 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1355 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1356 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1357 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1358 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1359 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1360 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1361 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1362 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1363 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1364 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1365 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1366 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1367 { 0, } 1368}; 1369 1370static int pci_quatech_rqopr(struct uart_8250_port *port) 1371{ 1372 unsigned long base = port->port.iobase; 1373 u8 LCR, val; 1374 1375 LCR = inb(base + UART_LCR); 1376 outb(0xBF, base + UART_LCR); 1377 val = inb(base + UART_SCR); 1378 outb(LCR, base + UART_LCR); 1379 return val; 1380} 1381 1382static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1383{ 1384 unsigned long base = port->port.iobase; 1385 u8 LCR; 1386 1387 LCR = inb(base + UART_LCR); 1388 outb(0xBF, base + UART_LCR); 1389 inb(base + UART_SCR); 1390 outb(qopr, base + UART_SCR); 1391 outb(LCR, base + UART_LCR); 1392} 1393 1394static int pci_quatech_rqmcr(struct uart_8250_port *port) 1395{ 1396 unsigned long base = port->port.iobase; 1397 u8 LCR, val, qmcr; 1398 1399 LCR = inb(base + UART_LCR); 1400 outb(0xBF, base + UART_LCR); 1401 val = inb(base + UART_SCR); 1402 outb(val | 0x10, base + UART_SCR); 1403 qmcr = inb(base + UART_MCR); 1404 outb(val, base + UART_SCR); 1405 outb(LCR, base + UART_LCR); 1406 1407 return qmcr; 1408} 1409 1410static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1411{ 1412 unsigned long base = port->port.iobase; 1413 u8 LCR, val; 1414 1415 LCR = inb(base + UART_LCR); 1416 outb(0xBF, base + UART_LCR); 1417 val = inb(base + UART_SCR); 1418 outb(val | 0x10, base + UART_SCR); 1419 outb(qmcr, base + UART_MCR); 1420 outb(val, base + UART_SCR); 1421 outb(LCR, base + UART_LCR); 1422} 1423 1424static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1425{ 1426 unsigned long base = port->port.iobase; 1427 u8 LCR, val; 1428 1429 LCR = inb(base + UART_LCR); 1430 outb(0xBF, base + UART_LCR); 1431 val = inb(base + UART_SCR); 1432 if (val & 0x20) { 1433 outb(0x80, UART_LCR); 1434 if (!(inb(UART_SCR) & 0x20)) { 1435 outb(LCR, base + UART_LCR); 1436 return 1; 1437 } 1438 } 1439 return 0; 1440} 1441 1442static int pci_quatech_test(struct uart_8250_port *port) 1443{ 1444 u8 reg, qopr; 1445 1446 qopr = pci_quatech_rqopr(port); 1447 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1448 reg = pci_quatech_rqopr(port) & 0xC0; 1449 if (reg != QPCR_TEST_GET1) 1450 return -EINVAL; 1451 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1452 reg = pci_quatech_rqopr(port) & 0xC0; 1453 if (reg != QPCR_TEST_GET2) 1454 return -EINVAL; 1455 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1456 reg = pci_quatech_rqopr(port) & 0xC0; 1457 if (reg != QPCR_TEST_GET3) 1458 return -EINVAL; 1459 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1460 reg = pci_quatech_rqopr(port) & 0xC0; 1461 if (reg != QPCR_TEST_GET4) 1462 return -EINVAL; 1463 1464 pci_quatech_wqopr(port, qopr); 1465 return 0; 1466} 1467 1468static int pci_quatech_clock(struct uart_8250_port *port) 1469{ 1470 u8 qopr, reg, set; 1471 unsigned long clock; 1472 1473 if (pci_quatech_test(port) < 0) 1474 return 1843200; 1475 1476 qopr = pci_quatech_rqopr(port); 1477 1478 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1479 reg = pci_quatech_rqopr(port); 1480 if (reg & QOPR_CLOCK_X8) { 1481 clock = 1843200; 1482 goto out; 1483 } 1484 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1485 reg = pci_quatech_rqopr(port); 1486 if (!(reg & QOPR_CLOCK_X8)) { 1487 clock = 1843200; 1488 goto out; 1489 } 1490 reg &= QOPR_CLOCK_X8; 1491 if (reg == QOPR_CLOCK_X2) { 1492 clock = 3685400; 1493 set = QOPR_CLOCK_X2; 1494 } else if (reg == QOPR_CLOCK_X4) { 1495 clock = 7372800; 1496 set = QOPR_CLOCK_X4; 1497 } else if (reg == QOPR_CLOCK_X8) { 1498 clock = 14745600; 1499 set = QOPR_CLOCK_X8; 1500 } else { 1501 clock = 1843200; 1502 set = QOPR_CLOCK_X1; 1503 } 1504 qopr &= ~QOPR_CLOCK_RATE_MASK; 1505 qopr |= set; 1506 1507out: 1508 pci_quatech_wqopr(port, qopr); 1509 return clock; 1510} 1511 1512static int pci_quatech_rs422(struct uart_8250_port *port) 1513{ 1514 u8 qmcr; 1515 int rs422 = 0; 1516 1517 if (!pci_quatech_has_qmcr(port)) 1518 return 0; 1519 qmcr = pci_quatech_rqmcr(port); 1520 pci_quatech_wqmcr(port, 0xFF); 1521 if (pci_quatech_rqmcr(port)) 1522 rs422 = 1; 1523 pci_quatech_wqmcr(port, qmcr); 1524 return rs422; 1525} 1526 1527static int pci_quatech_init(struct pci_dev *dev) 1528{ 1529 const struct pci_device_id *match; 1530 bool amcc = false; 1531 1532 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1533 return serial_8250_warn_need_ioport(dev); 1534 1535 match = pci_match_id(quatech_cards, dev); 1536 if (match) 1537 amcc = match->driver_data; 1538 else 1539 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1540 1541 if (amcc) { 1542 unsigned long base = pci_resource_start(dev, 0); 1543 if (base) { 1544 u32 tmp; 1545 1546 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1547 tmp = inl(base + 0x3c); 1548 outl(tmp | 0x01000000, base + 0x3c); 1549 outl(tmp & ~0x01000000, base + 0x3c); 1550 } 1551 } 1552 return 0; 1553} 1554 1555static int pci_quatech_setup(struct serial_private *priv, 1556 const struct pciserial_board *board, 1557 struct uart_8250_port *port, int idx) 1558{ 1559 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1560 return serial_8250_warn_need_ioport(priv->dev); 1561 1562 /* Needed by pci_quatech calls below */ 1563 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1564 /* Set up the clocking */ 1565 port->port.uartclk = pci_quatech_clock(port); 1566 /* For now just warn about RS422 */ 1567 if (pci_quatech_rs422(port)) 1568 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1569 return pci_default_setup(priv, board, port, idx); 1570} 1571 1572static int pci_default_setup(struct serial_private *priv, 1573 const struct pciserial_board *board, 1574 struct uart_8250_port *port, int idx) 1575{ 1576 unsigned int bar, offset = board->first_offset, maxnr; 1577 1578 bar = FL_GET_BASE(board->flags); 1579 if (board->flags & FL_BASE_BARS) 1580 bar += idx; 1581 else 1582 offset += idx * board->uart_offset; 1583 1584 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1585 (board->reg_shift + 3); 1586 1587 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1588 return 1; 1589 1590 return setup_port(priv, port, bar, offset, board->reg_shift); 1591} 1592 1593static int 1594ce4100_serial_setup(struct serial_private *priv, 1595 const struct pciserial_board *board, 1596 struct uart_8250_port *port, int idx) 1597{ 1598 int ret; 1599 1600 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1601 port->port.iotype = UPIO_MEM32; 1602 port->port.type = PORT_XSCALE; 1603 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1604 port->port.regshift = 2; 1605 1606 return ret; 1607} 1608 1609static int 1610pci_omegapci_setup(struct serial_private *priv, 1611 const struct pciserial_board *board, 1612 struct uart_8250_port *port, int idx) 1613{ 1614 return setup_port(priv, port, 2, idx * 8, 0); 1615} 1616 1617static int 1618pci_brcm_trumanage_setup(struct serial_private *priv, 1619 const struct pciserial_board *board, 1620 struct uart_8250_port *port, int idx) 1621{ 1622 int ret = pci_default_setup(priv, board, port, idx); 1623 1624 port->port.type = PORT_BRCM_TRUMANAGE; 1625 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1626 return ret; 1627} 1628 1629/* RTS will control by MCR if this bit is 0 */ 1630#define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1631/* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1632#define FINTEK_RTS_INVERT BIT(5) 1633 1634/* We should do proper H/W transceiver setting before change to RS485 mode */ 1635static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1636 struct serial_rs485 *rs485) 1637{ 1638 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1639 u8 setting; 1640 u8 *index = (u8 *) port->private_data; 1641 1642 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1643 1644 if (rs485->flags & SER_RS485_ENABLED) { 1645 /* Enable RTS H/W control mode */ 1646 setting |= FINTEK_RTS_CONTROL_BY_HW; 1647 1648 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1649 /* RTS driving high on TX */ 1650 setting &= ~FINTEK_RTS_INVERT; 1651 } else { 1652 /* RTS driving low on TX */ 1653 setting |= FINTEK_RTS_INVERT; 1654 } 1655 } else { 1656 /* Disable RTS H/W control mode */ 1657 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1658 } 1659 1660 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1661 1662 return 0; 1663} 1664 1665static const struct serial_rs485 pci_fintek_rs485_supported = { 1666 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 1667 /* F81504/508/512 does not support RTS delay before or after send */ 1668}; 1669 1670static int pci_fintek_setup(struct serial_private *priv, 1671 const struct pciserial_board *board, 1672 struct uart_8250_port *port, int idx) 1673{ 1674 struct pci_dev *pdev = priv->dev; 1675 u8 *data; 1676 u8 config_base; 1677 u16 iobase; 1678 1679 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1680 return serial_8250_warn_need_ioport(pdev); 1681 1682 config_base = 0x40 + 0x08 * idx; 1683 1684 /* Get the io address from configuration space */ 1685 pci_read_config_word(pdev, config_base + 4, &iobase); 1686 1687 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1688 1689 port->port.iotype = UPIO_PORT; 1690 port->port.iobase = iobase; 1691 port->port.rs485_config = pci_fintek_rs485_config; 1692 port->port.rs485_supported = pci_fintek_rs485_supported; 1693 1694 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1695 if (!data) 1696 return -ENOMEM; 1697 1698 /* preserve index in PCI configuration space */ 1699 *data = idx; 1700 port->port.private_data = data; 1701 1702 return 0; 1703} 1704 1705static int pci_fintek_init(struct pci_dev *dev) 1706{ 1707 unsigned long iobase; 1708 u32 max_port, i; 1709 resource_size_t bar_data[3]; 1710 u8 config_base; 1711 struct serial_private *priv = pci_get_drvdata(dev); 1712 1713 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1714 return serial_8250_warn_need_ioport(dev); 1715 1716 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1717 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1718 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1719 return -ENODEV; 1720 1721 switch (dev->device) { 1722 case 0x1104: /* 4 ports */ 1723 case 0x1108: /* 8 ports */ 1724 max_port = dev->device & 0xff; 1725 break; 1726 case 0x1112: /* 12 ports */ 1727 max_port = 12; 1728 break; 1729 default: 1730 return -EINVAL; 1731 } 1732 1733 /* Get the io address dispatch from the BIOS */ 1734 bar_data[0] = pci_resource_start(dev, 5); 1735 bar_data[1] = pci_resource_start(dev, 4); 1736 bar_data[2] = pci_resource_start(dev, 3); 1737 1738 for (i = 0; i < max_port; ++i) { 1739 /* UART0 configuration offset start from 0x40 */ 1740 config_base = 0x40 + 0x08 * i; 1741 1742 /* Calculate Real IO Port */ 1743 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1744 1745 /* Enable UART I/O port */ 1746 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1747 1748 /* Select 128-byte FIFO and 8x FIFO threshold */ 1749 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1750 1751 /* LSB UART */ 1752 pci_write_config_byte(dev, config_base + 0x04, 1753 (u8)(iobase & 0xff)); 1754 1755 /* MSB UART */ 1756 pci_write_config_byte(dev, config_base + 0x05, 1757 (u8)((iobase & 0xff00) >> 8)); 1758 1759 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1760 1761 if (!priv) { 1762 /* First init without port data 1763 * force init to RS232 Mode 1764 */ 1765 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1766 } 1767 } 1768 1769 return max_port; 1770} 1771 1772static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value) 1773{ 1774 struct f815xxa_data *data = p->private_data; 1775 unsigned long flags; 1776 1777 spin_lock_irqsave(&data->lock, flags); 1778 writeb(value, p->membase + offset); 1779 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1780 spin_unlock_irqrestore(&data->lock, flags); 1781} 1782 1783static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1784 const struct pciserial_board *board, 1785 struct uart_8250_port *port, int idx) 1786{ 1787 struct pci_dev *pdev = priv->dev; 1788 struct f815xxa_data *data; 1789 1790 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1791 if (!data) 1792 return -ENOMEM; 1793 1794 data->idx = idx; 1795 spin_lock_init(&data->lock); 1796 1797 port->port.private_data = data; 1798 port->port.iotype = UPIO_MEM; 1799 port->port.flags |= UPF_IOREMAP; 1800 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1801 port->port.serial_out = f815xxa_mem_serial_out; 1802 1803 return 0; 1804} 1805 1806static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1807{ 1808 u32 max_port, i; 1809 int config_base; 1810 1811 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1812 return -ENODEV; 1813 1814 switch (dev->device) { 1815 case 0x1204: /* 4 ports */ 1816 case 0x1208: /* 8 ports */ 1817 max_port = dev->device & 0xff; 1818 break; 1819 case 0x1212: /* 12 ports */ 1820 max_port = 12; 1821 break; 1822 default: 1823 return -EINVAL; 1824 } 1825 1826 /* Set to mmio decode */ 1827 pci_write_config_byte(dev, 0x209, 0x40); 1828 1829 for (i = 0; i < max_port; ++i) { 1830 /* UART0 configuration offset start from 0x2A0 */ 1831 config_base = 0x2A0 + 0x08 * i; 1832 1833 /* Select 128-byte FIFO and 8x FIFO threshold */ 1834 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1835 1836 /* Enable UART I/O port */ 1837 pci_write_config_byte(dev, config_base + 0, 0x01); 1838 } 1839 1840 return max_port; 1841} 1842 1843static int skip_tx_en_setup(struct serial_private *priv, 1844 const struct pciserial_board *board, 1845 struct uart_8250_port *port, int idx) 1846{ 1847 port->port.quirks |= UPQ_NO_TXEN_TEST; 1848 pci_dbg(priv->dev, 1849 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1850 priv->dev->vendor, priv->dev->device, 1851 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1852 1853 return pci_default_setup(priv, board, port, idx); 1854} 1855 1856static void kt_handle_break(struct uart_port *p) 1857{ 1858 struct uart_8250_port *up = up_to_u8250p(p); 1859 /* 1860 * On receipt of a BI, serial device in Intel ME (Intel 1861 * management engine) needs to have its fifos cleared for sane 1862 * SOL (Serial Over Lan) output. 1863 */ 1864 serial8250_clear_and_reinit_fifos(up); 1865} 1866 1867static u32 kt_serial_in(struct uart_port *p, unsigned int offset) 1868{ 1869 struct uart_8250_port *up = up_to_u8250p(p); 1870 u32 val; 1871 1872 /* 1873 * When the Intel ME (management engine) gets reset its serial 1874 * port registers could return 0 momentarily. Functions like 1875 * serial8250_console_write, read and save the IER, perform 1876 * some operation and then restore it. In order to avoid 1877 * setting IER register inadvertently to 0, if the value read 1878 * is 0, double check with ier value in uart_8250_port and use 1879 * that instead. up->ier should be the same value as what is 1880 * currently configured. 1881 */ 1882 val = inb(p->iobase + offset); 1883 if (offset == UART_IER) { 1884 if (val == 0) 1885 val = up->ier; 1886 } 1887 return val; 1888} 1889 1890static int kt_serial_setup(struct serial_private *priv, 1891 const struct pciserial_board *board, 1892 struct uart_8250_port *port, int idx) 1893{ 1894 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1895 return serial_8250_warn_need_ioport(priv->dev); 1896 1897 port->port.flags |= UPF_BUG_THRE; 1898 port->port.serial_in = kt_serial_in; 1899 port->port.handle_break = kt_handle_break; 1900 return skip_tx_en_setup(priv, board, port, idx); 1901} 1902 1903static int pci_eg20t_init(struct pci_dev *dev) 1904{ 1905#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1906 return -ENODEV; 1907#else 1908 return 0; 1909#endif 1910} 1911 1912static int 1913pci_wch_ch353_setup(struct serial_private *priv, 1914 const struct pciserial_board *board, 1915 struct uart_8250_port *port, int idx) 1916{ 1917 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1918 return serial_8250_warn_need_ioport(priv->dev); 1919 1920 port->port.flags |= UPF_FIXED_TYPE; 1921 port->port.type = PORT_16550A; 1922 return pci_default_setup(priv, board, port, idx); 1923} 1924 1925static int 1926pci_wch_ch355_setup(struct serial_private *priv, 1927 const struct pciserial_board *board, 1928 struct uart_8250_port *port, int idx) 1929{ 1930 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1931 return serial_8250_warn_need_ioport(priv->dev); 1932 1933 port->port.flags |= UPF_FIXED_TYPE; 1934 port->port.type = PORT_16550A; 1935 return pci_default_setup(priv, board, port, idx); 1936} 1937 1938static int 1939pci_wch_ch38x_setup(struct serial_private *priv, 1940 const struct pciserial_board *board, 1941 struct uart_8250_port *port, int idx) 1942{ 1943 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1944 return serial_8250_warn_need_ioport(priv->dev); 1945 1946 port->port.flags |= UPF_FIXED_TYPE; 1947 port->port.type = PORT_16850; 1948 return pci_default_setup(priv, board, port, idx); 1949} 1950 1951 1952#define CH384_XINT_ENABLE_REG 0xEB 1953#define CH384_XINT_ENABLE_BIT 0x02 1954 1955static int pci_wch_ch38x_init(struct pci_dev *dev) 1956{ 1957 int max_port; 1958 unsigned long iobase; 1959 1960 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1961 return serial_8250_warn_need_ioport(dev); 1962 1963 switch (dev->device) { 1964 case 0x3853: /* 8 ports */ 1965 max_port = 8; 1966 break; 1967 default: 1968 return -EINVAL; 1969 } 1970 1971 iobase = pci_resource_start(dev, 0); 1972 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1973 1974 return max_port; 1975} 1976 1977static void pci_wch_ch38x_exit(struct pci_dev *dev) 1978{ 1979 unsigned long iobase; 1980 1981 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) { 1982 serial_8250_warn_need_ioport(dev); 1983 return; 1984 } 1985 1986 iobase = pci_resource_start(dev, 0); 1987 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1988} 1989 1990 1991static int 1992pci_sunix_setup(struct serial_private *priv, 1993 const struct pciserial_board *board, 1994 struct uart_8250_port *port, int idx) 1995{ 1996 int bar; 1997 int offset; 1998 1999 port->port.flags |= UPF_FIXED_TYPE; 2000 port->port.type = PORT_SUNIX; 2001 2002 if (idx < 4) { 2003 bar = 0; 2004 offset = idx * board->uart_offset; 2005 } else { 2006 bar = 1; 2007 idx -= 4; 2008 idx = div_s64_rem(idx, 4, &offset); 2009 offset = idx * 64 + offset * board->uart_offset; 2010 } 2011 2012 return setup_port(priv, port, bar, offset, 0); 2013} 2014 2015#define MOXA_PUART_GPIO_EN 0x09 2016#define MOXA_PUART_GPIO_OUT 0x0A 2017 2018#define MOXA_GPIO_PIN2 BIT(2) 2019 2020#define MOXA_RS232 0x00 2021#define MOXA_RS422 0x01 2022#define MOXA_RS485_4W 0x0B 2023#define MOXA_RS485_2W 0x0F 2024#define MOXA_UIR_OFFSET 0x04 2025#define MOXA_EVEN_RS_MASK GENMASK(3, 0) 2026#define MOXA_ODD_RS_MASK GENMASK(7, 4) 2027 2028enum { 2029 MOXA_SUPP_RS232 = BIT(0), 2030 MOXA_SUPP_RS422 = BIT(1), 2031 MOXA_SUPP_RS485 = BIT(2), 2032}; 2033 2034static unsigned short moxa_get_nports(unsigned short device) 2035{ 2036 switch (device) { 2037 case PCI_DEVICE_ID_MOXA_CP116E_A_A: 2038 case PCI_DEVICE_ID_MOXA_CP116E_A_B: 2039 return 8; 2040 } 2041 2042 return FIELD_GET(0x00F0, device); 2043} 2044 2045static bool pci_moxa_is_mini_pcie(unsigned short device) 2046{ 2047 if (device == PCI_DEVICE_ID_MOXA_CP102N || 2048 device == PCI_DEVICE_ID_MOXA_CP104N || 2049 device == PCI_DEVICE_ID_MOXA_CP112N || 2050 device == PCI_DEVICE_ID_MOXA_CP114N || 2051 device == PCI_DEVICE_ID_MOXA_CP132N || 2052 device == PCI_DEVICE_ID_MOXA_CP134N) 2053 return true; 2054 2055 return false; 2056} 2057 2058static unsigned int pci_moxa_supported_rs(struct pci_dev *dev) 2059{ 2060 switch (dev->device & 0x0F00) { 2061 case 0x0000: 2062 case 0x0600: 2063 return MOXA_SUPP_RS232; 2064 case 0x0100: 2065 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2066 case 0x0300: 2067 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2068 } 2069 return 0; 2070} 2071 2072static int pci_moxa_set_interface(const struct pci_dev *dev, 2073 unsigned int port_idx, 2074 u8 mode) 2075{ 2076 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2077 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2; 2078 u8 val; 2079 2080 val = inb(UIR_addr); 2081 2082 if (port_idx % 2) { 2083 val &= ~MOXA_ODD_RS_MASK; 2084 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode); 2085 } else { 2086 val &= ~MOXA_EVEN_RS_MASK; 2087 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode); 2088 } 2089 outb(val, UIR_addr); 2090 2091 return 0; 2092} 2093 2094static int pci_moxa_init(struct pci_dev *dev) 2095{ 2096 unsigned short device = dev->device; 2097 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2098 unsigned int i, num_ports = moxa_get_nports(device); 2099 u8 val, init_mode = MOXA_RS232; 2100 2101 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2102 return serial_8250_warn_need_ioport(dev); 2103 2104 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) { 2105 init_mode = MOXA_RS422; 2106 } 2107 for (i = 0; i < num_ports; ++i) 2108 pci_moxa_set_interface(dev, i, init_mode); 2109 2110 /* 2111 * Enable hardware buffer to prevent break signal output when system boots up. 2112 * This hardware buffer is only supported on Mini PCIe series. 2113 */ 2114 if (pci_moxa_is_mini_pcie(device)) { 2115 /* Set GPIO direction */ 2116 val = inb(iobar_addr + MOXA_PUART_GPIO_EN); 2117 val |= MOXA_GPIO_PIN2; 2118 outb(val, iobar_addr + MOXA_PUART_GPIO_EN); 2119 /* Enable low GPIO */ 2120 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT); 2121 val &= ~MOXA_GPIO_PIN2; 2122 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT); 2123 } 2124 2125 return num_ports; 2126} 2127 2128static int 2129pci_moxa_setup(struct serial_private *priv, 2130 const struct pciserial_board *board, 2131 struct uart_8250_port *port, int idx) 2132{ 2133 unsigned int bar = FL_GET_BASE(board->flags); 2134 int offset; 2135 2136 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2137 return serial_8250_warn_need_ioport(priv->dev); 2138 2139 if (board->num_ports == 4 && idx == 3) 2140 offset = 7 * board->uart_offset; 2141 else 2142 offset = idx * board->uart_offset; 2143 2144 return setup_port(priv, port, bar, offset, 0); 2145} 2146 2147/* 2148 * Master list of serial port init/setup/exit quirks. 2149 * This does not describe the general nature of the port. 2150 * (ie, baud base, number and location of ports, etc) 2151 * 2152 * This list is ordered alphabetically by vendor then device. 2153 * Specific entries must come before more generic entries. 2154 */ 2155static struct pci_serial_quirk pci_serial_quirks[] = { 2156 /* 2157 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2158 */ 2159 { 2160 .vendor = PCI_VENDOR_ID_AMCC, 2161 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2162 .subvendor = PCI_ANY_ID, 2163 .subdevice = PCI_ANY_ID, 2164 .setup = addidata_apci7800_setup, 2165 }, 2166 /* 2167 * AFAVLAB cards - these may be called via parport_serial 2168 * It is not clear whether this applies to all products. 2169 */ 2170 { 2171 .vendor = PCI_VENDOR_ID_AFAVLAB, 2172 .device = PCI_ANY_ID, 2173 .subvendor = PCI_ANY_ID, 2174 .subdevice = PCI_ANY_ID, 2175 .setup = afavlab_setup, 2176 }, 2177 /* 2178 * HP Diva 2179 */ 2180 { 2181 .vendor = PCI_VENDOR_ID_HP, 2182 .device = PCI_DEVICE_ID_HP_DIVA, 2183 .subvendor = PCI_ANY_ID, 2184 .subdevice = PCI_ANY_ID, 2185 .init = pci_hp_diva_init, 2186 .setup = pci_hp_diva_setup, 2187 }, 2188 /* 2189 * HPE PCI serial device 2190 */ 2191 { 2192 .vendor = PCI_VENDOR_ID_HP_3PAR, 2193 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2194 .subvendor = PCI_ANY_ID, 2195 .subdevice = PCI_ANY_ID, 2196 .setup = pci_hp_diva_setup, 2197 }, 2198 /* 2199 * Intel 2200 */ 2201 { 2202 .vendor = PCI_VENDOR_ID_INTEL, 2203 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2204 .subvendor = 0xe4bf, 2205 .subdevice = PCI_ANY_ID, 2206 .init = pci_inteli960ni_init, 2207 .setup = pci_default_setup, 2208 }, 2209 { 2210 .vendor = PCI_VENDOR_ID_INTEL, 2211 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2212 .subvendor = PCI_ANY_ID, 2213 .subdevice = PCI_ANY_ID, 2214 .setup = skip_tx_en_setup, 2215 }, 2216 { 2217 .vendor = PCI_VENDOR_ID_INTEL, 2218 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2219 .subvendor = PCI_ANY_ID, 2220 .subdevice = PCI_ANY_ID, 2221 .setup = skip_tx_en_setup, 2222 }, 2223 { 2224 .vendor = PCI_VENDOR_ID_INTEL, 2225 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2226 .subvendor = PCI_ANY_ID, 2227 .subdevice = PCI_ANY_ID, 2228 .setup = skip_tx_en_setup, 2229 }, 2230 { 2231 .vendor = PCI_VENDOR_ID_INTEL, 2232 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2233 .subvendor = PCI_ANY_ID, 2234 .subdevice = PCI_ANY_ID, 2235 .setup = ce4100_serial_setup, 2236 }, 2237 { 2238 .vendor = PCI_VENDOR_ID_INTEL, 2239 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2240 .subvendor = PCI_ANY_ID, 2241 .subdevice = PCI_ANY_ID, 2242 .setup = kt_serial_setup, 2243 }, 2244 /* 2245 * ITE 2246 */ 2247 { 2248 .vendor = PCI_VENDOR_ID_ITE, 2249 .device = PCI_DEVICE_ID_ITE_8872, 2250 .subvendor = PCI_ANY_ID, 2251 .subdevice = PCI_ANY_ID, 2252 .init = pci_ite887x_init, 2253 .setup = pci_default_setup, 2254 .exit = pci_ite887x_exit, 2255 }, 2256 /* 2257 * National Instruments 2258 */ 2259 { 2260 .vendor = PCI_VENDOR_ID_NI, 2261 .device = PCI_DEVICE_ID_NI_PCI23216, 2262 .subvendor = PCI_ANY_ID, 2263 .subdevice = PCI_ANY_ID, 2264 .init = pci_ni8420_init, 2265 .setup = pci_default_setup, 2266 .exit = pci_ni8420_exit, 2267 }, 2268 { 2269 .vendor = PCI_VENDOR_ID_NI, 2270 .device = PCI_DEVICE_ID_NI_PCI2328, 2271 .subvendor = PCI_ANY_ID, 2272 .subdevice = PCI_ANY_ID, 2273 .init = pci_ni8420_init, 2274 .setup = pci_default_setup, 2275 .exit = pci_ni8420_exit, 2276 }, 2277 { 2278 .vendor = PCI_VENDOR_ID_NI, 2279 .device = PCI_DEVICE_ID_NI_PCI2324, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .init = pci_ni8420_init, 2283 .setup = pci_default_setup, 2284 .exit = pci_ni8420_exit, 2285 }, 2286 { 2287 .vendor = PCI_VENDOR_ID_NI, 2288 .device = PCI_DEVICE_ID_NI_PCI2322, 2289 .subvendor = PCI_ANY_ID, 2290 .subdevice = PCI_ANY_ID, 2291 .init = pci_ni8420_init, 2292 .setup = pci_default_setup, 2293 .exit = pci_ni8420_exit, 2294 }, 2295 { 2296 .vendor = PCI_VENDOR_ID_NI, 2297 .device = PCI_DEVICE_ID_NI_PCI2324I, 2298 .subvendor = PCI_ANY_ID, 2299 .subdevice = PCI_ANY_ID, 2300 .init = pci_ni8420_init, 2301 .setup = pci_default_setup, 2302 .exit = pci_ni8420_exit, 2303 }, 2304 { 2305 .vendor = PCI_VENDOR_ID_NI, 2306 .device = PCI_DEVICE_ID_NI_PCI2322I, 2307 .subvendor = PCI_ANY_ID, 2308 .subdevice = PCI_ANY_ID, 2309 .init = pci_ni8420_init, 2310 .setup = pci_default_setup, 2311 .exit = pci_ni8420_exit, 2312 }, 2313 { 2314 .vendor = PCI_VENDOR_ID_NI, 2315 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2316 .subvendor = PCI_ANY_ID, 2317 .subdevice = PCI_ANY_ID, 2318 .init = pci_ni8420_init, 2319 .setup = pci_default_setup, 2320 .exit = pci_ni8420_exit, 2321 }, 2322 { 2323 .vendor = PCI_VENDOR_ID_NI, 2324 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2325 .subvendor = PCI_ANY_ID, 2326 .subdevice = PCI_ANY_ID, 2327 .init = pci_ni8420_init, 2328 .setup = pci_default_setup, 2329 .exit = pci_ni8420_exit, 2330 }, 2331 { 2332 .vendor = PCI_VENDOR_ID_NI, 2333 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2334 .subvendor = PCI_ANY_ID, 2335 .subdevice = PCI_ANY_ID, 2336 .init = pci_ni8420_init, 2337 .setup = pci_default_setup, 2338 .exit = pci_ni8420_exit, 2339 }, 2340 { 2341 .vendor = PCI_VENDOR_ID_NI, 2342 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2343 .subvendor = PCI_ANY_ID, 2344 .subdevice = PCI_ANY_ID, 2345 .init = pci_ni8420_init, 2346 .setup = pci_default_setup, 2347 .exit = pci_ni8420_exit, 2348 }, 2349 { 2350 .vendor = PCI_VENDOR_ID_NI, 2351 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2352 .subvendor = PCI_ANY_ID, 2353 .subdevice = PCI_ANY_ID, 2354 .init = pci_ni8420_init, 2355 .setup = pci_default_setup, 2356 .exit = pci_ni8420_exit, 2357 }, 2358 { 2359 .vendor = PCI_VENDOR_ID_NI, 2360 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2361 .subvendor = PCI_ANY_ID, 2362 .subdevice = PCI_ANY_ID, 2363 .init = pci_ni8420_init, 2364 .setup = pci_default_setup, 2365 .exit = pci_ni8420_exit, 2366 }, 2367 { 2368 .vendor = PCI_VENDOR_ID_NI, 2369 .device = PCI_ANY_ID, 2370 .subvendor = PCI_ANY_ID, 2371 .subdevice = PCI_ANY_ID, 2372 .init = pci_ni8430_init, 2373 .setup = pci_ni8430_setup, 2374 .exit = pci_ni8430_exit, 2375 }, 2376 /* Quatech */ 2377 { 2378 .vendor = PCI_VENDOR_ID_QUATECH, 2379 .device = PCI_ANY_ID, 2380 .subvendor = PCI_ANY_ID, 2381 .subdevice = PCI_ANY_ID, 2382 .init = pci_quatech_init, 2383 .setup = pci_quatech_setup, 2384 }, 2385 /* 2386 * Panacom 2387 */ 2388 { 2389 .vendor = PCI_VENDOR_ID_PANACOM, 2390 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2391 .subvendor = PCI_ANY_ID, 2392 .subdevice = PCI_ANY_ID, 2393 .init = pci_plx9050_init, 2394 .setup = pci_default_setup, 2395 .exit = pci_plx9050_exit, 2396 }, 2397 { 2398 .vendor = PCI_VENDOR_ID_PANACOM, 2399 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2400 .subvendor = PCI_ANY_ID, 2401 .subdevice = PCI_ANY_ID, 2402 .init = pci_plx9050_init, 2403 .setup = pci_default_setup, 2404 .exit = pci_plx9050_exit, 2405 }, 2406 /* 2407 * PLX 2408 */ 2409 { 2410 .vendor = PCI_VENDOR_ID_PLX, 2411 .device = PCI_DEVICE_ID_PLX_9050, 2412 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2413 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2414 .init = pci_plx9050_init, 2415 .setup = pci_default_setup, 2416 .exit = pci_plx9050_exit, 2417 }, 2418 { 2419 .vendor = PCI_VENDOR_ID_PLX, 2420 .device = PCI_DEVICE_ID_PLX_9050, 2421 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2422 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2423 .init = pci_plx9050_init, 2424 .setup = pci_default_setup, 2425 .exit = pci_plx9050_exit, 2426 }, 2427 { 2428 .vendor = PCI_VENDOR_ID_PLX, 2429 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2430 .subvendor = PCI_VENDOR_ID_PLX, 2431 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2432 .init = pci_plx9050_init, 2433 .setup = pci_default_setup, 2434 .exit = pci_plx9050_exit, 2435 }, 2436 /* 2437 * SBS Technologies, Inc., PMC-OCTALPRO 232 2438 */ 2439 { 2440 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2441 .device = PCI_DEVICE_ID_OCTPRO, 2442 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2443 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2444 .init = sbs_init, 2445 .setup = sbs_setup, 2446 .exit = sbs_exit, 2447 }, 2448 /* 2449 * SBS Technologies, Inc., PMC-OCTALPRO 422 2450 */ 2451 { 2452 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2453 .device = PCI_DEVICE_ID_OCTPRO, 2454 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2455 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2456 .init = sbs_init, 2457 .setup = sbs_setup, 2458 .exit = sbs_exit, 2459 }, 2460 /* 2461 * SBS Technologies, Inc., P-Octal 232 2462 */ 2463 { 2464 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2465 .device = PCI_DEVICE_ID_OCTPRO, 2466 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2467 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2468 .init = sbs_init, 2469 .setup = sbs_setup, 2470 .exit = sbs_exit, 2471 }, 2472 /* 2473 * SBS Technologies, Inc., P-Octal 422 2474 */ 2475 { 2476 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2477 .device = PCI_DEVICE_ID_OCTPRO, 2478 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2479 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2480 .init = sbs_init, 2481 .setup = sbs_setup, 2482 .exit = sbs_exit, 2483 }, 2484 /* 2485 * SIIG cards - these may be called via parport_serial 2486 */ 2487 { 2488 .vendor = PCI_VENDOR_ID_SIIG, 2489 .device = PCI_ANY_ID, 2490 .subvendor = PCI_ANY_ID, 2491 .subdevice = PCI_ANY_ID, 2492 .init = pci_siig_init, 2493 .setup = pci_siig_setup, 2494 }, 2495 /* 2496 * Titan cards 2497 */ 2498 { 2499 .vendor = PCI_VENDOR_ID_TITAN, 2500 .device = PCI_DEVICE_ID_TITAN_400L, 2501 .subvendor = PCI_ANY_ID, 2502 .subdevice = PCI_ANY_ID, 2503 .setup = titan_400l_800l_setup, 2504 }, 2505 { 2506 .vendor = PCI_VENDOR_ID_TITAN, 2507 .device = PCI_DEVICE_ID_TITAN_800L, 2508 .subvendor = PCI_ANY_ID, 2509 .subdevice = PCI_ANY_ID, 2510 .setup = titan_400l_800l_setup, 2511 }, 2512 /* 2513 * Timedia cards 2514 */ 2515 { 2516 .vendor = PCI_VENDOR_ID_TIMEDIA, 2517 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2518 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2519 .subdevice = PCI_ANY_ID, 2520 .probe = pci_timedia_probe, 2521 .init = pci_timedia_init, 2522 .setup = pci_timedia_setup, 2523 }, 2524 { 2525 .vendor = PCI_VENDOR_ID_TIMEDIA, 2526 .device = PCI_ANY_ID, 2527 .subvendor = PCI_ANY_ID, 2528 .subdevice = PCI_ANY_ID, 2529 .setup = pci_timedia_setup, 2530 }, 2531 /* 2532 * Sunix PCI serial boards 2533 */ 2534 { 2535 .vendor = PCI_VENDOR_ID_SUNIX, 2536 .device = PCI_DEVICE_ID_SUNIX_1999, 2537 .subvendor = PCI_VENDOR_ID_SUNIX, 2538 .subdevice = PCI_ANY_ID, 2539 .setup = pci_sunix_setup, 2540 }, 2541 /* 2542 * Xircom cards 2543 */ 2544 { 2545 .vendor = PCI_VENDOR_ID_XIRCOM, 2546 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2547 .subvendor = PCI_ANY_ID, 2548 .subdevice = PCI_ANY_ID, 2549 .init = pci_xircom_init, 2550 .setup = pci_default_setup, 2551 }, 2552 /* 2553 * Netmos cards - these may be called via parport_serial 2554 */ 2555 { 2556 .vendor = PCI_VENDOR_ID_NETMOS, 2557 .device = PCI_ANY_ID, 2558 .subvendor = PCI_ANY_ID, 2559 .subdevice = PCI_ANY_ID, 2560 .init = pci_netmos_init, 2561 .setup = pci_netmos_9900_setup, 2562 }, 2563 { 2564 .vendor = PCIE_VENDOR_ID_ASIX, 2565 .device = PCI_ANY_ID, 2566 .subvendor = PCI_ANY_ID, 2567 .subdevice = PCI_ANY_ID, 2568 .init = pci_netmos_init, 2569 .setup = pci_netmos_9900_setup, 2570 }, 2571 /* 2572 * EndRun Technologies 2573 */ 2574 { 2575 .vendor = PCI_VENDOR_ID_ENDRUN, 2576 .device = PCI_ANY_ID, 2577 .subvendor = PCI_ANY_ID, 2578 .subdevice = PCI_ANY_ID, 2579 .init = pci_oxsemi_tornado_init, 2580 .setup = pci_default_setup, 2581 }, 2582 /* 2583 * For Oxford Semiconductor Tornado based devices 2584 */ 2585 { 2586 .vendor = PCI_VENDOR_ID_OXSEMI, 2587 .device = PCI_ANY_ID, 2588 .subvendor = PCI_ANY_ID, 2589 .subdevice = PCI_ANY_ID, 2590 .init = pci_oxsemi_tornado_init, 2591 .setup = pci_oxsemi_tornado_setup, 2592 }, 2593 { 2594 .vendor = PCI_VENDOR_ID_MAINPINE, 2595 .device = PCI_ANY_ID, 2596 .subvendor = PCI_ANY_ID, 2597 .subdevice = PCI_ANY_ID, 2598 .init = pci_oxsemi_tornado_init, 2599 .setup = pci_oxsemi_tornado_setup, 2600 }, 2601 { 2602 .vendor = PCI_VENDOR_ID_DIGI, 2603 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2604 .subvendor = PCI_SUBVENDOR_ID_IBM, 2605 .subdevice = PCI_ANY_ID, 2606 .init = pci_oxsemi_tornado_init, 2607 .setup = pci_oxsemi_tornado_setup, 2608 }, 2609 /* 2610 * Brainboxes devices - all Oxsemi based 2611 */ 2612 { 2613 .vendor = PCI_VENDOR_ID_INTASHIELD, 2614 .device = 0x4027, 2615 .subvendor = PCI_ANY_ID, 2616 .subdevice = PCI_ANY_ID, 2617 .init = pci_oxsemi_tornado_init, 2618 .setup = pci_oxsemi_tornado_setup, 2619 }, 2620 { 2621 .vendor = PCI_VENDOR_ID_INTASHIELD, 2622 .device = 0x4028, 2623 .subvendor = PCI_ANY_ID, 2624 .subdevice = PCI_ANY_ID, 2625 .init = pci_oxsemi_tornado_init, 2626 .setup = pci_oxsemi_tornado_setup, 2627 }, 2628 { 2629 .vendor = PCI_VENDOR_ID_INTASHIELD, 2630 .device = 0x4029, 2631 .subvendor = PCI_ANY_ID, 2632 .subdevice = PCI_ANY_ID, 2633 .init = pci_oxsemi_tornado_init, 2634 .setup = pci_oxsemi_tornado_setup, 2635 }, 2636 { 2637 .vendor = PCI_VENDOR_ID_INTASHIELD, 2638 .device = 0x4019, 2639 .subvendor = PCI_ANY_ID, 2640 .subdevice = PCI_ANY_ID, 2641 .init = pci_oxsemi_tornado_init, 2642 .setup = pci_oxsemi_tornado_setup, 2643 }, 2644 { 2645 .vendor = PCI_VENDOR_ID_INTASHIELD, 2646 .device = 0x4016, 2647 .subvendor = PCI_ANY_ID, 2648 .subdevice = PCI_ANY_ID, 2649 .init = pci_oxsemi_tornado_init, 2650 .setup = pci_oxsemi_tornado_setup, 2651 }, 2652 { 2653 .vendor = PCI_VENDOR_ID_INTASHIELD, 2654 .device = 0x4015, 2655 .subvendor = PCI_ANY_ID, 2656 .subdevice = PCI_ANY_ID, 2657 .init = pci_oxsemi_tornado_init, 2658 .setup = pci_oxsemi_tornado_setup, 2659 }, 2660 { 2661 .vendor = PCI_VENDOR_ID_INTASHIELD, 2662 .device = 0x400A, 2663 .subvendor = PCI_ANY_ID, 2664 .subdevice = PCI_ANY_ID, 2665 .init = pci_oxsemi_tornado_init, 2666 .setup = pci_oxsemi_tornado_setup, 2667 }, 2668 { 2669 .vendor = PCI_VENDOR_ID_INTASHIELD, 2670 .device = 0x400E, 2671 .subvendor = PCI_ANY_ID, 2672 .subdevice = PCI_ANY_ID, 2673 .init = pci_oxsemi_tornado_init, 2674 .setup = pci_oxsemi_tornado_setup, 2675 }, 2676 { 2677 .vendor = PCI_VENDOR_ID_INTASHIELD, 2678 .device = 0x400C, 2679 .subvendor = PCI_ANY_ID, 2680 .subdevice = PCI_ANY_ID, 2681 .init = pci_oxsemi_tornado_init, 2682 .setup = pci_oxsemi_tornado_setup, 2683 }, 2684 { 2685 .vendor = PCI_VENDOR_ID_INTASHIELD, 2686 .device = 0x400B, 2687 .subvendor = PCI_ANY_ID, 2688 .subdevice = PCI_ANY_ID, 2689 .init = pci_oxsemi_tornado_init, 2690 .setup = pci_oxsemi_tornado_setup, 2691 }, 2692 { 2693 .vendor = PCI_VENDOR_ID_INTASHIELD, 2694 .device = 0x400F, 2695 .subvendor = PCI_ANY_ID, 2696 .subdevice = PCI_ANY_ID, 2697 .init = pci_oxsemi_tornado_init, 2698 .setup = pci_oxsemi_tornado_setup, 2699 }, 2700 { 2701 .vendor = PCI_VENDOR_ID_INTASHIELD, 2702 .device = 0x4010, 2703 .subvendor = PCI_ANY_ID, 2704 .subdevice = PCI_ANY_ID, 2705 .init = pci_oxsemi_tornado_init, 2706 .setup = pci_oxsemi_tornado_setup, 2707 }, 2708 { 2709 .vendor = PCI_VENDOR_ID_INTASHIELD, 2710 .device = 0x4011, 2711 .subvendor = PCI_ANY_ID, 2712 .subdevice = PCI_ANY_ID, 2713 .init = pci_oxsemi_tornado_init, 2714 .setup = pci_oxsemi_tornado_setup, 2715 }, 2716 { 2717 .vendor = PCI_VENDOR_ID_INTASHIELD, 2718 .device = 0x401D, 2719 .subvendor = PCI_ANY_ID, 2720 .subdevice = PCI_ANY_ID, 2721 .init = pci_oxsemi_tornado_init, 2722 .setup = pci_oxsemi_tornado_setup, 2723 }, 2724 { 2725 .vendor = PCI_VENDOR_ID_INTASHIELD, 2726 .device = 0x401E, 2727 .subvendor = PCI_ANY_ID, 2728 .subdevice = PCI_ANY_ID, 2729 .init = pci_oxsemi_tornado_init, 2730 .setup = pci_oxsemi_tornado_setup, 2731 }, 2732 { 2733 .vendor = PCI_VENDOR_ID_INTASHIELD, 2734 .device = 0x4013, 2735 .subvendor = PCI_ANY_ID, 2736 .subdevice = PCI_ANY_ID, 2737 .init = pci_oxsemi_tornado_init, 2738 .setup = pci_oxsemi_tornado_setup, 2739 }, 2740 { 2741 .vendor = PCI_VENDOR_ID_INTASHIELD, 2742 .device = 0x4017, 2743 .subvendor = PCI_ANY_ID, 2744 .subdevice = PCI_ANY_ID, 2745 .init = pci_oxsemi_tornado_init, 2746 .setup = pci_oxsemi_tornado_setup, 2747 }, 2748 { 2749 .vendor = PCI_VENDOR_ID_INTASHIELD, 2750 .device = 0x4018, 2751 .subvendor = PCI_ANY_ID, 2752 .subdevice = PCI_ANY_ID, 2753 .init = pci_oxsemi_tornado_init, 2754 .setup = pci_oxsemi_tornado_setup, 2755 }, 2756 { 2757 .vendor = PCI_VENDOR_ID_INTASHIELD, 2758 .device = 0x4026, 2759 .subvendor = PCI_ANY_ID, 2760 .subdevice = PCI_ANY_ID, 2761 .init = pci_oxsemi_tornado_init, 2762 .setup = pci_oxsemi_tornado_setup, 2763 }, 2764 { 2765 .vendor = PCI_VENDOR_ID_INTASHIELD, 2766 .device = 0x4021, 2767 .subvendor = PCI_ANY_ID, 2768 .subdevice = PCI_ANY_ID, 2769 .init = pci_oxsemi_tornado_init, 2770 .setup = pci_oxsemi_tornado_setup, 2771 }, 2772 { 2773 .vendor = PCI_VENDOR_ID_INTEL, 2774 .device = 0x8811, 2775 .subvendor = PCI_ANY_ID, 2776 .subdevice = PCI_ANY_ID, 2777 .init = pci_eg20t_init, 2778 .setup = pci_default_setup, 2779 }, 2780 { 2781 .vendor = PCI_VENDOR_ID_INTEL, 2782 .device = 0x8812, 2783 .subvendor = PCI_ANY_ID, 2784 .subdevice = PCI_ANY_ID, 2785 .init = pci_eg20t_init, 2786 .setup = pci_default_setup, 2787 }, 2788 { 2789 .vendor = PCI_VENDOR_ID_INTEL, 2790 .device = 0x8813, 2791 .subvendor = PCI_ANY_ID, 2792 .subdevice = PCI_ANY_ID, 2793 .init = pci_eg20t_init, 2794 .setup = pci_default_setup, 2795 }, 2796 { 2797 .vendor = PCI_VENDOR_ID_INTEL, 2798 .device = 0x8814, 2799 .subvendor = PCI_ANY_ID, 2800 .subdevice = PCI_ANY_ID, 2801 .init = pci_eg20t_init, 2802 .setup = pci_default_setup, 2803 }, 2804 { 2805 .vendor = 0x10DB, 2806 .device = 0x8027, 2807 .subvendor = PCI_ANY_ID, 2808 .subdevice = PCI_ANY_ID, 2809 .init = pci_eg20t_init, 2810 .setup = pci_default_setup, 2811 }, 2812 { 2813 .vendor = 0x10DB, 2814 .device = 0x8028, 2815 .subvendor = PCI_ANY_ID, 2816 .subdevice = PCI_ANY_ID, 2817 .init = pci_eg20t_init, 2818 .setup = pci_default_setup, 2819 }, 2820 { 2821 .vendor = 0x10DB, 2822 .device = 0x8029, 2823 .subvendor = PCI_ANY_ID, 2824 .subdevice = PCI_ANY_ID, 2825 .init = pci_eg20t_init, 2826 .setup = pci_default_setup, 2827 }, 2828 { 2829 .vendor = 0x10DB, 2830 .device = 0x800C, 2831 .subvendor = PCI_ANY_ID, 2832 .subdevice = PCI_ANY_ID, 2833 .init = pci_eg20t_init, 2834 .setup = pci_default_setup, 2835 }, 2836 { 2837 .vendor = 0x10DB, 2838 .device = 0x800D, 2839 .subvendor = PCI_ANY_ID, 2840 .subdevice = PCI_ANY_ID, 2841 .init = pci_eg20t_init, 2842 .setup = pci_default_setup, 2843 }, 2844 /* 2845 * Cronyx Omega PCI (PLX-chip based) 2846 */ 2847 { 2848 .vendor = PCI_VENDOR_ID_PLX, 2849 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2850 .subvendor = PCI_ANY_ID, 2851 .subdevice = PCI_ANY_ID, 2852 .setup = pci_omegapci_setup, 2853 }, 2854 /* WCH CH353 1S1P card (16550 clone) */ 2855 { 2856 .vendor = PCI_VENDOR_ID_WCHCN, 2857 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P, 2858 .subvendor = PCI_ANY_ID, 2859 .subdevice = PCI_ANY_ID, 2860 .setup = pci_wch_ch353_setup, 2861 }, 2862 /* WCH CH353 2S1P card (16550 clone) */ 2863 { 2864 .vendor = PCI_VENDOR_ID_WCHCN, 2865 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P, 2866 .subvendor = PCI_ANY_ID, 2867 .subdevice = PCI_ANY_ID, 2868 .setup = pci_wch_ch353_setup, 2869 }, 2870 /* WCH CH353 4S card (16550 clone) */ 2871 { 2872 .vendor = PCI_VENDOR_ID_WCHCN, 2873 .device = PCI_DEVICE_ID_WCHCN_CH353_4S, 2874 .subvendor = PCI_ANY_ID, 2875 .subdevice = PCI_ANY_ID, 2876 .setup = pci_wch_ch353_setup, 2877 }, 2878 /* WCH CH353 2S1PF card (16550 clone) */ 2879 { 2880 .vendor = PCI_VENDOR_ID_WCHCN, 2881 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF, 2882 .subvendor = PCI_ANY_ID, 2883 .subdevice = PCI_ANY_ID, 2884 .setup = pci_wch_ch353_setup, 2885 }, 2886 /* WCH CH352 2S card (16550 clone) */ 2887 { 2888 .vendor = PCI_VENDOR_ID_WCHCN, 2889 .device = PCI_DEVICE_ID_WCHCN_CH352_2S, 2890 .subvendor = PCI_ANY_ID, 2891 .subdevice = PCI_ANY_ID, 2892 .setup = pci_wch_ch353_setup, 2893 }, 2894 /* WCH CH355 4S card (16550 clone) */ 2895 { 2896 .vendor = PCI_VENDOR_ID_WCHCN, 2897 .device = PCI_DEVICE_ID_WCHCN_CH355_4S, 2898 .subvendor = PCI_ANY_ID, 2899 .subdevice = PCI_ANY_ID, 2900 .setup = pci_wch_ch355_setup, 2901 }, 2902 /* WCH CH382 2S card (16850 clone) */ 2903 { 2904 .vendor = PCI_VENDOR_ID_WCHIC, 2905 .device = PCI_DEVICE_ID_WCHIC_CH382_2S, 2906 .subvendor = PCI_ANY_ID, 2907 .subdevice = PCI_ANY_ID, 2908 .setup = pci_wch_ch38x_setup, 2909 }, 2910 /* WCH CH382 2S1P card (16850 clone) */ 2911 { 2912 .vendor = PCI_VENDOR_ID_WCHIC, 2913 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P, 2914 .subvendor = PCI_ANY_ID, 2915 .subdevice = PCI_ANY_ID, 2916 .setup = pci_wch_ch38x_setup, 2917 }, 2918 /* WCH CH384 4S card (16850 clone) */ 2919 { 2920 .vendor = PCI_VENDOR_ID_WCHIC, 2921 .device = PCI_DEVICE_ID_WCHIC_CH384_4S, 2922 .subvendor = PCI_ANY_ID, 2923 .subdevice = PCI_ANY_ID, 2924 .setup = pci_wch_ch38x_setup, 2925 }, 2926 /* WCH CH384 8S card (16850 clone) */ 2927 { 2928 .vendor = PCI_VENDOR_ID_WCHIC, 2929 .device = PCI_DEVICE_ID_WCHIC_CH384_8S, 2930 .subvendor = PCI_ANY_ID, 2931 .subdevice = PCI_ANY_ID, 2932 .init = pci_wch_ch38x_init, 2933 .exit = pci_wch_ch38x_exit, 2934 .setup = pci_wch_ch38x_setup, 2935 }, 2936 /* 2937 * Broadcom TruManage (NetXtreme) 2938 */ 2939 { 2940 .vendor = PCI_VENDOR_ID_BROADCOM, 2941 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2942 .subvendor = PCI_ANY_ID, 2943 .subdevice = PCI_ANY_ID, 2944 .setup = pci_brcm_trumanage_setup, 2945 }, 2946 { 2947 .vendor = 0x1c29, 2948 .device = 0x1104, 2949 .subvendor = PCI_ANY_ID, 2950 .subdevice = PCI_ANY_ID, 2951 .setup = pci_fintek_setup, 2952 .init = pci_fintek_init, 2953 }, 2954 { 2955 .vendor = 0x1c29, 2956 .device = 0x1108, 2957 .subvendor = PCI_ANY_ID, 2958 .subdevice = PCI_ANY_ID, 2959 .setup = pci_fintek_setup, 2960 .init = pci_fintek_init, 2961 }, 2962 { 2963 .vendor = 0x1c29, 2964 .device = 0x1112, 2965 .subvendor = PCI_ANY_ID, 2966 .subdevice = PCI_ANY_ID, 2967 .setup = pci_fintek_setup, 2968 .init = pci_fintek_init, 2969 }, 2970 /* 2971 * MOXA 2972 */ 2973 { 2974 .vendor = PCI_VENDOR_ID_MOXA, 2975 .device = PCI_ANY_ID, 2976 .subvendor = PCI_ANY_ID, 2977 .subdevice = PCI_ANY_ID, 2978 .init = pci_moxa_init, 2979 .setup = pci_moxa_setup, 2980 }, 2981 { 2982 .vendor = 0x1c29, 2983 .device = 0x1204, 2984 .subvendor = PCI_ANY_ID, 2985 .subdevice = PCI_ANY_ID, 2986 .setup = pci_fintek_f815xxa_setup, 2987 .init = pci_fintek_f815xxa_init, 2988 }, 2989 { 2990 .vendor = 0x1c29, 2991 .device = 0x1208, 2992 .subvendor = PCI_ANY_ID, 2993 .subdevice = PCI_ANY_ID, 2994 .setup = pci_fintek_f815xxa_setup, 2995 .init = pci_fintek_f815xxa_init, 2996 }, 2997 { 2998 .vendor = 0x1c29, 2999 .device = 0x1212, 3000 .subvendor = PCI_ANY_ID, 3001 .subdevice = PCI_ANY_ID, 3002 .setup = pci_fintek_f815xxa_setup, 3003 .init = pci_fintek_f815xxa_init, 3004 }, 3005 3006 /* 3007 * Default "match everything" terminator entry 3008 */ 3009 { 3010 .vendor = PCI_ANY_ID, 3011 .device = PCI_ANY_ID, 3012 .subvendor = PCI_ANY_ID, 3013 .subdevice = PCI_ANY_ID, 3014 .setup = pci_default_setup, 3015 } 3016}; 3017 3018static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 3019{ 3020 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 3021} 3022 3023static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 3024{ 3025 struct pci_serial_quirk *quirk; 3026 3027 for (quirk = pci_serial_quirks; ; quirk++) 3028 if (quirk_id_matches(quirk->vendor, dev->vendor) && 3029 quirk_id_matches(quirk->device, dev->device) && 3030 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 3031 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 3032 break; 3033 return quirk; 3034} 3035 3036/* 3037 * This is the configuration table for all of the PCI serial boards 3038 * which we support. It is directly indexed by the pci_board_num_t enum 3039 * value, which is encoded in the pci_device_id PCI probe table's 3040 * driver_data member. 3041 * 3042 * The makeup of these names are: 3043 * pbn_bn{_bt}_n_baud{_offsetinhex} 3044 * 3045 * bn = PCI BAR number 3046 * bt = Index using PCI BARs 3047 * n = number of serial ports 3048 * baud = baud rate 3049 * offsetinhex = offset for each sequential port (in hex) 3050 * 3051 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 3052 * 3053 * Please note: in theory if n = 1, _bt infix should make no difference. 3054 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 3055 */ 3056enum pci_board_num_t { 3057 pbn_default = 0, 3058 3059 pbn_b0_1_115200, 3060 pbn_b0_2_115200, 3061 pbn_b0_4_115200, 3062 pbn_b0_5_115200, 3063 pbn_b0_8_115200, 3064 3065 pbn_b0_1_921600, 3066 pbn_b0_2_921600, 3067 pbn_b0_4_921600, 3068 3069 pbn_b0_2_1130000, 3070 3071 pbn_b0_4_1152000, 3072 3073 pbn_b0_4_1250000, 3074 3075 pbn_b0_2_1843200, 3076 pbn_b0_4_1843200, 3077 3078 pbn_b0_1_15625000, 3079 3080 pbn_b0_bt_1_115200, 3081 pbn_b0_bt_2_115200, 3082 pbn_b0_bt_4_115200, 3083 pbn_b0_bt_8_115200, 3084 3085 pbn_b0_bt_1_460800, 3086 pbn_b0_bt_2_460800, 3087 pbn_b0_bt_4_460800, 3088 3089 pbn_b0_bt_1_921600, 3090 pbn_b0_bt_2_921600, 3091 pbn_b0_bt_4_921600, 3092 pbn_b0_bt_8_921600, 3093 3094 pbn_b1_1_115200, 3095 pbn_b1_2_115200, 3096 pbn_b1_4_115200, 3097 pbn_b1_8_115200, 3098 pbn_b1_16_115200, 3099 3100 pbn_b1_1_921600, 3101 pbn_b1_2_921600, 3102 pbn_b1_4_921600, 3103 pbn_b1_8_921600, 3104 3105 pbn_b1_2_1250000, 3106 3107 pbn_b1_bt_1_115200, 3108 pbn_b1_bt_2_115200, 3109 pbn_b1_bt_4_115200, 3110 3111 pbn_b1_bt_2_921600, 3112 3113 pbn_b1_1_1382400, 3114 pbn_b1_2_1382400, 3115 pbn_b1_4_1382400, 3116 pbn_b1_8_1382400, 3117 3118 pbn_b2_1_115200, 3119 pbn_b2_2_115200, 3120 pbn_b2_4_115200, 3121 pbn_b2_8_115200, 3122 3123 pbn_b2_1_460800, 3124 pbn_b2_4_460800, 3125 pbn_b2_8_460800, 3126 pbn_b2_16_460800, 3127 3128 pbn_b2_1_921600, 3129 pbn_b2_4_921600, 3130 pbn_b2_8_921600, 3131 3132 pbn_b2_8_1152000, 3133 3134 pbn_b2_bt_1_115200, 3135 pbn_b2_bt_2_115200, 3136 pbn_b2_bt_4_115200, 3137 3138 pbn_b2_bt_2_921600, 3139 pbn_b2_bt_4_921600, 3140 3141 pbn_b3_2_115200, 3142 pbn_b3_4_115200, 3143 pbn_b3_8_115200, 3144 3145 pbn_b4_bt_2_921600, 3146 pbn_b4_bt_4_921600, 3147 pbn_b4_bt_8_921600, 3148 3149 /* 3150 * Board-specific versions. 3151 */ 3152 pbn_panacom, 3153 pbn_panacom2, 3154 pbn_panacom4, 3155 pbn_plx_romulus, 3156 pbn_oxsemi, 3157 pbn_oxsemi_1_15625000, 3158 pbn_oxsemi_2_15625000, 3159 pbn_oxsemi_4_15625000, 3160 pbn_oxsemi_8_15625000, 3161 pbn_intel_i960, 3162 pbn_sgi_ioc3, 3163 pbn_computone_4, 3164 pbn_computone_6, 3165 pbn_computone_8, 3166 pbn_sbsxrsio, 3167 pbn_pasemi_1682M, 3168 pbn_ni8430_2, 3169 pbn_ni8430_4, 3170 pbn_ni8430_8, 3171 pbn_ni8430_16, 3172 pbn_ADDIDATA_PCIe_1_3906250, 3173 pbn_ADDIDATA_PCIe_2_3906250, 3174 pbn_ADDIDATA_PCIe_4_3906250, 3175 pbn_ADDIDATA_PCIe_8_3906250, 3176 pbn_ce4100_1_115200, 3177 pbn_omegapci, 3178 pbn_NETMOS9900_2s_115200, 3179 pbn_brcm_trumanage, 3180 pbn_fintek_4, 3181 pbn_fintek_8, 3182 pbn_fintek_12, 3183 pbn_fintek_F81504A, 3184 pbn_fintek_F81508A, 3185 pbn_fintek_F81512A, 3186 pbn_wch382_2, 3187 pbn_wch384_4, 3188 pbn_wch384_8, 3189 pbn_sunix_pci_1s, 3190 pbn_sunix_pci_2s, 3191 pbn_sunix_pci_4s, 3192 pbn_sunix_pci_8s, 3193 pbn_sunix_pci_16s, 3194 pbn_titan_1_4000000, 3195 pbn_titan_2_4000000, 3196 pbn_titan_4_4000000, 3197 pbn_titan_8_4000000, 3198 pbn_moxa_2, 3199 pbn_moxa_4, 3200 pbn_moxa_8, 3201}; 3202 3203/* 3204 * uart_offset - the space between channels 3205 * reg_shift - describes how the UART registers are mapped 3206 * to PCI memory by the card. 3207 * For example IER register on SBS, Inc. PMC-OctPro is located at 3208 * offset 0x10 from the UART base, while UART_IER is defined as 1 3209 * in include/linux/serial_reg.h, 3210 * see first lines of serial_in() and serial_out() in 8250.c 3211*/ 3212 3213static struct pciserial_board pci_boards[] = { 3214 [pbn_default] = { 3215 .flags = FL_BASE0, 3216 .num_ports = 1, 3217 .base_baud = 115200, 3218 .uart_offset = 8, 3219 }, 3220 [pbn_b0_1_115200] = { 3221 .flags = FL_BASE0, 3222 .num_ports = 1, 3223 .base_baud = 115200, 3224 .uart_offset = 8, 3225 }, 3226 [pbn_b0_2_115200] = { 3227 .flags = FL_BASE0, 3228 .num_ports = 2, 3229 .base_baud = 115200, 3230 .uart_offset = 8, 3231 }, 3232 [pbn_b0_4_115200] = { 3233 .flags = FL_BASE0, 3234 .num_ports = 4, 3235 .base_baud = 115200, 3236 .uart_offset = 8, 3237 }, 3238 [pbn_b0_5_115200] = { 3239 .flags = FL_BASE0, 3240 .num_ports = 5, 3241 .base_baud = 115200, 3242 .uart_offset = 8, 3243 }, 3244 [pbn_b0_8_115200] = { 3245 .flags = FL_BASE0, 3246 .num_ports = 8, 3247 .base_baud = 115200, 3248 .uart_offset = 8, 3249 }, 3250 [pbn_b0_1_921600] = { 3251 .flags = FL_BASE0, 3252 .num_ports = 1, 3253 .base_baud = 921600, 3254 .uart_offset = 8, 3255 }, 3256 [pbn_b0_2_921600] = { 3257 .flags = FL_BASE0, 3258 .num_ports = 2, 3259 .base_baud = 921600, 3260 .uart_offset = 8, 3261 }, 3262 [pbn_b0_4_921600] = { 3263 .flags = FL_BASE0, 3264 .num_ports = 4, 3265 .base_baud = 921600, 3266 .uart_offset = 8, 3267 }, 3268 3269 [pbn_b0_2_1130000] = { 3270 .flags = FL_BASE0, 3271 .num_ports = 2, 3272 .base_baud = 1130000, 3273 .uart_offset = 8, 3274 }, 3275 3276 [pbn_b0_4_1152000] = { 3277 .flags = FL_BASE0, 3278 .num_ports = 4, 3279 .base_baud = 1152000, 3280 .uart_offset = 8, 3281 }, 3282 3283 [pbn_b0_4_1250000] = { 3284 .flags = FL_BASE0, 3285 .num_ports = 4, 3286 .base_baud = 1250000, 3287 .uart_offset = 8, 3288 }, 3289 3290 [pbn_b0_2_1843200] = { 3291 .flags = FL_BASE0, 3292 .num_ports = 2, 3293 .base_baud = 1843200, 3294 .uart_offset = 8, 3295 }, 3296 [pbn_b0_4_1843200] = { 3297 .flags = FL_BASE0, 3298 .num_ports = 4, 3299 .base_baud = 1843200, 3300 .uart_offset = 8, 3301 }, 3302 3303 [pbn_b0_1_15625000] = { 3304 .flags = FL_BASE0, 3305 .num_ports = 1, 3306 .base_baud = 15625000, 3307 .uart_offset = 8, 3308 }, 3309 3310 [pbn_b0_bt_1_115200] = { 3311 .flags = FL_BASE0|FL_BASE_BARS, 3312 .num_ports = 1, 3313 .base_baud = 115200, 3314 .uart_offset = 8, 3315 }, 3316 [pbn_b0_bt_2_115200] = { 3317 .flags = FL_BASE0|FL_BASE_BARS, 3318 .num_ports = 2, 3319 .base_baud = 115200, 3320 .uart_offset = 8, 3321 }, 3322 [pbn_b0_bt_4_115200] = { 3323 .flags = FL_BASE0|FL_BASE_BARS, 3324 .num_ports = 4, 3325 .base_baud = 115200, 3326 .uart_offset = 8, 3327 }, 3328 [pbn_b0_bt_8_115200] = { 3329 .flags = FL_BASE0|FL_BASE_BARS, 3330 .num_ports = 8, 3331 .base_baud = 115200, 3332 .uart_offset = 8, 3333 }, 3334 3335 [pbn_b0_bt_1_460800] = { 3336 .flags = FL_BASE0|FL_BASE_BARS, 3337 .num_ports = 1, 3338 .base_baud = 460800, 3339 .uart_offset = 8, 3340 }, 3341 [pbn_b0_bt_2_460800] = { 3342 .flags = FL_BASE0|FL_BASE_BARS, 3343 .num_ports = 2, 3344 .base_baud = 460800, 3345 .uart_offset = 8, 3346 }, 3347 [pbn_b0_bt_4_460800] = { 3348 .flags = FL_BASE0|FL_BASE_BARS, 3349 .num_ports = 4, 3350 .base_baud = 460800, 3351 .uart_offset = 8, 3352 }, 3353 3354 [pbn_b0_bt_1_921600] = { 3355 .flags = FL_BASE0|FL_BASE_BARS, 3356 .num_ports = 1, 3357 .base_baud = 921600, 3358 .uart_offset = 8, 3359 }, 3360 [pbn_b0_bt_2_921600] = { 3361 .flags = FL_BASE0|FL_BASE_BARS, 3362 .num_ports = 2, 3363 .base_baud = 921600, 3364 .uart_offset = 8, 3365 }, 3366 [pbn_b0_bt_4_921600] = { 3367 .flags = FL_BASE0|FL_BASE_BARS, 3368 .num_ports = 4, 3369 .base_baud = 921600, 3370 .uart_offset = 8, 3371 }, 3372 [pbn_b0_bt_8_921600] = { 3373 .flags = FL_BASE0|FL_BASE_BARS, 3374 .num_ports = 8, 3375 .base_baud = 921600, 3376 .uart_offset = 8, 3377 }, 3378 3379 [pbn_b1_1_115200] = { 3380 .flags = FL_BASE1, 3381 .num_ports = 1, 3382 .base_baud = 115200, 3383 .uart_offset = 8, 3384 }, 3385 [pbn_b1_2_115200] = { 3386 .flags = FL_BASE1, 3387 .num_ports = 2, 3388 .base_baud = 115200, 3389 .uart_offset = 8, 3390 }, 3391 [pbn_b1_4_115200] = { 3392 .flags = FL_BASE1, 3393 .num_ports = 4, 3394 .base_baud = 115200, 3395 .uart_offset = 8, 3396 }, 3397 [pbn_b1_8_115200] = { 3398 .flags = FL_BASE1, 3399 .num_ports = 8, 3400 .base_baud = 115200, 3401 .uart_offset = 8, 3402 }, 3403 [pbn_b1_16_115200] = { 3404 .flags = FL_BASE1, 3405 .num_ports = 16, 3406 .base_baud = 115200, 3407 .uart_offset = 8, 3408 }, 3409 3410 [pbn_b1_1_921600] = { 3411 .flags = FL_BASE1, 3412 .num_ports = 1, 3413 .base_baud = 921600, 3414 .uart_offset = 8, 3415 }, 3416 [pbn_b1_2_921600] = { 3417 .flags = FL_BASE1, 3418 .num_ports = 2, 3419 .base_baud = 921600, 3420 .uart_offset = 8, 3421 }, 3422 [pbn_b1_4_921600] = { 3423 .flags = FL_BASE1, 3424 .num_ports = 4, 3425 .base_baud = 921600, 3426 .uart_offset = 8, 3427 }, 3428 [pbn_b1_8_921600] = { 3429 .flags = FL_BASE1, 3430 .num_ports = 8, 3431 .base_baud = 921600, 3432 .uart_offset = 8, 3433 }, 3434 [pbn_b1_2_1250000] = { 3435 .flags = FL_BASE1, 3436 .num_ports = 2, 3437 .base_baud = 1250000, 3438 .uart_offset = 8, 3439 }, 3440 3441 [pbn_b1_bt_1_115200] = { 3442 .flags = FL_BASE1|FL_BASE_BARS, 3443 .num_ports = 1, 3444 .base_baud = 115200, 3445 .uart_offset = 8, 3446 }, 3447 [pbn_b1_bt_2_115200] = { 3448 .flags = FL_BASE1|FL_BASE_BARS, 3449 .num_ports = 2, 3450 .base_baud = 115200, 3451 .uart_offset = 8, 3452 }, 3453 [pbn_b1_bt_4_115200] = { 3454 .flags = FL_BASE1|FL_BASE_BARS, 3455 .num_ports = 4, 3456 .base_baud = 115200, 3457 .uart_offset = 8, 3458 }, 3459 3460 [pbn_b1_bt_2_921600] = { 3461 .flags = FL_BASE1|FL_BASE_BARS, 3462 .num_ports = 2, 3463 .base_baud = 921600, 3464 .uart_offset = 8, 3465 }, 3466 3467 [pbn_b1_1_1382400] = { 3468 .flags = FL_BASE1, 3469 .num_ports = 1, 3470 .base_baud = 1382400, 3471 .uart_offset = 8, 3472 }, 3473 [pbn_b1_2_1382400] = { 3474 .flags = FL_BASE1, 3475 .num_ports = 2, 3476 .base_baud = 1382400, 3477 .uart_offset = 8, 3478 }, 3479 [pbn_b1_4_1382400] = { 3480 .flags = FL_BASE1, 3481 .num_ports = 4, 3482 .base_baud = 1382400, 3483 .uart_offset = 8, 3484 }, 3485 [pbn_b1_8_1382400] = { 3486 .flags = FL_BASE1, 3487 .num_ports = 8, 3488 .base_baud = 1382400, 3489 .uart_offset = 8, 3490 }, 3491 3492 [pbn_b2_1_115200] = { 3493 .flags = FL_BASE2, 3494 .num_ports = 1, 3495 .base_baud = 115200, 3496 .uart_offset = 8, 3497 }, 3498 [pbn_b2_2_115200] = { 3499 .flags = FL_BASE2, 3500 .num_ports = 2, 3501 .base_baud = 115200, 3502 .uart_offset = 8, 3503 }, 3504 [pbn_b2_4_115200] = { 3505 .flags = FL_BASE2, 3506 .num_ports = 4, 3507 .base_baud = 115200, 3508 .uart_offset = 8, 3509 }, 3510 [pbn_b2_8_115200] = { 3511 .flags = FL_BASE2, 3512 .num_ports = 8, 3513 .base_baud = 115200, 3514 .uart_offset = 8, 3515 }, 3516 3517 [pbn_b2_1_460800] = { 3518 .flags = FL_BASE2, 3519 .num_ports = 1, 3520 .base_baud = 460800, 3521 .uart_offset = 8, 3522 }, 3523 [pbn_b2_4_460800] = { 3524 .flags = FL_BASE2, 3525 .num_ports = 4, 3526 .base_baud = 460800, 3527 .uart_offset = 8, 3528 }, 3529 [pbn_b2_8_460800] = { 3530 .flags = FL_BASE2, 3531 .num_ports = 8, 3532 .base_baud = 460800, 3533 .uart_offset = 8, 3534 }, 3535 [pbn_b2_16_460800] = { 3536 .flags = FL_BASE2, 3537 .num_ports = 16, 3538 .base_baud = 460800, 3539 .uart_offset = 8, 3540 }, 3541 3542 [pbn_b2_1_921600] = { 3543 .flags = FL_BASE2, 3544 .num_ports = 1, 3545 .base_baud = 921600, 3546 .uart_offset = 8, 3547 }, 3548 [pbn_b2_4_921600] = { 3549 .flags = FL_BASE2, 3550 .num_ports = 4, 3551 .base_baud = 921600, 3552 .uart_offset = 8, 3553 }, 3554 [pbn_b2_8_921600] = { 3555 .flags = FL_BASE2, 3556 .num_ports = 8, 3557 .base_baud = 921600, 3558 .uart_offset = 8, 3559 }, 3560 3561 [pbn_b2_8_1152000] = { 3562 .flags = FL_BASE2, 3563 .num_ports = 8, 3564 .base_baud = 1152000, 3565 .uart_offset = 8, 3566 }, 3567 3568 [pbn_b2_bt_1_115200] = { 3569 .flags = FL_BASE2|FL_BASE_BARS, 3570 .num_ports = 1, 3571 .base_baud = 115200, 3572 .uart_offset = 8, 3573 }, 3574 [pbn_b2_bt_2_115200] = { 3575 .flags = FL_BASE2|FL_BASE_BARS, 3576 .num_ports = 2, 3577 .base_baud = 115200, 3578 .uart_offset = 8, 3579 }, 3580 [pbn_b2_bt_4_115200] = { 3581 .flags = FL_BASE2|FL_BASE_BARS, 3582 .num_ports = 4, 3583 .base_baud = 115200, 3584 .uart_offset = 8, 3585 }, 3586 3587 [pbn_b2_bt_2_921600] = { 3588 .flags = FL_BASE2|FL_BASE_BARS, 3589 .num_ports = 2, 3590 .base_baud = 921600, 3591 .uart_offset = 8, 3592 }, 3593 [pbn_b2_bt_4_921600] = { 3594 .flags = FL_BASE2|FL_BASE_BARS, 3595 .num_ports = 4, 3596 .base_baud = 921600, 3597 .uart_offset = 8, 3598 }, 3599 3600 [pbn_b3_2_115200] = { 3601 .flags = FL_BASE3, 3602 .num_ports = 2, 3603 .base_baud = 115200, 3604 .uart_offset = 8, 3605 }, 3606 [pbn_b3_4_115200] = { 3607 .flags = FL_BASE3, 3608 .num_ports = 4, 3609 .base_baud = 115200, 3610 .uart_offset = 8, 3611 }, 3612 [pbn_b3_8_115200] = { 3613 .flags = FL_BASE3, 3614 .num_ports = 8, 3615 .base_baud = 115200, 3616 .uart_offset = 8, 3617 }, 3618 3619 [pbn_b4_bt_2_921600] = { 3620 .flags = FL_BASE4, 3621 .num_ports = 2, 3622 .base_baud = 921600, 3623 .uart_offset = 8, 3624 }, 3625 [pbn_b4_bt_4_921600] = { 3626 .flags = FL_BASE4, 3627 .num_ports = 4, 3628 .base_baud = 921600, 3629 .uart_offset = 8, 3630 }, 3631 [pbn_b4_bt_8_921600] = { 3632 .flags = FL_BASE4, 3633 .num_ports = 8, 3634 .base_baud = 921600, 3635 .uart_offset = 8, 3636 }, 3637 3638 /* 3639 * Entries following this are board-specific. 3640 */ 3641 3642 /* 3643 * Panacom - IOMEM 3644 */ 3645 [pbn_panacom] = { 3646 .flags = FL_BASE2, 3647 .num_ports = 2, 3648 .base_baud = 921600, 3649 .uart_offset = 0x400, 3650 .reg_shift = 7, 3651 }, 3652 [pbn_panacom2] = { 3653 .flags = FL_BASE2|FL_BASE_BARS, 3654 .num_ports = 2, 3655 .base_baud = 921600, 3656 .uart_offset = 0x400, 3657 .reg_shift = 7, 3658 }, 3659 [pbn_panacom4] = { 3660 .flags = FL_BASE2|FL_BASE_BARS, 3661 .num_ports = 4, 3662 .base_baud = 921600, 3663 .uart_offset = 0x400, 3664 .reg_shift = 7, 3665 }, 3666 3667 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3668 [pbn_plx_romulus] = { 3669 .flags = FL_BASE2, 3670 .num_ports = 4, 3671 .base_baud = 921600, 3672 .uart_offset = 8 << 2, 3673 .reg_shift = 2, 3674 .first_offset = 0x03, 3675 }, 3676 3677 /* 3678 * This board uses the size of PCI Base region 0 to 3679 * signal now many ports are available 3680 */ 3681 [pbn_oxsemi] = { 3682 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3683 .num_ports = 32, 3684 .base_baud = 115200, 3685 .uart_offset = 8, 3686 }, 3687 [pbn_oxsemi_1_15625000] = { 3688 .flags = FL_BASE0, 3689 .num_ports = 1, 3690 .base_baud = 15625000, 3691 .uart_offset = 0x200, 3692 .first_offset = 0x1000, 3693 }, 3694 [pbn_oxsemi_2_15625000] = { 3695 .flags = FL_BASE0, 3696 .num_ports = 2, 3697 .base_baud = 15625000, 3698 .uart_offset = 0x200, 3699 .first_offset = 0x1000, 3700 }, 3701 [pbn_oxsemi_4_15625000] = { 3702 .flags = FL_BASE0, 3703 .num_ports = 4, 3704 .base_baud = 15625000, 3705 .uart_offset = 0x200, 3706 .first_offset = 0x1000, 3707 }, 3708 [pbn_oxsemi_8_15625000] = { 3709 .flags = FL_BASE0, 3710 .num_ports = 8, 3711 .base_baud = 15625000, 3712 .uart_offset = 0x200, 3713 .first_offset = 0x1000, 3714 }, 3715 3716 3717 /* 3718 * EKF addition for i960 Boards form EKF with serial port. 3719 * Max 256 ports. 3720 */ 3721 [pbn_intel_i960] = { 3722 .flags = FL_BASE0, 3723 .num_ports = 32, 3724 .base_baud = 921600, 3725 .uart_offset = 8 << 2, 3726 .reg_shift = 2, 3727 .first_offset = 0x10000, 3728 }, 3729 [pbn_sgi_ioc3] = { 3730 .flags = FL_BASE0|FL_NOIRQ, 3731 .num_ports = 1, 3732 .base_baud = 458333, 3733 .uart_offset = 8, 3734 .reg_shift = 0, 3735 .first_offset = 0x20178, 3736 }, 3737 3738 /* 3739 * Computone - uses IOMEM. 3740 */ 3741 [pbn_computone_4] = { 3742 .flags = FL_BASE0, 3743 .num_ports = 4, 3744 .base_baud = 921600, 3745 .uart_offset = 0x40, 3746 .reg_shift = 2, 3747 .first_offset = 0x200, 3748 }, 3749 [pbn_computone_6] = { 3750 .flags = FL_BASE0, 3751 .num_ports = 6, 3752 .base_baud = 921600, 3753 .uart_offset = 0x40, 3754 .reg_shift = 2, 3755 .first_offset = 0x200, 3756 }, 3757 [pbn_computone_8] = { 3758 .flags = FL_BASE0, 3759 .num_ports = 8, 3760 .base_baud = 921600, 3761 .uart_offset = 0x40, 3762 .reg_shift = 2, 3763 .first_offset = 0x200, 3764 }, 3765 [pbn_sbsxrsio] = { 3766 .flags = FL_BASE0, 3767 .num_ports = 8, 3768 .base_baud = 460800, 3769 .uart_offset = 256, 3770 .reg_shift = 4, 3771 }, 3772 /* 3773 * PA Semi PWRficient PA6T-1682M on-chip UART 3774 */ 3775 [pbn_pasemi_1682M] = { 3776 .flags = FL_BASE0, 3777 .num_ports = 1, 3778 .base_baud = 8333333, 3779 }, 3780 /* 3781 * National Instruments 843x 3782 */ 3783 [pbn_ni8430_16] = { 3784 .flags = FL_BASE0, 3785 .num_ports = 16, 3786 .base_baud = 3686400, 3787 .uart_offset = 0x10, 3788 .first_offset = 0x800, 3789 }, 3790 [pbn_ni8430_8] = { 3791 .flags = FL_BASE0, 3792 .num_ports = 8, 3793 .base_baud = 3686400, 3794 .uart_offset = 0x10, 3795 .first_offset = 0x800, 3796 }, 3797 [pbn_ni8430_4] = { 3798 .flags = FL_BASE0, 3799 .num_ports = 4, 3800 .base_baud = 3686400, 3801 .uart_offset = 0x10, 3802 .first_offset = 0x800, 3803 }, 3804 [pbn_ni8430_2] = { 3805 .flags = FL_BASE0, 3806 .num_ports = 2, 3807 .base_baud = 3686400, 3808 .uart_offset = 0x10, 3809 .first_offset = 0x800, 3810 }, 3811 /* 3812 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3813 */ 3814 [pbn_ADDIDATA_PCIe_1_3906250] = { 3815 .flags = FL_BASE0, 3816 .num_ports = 1, 3817 .base_baud = 3906250, 3818 .uart_offset = 0x200, 3819 .first_offset = 0x1000, 3820 }, 3821 [pbn_ADDIDATA_PCIe_2_3906250] = { 3822 .flags = FL_BASE0, 3823 .num_ports = 2, 3824 .base_baud = 3906250, 3825 .uart_offset = 0x200, 3826 .first_offset = 0x1000, 3827 }, 3828 [pbn_ADDIDATA_PCIe_4_3906250] = { 3829 .flags = FL_BASE0, 3830 .num_ports = 4, 3831 .base_baud = 3906250, 3832 .uart_offset = 0x200, 3833 .first_offset = 0x1000, 3834 }, 3835 [pbn_ADDIDATA_PCIe_8_3906250] = { 3836 .flags = FL_BASE0, 3837 .num_ports = 8, 3838 .base_baud = 3906250, 3839 .uart_offset = 0x200, 3840 .first_offset = 0x1000, 3841 }, 3842 [pbn_ce4100_1_115200] = { 3843 .flags = FL_BASE_BARS, 3844 .num_ports = 2, 3845 .base_baud = 921600, 3846 .reg_shift = 2, 3847 }, 3848 [pbn_omegapci] = { 3849 .flags = FL_BASE0, 3850 .num_ports = 8, 3851 .base_baud = 115200, 3852 .uart_offset = 0x200, 3853 }, 3854 [pbn_NETMOS9900_2s_115200] = { 3855 .flags = FL_BASE0, 3856 .num_ports = 2, 3857 .base_baud = 115200, 3858 }, 3859 [pbn_brcm_trumanage] = { 3860 .flags = FL_BASE0, 3861 .num_ports = 1, 3862 .reg_shift = 2, 3863 .base_baud = 115200, 3864 }, 3865 [pbn_fintek_4] = { 3866 .num_ports = 4, 3867 .uart_offset = 8, 3868 .base_baud = 115200, 3869 .first_offset = 0x40, 3870 }, 3871 [pbn_fintek_8] = { 3872 .num_ports = 8, 3873 .uart_offset = 8, 3874 .base_baud = 115200, 3875 .first_offset = 0x40, 3876 }, 3877 [pbn_fintek_12] = { 3878 .num_ports = 12, 3879 .uart_offset = 8, 3880 .base_baud = 115200, 3881 .first_offset = 0x40, 3882 }, 3883 [pbn_fintek_F81504A] = { 3884 .num_ports = 4, 3885 .uart_offset = 8, 3886 .base_baud = 115200, 3887 }, 3888 [pbn_fintek_F81508A] = { 3889 .num_ports = 8, 3890 .uart_offset = 8, 3891 .base_baud = 115200, 3892 }, 3893 [pbn_fintek_F81512A] = { 3894 .num_ports = 12, 3895 .uart_offset = 8, 3896 .base_baud = 115200, 3897 }, 3898 [pbn_wch382_2] = { 3899 .flags = FL_BASE0, 3900 .num_ports = 2, 3901 .base_baud = 115200, 3902 .uart_offset = 8, 3903 .first_offset = 0xC0, 3904 }, 3905 [pbn_wch384_4] = { 3906 .flags = FL_BASE0, 3907 .num_ports = 4, 3908 .base_baud = 115200, 3909 .uart_offset = 8, 3910 .first_offset = 0xC0, 3911 }, 3912 [pbn_wch384_8] = { 3913 .flags = FL_BASE0, 3914 .num_ports = 8, 3915 .base_baud = 115200, 3916 .uart_offset = 8, 3917 .first_offset = 0x00, 3918 }, 3919 [pbn_sunix_pci_1s] = { 3920 .num_ports = 1, 3921 .base_baud = 921600, 3922 .uart_offset = 0x8, 3923 }, 3924 [pbn_sunix_pci_2s] = { 3925 .num_ports = 2, 3926 .base_baud = 921600, 3927 .uart_offset = 0x8, 3928 }, 3929 [pbn_sunix_pci_4s] = { 3930 .num_ports = 4, 3931 .base_baud = 921600, 3932 .uart_offset = 0x8, 3933 }, 3934 [pbn_sunix_pci_8s] = { 3935 .num_ports = 8, 3936 .base_baud = 921600, 3937 .uart_offset = 0x8, 3938 }, 3939 [pbn_sunix_pci_16s] = { 3940 .num_ports = 16, 3941 .base_baud = 921600, 3942 .uart_offset = 0x8, 3943 }, 3944 [pbn_titan_1_4000000] = { 3945 .flags = FL_BASE0, 3946 .num_ports = 1, 3947 .base_baud = 4000000, 3948 .uart_offset = 0x200, 3949 .first_offset = 0x1000, 3950 }, 3951 [pbn_titan_2_4000000] = { 3952 .flags = FL_BASE0, 3953 .num_ports = 2, 3954 .base_baud = 4000000, 3955 .uart_offset = 0x200, 3956 .first_offset = 0x1000, 3957 }, 3958 [pbn_titan_4_4000000] = { 3959 .flags = FL_BASE0, 3960 .num_ports = 4, 3961 .base_baud = 4000000, 3962 .uart_offset = 0x200, 3963 .first_offset = 0x1000, 3964 }, 3965 [pbn_titan_8_4000000] = { 3966 .flags = FL_BASE0, 3967 .num_ports = 8, 3968 .base_baud = 4000000, 3969 .uart_offset = 0x200, 3970 .first_offset = 0x1000, 3971 }, 3972 [pbn_moxa_2] = { 3973 .flags = FL_BASE1, 3974 .num_ports = 2, 3975 .base_baud = 921600, 3976 .uart_offset = 0x200, 3977 }, 3978 [pbn_moxa_4] = { 3979 .flags = FL_BASE1, 3980 .num_ports = 4, 3981 .base_baud = 921600, 3982 .uart_offset = 0x200, 3983 }, 3984 [pbn_moxa_8] = { 3985 .flags = FL_BASE1, 3986 .num_ports = 8, 3987 .base_baud = 921600, 3988 .uart_offset = 0x200, 3989 }, 3990}; 3991 3992#define REPORT_CONFIG(option) \ 3993 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3994#define REPORT_8250_CONFIG(option) \ 3995 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3996 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3997 3998static const struct pci_device_id blacklist[] = { 3999 /* softmodems */ 4000 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 4001 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 4002 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 4003 4004 /* multi-io cards handled by parport_serial */ 4005 /* WCH CH353 2S1P */ 4006 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), }, 4007 /* WCH CH353 1S1P */ 4008 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), }, 4009 /* WCH CH382 2S1P */ 4010 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), }, 4011 4012 /* Intel platforms with MID UART */ 4013 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 4014 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 4015 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 4016 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 4017 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 4018 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 4019 4020 /* Intel platforms with DesignWare UART */ 4021 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 4022 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 4023 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 4024 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 4025 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 4026 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 4027 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 4028 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 4029 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 4030 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 4031 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 4032 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 4033 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 4034 4035 /* Exar devices */ 4036 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 4037 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 4038 4039 /* Pericom devices */ 4040 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 4041 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 4042 4043 /* End of the black list */ 4044 { } 4045}; 4046 4047static int serial_pci_is_class_communication(struct pci_dev *dev) 4048{ 4049 /* 4050 * If it is not a communications device or the programming 4051 * interface is greater than 6, give up. 4052 */ 4053 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 4054 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 4055 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 4056 (dev->class & 0xff) > 6) 4057 return -ENODEV; 4058 4059 return 0; 4060} 4061 4062/* 4063 * Given a complete unknown PCI device, try to use some heuristics to 4064 * guess what the configuration might be, based on the pitiful PCI 4065 * serial specs. Returns 0 on success, -ENODEV on failure. 4066 */ 4067static int 4068serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 4069{ 4070 int num_iomem, num_port, first_port = -1, i; 4071 int rc; 4072 4073 rc = serial_pci_is_class_communication(dev); 4074 if (rc) 4075 return rc; 4076 4077 /* 4078 * Should we try to make guesses for multiport serial devices later? 4079 */ 4080 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 4081 return -ENODEV; 4082 4083 num_iomem = num_port = 0; 4084 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 4085 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 4086 num_port++; 4087 if (first_port == -1) 4088 first_port = i; 4089 } 4090 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 4091 num_iomem++; 4092 } 4093 4094 /* 4095 * If there is 1 or 0 iomem regions, and exactly one port, 4096 * use it. We guess the number of ports based on the IO 4097 * region size. 4098 */ 4099 if (num_iomem <= 1 && num_port == 1) { 4100 board->flags = first_port; 4101 board->num_ports = pci_resource_len(dev, first_port) / 8; 4102 return 0; 4103 } 4104 4105 /* 4106 * Now guess if we've got a board which indexes by BARs. 4107 * Each IO BAR should be 8 bytes, and they should follow 4108 * consecutively. 4109 */ 4110 first_port = -1; 4111 num_port = 0; 4112 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 4113 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 4114 pci_resource_len(dev, i) == 8 && 4115 (first_port == -1 || (first_port + num_port) == i)) { 4116 num_port++; 4117 if (first_port == -1) 4118 first_port = i; 4119 } 4120 } 4121 4122 if (num_port > 1) { 4123 board->flags = first_port | FL_BASE_BARS; 4124 board->num_ports = num_port; 4125 return 0; 4126 } 4127 4128 return -ENODEV; 4129} 4130 4131static inline int 4132serial_pci_matches(const struct pciserial_board *board, 4133 const struct pciserial_board *guessed) 4134{ 4135 return 4136 board->num_ports == guessed->num_ports && 4137 board->base_baud == guessed->base_baud && 4138 board->uart_offset == guessed->uart_offset && 4139 board->reg_shift == guessed->reg_shift && 4140 board->first_offset == guessed->first_offset; 4141} 4142 4143struct serial_private * 4144pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 4145{ 4146 struct uart_8250_port uart; 4147 struct serial_private *priv; 4148 struct pci_serial_quirk *quirk; 4149 int rc, nr_ports, i; 4150 4151 nr_ports = board->num_ports; 4152 4153 /* 4154 * Find an init and setup quirks. 4155 */ 4156 quirk = find_quirk(dev); 4157 4158 /* 4159 * Run the new-style initialization function. 4160 * The initialization function returns: 4161 * <0 - error 4162 * 0 - use board->num_ports 4163 * >0 - number of ports 4164 */ 4165 if (quirk->init) { 4166 rc = quirk->init(dev); 4167 if (rc < 0) { 4168 priv = ERR_PTR(rc); 4169 goto err_out; 4170 } 4171 if (rc) 4172 nr_ports = rc; 4173 } 4174 4175 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 4176 if (!priv) { 4177 priv = ERR_PTR(-ENOMEM); 4178 goto err_deinit; 4179 } 4180 4181 priv->dev = dev; 4182 priv->quirk = quirk; 4183 4184 memset(&uart, 0, sizeof(uart)); 4185 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 4186 uart.port.uartclk = board->base_baud * 16; 4187 4188 if (board->flags & FL_NOIRQ) { 4189 uart.port.irq = 0; 4190 } else { 4191 if (pci_match_id(pci_use_msi, dev)) { 4192 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 4193 pci_set_master(dev); 4194 uart.port.flags &= ~UPF_SHARE_IRQ; 4195 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 4196 } else { 4197 pci_dbg(dev, "Using legacy interrupts\n"); 4198 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX); 4199 } 4200 if (rc < 0) { 4201 kfree(priv); 4202 priv = ERR_PTR(rc); 4203 goto err_deinit; 4204 } 4205 4206 uart.port.irq = pci_irq_vector(dev, 0); 4207 } 4208 4209 uart.port.dev = &dev->dev; 4210 4211 for (i = 0; i < nr_ports; i++) { 4212 if (quirk->setup(priv, board, &uart, i)) 4213 break; 4214 4215 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4216 uart.port.iobase, uart.port.irq, uart.port.iotype); 4217 4218 priv->line[i] = serial8250_register_8250_port(&uart); 4219 if (priv->line[i] < 0) { 4220 pci_err(dev, 4221 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4222 uart.port.iobase, uart.port.irq, 4223 uart.port.iotype, priv->line[i]); 4224 break; 4225 } 4226 } 4227 priv->nr = i; 4228 priv->board = board; 4229 return priv; 4230 4231err_deinit: 4232 if (quirk->exit) 4233 quirk->exit(dev); 4234err_out: 4235 return priv; 4236} 4237EXPORT_SYMBOL_GPL(pciserial_init_ports); 4238 4239static void pciserial_detach_ports(struct serial_private *priv) 4240{ 4241 struct pci_serial_quirk *quirk; 4242 int i; 4243 4244 for (i = 0; i < priv->nr; i++) 4245 serial8250_unregister_port(priv->line[i]); 4246 4247 /* 4248 * Find the exit quirks. 4249 */ 4250 quirk = find_quirk(priv->dev); 4251 if (quirk->exit) 4252 quirk->exit(priv->dev); 4253} 4254 4255void pciserial_remove_ports(struct serial_private *priv) 4256{ 4257 pciserial_detach_ports(priv); 4258 kfree(priv); 4259} 4260EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4261 4262void pciserial_suspend_ports(struct serial_private *priv) 4263{ 4264 int i; 4265 4266 for (i = 0; i < priv->nr; i++) 4267 if (priv->line[i] >= 0) 4268 serial8250_suspend_port(priv->line[i]); 4269 4270 /* 4271 * Ensure that every init quirk is properly torn down 4272 */ 4273 if (priv->quirk->exit) 4274 priv->quirk->exit(priv->dev); 4275} 4276EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4277 4278void pciserial_resume_ports(struct serial_private *priv) 4279{ 4280 int i; 4281 4282 /* 4283 * Ensure that the board is correctly configured. 4284 */ 4285 if (priv->quirk->init) 4286 priv->quirk->init(priv->dev); 4287 4288 for (i = 0; i < priv->nr; i++) 4289 if (priv->line[i] >= 0) 4290 serial8250_resume_port(priv->line[i]); 4291} 4292EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4293 4294/* 4295 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4296 * to the arrangement of serial ports on a PCI card. 4297 */ 4298static int 4299pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4300{ 4301 struct pci_serial_quirk *quirk; 4302 struct serial_private *priv; 4303 const struct pciserial_board *board; 4304 const struct pci_device_id *exclude; 4305 struct pciserial_board tmp; 4306 int rc; 4307 4308 quirk = find_quirk(dev); 4309 if (quirk->probe) { 4310 rc = quirk->probe(dev); 4311 if (rc) 4312 return rc; 4313 } 4314 4315 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4316 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4317 return -EINVAL; 4318 } 4319 4320 board = &pci_boards[ent->driver_data]; 4321 4322 exclude = pci_match_id(blacklist, dev); 4323 if (exclude) { 4324 if (exclude->driver_data) 4325 pci_warn(dev, "ignoring port, enable %s to handle\n", 4326 (const char *)exclude->driver_data); 4327 return -ENODEV; 4328 } 4329 4330 rc = pcim_enable_device(dev); 4331 pci_save_state(dev); 4332 if (rc) 4333 return rc; 4334 4335 if (ent->driver_data == pbn_default) { 4336 /* 4337 * Use a copy of the pci_board entry for this; 4338 * avoid changing entries in the table. 4339 */ 4340 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4341 board = &tmp; 4342 4343 /* 4344 * We matched one of our class entries. Try to 4345 * determine the parameters of this board. 4346 */ 4347 rc = serial_pci_guess_board(dev, &tmp); 4348 if (rc) 4349 return rc; 4350 } else { 4351 /* 4352 * We matched an explicit entry. If we are able to 4353 * detect this boards settings with our heuristic, 4354 * then we no longer need this entry. 4355 */ 4356 memcpy(&tmp, &pci_boards[pbn_default], 4357 sizeof(struct pciserial_board)); 4358 rc = serial_pci_guess_board(dev, &tmp); 4359 if (rc == 0 && serial_pci_matches(board, &tmp)) 4360 moan_device("Redundant entry in serial pci_table.", 4361 dev); 4362 } 4363 4364 priv = pciserial_init_ports(dev, board); 4365 if (IS_ERR(priv)) 4366 return PTR_ERR(priv); 4367 4368 pci_set_drvdata(dev, priv); 4369 return 0; 4370} 4371 4372static void pciserial_remove_one(struct pci_dev *dev) 4373{ 4374 struct serial_private *priv = pci_get_drvdata(dev); 4375 4376 pciserial_remove_ports(priv); 4377} 4378 4379#ifdef CONFIG_PM_SLEEP 4380static int pciserial_suspend_one(struct device *dev) 4381{ 4382 struct serial_private *priv = dev_get_drvdata(dev); 4383 4384 if (priv) 4385 pciserial_suspend_ports(priv); 4386 4387 return 0; 4388} 4389 4390static int pciserial_resume_one(struct device *dev) 4391{ 4392 struct pci_dev *pdev = to_pci_dev(dev); 4393 struct serial_private *priv = pci_get_drvdata(pdev); 4394 int err; 4395 4396 if (priv) { 4397 /* 4398 * The device may have been disabled. Re-enable it. 4399 */ 4400 err = pci_enable_device(pdev); 4401 /* FIXME: We cannot simply error out here */ 4402 if (err) 4403 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4404 pciserial_resume_ports(priv); 4405 } 4406 return 0; 4407} 4408#endif 4409 4410static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4411 pciserial_resume_one); 4412 4413static const struct pci_device_id serial_pci_tbl[] = { 4414 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4415 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4416 pbn_b0_4_921600 }, 4417 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4418 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4419 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4420 pbn_b2_8_921600 }, 4421 /* Advantech also use 0x3618 and 0xf618 */ 4422 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4423 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4424 pbn_b0_4_921600 }, 4425 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4426 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4427 pbn_b0_4_921600 }, 4428 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4429 PCI_SUBVENDOR_ID_CONNECT_TECH, 4430 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4431 pbn_b1_8_1382400 }, 4432 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4433 PCI_SUBVENDOR_ID_CONNECT_TECH, 4434 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4435 pbn_b1_4_1382400 }, 4436 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4437 PCI_SUBVENDOR_ID_CONNECT_TECH, 4438 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4439 pbn_b1_2_1382400 }, 4440 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4441 PCI_SUBVENDOR_ID_CONNECT_TECH, 4442 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4443 pbn_b1_8_1382400 }, 4444 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4445 PCI_SUBVENDOR_ID_CONNECT_TECH, 4446 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4447 pbn_b1_4_1382400 }, 4448 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4449 PCI_SUBVENDOR_ID_CONNECT_TECH, 4450 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4451 pbn_b1_2_1382400 }, 4452 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4453 PCI_SUBVENDOR_ID_CONNECT_TECH, 4454 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4455 pbn_b1_8_921600 }, 4456 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4457 PCI_SUBVENDOR_ID_CONNECT_TECH, 4458 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4459 pbn_b1_8_921600 }, 4460 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4461 PCI_SUBVENDOR_ID_CONNECT_TECH, 4462 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4463 pbn_b1_4_921600 }, 4464 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4465 PCI_SUBVENDOR_ID_CONNECT_TECH, 4466 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4467 pbn_b1_4_921600 }, 4468 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4469 PCI_SUBVENDOR_ID_CONNECT_TECH, 4470 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4471 pbn_b1_2_921600 }, 4472 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4473 PCI_SUBVENDOR_ID_CONNECT_TECH, 4474 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4475 pbn_b1_8_921600 }, 4476 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4477 PCI_SUBVENDOR_ID_CONNECT_TECH, 4478 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4479 pbn_b1_8_921600 }, 4480 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4481 PCI_SUBVENDOR_ID_CONNECT_TECH, 4482 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4483 pbn_b1_4_921600 }, 4484 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4485 PCI_SUBVENDOR_ID_CONNECT_TECH, 4486 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4487 pbn_b1_2_1250000 }, 4488 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4489 PCI_SUBVENDOR_ID_CONNECT_TECH, 4490 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4491 pbn_b0_2_1843200 }, 4492 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4493 PCI_SUBVENDOR_ID_CONNECT_TECH, 4494 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4495 pbn_b0_4_1843200 }, 4496 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4497 PCI_VENDOR_ID_AFAVLAB, 4498 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4499 pbn_b0_4_1152000 }, 4500 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_b2_bt_1_115200 }, 4503 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_b2_bt_2_115200 }, 4506 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4508 pbn_b2_bt_4_115200 }, 4509 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4511 pbn_b2_bt_2_115200 }, 4512 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4514 pbn_b2_bt_4_115200 }, 4515 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_b2_8_115200 }, 4518 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4520 pbn_b2_8_460800 }, 4521 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4523 pbn_b2_8_115200 }, 4524 4525 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4527 pbn_b2_bt_2_115200 }, 4528 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4530 pbn_b2_bt_2_921600 }, 4531 /* 4532 * VScom SPCOM800, from sl@s.pl 4533 */ 4534 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4536 pbn_b2_8_921600 }, 4537 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4539 pbn_b2_4_921600 }, 4540 /* Unknown card - subdevice 0x1584 */ 4541 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4542 PCI_VENDOR_ID_PLX, 4543 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4544 pbn_b2_4_115200 }, 4545 /* Unknown card - subdevice 0x1588 */ 4546 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4547 PCI_VENDOR_ID_PLX, 4548 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4549 pbn_b2_8_115200 }, 4550 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4551 PCI_SUBVENDOR_ID_KEYSPAN, 4552 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4553 pbn_panacom }, 4554 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4556 pbn_panacom4 }, 4557 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4559 pbn_panacom2 }, 4560 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4561 PCI_VENDOR_ID_ESDGMBH, 4562 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4563 pbn_b2_4_115200 }, 4564 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4565 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4566 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4567 pbn_b2_4_460800 }, 4568 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4569 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4570 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4571 pbn_b2_8_460800 }, 4572 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4573 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4574 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4575 pbn_b2_16_460800 }, 4576 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4577 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4578 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4579 pbn_b2_16_460800 }, 4580 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4581 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4582 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4583 pbn_b2_4_460800 }, 4584 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4585 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4586 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4587 pbn_b2_8_460800 }, 4588 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4589 PCI_SUBVENDOR_ID_EXSYS, 4590 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4591 pbn_b2_4_115200 }, 4592 /* 4593 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4594 * (Exoray@isys.ca) 4595 */ 4596 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4597 0x10b5, 0x106a, 0, 0, 4598 pbn_plx_romulus }, 4599 /* 4600 * Quatech cards. These actually have configurable clocks but for 4601 * now we just use the default. 4602 * 4603 * 100 series are RS232, 200 series RS422, 4604 */ 4605 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_b1_4_115200 }, 4608 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_b1_2_115200 }, 4611 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_b2_2_115200 }, 4614 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_b1_2_115200 }, 4617 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_b2_2_115200 }, 4620 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4622 pbn_b1_4_115200 }, 4623 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4625 pbn_b1_8_115200 }, 4626 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4628 pbn_b1_8_115200 }, 4629 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_b1_4_115200 }, 4632 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4634 pbn_b1_2_115200 }, 4635 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_b1_4_115200 }, 4638 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4640 pbn_b1_2_115200 }, 4641 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4643 pbn_b2_4_115200 }, 4644 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4646 pbn_b2_2_115200 }, 4647 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4649 pbn_b2_1_115200 }, 4650 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4652 pbn_b2_4_115200 }, 4653 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_b2_2_115200 }, 4656 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_b2_1_115200 }, 4659 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b0_8_115200 }, 4662 4663 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4664 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4665 0, 0, 4666 pbn_b0_4_921600 }, 4667 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4668 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4669 0, 0, 4670 pbn_b0_4_1152000 }, 4671 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b0_bt_2_921600 }, 4674 4675 /* 4676 * The below card is a little controversial since it is the 4677 * subject of a PCI vendor/device ID clash. (See 4678 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4679 * For now just used the hex ID 0x950a. 4680 */ 4681 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4682 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4683 0, 0, pbn_b0_2_115200 }, 4684 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4685 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4686 0, 0, pbn_b0_2_115200 }, 4687 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4689 pbn_b0_2_1130000 }, 4690 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4691 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4692 pbn_b0_1_921600 }, 4693 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4695 pbn_b0_4_115200 }, 4696 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_b0_bt_2_921600 }, 4699 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_b2_8_1152000 }, 4702 4703 /* 4704 * Oxford Semiconductor Inc. Tornado PCI express device range. 4705 */ 4706 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4708 pbn_b0_1_15625000 }, 4709 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4711 pbn_b0_1_15625000 }, 4712 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4714 pbn_oxsemi_1_15625000 }, 4715 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4717 pbn_oxsemi_1_15625000 }, 4718 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4720 pbn_b0_1_15625000 }, 4721 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4723 pbn_b0_1_15625000 }, 4724 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4726 pbn_oxsemi_1_15625000 }, 4727 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4729 pbn_oxsemi_1_15625000 }, 4730 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4732 pbn_b0_1_15625000 }, 4733 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4735 pbn_b0_1_15625000 }, 4736 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4738 pbn_b0_1_15625000 }, 4739 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4741 pbn_b0_1_15625000 }, 4742 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4744 pbn_oxsemi_2_15625000 }, 4745 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4747 pbn_oxsemi_2_15625000 }, 4748 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4750 pbn_oxsemi_4_15625000 }, 4751 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4753 pbn_oxsemi_4_15625000 }, 4754 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4756 pbn_oxsemi_8_15625000 }, 4757 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_oxsemi_8_15625000 }, 4760 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_oxsemi_1_15625000 }, 4763 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_oxsemi_1_15625000 }, 4766 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_oxsemi_1_15625000 }, 4769 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_oxsemi_1_15625000 }, 4772 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4774 pbn_oxsemi_1_15625000 }, 4775 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_oxsemi_1_15625000 }, 4778 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_oxsemi_1_15625000 }, 4781 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4783 pbn_oxsemi_1_15625000 }, 4784 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4786 pbn_oxsemi_1_15625000 }, 4787 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_oxsemi_1_15625000 }, 4790 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_oxsemi_1_15625000 }, 4793 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4795 pbn_oxsemi_1_15625000 }, 4796 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4798 pbn_oxsemi_1_15625000 }, 4799 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4801 pbn_oxsemi_1_15625000 }, 4802 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4804 pbn_oxsemi_1_15625000 }, 4805 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4807 pbn_oxsemi_1_15625000 }, 4808 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4810 pbn_oxsemi_1_15625000 }, 4811 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4813 pbn_oxsemi_1_15625000 }, 4814 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4816 pbn_oxsemi_1_15625000 }, 4817 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4819 pbn_oxsemi_1_15625000 }, 4820 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4822 pbn_oxsemi_1_15625000 }, 4823 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4824 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4825 pbn_oxsemi_1_15625000 }, 4826 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4827 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4828 pbn_oxsemi_1_15625000 }, 4829 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4830 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4831 pbn_oxsemi_1_15625000 }, 4832 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4833 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4834 pbn_oxsemi_1_15625000 }, 4835 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4837 pbn_oxsemi_1_15625000 }, 4838 /* 4839 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4840 */ 4841 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4842 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4843 pbn_oxsemi_1_15625000 }, 4844 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4845 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4846 pbn_oxsemi_2_15625000 }, 4847 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4848 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4849 pbn_oxsemi_4_15625000 }, 4850 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4851 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4852 pbn_oxsemi_8_15625000 }, 4853 4854 /* 4855 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4856 */ 4857 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4858 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4859 pbn_oxsemi_2_15625000 }, 4860 /* 4861 * EndRun Technologies. PCI express device range. 4862 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4863 */ 4864 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4866 pbn_oxsemi_2_15625000 }, 4867 4868 /* 4869 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4870 * from skokodyn@yahoo.com 4871 */ 4872 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4873 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4874 pbn_sbsxrsio }, 4875 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4876 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4877 pbn_sbsxrsio }, 4878 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4879 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4880 pbn_sbsxrsio }, 4881 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4882 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4883 pbn_sbsxrsio }, 4884 4885 /* 4886 * Digitan DS560-558, from jimd@esoft.com 4887 */ 4888 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4890 pbn_b1_1_115200 }, 4891 4892 /* 4893 * Titan Electronic cards 4894 * The 400L and 800L have a custom setup quirk. 4895 */ 4896 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4898 pbn_b0_1_921600 }, 4899 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4901 pbn_b0_2_921600 }, 4902 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4904 pbn_b0_4_921600 }, 4905 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4907 pbn_b0_4_921600 }, 4908 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4910 pbn_b1_1_921600 }, 4911 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4913 pbn_b1_bt_2_921600 }, 4914 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4916 pbn_b0_bt_4_921600 }, 4917 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4919 pbn_b0_bt_8_921600 }, 4920 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4922 pbn_b4_bt_2_921600 }, 4923 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4925 pbn_b4_bt_4_921600 }, 4926 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4928 pbn_b4_bt_8_921600 }, 4929 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4931 pbn_b0_4_921600 }, 4932 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4934 pbn_b0_4_921600 }, 4935 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4937 pbn_b0_4_921600 }, 4938 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4939 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4940 pbn_titan_1_4000000 }, 4941 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4943 pbn_titan_2_4000000 }, 4944 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4946 pbn_titan_4_4000000 }, 4947 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4949 pbn_titan_8_4000000 }, 4950 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4952 pbn_titan_2_4000000 }, 4953 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4955 pbn_titan_2_4000000 }, 4956 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4958 pbn_b0_bt_2_921600 }, 4959 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4961 pbn_b0_4_921600 }, 4962 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4964 pbn_b0_4_921600 }, 4965 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4967 pbn_b0_4_921600 }, 4968 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4970 pbn_b0_4_921600 }, 4971 4972 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4974 pbn_b2_1_460800 }, 4975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4977 pbn_b2_1_460800 }, 4978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4980 pbn_b2_1_460800 }, 4981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4983 pbn_b2_bt_2_921600 }, 4984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4986 pbn_b2_bt_2_921600 }, 4987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4989 pbn_b2_bt_2_921600 }, 4990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4992 pbn_b2_bt_4_921600 }, 4993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4995 pbn_b2_bt_4_921600 }, 4996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4998 pbn_b2_bt_4_921600 }, 4999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5001 pbn_b0_1_921600 }, 5002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5004 pbn_b0_1_921600 }, 5005 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5007 pbn_b0_1_921600 }, 5008 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5010 pbn_b0_bt_2_921600 }, 5011 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5013 pbn_b0_bt_2_921600 }, 5014 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5016 pbn_b0_bt_2_921600 }, 5017 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5019 pbn_b0_bt_4_921600 }, 5020 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5022 pbn_b0_bt_4_921600 }, 5023 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5025 pbn_b0_bt_4_921600 }, 5026 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5028 pbn_b0_bt_8_921600 }, 5029 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 5030 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5031 pbn_b0_bt_8_921600 }, 5032 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 5033 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5034 pbn_b0_bt_8_921600 }, 5035 5036 /* 5037 * Computone devices submitted by Doug McNash dmcnash@computone.com 5038 */ 5039 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5040 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 5041 0, 0, pbn_computone_4 }, 5042 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5043 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 5044 0, 0, pbn_computone_8 }, 5045 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5046 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 5047 0, 0, pbn_computone_6 }, 5048 5049 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5051 pbn_oxsemi }, 5052 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 5053 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 5054 pbn_b0_bt_1_921600 }, 5055 5056 /* 5057 * Sunix PCI serial boards 5058 */ 5059 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5060 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 5061 pbn_sunix_pci_1s }, 5062 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5063 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 5064 pbn_sunix_pci_2s }, 5065 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5066 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 5067 pbn_sunix_pci_4s }, 5068 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5069 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 5070 pbn_sunix_pci_4s }, 5071 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5072 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 5073 pbn_sunix_pci_8s }, 5074 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5075 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 5076 pbn_sunix_pci_8s }, 5077 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5078 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 5079 pbn_sunix_pci_16s }, 5080 5081 /* 5082 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 5083 */ 5084 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5086 pbn_b0_bt_8_115200 }, 5087 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5089 pbn_b0_bt_8_115200 }, 5090 5091 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5093 pbn_b0_bt_2_115200 }, 5094 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5096 pbn_b0_bt_2_115200 }, 5097 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5099 pbn_b0_bt_2_115200 }, 5100 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5102 pbn_b0_bt_4_460800 }, 5103 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5105 pbn_b0_bt_4_460800 }, 5106 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5108 pbn_b0_bt_2_460800 }, 5109 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5111 pbn_b0_bt_2_460800 }, 5112 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5114 pbn_b0_bt_2_460800 }, 5115 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5117 pbn_b0_bt_1_115200 }, 5118 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5120 pbn_b0_bt_1_460800 }, 5121 5122 /* 5123 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 5124 * Cards are identified by their subsystem vendor IDs, which 5125 * (in hex) match the model number. 5126 * 5127 * Note that JC140x are RS422/485 cards which require ox950 5128 * ACR = 0x10, and as such are not currently fully supported. 5129 */ 5130 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5131 0x1204, 0x0004, 0, 0, 5132 pbn_b0_4_921600 }, 5133 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5134 0x1208, 0x0004, 0, 0, 5135 pbn_b0_4_921600 }, 5136/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5137 0x1402, 0x0002, 0, 0, 5138 pbn_b0_2_921600 }, */ 5139/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5140 0x1404, 0x0004, 0, 0, 5141 pbn_b0_4_921600 }, */ 5142 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 5143 0x1208, 0x0004, 0, 0, 5144 pbn_b0_4_921600 }, 5145 5146 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5147 0x1204, 0x0004, 0, 0, 5148 pbn_b0_4_921600 }, 5149 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5150 0x1208, 0x0004, 0, 0, 5151 pbn_b0_4_921600 }, 5152 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 5153 0x1208, 0x0004, 0, 0, 5154 pbn_b0_4_921600 }, 5155 /* 5156 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 5157 */ 5158 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5160 pbn_b1_1_1382400 }, 5161 5162 /* 5163 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 5164 */ 5165 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 5166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5167 pbn_b1_1_1382400 }, 5168 5169 /* 5170 * RAStel 2 port modem, gerg@moreton.com.au 5171 */ 5172 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 5173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5174 pbn_b2_bt_2_115200 }, 5175 5176 /* 5177 * EKF addition for i960 Boards form EKF with serial port 5178 */ 5179 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 5180 0xE4BF, PCI_ANY_ID, 0, 0, 5181 pbn_intel_i960 }, 5182 5183 /* 5184 * Xircom Cardbus/Ethernet combos 5185 */ 5186 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 5187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5188 pbn_b0_1_115200 }, 5189 /* 5190 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 5191 */ 5192 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 5193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5194 pbn_b0_1_115200 }, 5195 5196 /* 5197 * Untested PCI modems, sent in from various folks... 5198 */ 5199 5200 /* 5201 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 5202 */ 5203 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 5204 0x1048, 0x1500, 0, 0, 5205 pbn_b1_1_115200 }, 5206 5207 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 5208 0xFF00, 0, 0, 0, 5209 pbn_sgi_ioc3 }, 5210 5211 /* 5212 * HP Diva card 5213 */ 5214 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5215 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 5216 pbn_b1_1_115200 }, 5217 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5219 pbn_b0_5_115200 }, 5220 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5222 pbn_b2_1_115200 }, 5223 /* HPE PCI serial device */ 5224 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 5225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5226 pbn_b1_1_115200 }, 5227 5228 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5230 pbn_b3_2_115200 }, 5231 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5233 pbn_b3_4_115200 }, 5234 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5236 pbn_b3_8_115200 }, 5237 /* 5238 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5239 */ 5240 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5242 pbn_b0_1_115200 }, 5243 /* 5244 * ITE 5245 */ 5246 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5247 PCI_ANY_ID, PCI_ANY_ID, 5248 0, 0, 5249 pbn_b1_bt_1_115200 }, 5250 5251 /* 5252 * IntaShield IS-100 5253 */ 5254 { PCI_VENDOR_ID_INTASHIELD, 0x0D60, 5255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5256 pbn_b2_1_115200 }, 5257 /* 5258 * IntaShield IS-200 5259 */ 5260 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */ 5262 pbn_b2_2_115200 }, 5263 /* 5264 * IntaShield IS-400 5265 */ 5266 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5268 pbn_b2_4_115200 }, 5269 /* 5270 * IntaShield IX-100 5271 */ 5272 { PCI_VENDOR_ID_INTASHIELD, 0x4027, 5273 PCI_ANY_ID, PCI_ANY_ID, 5274 0, 0, 5275 pbn_oxsemi_1_15625000 }, 5276 /* 5277 * IntaShield IX-200 5278 */ 5279 { PCI_VENDOR_ID_INTASHIELD, 0x4028, 5280 PCI_ANY_ID, PCI_ANY_ID, 5281 0, 0, 5282 pbn_oxsemi_2_15625000 }, 5283 /* 5284 * IntaShield IX-400 5285 */ 5286 { PCI_VENDOR_ID_INTASHIELD, 0x4029, 5287 PCI_ANY_ID, PCI_ANY_ID, 5288 0, 0, 5289 pbn_oxsemi_4_15625000 }, 5290 /* Brainboxes Devices */ 5291 /* 5292 * Brainboxes UC-101 5293 */ 5294 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 5295 PCI_ANY_ID, PCI_ANY_ID, 5296 0, 0, 5297 pbn_b2_2_115200 }, 5298 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2, 5299 PCI_ANY_ID, PCI_ANY_ID, 5300 0, 0, 5301 pbn_b2_2_115200 }, 5302 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3, 5303 PCI_ANY_ID, PCI_ANY_ID, 5304 0, 0, 5305 pbn_b2_2_115200 }, 5306 /* 5307 * Brainboxes UC-235/246 5308 */ 5309 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 5310 PCI_ANY_ID, PCI_ANY_ID, 5311 0, 0, 5312 pbn_b2_1_115200 }, 5313 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, 5314 PCI_ANY_ID, PCI_ANY_ID, 5315 0, 0, 5316 pbn_b2_1_115200 }, 5317 /* 5318 * Brainboxes UC-253/UC-734 5319 */ 5320 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, 5321 PCI_ANY_ID, PCI_ANY_ID, 5322 0, 0, 5323 pbn_b2_2_115200 }, 5324 /* 5325 * Brainboxes UC-260/271/701/756 5326 */ 5327 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5328 PCI_ANY_ID, PCI_ANY_ID, 5329 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5330 pbn_b2_4_115200 }, 5331 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5332 PCI_ANY_ID, PCI_ANY_ID, 5333 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5334 pbn_b2_4_115200 }, 5335 /* 5336 * Brainboxes UC-268 5337 */ 5338 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 5339 PCI_ANY_ID, PCI_ANY_ID, 5340 0, 0, 5341 pbn_b2_4_115200 }, 5342 /* 5343 * Brainboxes UC-275/279 5344 */ 5345 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5346 PCI_ANY_ID, PCI_ANY_ID, 5347 0, 0, 5348 pbn_b2_8_115200 }, 5349 /* 5350 * Brainboxes UC-302 5351 */ 5352 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5353 PCI_ANY_ID, PCI_ANY_ID, 5354 0, 0, 5355 pbn_b2_2_115200 }, 5356 { PCI_VENDOR_ID_INTASHIELD, 0x08E2, 5357 PCI_ANY_ID, PCI_ANY_ID, 5358 0, 0, 5359 pbn_b2_2_115200 }, 5360 { PCI_VENDOR_ID_INTASHIELD, 0x08E3, 5361 PCI_ANY_ID, PCI_ANY_ID, 5362 0, 0, 5363 pbn_b2_2_115200 }, 5364 /* 5365 * Brainboxes UC-310 5366 */ 5367 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5368 PCI_ANY_ID, PCI_ANY_ID, 5369 0, 0, 5370 pbn_b2_2_115200 }, 5371 /* 5372 * Brainboxes UC-313 5373 */ 5374 { PCI_VENDOR_ID_INTASHIELD, 0x08A1, 5375 PCI_ANY_ID, PCI_ANY_ID, 5376 0, 0, 5377 pbn_b2_2_115200 }, 5378 { PCI_VENDOR_ID_INTASHIELD, 0x08A2, 5379 PCI_ANY_ID, PCI_ANY_ID, 5380 0, 0, 5381 pbn_b2_2_115200 }, 5382 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5383 PCI_ANY_ID, PCI_ANY_ID, 5384 0, 0, 5385 pbn_b2_2_115200 }, 5386 /* 5387 * Brainboxes UC-320/324 5388 */ 5389 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5390 PCI_ANY_ID, PCI_ANY_ID, 5391 0, 0, 5392 pbn_b2_1_115200 }, 5393 /* 5394 * Brainboxes UC-346 5395 */ 5396 { PCI_VENDOR_ID_INTASHIELD, 0x0B01, 5397 PCI_ANY_ID, PCI_ANY_ID, 5398 0, 0, 5399 pbn_b2_4_115200 }, 5400 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5401 PCI_ANY_ID, PCI_ANY_ID, 5402 0, 0, 5403 pbn_b2_4_115200 }, 5404 /* 5405 * Brainboxes UC-357 5406 */ 5407 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5408 PCI_ANY_ID, PCI_ANY_ID, 5409 0, 0, 5410 pbn_b2_2_115200 }, 5411 { PCI_VENDOR_ID_INTASHIELD, 0x0A82, 5412 PCI_ANY_ID, PCI_ANY_ID, 5413 0, 0, 5414 pbn_b2_2_115200 }, 5415 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5416 PCI_ANY_ID, PCI_ANY_ID, 5417 0, 0, 5418 pbn_b2_2_115200 }, 5419 /* 5420 * Brainboxes UC-368 5421 */ 5422 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5423 PCI_ANY_ID, PCI_ANY_ID, 5424 0, 0, 5425 pbn_b2_4_115200 }, 5426 { PCI_VENDOR_ID_INTASHIELD, 0x0C42, 5427 PCI_ANY_ID, PCI_ANY_ID, 5428 0, 0, 5429 pbn_b2_4_115200 }, 5430 { PCI_VENDOR_ID_INTASHIELD, 0x0C43, 5431 PCI_ANY_ID, PCI_ANY_ID, 5432 0, 0, 5433 pbn_b2_4_115200 }, 5434 /* 5435 * Brainboxes UC-420 5436 */ 5437 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5438 PCI_ANY_ID, PCI_ANY_ID, 5439 0, 0, 5440 pbn_b2_4_115200 }, 5441 /* 5442 * Brainboxes UC-607 5443 */ 5444 { PCI_VENDOR_ID_INTASHIELD, 0x09A1, 5445 PCI_ANY_ID, PCI_ANY_ID, 5446 0, 0, 5447 pbn_b2_2_115200 }, 5448 { PCI_VENDOR_ID_INTASHIELD, 0x09A2, 5449 PCI_ANY_ID, PCI_ANY_ID, 5450 0, 0, 5451 pbn_b2_2_115200 }, 5452 { PCI_VENDOR_ID_INTASHIELD, 0x09A3, 5453 PCI_ANY_ID, PCI_ANY_ID, 5454 0, 0, 5455 pbn_b2_2_115200 }, 5456 /* 5457 * Brainboxes UC-836 5458 */ 5459 { PCI_VENDOR_ID_INTASHIELD, 0x0D41, 5460 PCI_ANY_ID, PCI_ANY_ID, 5461 0, 0, 5462 pbn_b2_4_115200 }, 5463 /* 5464 * Brainboxes UP-189 5465 */ 5466 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, 5467 PCI_ANY_ID, PCI_ANY_ID, 5468 0, 0, 5469 pbn_b2_2_115200 }, 5470 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, 5471 PCI_ANY_ID, PCI_ANY_ID, 5472 0, 0, 5473 pbn_b2_2_115200 }, 5474 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, 5475 PCI_ANY_ID, PCI_ANY_ID, 5476 0, 0, 5477 pbn_b2_2_115200 }, 5478 /* 5479 * Brainboxes UP-200 5480 */ 5481 { PCI_VENDOR_ID_INTASHIELD, 0x0B21, 5482 PCI_ANY_ID, PCI_ANY_ID, 5483 0, 0, 5484 pbn_b2_2_115200 }, 5485 { PCI_VENDOR_ID_INTASHIELD, 0x0B22, 5486 PCI_ANY_ID, PCI_ANY_ID, 5487 0, 0, 5488 pbn_b2_2_115200 }, 5489 { PCI_VENDOR_ID_INTASHIELD, 0x0B23, 5490 PCI_ANY_ID, PCI_ANY_ID, 5491 0, 0, 5492 pbn_b2_2_115200 }, 5493 /* 5494 * Brainboxes UP-869 5495 */ 5496 { PCI_VENDOR_ID_INTASHIELD, 0x0C01, 5497 PCI_ANY_ID, PCI_ANY_ID, 5498 0, 0, 5499 pbn_b2_2_115200 }, 5500 { PCI_VENDOR_ID_INTASHIELD, 0x0C02, 5501 PCI_ANY_ID, PCI_ANY_ID, 5502 0, 0, 5503 pbn_b2_2_115200 }, 5504 { PCI_VENDOR_ID_INTASHIELD, 0x0C03, 5505 PCI_ANY_ID, PCI_ANY_ID, 5506 0, 0, 5507 pbn_b2_2_115200 }, 5508 /* 5509 * Brainboxes UP-880 5510 */ 5511 { PCI_VENDOR_ID_INTASHIELD, 0x0C21, 5512 PCI_ANY_ID, PCI_ANY_ID, 5513 0, 0, 5514 pbn_b2_2_115200 }, 5515 { PCI_VENDOR_ID_INTASHIELD, 0x0C22, 5516 PCI_ANY_ID, PCI_ANY_ID, 5517 0, 0, 5518 pbn_b2_2_115200 }, 5519 { PCI_VENDOR_ID_INTASHIELD, 0x0C23, 5520 PCI_ANY_ID, PCI_ANY_ID, 5521 0, 0, 5522 pbn_b2_2_115200 }, 5523 /* 5524 * Brainboxes PX-101 5525 */ 5526 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5527 PCI_ANY_ID, PCI_ANY_ID, 5528 0, 0, 5529 pbn_b0_2_115200 }, 5530 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5531 PCI_ANY_ID, PCI_ANY_ID, 5532 0, 0, 5533 pbn_oxsemi_2_15625000 }, 5534 /* 5535 * Brainboxes PX-235/246 5536 */ 5537 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5538 PCI_ANY_ID, PCI_ANY_ID, 5539 0, 0, 5540 pbn_b0_1_115200 }, 5541 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5542 PCI_ANY_ID, PCI_ANY_ID, 5543 0, 0, 5544 pbn_oxsemi_1_15625000 }, 5545 /* 5546 * Brainboxes PX-203/PX-257 5547 */ 5548 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5549 PCI_ANY_ID, PCI_ANY_ID, 5550 0, 0, 5551 pbn_b0_2_115200 }, 5552 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5553 PCI_ANY_ID, PCI_ANY_ID, 5554 0, 0, 5555 pbn_oxsemi_2_15625000 }, 5556 /* 5557 * Brainboxes PX-260/PX-701 5558 */ 5559 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5560 PCI_ANY_ID, PCI_ANY_ID, 5561 0, 0, 5562 pbn_oxsemi_4_15625000 }, 5563 /* 5564 * Brainboxes PX-275/279 5565 */ 5566 { PCI_VENDOR_ID_INTASHIELD, 0x0E41, 5567 PCI_ANY_ID, PCI_ANY_ID, 5568 0, 0, 5569 pbn_b2_8_115200 }, 5570 /* 5571 * Brainboxes PX-310 5572 */ 5573 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5574 PCI_ANY_ID, PCI_ANY_ID, 5575 0, 0, 5576 pbn_oxsemi_2_15625000 }, 5577 /* 5578 * Brainboxes PX-313 5579 */ 5580 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5581 PCI_ANY_ID, PCI_ANY_ID, 5582 0, 0, 5583 pbn_oxsemi_2_15625000 }, 5584 /* 5585 * Brainboxes PX-320/324/PX-376/PX-387 5586 */ 5587 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5588 PCI_ANY_ID, PCI_ANY_ID, 5589 0, 0, 5590 pbn_oxsemi_1_15625000 }, 5591 /* 5592 * Brainboxes PX-335/346 5593 */ 5594 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5595 PCI_ANY_ID, PCI_ANY_ID, 5596 0, 0, 5597 pbn_oxsemi_4_15625000 }, 5598 /* 5599 * Brainboxes PX-368 5600 */ 5601 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5602 PCI_ANY_ID, PCI_ANY_ID, 5603 0, 0, 5604 pbn_oxsemi_4_15625000 }, 5605 /* 5606 * Brainboxes PX-420 5607 */ 5608 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5609 PCI_ANY_ID, PCI_ANY_ID, 5610 0, 0, 5611 pbn_b0_4_115200 }, 5612 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5613 PCI_ANY_ID, PCI_ANY_ID, 5614 0, 0, 5615 pbn_oxsemi_4_15625000 }, 5616 /* 5617 * Brainboxes PX-475 5618 */ 5619 { PCI_VENDOR_ID_INTASHIELD, 0x401D, 5620 PCI_ANY_ID, PCI_ANY_ID, 5621 0, 0, 5622 pbn_oxsemi_1_15625000 }, 5623 /* 5624 * Brainboxes PX-803/PX-857 5625 */ 5626 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5627 PCI_ANY_ID, PCI_ANY_ID, 5628 0, 0, 5629 pbn_b0_2_115200 }, 5630 { PCI_VENDOR_ID_INTASHIELD, 0x4018, 5631 PCI_ANY_ID, PCI_ANY_ID, 5632 0, 0, 5633 pbn_oxsemi_2_15625000 }, 5634 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5635 PCI_ANY_ID, PCI_ANY_ID, 5636 0, 0, 5637 pbn_oxsemi_2_15625000 }, 5638 /* 5639 * Brainboxes PX-820 5640 */ 5641 { PCI_VENDOR_ID_INTASHIELD, 0x4002, 5642 PCI_ANY_ID, PCI_ANY_ID, 5643 0, 0, 5644 pbn_b0_4_115200 }, 5645 { PCI_VENDOR_ID_INTASHIELD, 0x4013, 5646 PCI_ANY_ID, PCI_ANY_ID, 5647 0, 0, 5648 pbn_oxsemi_4_15625000 }, 5649 /* 5650 * Brainboxes PX-835/PX-846 5651 */ 5652 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5653 PCI_ANY_ID, PCI_ANY_ID, 5654 0, 0, 5655 pbn_b0_1_115200 }, 5656 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5657 PCI_ANY_ID, PCI_ANY_ID, 5658 0, 0, 5659 pbn_oxsemi_1_15625000 }, 5660 /* 5661 * Brainboxes XC-235 5662 */ 5663 { PCI_VENDOR_ID_INTASHIELD, 0x4026, 5664 PCI_ANY_ID, PCI_ANY_ID, 5665 0, 0, 5666 pbn_oxsemi_1_15625000 }, 5667 /* 5668 * Brainboxes XC-475 5669 */ 5670 { PCI_VENDOR_ID_INTASHIELD, 0x4021, 5671 PCI_ANY_ID, PCI_ANY_ID, 5672 0, 0, 5673 pbn_oxsemi_1_15625000 }, 5674 5675 /* 5676 * Perle PCI-RAS cards 5677 */ 5678 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5679 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5680 0, 0, pbn_b2_4_921600 }, 5681 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5682 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5683 0, 0, pbn_b2_8_921600 }, 5684 5685 /* 5686 * Mainpine series cards: Fairly standard layout but fools 5687 * parts of the autodetect in some cases and uses otherwise 5688 * unmatched communications subclasses in the PCI Express case 5689 */ 5690 5691 { /* RockForceDUO */ 5692 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5693 PCI_VENDOR_ID_MAINPINE, 0x0200, 5694 0, 0, pbn_b0_2_115200 }, 5695 { /* RockForceQUATRO */ 5696 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5697 PCI_VENDOR_ID_MAINPINE, 0x0300, 5698 0, 0, pbn_b0_4_115200 }, 5699 { /* RockForceDUO+ */ 5700 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5701 PCI_VENDOR_ID_MAINPINE, 0x0400, 5702 0, 0, pbn_b0_2_115200 }, 5703 { /* RockForceQUATRO+ */ 5704 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5705 PCI_VENDOR_ID_MAINPINE, 0x0500, 5706 0, 0, pbn_b0_4_115200 }, 5707 { /* RockForce+ */ 5708 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5709 PCI_VENDOR_ID_MAINPINE, 0x0600, 5710 0, 0, pbn_b0_2_115200 }, 5711 { /* RockForce+ */ 5712 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5713 PCI_VENDOR_ID_MAINPINE, 0x0700, 5714 0, 0, pbn_b0_4_115200 }, 5715 { /* RockForceOCTO+ */ 5716 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5717 PCI_VENDOR_ID_MAINPINE, 0x0800, 5718 0, 0, pbn_b0_8_115200 }, 5719 { /* RockForceDUO+ */ 5720 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5721 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5722 0, 0, pbn_b0_2_115200 }, 5723 { /* RockForceQUARTRO+ */ 5724 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5725 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5726 0, 0, pbn_b0_4_115200 }, 5727 { /* RockForceOCTO+ */ 5728 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5729 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5730 0, 0, pbn_b0_8_115200 }, 5731 { /* RockForceD1 */ 5732 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5733 PCI_VENDOR_ID_MAINPINE, 0x2000, 5734 0, 0, pbn_b0_1_115200 }, 5735 { /* RockForceF1 */ 5736 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5737 PCI_VENDOR_ID_MAINPINE, 0x2100, 5738 0, 0, pbn_b0_1_115200 }, 5739 { /* RockForceD2 */ 5740 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5741 PCI_VENDOR_ID_MAINPINE, 0x2200, 5742 0, 0, pbn_b0_2_115200 }, 5743 { /* RockForceF2 */ 5744 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5745 PCI_VENDOR_ID_MAINPINE, 0x2300, 5746 0, 0, pbn_b0_2_115200 }, 5747 { /* RockForceD4 */ 5748 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5749 PCI_VENDOR_ID_MAINPINE, 0x2400, 5750 0, 0, pbn_b0_4_115200 }, 5751 { /* RockForceF4 */ 5752 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5753 PCI_VENDOR_ID_MAINPINE, 0x2500, 5754 0, 0, pbn_b0_4_115200 }, 5755 { /* RockForceD8 */ 5756 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5757 PCI_VENDOR_ID_MAINPINE, 0x2600, 5758 0, 0, pbn_b0_8_115200 }, 5759 { /* RockForceF8 */ 5760 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5761 PCI_VENDOR_ID_MAINPINE, 0x2700, 5762 0, 0, pbn_b0_8_115200 }, 5763 { /* IQ Express D1 */ 5764 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5765 PCI_VENDOR_ID_MAINPINE, 0x3000, 5766 0, 0, pbn_b0_1_115200 }, 5767 { /* IQ Express F1 */ 5768 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5769 PCI_VENDOR_ID_MAINPINE, 0x3100, 5770 0, 0, pbn_b0_1_115200 }, 5771 { /* IQ Express D2 */ 5772 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5773 PCI_VENDOR_ID_MAINPINE, 0x3200, 5774 0, 0, pbn_b0_2_115200 }, 5775 { /* IQ Express F2 */ 5776 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5777 PCI_VENDOR_ID_MAINPINE, 0x3300, 5778 0, 0, pbn_b0_2_115200 }, 5779 { /* IQ Express D4 */ 5780 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5781 PCI_VENDOR_ID_MAINPINE, 0x3400, 5782 0, 0, pbn_b0_4_115200 }, 5783 { /* IQ Express F4 */ 5784 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5785 PCI_VENDOR_ID_MAINPINE, 0x3500, 5786 0, 0, pbn_b0_4_115200 }, 5787 { /* IQ Express D8 */ 5788 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5789 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5790 0, 0, pbn_b0_8_115200 }, 5791 { /* IQ Express F8 */ 5792 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5793 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5794 0, 0, pbn_b0_8_115200 }, 5795 5796 5797 /* 5798 * PA Semi PA6T-1682M on-chip UART 5799 */ 5800 { PCI_VENDOR_ID_PASEMI, 0xa004, 5801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5802 pbn_pasemi_1682M }, 5803 5804 /* 5805 * National Instruments 5806 */ 5807 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5808 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5809 pbn_b1_16_115200 }, 5810 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5812 pbn_b1_8_115200 }, 5813 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5814 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5815 pbn_b1_bt_4_115200 }, 5816 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5818 pbn_b1_bt_2_115200 }, 5819 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5820 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5821 pbn_b1_bt_4_115200 }, 5822 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5824 pbn_b1_bt_2_115200 }, 5825 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5826 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5827 pbn_b1_16_115200 }, 5828 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5830 pbn_b1_8_115200 }, 5831 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5832 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5833 pbn_b1_bt_4_115200 }, 5834 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5836 pbn_b1_bt_2_115200 }, 5837 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5838 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5839 pbn_b1_bt_4_115200 }, 5840 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5842 pbn_b1_bt_2_115200 }, 5843 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5844 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5845 pbn_ni8430_2 }, 5846 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5848 pbn_ni8430_2 }, 5849 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5851 pbn_ni8430_4 }, 5852 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5853 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5854 pbn_ni8430_4 }, 5855 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5857 pbn_ni8430_8 }, 5858 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5859 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5860 pbn_ni8430_8 }, 5861 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5862 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5863 pbn_ni8430_16 }, 5864 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5865 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5866 pbn_ni8430_16 }, 5867 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5868 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5869 pbn_ni8430_2 }, 5870 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5871 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5872 pbn_ni8430_2 }, 5873 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5874 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5875 pbn_ni8430_4 }, 5876 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5877 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5878 pbn_ni8430_4 }, 5879 5880 /* 5881 * MOXA 5882 */ 5883 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 }, 5884 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 }, 5885 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 }, 5886 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 }, 5887 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 }, 5888 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 }, 5889 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 }, 5890 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 }, 5891 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 }, 5892 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 }, 5893 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 }, 5894 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 }, 5895 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 }, 5896 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 }, 5897 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 }, 5898 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 }, 5899 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 }, 5900 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 }, 5901 5902 /* 5903 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5904 */ 5905 { PCI_VENDOR_ID_ADDIDATA, 5906 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5907 PCI_ANY_ID, 5908 PCI_ANY_ID, 5909 0, 5910 0, 5911 pbn_b0_4_115200 }, 5912 5913 { PCI_VENDOR_ID_ADDIDATA, 5914 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5915 PCI_ANY_ID, 5916 PCI_ANY_ID, 5917 0, 5918 0, 5919 pbn_b0_2_115200 }, 5920 5921 { PCI_VENDOR_ID_ADDIDATA, 5922 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5923 PCI_ANY_ID, 5924 PCI_ANY_ID, 5925 0, 5926 0, 5927 pbn_b0_1_115200 }, 5928 5929 { PCI_VENDOR_ID_AMCC, 5930 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5931 PCI_ANY_ID, 5932 PCI_ANY_ID, 5933 0, 5934 0, 5935 pbn_b1_8_115200 }, 5936 5937 { PCI_VENDOR_ID_ADDIDATA, 5938 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5939 PCI_ANY_ID, 5940 PCI_ANY_ID, 5941 0, 5942 0, 5943 pbn_b0_4_115200 }, 5944 5945 { PCI_VENDOR_ID_ADDIDATA, 5946 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5947 PCI_ANY_ID, 5948 PCI_ANY_ID, 5949 0, 5950 0, 5951 pbn_b0_2_115200 }, 5952 5953 { PCI_VENDOR_ID_ADDIDATA, 5954 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5955 PCI_ANY_ID, 5956 PCI_ANY_ID, 5957 0, 5958 0, 5959 pbn_b0_1_115200 }, 5960 5961 { PCI_VENDOR_ID_ADDIDATA, 5962 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5963 PCI_ANY_ID, 5964 PCI_ANY_ID, 5965 0, 5966 0, 5967 pbn_b0_4_115200 }, 5968 5969 { PCI_VENDOR_ID_ADDIDATA, 5970 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5971 PCI_ANY_ID, 5972 PCI_ANY_ID, 5973 0, 5974 0, 5975 pbn_b0_2_115200 }, 5976 5977 { PCI_VENDOR_ID_ADDIDATA, 5978 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5979 PCI_ANY_ID, 5980 PCI_ANY_ID, 5981 0, 5982 0, 5983 pbn_b0_1_115200 }, 5984 5985 { PCI_VENDOR_ID_ADDIDATA, 5986 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5987 PCI_ANY_ID, 5988 PCI_ANY_ID, 5989 0, 5990 0, 5991 pbn_b0_8_115200 }, 5992 5993 { PCI_VENDOR_ID_ADDIDATA, 5994 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5995 PCI_ANY_ID, 5996 PCI_ANY_ID, 5997 0, 5998 0, 5999 pbn_ADDIDATA_PCIe_4_3906250 }, 6000 6001 { PCI_VENDOR_ID_ADDIDATA, 6002 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 6003 PCI_ANY_ID, 6004 PCI_ANY_ID, 6005 0, 6006 0, 6007 pbn_ADDIDATA_PCIe_2_3906250 }, 6008 6009 { PCI_VENDOR_ID_ADDIDATA, 6010 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 6011 PCI_ANY_ID, 6012 PCI_ANY_ID, 6013 0, 6014 0, 6015 pbn_ADDIDATA_PCIe_1_3906250 }, 6016 6017 { PCI_VENDOR_ID_ADDIDATA, 6018 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 6019 PCI_ANY_ID, 6020 PCI_ANY_ID, 6021 0, 6022 0, 6023 pbn_ADDIDATA_PCIe_8_3906250 }, 6024 6025 { PCI_VENDOR_ID_ADDIDATA, 6026 PCI_DEVICE_ID_ADDIDATA_CPCI7500, 6027 PCI_ANY_ID, 6028 PCI_ANY_ID, 6029 0, 6030 0, 6031 pbn_b0_4_115200 }, 6032 6033 { PCI_VENDOR_ID_ADDIDATA, 6034 PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG, 6035 PCI_ANY_ID, 6036 PCI_ANY_ID, 6037 0, 6038 0, 6039 pbn_b0_4_115200 }, 6040 6041 { PCI_VENDOR_ID_ADDIDATA, 6042 PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG, 6043 PCI_ANY_ID, 6044 PCI_ANY_ID, 6045 0, 6046 0, 6047 pbn_b0_2_115200 }, 6048 6049 { PCI_VENDOR_ID_ADDIDATA, 6050 PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG, 6051 PCI_ANY_ID, 6052 PCI_ANY_ID, 6053 0, 6054 0, 6055 pbn_b0_1_115200 }, 6056 6057 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 6058 PCI_VENDOR_ID_IBM, 0x0299, 6059 0, 0, pbn_b0_bt_2_115200 }, 6060 6061 /* 6062 * other NetMos 9835 devices are most likely handled by the 6063 * parport_serial driver, check drivers/parport/parport_serial.c 6064 * before adding them here. 6065 */ 6066 6067 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 6068 0xA000, 0x1000, 6069 0, 0, pbn_b0_1_115200 }, 6070 6071 /* the 9901 is a rebranded 9912 */ 6072 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 6073 0xA000, 0x1000, 6074 0, 0, pbn_b0_1_115200 }, 6075 6076 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 6077 0xA000, 0x1000, 6078 0, 0, pbn_b0_1_115200 }, 6079 6080 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 6081 0xA000, 0x1000, 6082 0, 0, pbn_b0_1_115200 }, 6083 6084 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 6085 0xA000, 0x1000, 6086 0, 0, pbn_b0_1_115200 }, 6087 6088 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 6089 0xA000, 0x3002, 6090 0, 0, pbn_NETMOS9900_2s_115200 }, 6091 6092 { PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100, 6093 0xA000, 0x1000, 6094 0, 0, pbn_b0_1_115200 }, 6095 6096 /* 6097 * Best Connectivity and Rosewill PCI Multi I/O cards 6098 */ 6099 6100 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 6101 0xA000, 0x1000, 6102 0, 0, pbn_b0_1_115200 }, 6103 6104 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 6105 0xA000, 0x3002, 6106 0, 0, pbn_b0_bt_2_115200 }, 6107 6108 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 6109 0xA000, 0x3004, 6110 0, 0, pbn_b0_bt_4_115200 }, 6111 6112 /* 6113 * ASIX AX99100 PCIe to Multi I/O Controller 6114 */ 6115 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100, 6116 0xA000, 0x1000, 6117 0, 0, pbn_b0_1_115200 }, 6118 6119 /* Intel CE4100 */ 6120 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 6121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6122 pbn_ce4100_1_115200 }, 6123 6124 /* 6125 * Cronyx Omega PCI 6126 */ 6127 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 6128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6129 pbn_omegapci }, 6130 6131 /* 6132 * Broadcom TruManage 6133 */ 6134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 6135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6136 pbn_brcm_trumanage }, 6137 6138 /* 6139 * AgeStar as-prs2-009 6140 */ 6141 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 6142 PCI_ANY_ID, PCI_ANY_ID, 6143 0, 0, pbn_b0_bt_2_115200 }, 6144 6145 /* 6146 * WCH CH353 series devices: The 2S1P is handled by parport_serial 6147 * so not listed here. 6148 */ 6149 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S, 6150 PCI_ANY_ID, PCI_ANY_ID, 6151 0, 0, pbn_b0_bt_4_115200 }, 6152 6153 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF, 6154 PCI_ANY_ID, PCI_ANY_ID, 6155 0, 0, pbn_b0_bt_2_115200 }, 6156 6157 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S, 6158 PCI_ANY_ID, PCI_ANY_ID, 6159 0, 0, pbn_b0_bt_4_115200 }, 6160 6161 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S, 6162 PCI_ANY_ID, PCI_ANY_ID, 6163 0, 0, pbn_wch382_2 }, 6164 6165 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S, 6166 PCI_ANY_ID, PCI_ANY_ID, 6167 0, 0, pbn_wch384_4 }, 6168 6169 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S, 6170 PCI_ANY_ID, PCI_ANY_ID, 6171 0, 0, pbn_wch384_8 }, 6172 /* 6173 * Realtek RealManage 6174 */ 6175 { PCI_VENDOR_ID_REALTEK, 0x816a, 6176 PCI_ANY_ID, PCI_ANY_ID, 6177 0, 0, pbn_b0_1_115200 }, 6178 6179 { PCI_VENDOR_ID_REALTEK, 0x816b, 6180 PCI_ANY_ID, PCI_ANY_ID, 6181 0, 0, pbn_b0_1_115200 }, 6182 6183 /* Fintek PCI serial cards */ 6184 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 6185 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 6186 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 6187 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 6188 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 6189 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 6190 6191 /* MKS Tenta SCOM-080x serial cards */ 6192 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 6193 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 6194 6195 /* Amazon PCI serial device */ 6196 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 6197 6198 /* 6199 * These entries match devices with class COMMUNICATION_SERIAL, 6200 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 6201 */ 6202 { PCI_ANY_ID, PCI_ANY_ID, 6203 PCI_ANY_ID, PCI_ANY_ID, 6204 PCI_CLASS_COMMUNICATION_SERIAL << 8, 6205 0xffff00, pbn_default }, 6206 { PCI_ANY_ID, PCI_ANY_ID, 6207 PCI_ANY_ID, PCI_ANY_ID, 6208 PCI_CLASS_COMMUNICATION_MODEM << 8, 6209 0xffff00, pbn_default }, 6210 { PCI_ANY_ID, PCI_ANY_ID, 6211 PCI_ANY_ID, PCI_ANY_ID, 6212 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 6213 0xffff00, pbn_default }, 6214 { 0, } 6215}; 6216 6217static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 6218 pci_channel_state_t state) 6219{ 6220 struct serial_private *priv = pci_get_drvdata(dev); 6221 6222 if (state == pci_channel_io_perm_failure) 6223 return PCI_ERS_RESULT_DISCONNECT; 6224 6225 if (priv) 6226 pciserial_detach_ports(priv); 6227 6228 pci_disable_device(dev); 6229 6230 return PCI_ERS_RESULT_NEED_RESET; 6231} 6232 6233static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 6234{ 6235 int rc; 6236 6237 rc = pci_enable_device(dev); 6238 6239 if (rc) 6240 return PCI_ERS_RESULT_DISCONNECT; 6241 6242 pci_restore_state(dev); 6243 6244 return PCI_ERS_RESULT_RECOVERED; 6245} 6246 6247static void serial8250_io_resume(struct pci_dev *dev) 6248{ 6249 struct serial_private *priv = pci_get_drvdata(dev); 6250 struct serial_private *new; 6251 6252 if (!priv) 6253 return; 6254 6255 new = pciserial_init_ports(dev, priv->board); 6256 if (!IS_ERR(new)) { 6257 pci_set_drvdata(dev, new); 6258 kfree(priv); 6259 } 6260} 6261 6262static const struct pci_error_handlers serial8250_err_handler = { 6263 .error_detected = serial8250_io_error_detected, 6264 .slot_reset = serial8250_io_slot_reset, 6265 .resume = serial8250_io_resume, 6266}; 6267 6268static struct pci_driver serial_pci_driver = { 6269 .name = "serial", 6270 .probe = pciserial_init_one, 6271 .remove = pciserial_remove_one, 6272 .driver = { 6273 .pm = &pciserial_pm_ops, 6274 }, 6275 .id_table = serial_pci_tbl, 6276 .err_handler = &serial8250_err_handler, 6277}; 6278 6279module_pci_driver(serial_pci_driver); 6280 6281MODULE_LICENSE("GPL"); 6282MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 6283MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 6284MODULE_IMPORT_NS("SERIAL_8250_PCI");
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