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8250_omap.c
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linux-6.19.14/drivers/tty/serial/8250/8250_omap.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11#include <linux/atomic.h> 12#include <linux/clk.h> 13#include <linux/device.h> 14#include <linux/io.h> 15#include <linux/module.h> 16#include <linux/serial_8250.h> 17#include <linux/serial_reg.h> 18#include <linux/tty_flip.h> 19#include <linux/platform_device.h> 20#include <linux/slab.h> 21#include <linux/of.h> 22#include <linux/of_irq.h> 23#include <linux/delay.h> 24#include <linux/pm_runtime.h> 25#include <linux/console.h> 26#include <linux/pm_qos.h> 27#include <linux/pm_wakeirq.h> 28#include <linux/dma-mapping.h> 29#include <linux/sys_soc.h> 30#include <linux/reboot.h> 31#include <linux/pinctrl/consumer.h> 32 33#include "8250.h" 34 35#define DEFAULT_CLK_SPEED 48000000 36#define OMAP_UART_REGSHIFT 2 37 38#define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 39#define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 40#define OMAP_DMA_TX_KICK (1 << 2) 41/* 42 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 43 * The same errata is applicable to AM335x and DRA7x processors too. 44 */ 45#define UART_ERRATA_CLOCK_DISABLE (1 << 3) 46#define UART_HAS_EFR2 BIT(4) 47#define UART_HAS_RHR_IT_DIS BIT(5) 48#define UART_RX_TIMEOUT_QUIRK BIT(6) 49#define UART_HAS_NATIVE_RS485 BIT(7) 50 51#define OMAP_UART_FCR_RX_TRIG 6 52#define OMAP_UART_FCR_TX_TRIG 4 53 54/* SCR register bitmasks */ 55#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 56#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 57#define OMAP_UART_SCR_TX_EMPTY (1 << 3) 58#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 59#define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 60#define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 61 62/* MVR register bitmasks */ 63#define OMAP_UART_MVR_SCHEME_SHIFT 30 64#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 65#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 66#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 67#define OMAP_UART_MVR_MAJ_MASK 0x700 68#define OMAP_UART_MVR_MAJ_SHIFT 8 69#define OMAP_UART_MVR_MIN_MASK 0x3f 70 71/* SYSC register bitmasks */ 72#define OMAP_UART_SYSC_SOFTRESET (1 << 1) 73 74/* SYSS register bitmasks */ 75#define OMAP_UART_SYSS_RESETDONE (1 << 0) 76 77#define UART_TI752_TLR_TX 0 78#define UART_TI752_TLR_RX 4 79 80#define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 81#define TRIGGER_FCR_MASK(x) (x & 3) 82 83/* Enable XON/XOFF flow control on output */ 84#define OMAP_UART_SW_TX 0x08 85/* Enable XON/XOFF flow control on input */ 86#define OMAP_UART_SW_RX 0x02 87 88#define OMAP_UART_WER_MOD_WKUP 0x7f 89#define OMAP_UART_TX_WAKEUP_EN (1 << 7) 90 91#define TX_TRIGGER 1 92#define RX_TRIGGER 48 93 94#define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 95#define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 96 97#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 98 99#define OMAP_UART_REV_46 0x0406 100#define OMAP_UART_REV_52 0x0502 101#define OMAP_UART_REV_63 0x0603 102 103/* Resume register */ 104#define UART_OMAP_RESUME 0x0B 105 106/* Interrupt Enable Register 2 */ 107#define UART_OMAP_IER2 0x1B 108#define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 109 110/* Mode Definition Register 3 */ 111#define UART_OMAP_MDR3 0x20 112#define UART_OMAP_MDR3_DIR_POL BIT(3) 113#define UART_OMAP_MDR3_DIR_EN BIT(4) 114 115/* Enhanced features register 2 */ 116#define UART_OMAP_EFR2 0x23 117#define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 118 119/* RX FIFO occupancy indicator */ 120#define UART_OMAP_RX_LVL 0x19 121 122/* Timeout low and High */ 123#define UART_OMAP_TO_L 0x26 124#define UART_OMAP_TO_H 0x27 125struct omap8250_priv { 126 void __iomem *membase; 127 int line; 128 u8 habit; 129 u8 mdr1; 130 u8 mdr3; 131 u8 efr; 132 u8 scr; 133 u8 wer; 134 u8 xon; 135 u8 xoff; 136 u8 delayed_restore; 137 u16 quot; 138 139 u8 tx_trigger; 140 u8 rx_trigger; 141 atomic_t active; 142 bool is_suspending; 143 int wakeirq; 144 u32 latency; 145 u32 calc_latency; 146 struct pm_qos_request pm_qos_request; 147 struct work_struct qos_work; 148 struct uart_8250_dma omap8250_dma; 149 spinlock_t rx_dma_lock; 150 bool rx_dma_broken; 151 bool throttled; 152 153 struct pinctrl *pinctrl; 154 struct pinctrl_state *pinctrl_wakeup; 155}; 156 157struct omap8250_dma_params { 158 u32 rx_size; 159 u8 rx_trigger; 160 u8 tx_trigger; 161}; 162 163struct omap8250_platdata { 164 struct omap8250_dma_params *dma_params; 165 u8 habit; 166}; 167 168#ifdef CONFIG_SERIAL_8250_DMA 169static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 170#else 171static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 172#endif 173 174static u32 uart_read(struct omap8250_priv *priv, u32 reg) 175{ 176 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 177} 178 179/* 180 * Called on runtime PM resume path from omap8250_restore_regs(), and 181 * omap8250_set_mctrl(). 182 */ 183static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 184{ 185 struct uart_8250_port *up = up_to_u8250p(port); 186 struct omap8250_priv *priv = port->private_data; 187 u8 lcr; 188 189 serial8250_do_set_mctrl(port, mctrl); 190 191 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 192 /* 193 * Turn off autoRTS if RTS is lowered and restore autoRTS 194 * setting if RTS is raised 195 */ 196 lcr = serial_in(up, UART_LCR); 197 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 198 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 199 priv->efr |= UART_EFR_RTS; 200 else 201 priv->efr &= ~UART_EFR_RTS; 202 serial_out(up, UART_EFR, priv->efr); 203 serial_out(up, UART_LCR, lcr); 204 } 205} 206 207static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 208{ 209 int err; 210 211 err = pm_runtime_resume_and_get(port->dev); 212 if (err) 213 return; 214 215 __omap8250_set_mctrl(port, mctrl); 216 217 pm_runtime_mark_last_busy(port->dev); 218 pm_runtime_put_autosuspend(port->dev); 219} 220 221/* 222 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 223 * The access to uart register after MDR1 Access 224 * causes UART to corrupt data. 225 * 226 * Need a delay = 227 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 228 * give 10 times as much 229 */ 230static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 231 struct omap8250_priv *priv) 232{ 233 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 234 udelay(2); 235 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 236 UART_FCR_CLEAR_RCVR); 237} 238 239static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 240 struct omap8250_priv *priv) 241{ 242 unsigned int uartclk = port->uartclk; 243 unsigned int div_13, div_16; 244 unsigned int abs_d13, abs_d16; 245 246 /* 247 * Old custom speed handling. 248 */ 249 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 250 priv->quot = port->custom_divisor & UART_DIV_MAX; 251 /* 252 * I assume that nobody is using this. But hey, if somebody 253 * would like to specify the divisor _and_ the mode then the 254 * driver is ready and waiting for it. 255 */ 256 if (port->custom_divisor & (1 << 16)) 257 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 258 else 259 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 260 return; 261 } 262 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 263 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 264 265 if (!div_13) 266 div_13 = 1; 267 if (!div_16) 268 div_16 = 1; 269 270 abs_d13 = abs(baud - uartclk / 13 / div_13); 271 abs_d16 = abs(baud - uartclk / 16 / div_16); 272 273 if (abs_d13 >= abs_d16) { 274 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 275 priv->quot = div_16; 276 } else { 277 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 278 priv->quot = div_13; 279 } 280} 281 282static void omap8250_update_scr(struct uart_8250_port *up, 283 struct omap8250_priv *priv) 284{ 285 u8 old_scr; 286 287 old_scr = serial_in(up, UART_OMAP_SCR); 288 if (old_scr == priv->scr) 289 return; 290 291 /* 292 * The manual recommends not to enable the DMA mode selector in the SCR 293 * (instead of the FCR) register _and_ selecting the DMA mode as one 294 * register write because this may lead to malfunction. 295 */ 296 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 297 serial_out(up, UART_OMAP_SCR, 298 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 299 serial_out(up, UART_OMAP_SCR, priv->scr); 300} 301 302static void omap8250_update_mdr1(struct uart_8250_port *up, 303 struct omap8250_priv *priv) 304{ 305 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 306 omap_8250_mdr1_errataset(up, priv); 307 else 308 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 309} 310 311static void omap8250_restore_regs(struct uart_8250_port *up) 312{ 313 struct uart_port *port = &up->port; 314 struct omap8250_priv *priv = port->private_data; 315 struct uart_8250_dma *dma = up->dma; 316 u8 mcr = serial8250_in_MCR(up); 317 318 /* Port locked to synchronize UART_IER access against the console. */ 319 lockdep_assert_held_once(&port->lock); 320 321 if (dma && dma->tx_running) { 322 /* 323 * TCSANOW requests the change to occur immediately however if 324 * we have a TX-DMA operation in progress then it has been 325 * observed that it might stall and never complete. Therefore we 326 * delay DMA completes to prevent this hang from happen. 327 */ 328 priv->delayed_restore = 1; 329 return; 330 } 331 332 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 333 serial_out(up, UART_EFR, UART_EFR_ECB); 334 335 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 336 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 337 serial_out(up, UART_FCR, up->fcr); 338 339 omap8250_update_scr(up, priv); 340 341 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 342 343 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 344 OMAP_UART_TCR_HALT(52)); 345 serial_out(up, UART_TI752_TLR, 346 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 347 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 348 349 serial_out(up, UART_LCR, 0); 350 351 /* drop TCR + TLR access, we setup XON/XOFF later */ 352 serial8250_out_MCR(up, mcr); 353 354 serial_out(up, UART_IER, up->ier); 355 356 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 357 serial_dl_write(up, priv->quot); 358 359 serial_out(up, UART_EFR, priv->efr); 360 361 /* Configure flow control */ 362 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 363 serial_out(up, UART_XON1, priv->xon); 364 serial_out(up, UART_XOFF1, priv->xoff); 365 366 serial_out(up, UART_LCR, up->lcr); 367 368 omap8250_update_mdr1(up, priv); 369 370 __omap8250_set_mctrl(port, port->mctrl); 371 372 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 373 374 if (port->rs485.flags & SER_RS485_ENABLED && 375 port->rs485_config == serial8250_em485_config) 376 serial8250_em485_stop_tx(up, true); 377} 378 379static void omap_8250_set_termios_atomic(struct uart_port *port, struct ktermios *termios, 380 const struct ktermios *old, unsigned int baud) 381{ 382 struct uart_8250_port *up = up_to_u8250p(port); 383 struct omap8250_priv *priv = port->private_data; 384 u8 cval; 385 386 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 387 388 if (termios->c_cflag & CSTOPB) 389 cval |= UART_LCR_STOP; 390 if (termios->c_cflag & PARENB) 391 cval |= UART_LCR_PARITY; 392 if (!(termios->c_cflag & PARODD)) 393 cval |= UART_LCR_EPAR; 394 if (termios->c_cflag & CMSPAR) 395 cval |= UART_LCR_SPAR; 396 397 omap_8250_get_divisor(port, baud, priv); 398 399 /* 400 * Ok, we're now changing the port state. Do it with 401 * interrupts disabled. 402 */ 403 guard(serial8250_rpm)(up); 404 guard(uart_port_lock_irq)(port); 405 406 /* 407 * Update the per-port timeout. 408 */ 409 uart_update_timeout(port, termios->c_cflag, baud); 410 411 /* 412 * Specify which conditions may be considered for error 413 * handling and the ignoring of characters. The actual 414 * ignoring of characters only occurs if the bit is set 415 * in @ignore_status_mask as well. 416 */ 417 port->read_status_mask = UART_LSR_OE | UART_LSR_DR; 418 if (termios->c_iflag & INPCK) 419 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 420 if (termios->c_iflag & (IGNBRK | PARMRK)) 421 port->read_status_mask |= UART_LSR_BI; 422 423 /* 424 * Characters to ignore 425 */ 426 port->ignore_status_mask = 0; 427 if (termios->c_iflag & IGNPAR) 428 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 429 if (termios->c_iflag & IGNBRK) { 430 port->ignore_status_mask |= UART_LSR_BI; 431 /* 432 * If we're ignoring parity and break indicators, 433 * ignore overruns too (for real raw support). 434 */ 435 if (termios->c_iflag & IGNPAR) 436 port->ignore_status_mask |= UART_LSR_OE; 437 } 438 439 /* 440 * ignore all characters if CREAD is not set 441 */ 442 if ((termios->c_cflag & CREAD) == 0) 443 port->ignore_status_mask |= UART_LSR_DR; 444 445 /* 446 * Modem status interrupts 447 */ 448 up->ier &= ~UART_IER_MSI; 449 if (UART_ENABLE_MS(port, termios->c_cflag)) 450 up->ier |= UART_IER_MSI; 451 452 up->lcr = cval; 453 /* Up to here it was mostly serial8250_do_set_termios() */ 454 455 /* 456 * We enable TRIG_GRANU for RX and TX and additionally we set 457 * SCR_TX_EMPTY bit. The result is the following: 458 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 459 * - less than RX_TRIGGER number of bytes will also cause an interrupt 460 * once the UART decides that there no new bytes arriving. 461 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 462 * empty - the trigger level is ignored here. 463 * 464 * Once DMA is enabled: 465 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 466 * bytes in the TX FIFO. On each assert the DMA engine will move 467 * TX_TRIGGER bytes into the FIFO. 468 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 469 * the FIFO and move RX_TRIGGER bytes. 470 * This is because threshold and trigger values are the same. 471 */ 472 up->fcr = UART_FCR_ENABLE_FIFO; 473 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 474 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 475 476 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 477 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 478 479 if (up->dma) 480 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 481 OMAP_UART_SCR_DMAMODE_CTL; 482 483 priv->xon = termios->c_cc[VSTART]; 484 priv->xoff = termios->c_cc[VSTOP]; 485 486 priv->efr = 0; 487 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 488 489 if (termios->c_cflag & CRTSCTS && port->flags & UPF_HARD_FLOW && 490 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 491 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 492 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 493 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 494 priv->efr |= UART_EFR_CTS; 495 } else if (port->flags & UPF_SOFT_FLOW) { 496 /* 497 * OMAP rx s/w flow control is borked; the transmitter remains 498 * stuck off even if rx flow control is subsequently disabled 499 */ 500 501 /* 502 * IXOFF Flag: 503 * Enable XON/XOFF flow control on output. 504 * Transmit XON1, XOFF1 505 */ 506 if (termios->c_iflag & IXOFF) { 507 port->status |= UPSTAT_AUTOXOFF; 508 priv->efr |= OMAP_UART_SW_TX; 509 } 510 } 511 omap8250_restore_regs(up); 512} 513 514/* 515 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 516 * some differences in how we want to handle flow control. 517 */ 518static void omap_8250_set_termios(struct uart_port *port, 519 struct ktermios *termios, 520 const struct ktermios *old) 521{ 522 struct omap8250_priv *priv = port->private_data; 523 unsigned int baud; 524 525 /* 526 * Ask the core to calculate the divisor for us. 527 */ 528 baud = uart_get_baud_rate(port, termios, old, 529 port->uartclk / 16 / UART_DIV_MAX, 530 port->uartclk / 13); 531 532 omap_8250_set_termios_atomic(port, termios, old, baud); 533 534 /* calculate wakeup latency constraint */ 535 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 536 priv->latency = priv->calc_latency; 537 538 schedule_work(&priv->qos_work); 539 540 /* Don't rewrite B0 */ 541 if (tty_termios_baud_rate(termios)) 542 tty_termios_encode_baud_rate(termios, baud, baud); 543} 544 545/* same as 8250 except that we may have extra flow bits set in EFR */ 546static void omap_8250_pm(struct uart_port *port, unsigned int state, 547 unsigned int oldstate) 548{ 549 struct uart_8250_port *up = up_to_u8250p(port); 550 u8 efr; 551 552 guard(serial8250_rpm)(up); 553 /* Synchronize UART_IER access against the console. */ 554 guard(uart_port_lock_irq)(port); 555 556 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 557 efr = serial_in(up, UART_EFR); 558 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 559 serial_out(up, UART_LCR, 0); 560 561 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 562 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 563 serial_out(up, UART_EFR, efr); 564 serial_out(up, UART_LCR, 0); 565} 566 567static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 568 struct omap8250_priv *priv) 569{ 570 static const struct soc_device_attribute k3_soc_devices[] = { 571 { .family = "AM65X", }, 572 { .family = "J721E", .revision = "SR1.0" }, 573 { /* sentinel */ } 574 }; 575 u32 mvr, scheme; 576 u16 revision, major, minor; 577 578 mvr = uart_read(priv, UART_OMAP_MVER); 579 580 /* Check revision register scheme */ 581 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 582 583 switch (scheme) { 584 case 0: /* Legacy Scheme: OMAP2/3 */ 585 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 586 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 587 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 588 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 589 break; 590 case 1: 591 /* New Scheme: OMAP4+ */ 592 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 593 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 594 OMAP_UART_MVR_MAJ_SHIFT; 595 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 596 break; 597 default: 598 dev_warn(up->port.dev, 599 "Unknown revision, defaulting to highest\n"); 600 /* highest possible revision */ 601 major = 0xff; 602 minor = 0xff; 603 } 604 /* normalize revision for the driver */ 605 revision = UART_BUILD_REVISION(major, minor); 606 607 switch (revision) { 608 case OMAP_UART_REV_46: 609 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 610 break; 611 case OMAP_UART_REV_52: 612 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 613 OMAP_UART_WER_HAS_TX_WAKEUP; 614 break; 615 case OMAP_UART_REV_63: 616 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 617 OMAP_UART_WER_HAS_TX_WAKEUP; 618 break; 619 default: 620 break; 621 } 622 623 /* 624 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 625 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 626 * to enable errata workaround. 627 */ 628 if (soc_device_match(k3_soc_devices)) 629 priv->habit &= ~UART_HAS_RHR_IT_DIS; 630} 631 632static void omap8250_uart_qos_work(struct work_struct *work) 633{ 634 struct omap8250_priv *priv; 635 636 priv = container_of(work, struct omap8250_priv, qos_work); 637 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 638} 639 640#ifdef CONFIG_SERIAL_8250_DMA 641static int omap_8250_dma_handle_irq(struct uart_port *port); 642#endif 643 644static irqreturn_t omap8250_irq(int irq, void *dev_id) 645{ 646 struct omap8250_priv *priv = dev_id; 647 struct uart_8250_port *up = serial8250_get_port(priv->line); 648 struct uart_port *port = &up->port; 649 unsigned int iir, lsr; 650 int ret; 651 652 pm_runtime_get_noresume(port->dev); 653 654 /* Shallow idle state wake-up to an IO interrupt? */ 655 if (atomic_add_unless(&priv->active, 1, 1)) { 656 priv->latency = priv->calc_latency; 657 schedule_work(&priv->qos_work); 658 } 659 660#ifdef CONFIG_SERIAL_8250_DMA 661 if (up->dma) { 662 ret = omap_8250_dma_handle_irq(port); 663 pm_runtime_mark_last_busy(port->dev); 664 pm_runtime_put(port->dev); 665 return IRQ_RETVAL(ret); 666 } 667#endif 668 669 lsr = serial_port_in(port, UART_LSR); 670 iir = serial_port_in(port, UART_IIR); 671 ret = serial8250_handle_irq(port, iir); 672 673 /* 674 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 675 * FIFO has been drained or erroneously. 676 * So apply solution of Errata i2310 as mentioned in 677 * https://www.ti.com/lit/pdf/sprz536 678 */ 679 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 680 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 681 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 682 unsigned char efr2, timeout_h, timeout_l; 683 684 efr2 = serial_in(up, UART_OMAP_EFR2); 685 timeout_h = serial_in(up, UART_OMAP_TO_H); 686 timeout_l = serial_in(up, UART_OMAP_TO_L); 687 serial_out(up, UART_OMAP_TO_H, 0xFF); 688 serial_out(up, UART_OMAP_TO_L, 0xFF); 689 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 690 serial_in(up, UART_IIR); 691 serial_out(up, UART_OMAP_EFR2, efr2); 692 serial_out(up, UART_OMAP_TO_H, timeout_h); 693 serial_out(up, UART_OMAP_TO_L, timeout_l); 694 } 695 696 /* Stop processing interrupts on input overrun */ 697 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 698 unsigned long delay; 699 700 /* Synchronize UART_IER access against the console. */ 701 uart_port_lock(port); 702 up->ier = serial_port_in(port, UART_IER); 703 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 704 port->ops->stop_rx(port); 705 } else { 706 /* Keep restarting the timer until 707 * the input overrun subsides. 708 */ 709 cancel_delayed_work(&up->overrun_backoff); 710 } 711 uart_port_unlock(port); 712 713 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 714 schedule_delayed_work(&up->overrun_backoff, delay); 715 } 716 717 pm_runtime_mark_last_busy(port->dev); 718 pm_runtime_put(port->dev); 719 720 return IRQ_RETVAL(ret); 721} 722 723static int omap_8250_startup(struct uart_port *port) 724{ 725 struct uart_8250_port *up = up_to_u8250p(port); 726 struct omap8250_priv *priv = port->private_data; 727 struct uart_8250_dma *dma = &priv->omap8250_dma; 728 int ret; 729 730 if (priv->wakeirq) { 731 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 732 if (ret) 733 return ret; 734 } 735 736#ifdef CONFIG_PM 737 up->capabilities |= UART_CAP_RPM; 738#endif 739 740 guard(serial8250_rpm)(up); 741 742 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 743 744 serial_out(up, UART_LCR, UART_LCR_WLEN8); 745 746 up->lsr_saved_flags = 0; 747 up->msr_saved_flags = 0; 748 749 /* Disable DMA for console UART */ 750 if (dma->fn && !uart_console(port)) { 751 up->dma = &priv->omap8250_dma; 752 ret = serial8250_request_dma(up); 753 if (ret) { 754 dev_warn_ratelimited(port->dev, 755 "failed to request DMA\n"); 756 up->dma = NULL; 757 } 758 } else { 759 up->dma = NULL; 760 } 761 762 /* Synchronize UART_IER access against the console. */ 763 scoped_guard(uart_port_lock_irq, port) { 764 up->ier = UART_IER_RLSI | UART_IER_RDI; 765 serial_out(up, UART_IER, up->ier); 766 } 767 768 /* Enable module level wake up */ 769 priv->wer = OMAP_UART_WER_MOD_WKUP; 770 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 771 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 772 serial_out(up, UART_OMAP_WER, priv->wer); 773 774 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 775 guard(uart_port_lock_irq)(port); 776 up->dma->rx_dma(up); 777 } 778 779 enable_irq(port->irq); 780 781 return 0; 782} 783 784static void omap_8250_shutdown(struct uart_port *port) 785{ 786 struct uart_8250_port *up = up_to_u8250p(port); 787 struct omap8250_priv *priv = port->private_data; 788 789 guard(serial8250_rpm)(up); 790 791 flush_work(&priv->qos_work); 792 if (up->dma) 793 omap_8250_rx_dma_flush(up); 794 795 serial_out(up, UART_OMAP_WER, 0); 796 if (priv->habit & UART_HAS_EFR2) 797 serial_out(up, UART_OMAP_EFR2, 0x0); 798 799 /* Synchronize UART_IER access against the console. */ 800 scoped_guard(uart_port_lock_irq, port) { 801 up->ier = 0; 802 serial_out(up, UART_IER, 0); 803 } 804 805 disable_irq_nosync(port->irq); 806 dev_pm_clear_wake_irq(port->dev); 807 808 serial8250_release_dma(up); 809 up->dma = NULL; 810 811 /* 812 * Disable break condition and FIFOs 813 */ 814 if (up->lcr & UART_LCR_SBC) 815 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 816 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 817} 818 819static void omap_8250_throttle(struct uart_port *port) 820{ 821 struct omap8250_priv *priv = port->private_data; 822 823 guard(serial8250_rpm)(up_to_u8250p(port)); 824 guard(uart_port_lock_irqsave)(port); 825 826 port->ops->stop_rx(port); 827 priv->throttled = true; 828} 829 830static void omap_8250_unthrottle(struct uart_port *port) 831{ 832 struct omap8250_priv *priv = port->private_data; 833 struct uart_8250_port *up = up_to_u8250p(port); 834 835 guard(serial8250_rpm)(up); 836 /* Synchronize UART_IER access against the console. */ 837 guard(uart_port_lock_irqsave)(port); 838 839 priv->throttled = false; 840 if (up->dma) 841 up->dma->rx_dma(up); 842 up->ier |= UART_IER_RLSI | UART_IER_RDI; 843 serial_out(up, UART_IER, up->ier); 844} 845 846static int omap8250_rs485_config(struct uart_port *port, 847 struct ktermios *termios, 848 struct serial_rs485 *rs485) 849{ 850 struct omap8250_priv *priv = port->private_data; 851 struct uart_8250_port *up = up_to_u8250p(port); 852 u32 fixed_delay_rts_before_send = 0; 853 u32 fixed_delay_rts_after_send = 0; 854 unsigned int baud; 855 856 /* 857 * There is a fixed delay of 3 bit clock cycles after the TX shift 858 * register is going empty to allow time for the stop bit to transition 859 * through the transceiver before direction is changed to receive. 860 * 861 * Additionally there appears to be a 1 bit clock delay between writing 862 * to the THR register and transmission of the start bit, per page 8783 863 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 864 */ 865 if (priv->quot) { 866 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 867 baud = port->uartclk / (16 * priv->quot); 868 else 869 baud = port->uartclk / (13 * priv->quot); 870 871 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 872 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 873 } 874 875 /* 876 * Fall back to RS485 software emulation if the UART is missing 877 * hardware support, if the device tree specifies an mctrl_gpio 878 * (indicates that RTS is unavailable due to a pinmux conflict) 879 * or if the requested delays exceed the fixed hardware delays. 880 */ 881 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 882 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 883 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 884 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 885 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 886 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 887 888 port->rs485_config = serial8250_em485_config; 889 return serial8250_em485_config(port, termios, rs485); 890 } 891 892 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 893 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 894 895 if (rs485->flags & SER_RS485_ENABLED) 896 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 897 else 898 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 899 900 /* 901 * Retain same polarity semantics as RS485 software emulation, 902 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 903 */ 904 if (rs485->flags & SER_RS485_RTS_ON_SEND) 905 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 906 else 907 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 908 909 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 910 911 return 0; 912} 913 914#ifdef CONFIG_SERIAL_8250_DMA 915static int omap_8250_rx_dma(struct uart_8250_port *p); 916 917/* Must be called while priv->rx_dma_lock is held */ 918static void __dma_rx_do_complete(struct uart_8250_port *p) 919{ 920 struct uart_8250_dma *dma = p->dma; 921 struct tty_port *tty_port = &p->port.state->port; 922 struct omap8250_priv *priv = p->port.private_data; 923 struct dma_chan *rxchan = dma->rxchan; 924 dma_cookie_t cookie; 925 struct dma_tx_state state; 926 int count; 927 int ret; 928 u32 reg; 929 930 if (!dma->rx_running) 931 goto out; 932 933 cookie = dma->rx_cookie; 934 935 /* Re-enable RX FIFO interrupt now that transfer is complete */ 936 if (priv->habit & UART_HAS_RHR_IT_DIS) { 937 reg = serial_in(p, UART_OMAP_IER2); 938 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 939 serial_out(p, UART_OMAP_IER2, reg); 940 } 941 942 dmaengine_tx_status(rxchan, cookie, &state); 943 944 count = dma->rx_size - state.residue + state.in_flight_bytes; 945 if (count < dma->rx_size) { 946 dmaengine_terminate_async(rxchan); 947 948 /* 949 * Poll for teardown to complete which guarantees in 950 * flight data is drained. 951 */ 952 if (state.in_flight_bytes) { 953 int poll_count = 25; 954 955 while (dmaengine_tx_status(rxchan, cookie, NULL) && 956 poll_count--) 957 cpu_relax(); 958 959 if (poll_count == -1) 960 dev_err(p->port.dev, "teardown incomplete\n"); 961 } 962 } 963 if (!count) 964 goto out; 965 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 966 967 dma->rx_running = 0; 968 p->port.icount.rx += ret; 969 p->port.icount.buf_overrun += count - ret; 970out: 971 972 tty_flip_buffer_push(tty_port); 973} 974 975static void __dma_rx_complete(void *param) 976{ 977 struct uart_8250_port *p = param; 978 struct omap8250_priv *priv = p->port.private_data; 979 struct uart_8250_dma *dma = p->dma; 980 struct dma_tx_state state; 981 982 /* Synchronize UART_IER access against the console. */ 983 guard(uart_port_lock_irqsave)(&p->port); 984 985 /* 986 * If the tx status is not DMA_COMPLETE, then this is a delayed 987 * completion callback. A previous RX timeout flush would have 988 * already pushed the data, so exit. 989 */ 990 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != DMA_COMPLETE) 991 return; 992 993 __dma_rx_do_complete(p); 994 if (priv->throttled) 995 return; 996 997 p->ier |= UART_IER_RLSI | UART_IER_RDI; 998 serial_out(p, UART_IER, p->ier); 999 if (!(priv->habit & UART_HAS_EFR2)) 1000 omap_8250_rx_dma(p); 1001} 1002 1003static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 1004{ 1005 struct omap8250_priv *priv = p->port.private_data; 1006 struct uart_8250_dma *dma = p->dma; 1007 struct dma_tx_state state; 1008 unsigned long flags; 1009 int ret; 1010 1011 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1012 1013 if (!dma->rx_running) { 1014 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1015 return; 1016 } 1017 1018 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1019 if (ret == DMA_IN_PROGRESS) { 1020 ret = dmaengine_pause(dma->rxchan); 1021 if (WARN_ON_ONCE(ret)) 1022 priv->rx_dma_broken = true; 1023 } 1024 __dma_rx_do_complete(p); 1025 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1026} 1027 1028static int omap_8250_rx_dma(struct uart_8250_port *p) 1029{ 1030 struct omap8250_priv *priv = p->port.private_data; 1031 struct uart_8250_dma *dma = p->dma; 1032 int err = 0; 1033 struct dma_async_tx_descriptor *desc; 1034 unsigned long flags; 1035 u32 reg; 1036 1037 /* Port locked to synchronize UART_IER access against the console. */ 1038 lockdep_assert_held_once(&p->port.lock); 1039 1040 if (priv->rx_dma_broken) 1041 return -EINVAL; 1042 1043 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1044 1045 if (dma->rx_running) { 1046 enum dma_status state; 1047 1048 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1049 if (state == DMA_COMPLETE) { 1050 /* 1051 * Disable RX interrupts to allow RX DMA completion 1052 * callback to run. 1053 */ 1054 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1055 serial_out(p, UART_IER, p->ier); 1056 } 1057 goto out; 1058 } 1059 1060 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1061 dma->rx_size, DMA_DEV_TO_MEM, 1062 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1063 if (!desc) { 1064 err = -EBUSY; 1065 goto out; 1066 } 1067 1068 dma->rx_running = 1; 1069 desc->callback = __dma_rx_complete; 1070 desc->callback_param = p; 1071 1072 dma->rx_cookie = dmaengine_submit(desc); 1073 1074 /* 1075 * Disable RX FIFO interrupt while RX DMA is enabled, else 1076 * spurious interrupt may be raised when data is in the RX FIFO 1077 * but is yet to be drained by DMA. 1078 */ 1079 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1080 reg = serial_in(p, UART_OMAP_IER2); 1081 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1082 serial_out(p, UART_OMAP_IER2, reg); 1083 } 1084 1085 dma_async_issue_pending(dma->rxchan); 1086out: 1087 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1088 return err; 1089} 1090 1091static int omap_8250_tx_dma(struct uart_8250_port *p); 1092 1093static void omap_8250_dma_tx_complete(void *param) 1094{ 1095 struct uart_8250_port *p = param; 1096 struct uart_8250_dma *dma = p->dma; 1097 struct tty_port *tport = &p->port.state->port; 1098 bool en_thri = false; 1099 struct omap8250_priv *priv = p->port.private_data; 1100 1101 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1102 UART_XMIT_SIZE, DMA_TO_DEVICE); 1103 1104 guard(uart_port_lock_irqsave)(&p->port); 1105 1106 dma->tx_running = 0; 1107 1108 uart_xmit_advance(&p->port, dma->tx_size); 1109 1110 if (priv->delayed_restore) { 1111 priv->delayed_restore = 0; 1112 omap8250_restore_regs(p); 1113 } 1114 1115 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) 1116 uart_write_wakeup(&p->port); 1117 1118 if (!kfifo_is_empty(&tport->xmit_fifo) && !uart_tx_stopped(&p->port)) { 1119 int ret; 1120 1121 ret = omap_8250_tx_dma(p); 1122 if (ret) 1123 en_thri = true; 1124 } else if (p->capabilities & UART_CAP_RPM) { 1125 en_thri = true; 1126 } 1127 1128 if (en_thri) { 1129 dma->tx_err = 1; 1130 serial8250_set_THRI(p); 1131 } 1132} 1133 1134static int omap_8250_tx_dma(struct uart_8250_port *p) 1135{ 1136 struct uart_8250_dma *dma = p->dma; 1137 struct omap8250_priv *priv = p->port.private_data; 1138 struct tty_port *tport = &p->port.state->port; 1139 struct dma_async_tx_descriptor *desc; 1140 struct scatterlist sg; 1141 int skip_byte = -1; 1142 int ret; 1143 1144 if (dma->tx_running) 1145 return 0; 1146 if (uart_tx_stopped(&p->port) || kfifo_is_empty(&tport->xmit_fifo)) { 1147 1148 /* 1149 * Even if no data, we need to return an error for the two cases 1150 * below so serial8250_tx_chars() is invoked and properly clears 1151 * THRI and/or runtime suspend. 1152 */ 1153 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1154 ret = -EBUSY; 1155 goto err; 1156 } 1157 serial8250_clear_THRI(p); 1158 return 0; 1159 } 1160 1161 if (priv->habit & OMAP_DMA_TX_KICK) { 1162 unsigned char c; 1163 u8 tx_lvl; 1164 1165 /* 1166 * We need to put the first byte into the FIFO in order to start 1167 * the DMA transfer. For transfers smaller than four bytes we 1168 * don't bother doing DMA at all. It seem not matter if there 1169 * are still bytes in the FIFO from the last transfer (in case 1170 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1171 * leaving the FIFO seem not to trigger the DMA transfer. It is 1172 * really the byte that we put into the FIFO. 1173 * If the FIFO is already full then we most likely got here from 1174 * omap_8250_dma_tx_complete(). And this means the DMA engine 1175 * just completed its work. We don't have to wait the complete 1176 * 86us at 115200,8n1 but around 60us (not to mention lower 1177 * baudrates). So in that case we take the interrupt and try 1178 * again with an empty FIFO. 1179 */ 1180 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1181 if (tx_lvl == p->tx_loadsz) { 1182 ret = -EBUSY; 1183 goto err; 1184 } 1185 if (kfifo_len(&tport->xmit_fifo) < 4) { 1186 ret = -EINVAL; 1187 goto err; 1188 } 1189 if (!uart_fifo_out(&p->port, &c, 1)) { 1190 ret = -EINVAL; 1191 goto err; 1192 } 1193 skip_byte = c; 1194 } 1195 1196 sg_init_table(&sg, 1); 1197 ret = kfifo_dma_out_prepare_mapped(&tport->xmit_fifo, &sg, 1, UART_XMIT_SIZE, dma->tx_addr); 1198 if (ret != 1) { 1199 ret = -EINVAL; 1200 goto err; 1201 } 1202 1203 desc = dmaengine_prep_slave_sg(dma->txchan, &sg, 1, DMA_MEM_TO_DEV, 1204 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1205 if (!desc) { 1206 ret = -EBUSY; 1207 goto err; 1208 } 1209 1210 dma->tx_size = sg_dma_len(&sg); 1211 dma->tx_running = 1; 1212 1213 desc->callback = omap_8250_dma_tx_complete; 1214 desc->callback_param = p; 1215 1216 dma->tx_cookie = dmaengine_submit(desc); 1217 1218 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1219 UART_XMIT_SIZE, DMA_TO_DEVICE); 1220 1221 dma_async_issue_pending(dma->txchan); 1222 if (dma->tx_err) 1223 dma->tx_err = 0; 1224 1225 serial8250_clear_THRI(p); 1226 ret = 0; 1227 goto out_skip; 1228err: 1229 dma->tx_err = 1; 1230out_skip: 1231 if (skip_byte >= 0) 1232 serial_out(p, UART_TX, skip_byte); 1233 return ret; 1234} 1235 1236static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1237{ 1238 switch (iir & 0x3f) { 1239 case UART_IIR_RLSI: 1240 case UART_IIR_RX_TIMEOUT: 1241 case UART_IIR_RDI: 1242 omap_8250_rx_dma_flush(up); 1243 return true; 1244 } 1245 return omap_8250_rx_dma(up); 1246} 1247 1248static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1249{ 1250 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1251 (iir & UART_IIR_RDI)) { 1252 if (handle_rx_dma(up, iir)) { 1253 status = serial8250_rx_chars(up, status); 1254 omap_8250_rx_dma(up); 1255 } 1256 } 1257 1258 return status; 1259} 1260 1261static void am654_8250_handle_uart_errors(struct uart_8250_port *up, u8 iir, u16 status) 1262{ 1263 if (status & UART_LSR_OE) { 1264 serial8250_clear_and_reinit_fifos(up); 1265 serial_in(up, UART_LSR); 1266 serial_in(up, UART_OMAP_RESUME); 1267 } else { 1268 if (status & (UART_LSR_FE | UART_LSR_PE | UART_LSR_BI)) 1269 serial_in(up, UART_RX); 1270 if (iir & UART_IIR_XOFF) 1271 serial_in(up, UART_IIR); 1272 } 1273} 1274 1275static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1276 u16 status) 1277{ 1278 /* Port locked to synchronize UART_IER access against the console. */ 1279 lockdep_assert_held_once(&up->port.lock); 1280 1281 /* 1282 * Queue a new transfer if FIFO has data. 1283 */ 1284 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1285 (up->ier & UART_IER_RDI) && !(status & UART_LSR_OE)) { 1286 am654_8250_handle_uart_errors(up, iir, status); 1287 omap_8250_rx_dma(up); 1288 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1289 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1290 /* 1291 * Disable RX timeout, read IIR to clear 1292 * current timeout condition, clear EFR2 to 1293 * periodic timeouts, re-enable interrupts. 1294 */ 1295 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1296 serial_out(up, UART_IER, up->ier); 1297 omap_8250_rx_dma_flush(up); 1298 serial_in(up, UART_IIR); 1299 serial_out(up, UART_OMAP_EFR2, 0x0); 1300 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1301 serial_out(up, UART_IER, up->ier); 1302 } else { 1303 am654_8250_handle_uart_errors(up, iir, status); 1304 } 1305} 1306 1307/* 1308 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1309 * hook for RX/TX and need different logic for them in the ISR. Therefore we 1310 * use the default routine in the non-DMA case and this one for with DMA. 1311 */ 1312static int omap_8250_dma_handle_irq(struct uart_port *port) 1313{ 1314 struct uart_8250_port *up = up_to_u8250p(port); 1315 struct omap8250_priv *priv = port->private_data; 1316 u16 status; 1317 u8 iir; 1318 1319 iir = serial_port_in(port, UART_IIR); 1320 if (iir & UART_IIR_NO_INT) { 1321 return IRQ_HANDLED; 1322 } 1323 1324 uart_port_lock(port); 1325 1326 status = serial_port_in(port, UART_LSR); 1327 1328 if ((iir & 0x3f) != UART_IIR_THRI) { 1329 if (priv->habit & UART_HAS_EFR2) 1330 am654_8250_handle_rx_dma(up, iir, status); 1331 else 1332 status = omap_8250_handle_rx_dma(up, iir, status); 1333 } 1334 1335 serial8250_modem_status(up); 1336 if (status & UART_LSR_THRE && up->dma->tx_err) { 1337 if (uart_tx_stopped(port) || 1338 kfifo_is_empty(&port->state->port.xmit_fifo)) { 1339 up->dma->tx_err = 0; 1340 serial8250_tx_chars(up); 1341 } else { 1342 /* 1343 * try again due to an earlier failure which 1344 * might have been resolved by now. 1345 */ 1346 if (omap_8250_tx_dma(up)) 1347 serial8250_tx_chars(up); 1348 } 1349 } 1350 1351 uart_unlock_and_check_sysrq(port); 1352 1353 return 1; 1354} 1355 1356static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1357{ 1358 return false; 1359} 1360 1361#else 1362 1363static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1364{ 1365 return -EINVAL; 1366} 1367#endif 1368 1369static int omap8250_no_handle_irq(struct uart_port *port) 1370{ 1371 /* IRQ has not been requested but handling irq? */ 1372 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1373 return 0; 1374} 1375 1376static int omap8250_select_wakeup_pinctrl(struct device *dev, 1377 struct omap8250_priv *priv) 1378{ 1379 if (IS_ERR_OR_NULL(priv->pinctrl_wakeup)) 1380 return 0; 1381 1382 if (!device_may_wakeup(dev)) 1383 return 0; 1384 1385 return pinctrl_select_state(priv->pinctrl, priv->pinctrl_wakeup); 1386} 1387 1388static struct omap8250_dma_params am654_dma = { 1389 .rx_size = SZ_2K, 1390 .rx_trigger = 1, 1391 .tx_trigger = TX_TRIGGER, 1392}; 1393 1394static struct omap8250_dma_params am33xx_dma = { 1395 .rx_size = RX_TRIGGER, 1396 .rx_trigger = RX_TRIGGER, 1397 .tx_trigger = TX_TRIGGER, 1398}; 1399 1400static struct omap8250_platdata am654_platdata = { 1401 .dma_params = &am654_dma, 1402 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1403 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1404}; 1405 1406static struct omap8250_platdata am33xx_platdata = { 1407 .dma_params = &am33xx_dma, 1408 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1409}; 1410 1411static struct omap8250_platdata omap4_platdata = { 1412 .dma_params = &am33xx_dma, 1413 .habit = UART_ERRATA_CLOCK_DISABLE, 1414}; 1415 1416static const struct of_device_id omap8250_dt_ids[] = { 1417 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1418 { .compatible = "ti,omap2-uart" }, 1419 { .compatible = "ti,omap3-uart" }, 1420 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1421 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1422 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1423 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1424 {}, 1425}; 1426MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1427 1428static int omap8250_probe(struct platform_device *pdev) 1429{ 1430 struct device_node *np = pdev->dev.of_node; 1431 struct omap8250_priv *priv; 1432 const struct omap8250_platdata *pdata; 1433 struct uart_8250_port up; 1434 struct resource *regs; 1435 void __iomem *membase; 1436 int ret; 1437 1438 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1439 if (!regs) { 1440 dev_err(&pdev->dev, "missing registers\n"); 1441 return -EINVAL; 1442 } 1443 1444 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1445 if (!priv) 1446 return -ENOMEM; 1447 1448 membase = devm_ioremap(&pdev->dev, regs->start, 1449 resource_size(regs)); 1450 if (!membase) 1451 return -ENODEV; 1452 1453 memset(&up, 0, sizeof(up)); 1454 up.port.dev = &pdev->dev; 1455 up.port.mapbase = regs->start; 1456 up.port.membase = membase; 1457 /* 1458 * It claims to be 16C750 compatible however it is a little different. 1459 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1460 * have) is enabled via EFR instead of MCR. The type is set here 8250 1461 * just to get things going. UNKNOWN does not work for a few reasons and 1462 * we don't need our own type since we don't use 8250's set_termios() 1463 * or pm callback. 1464 */ 1465 up.port.type = PORT_8250; 1466 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | UPF_HARD_FLOW; 1467 up.port.private_data = priv; 1468 1469 up.tx_loadsz = 64; 1470 up.capabilities = UART_CAP_FIFO; 1471#ifdef CONFIG_PM 1472 /* 1473 * Runtime PM is mostly transparent. However to do it right we need to a 1474 * TX empty interrupt before we can put the device to auto idle. So if 1475 * PM is not enabled we don't add that flag and can spare that one extra 1476 * interrupt in the TX path. 1477 */ 1478 up.capabilities |= UART_CAP_RPM; 1479#endif 1480 up.port.set_termios = omap_8250_set_termios; 1481 up.port.set_mctrl = omap8250_set_mctrl; 1482 up.port.pm = omap_8250_pm; 1483 up.port.startup = omap_8250_startup; 1484 up.port.shutdown = omap_8250_shutdown; 1485 up.port.throttle = omap_8250_throttle; 1486 up.port.unthrottle = omap_8250_unthrottle; 1487 up.port.rs485_config = omap8250_rs485_config; 1488 /* same rs485_supported for software emulation and native RS485 */ 1489 up.port.rs485_supported = serial8250_em485_supported; 1490 up.rs485_start_tx = serial8250_em485_start_tx; 1491 up.rs485_stop_tx = serial8250_em485_stop_tx; 1492 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1493 1494 ret = uart_read_port_properties(&up.port); 1495 if (ret) 1496 return ret; 1497 1498 up.port.regshift = OMAP_UART_REGSHIFT; 1499 up.port.fifosize = 64; 1500 1501 if (!up.port.uartclk) { 1502 struct clk *clk; 1503 1504 clk = devm_clk_get(&pdev->dev, NULL); 1505 if (IS_ERR(clk)) { 1506 if (PTR_ERR(clk) == -EPROBE_DEFER) 1507 return -EPROBE_DEFER; 1508 } else { 1509 up.port.uartclk = clk_get_rate(clk); 1510 } 1511 } 1512 1513 if (of_property_read_u32(np, "overrun-throttle-ms", 1514 &up.overrun_backoff_time_ms) != 0) 1515 up.overrun_backoff_time_ms = 0; 1516 1517 pdata = of_device_get_match_data(&pdev->dev); 1518 if (pdata) 1519 priv->habit |= pdata->habit; 1520 1521 if (!up.port.uartclk) { 1522 up.port.uartclk = DEFAULT_CLK_SPEED; 1523 dev_warn(&pdev->dev, 1524 "No clock speed specified: using default: %d\n", 1525 DEFAULT_CLK_SPEED); 1526 } 1527 1528 priv->membase = membase; 1529 priv->line = -ENODEV; 1530 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1531 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1532 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1533 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1534 1535 spin_lock_init(&priv->rx_dma_lock); 1536 1537 platform_set_drvdata(pdev, priv); 1538 1539 device_set_wakeup_capable(&pdev->dev, true); 1540 if (of_property_read_bool(np, "wakeup-source")) 1541 device_set_wakeup_enable(&pdev->dev, true); 1542 1543 pm_runtime_enable(&pdev->dev); 1544 pm_runtime_use_autosuspend(&pdev->dev); 1545 1546 /* 1547 * Disable runtime PM until autosuspend delay unless specifically 1548 * enabled by the user via sysfs. This is the historic way to 1549 * prevent an unsafe default policy with lossy characters on wake-up. 1550 * For serdev devices this is not needed, the policy can be managed by 1551 * the serdev driver. 1552 */ 1553 if (!of_get_available_child_count(pdev->dev.of_node)) 1554 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1555 1556 pm_runtime_get_sync(&pdev->dev); 1557 1558 omap_serial_fill_features_erratas(&up, priv); 1559 up.port.handle_irq = omap8250_no_handle_irq; 1560 priv->rx_trigger = RX_TRIGGER; 1561 priv->tx_trigger = TX_TRIGGER; 1562#ifdef CONFIG_SERIAL_8250_DMA 1563 /* 1564 * Oh DMA support. If there are no DMA properties in the DT then 1565 * we will fall back to a generic DMA channel which does not 1566 * really work here. To ensure that we do not get a generic DMA 1567 * channel assigned, we have the the_no_dma_filter_fn() here. 1568 * To avoid "failed to request DMA" messages we check for DMA 1569 * properties in DT. 1570 */ 1571 ret = of_property_count_strings(np, "dma-names"); 1572 if (ret == 2) { 1573 struct omap8250_dma_params *dma_params = NULL; 1574 struct uart_8250_dma *dma = &priv->omap8250_dma; 1575 1576 dma->fn = the_no_dma_filter_fn; 1577 dma->tx_dma = omap_8250_tx_dma; 1578 dma->rx_dma = omap_8250_rx_dma; 1579 if (pdata) 1580 dma_params = pdata->dma_params; 1581 1582 if (dma_params) { 1583 dma->rx_size = dma_params->rx_size; 1584 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1585 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1586 priv->rx_trigger = dma_params->rx_trigger; 1587 priv->tx_trigger = dma_params->tx_trigger; 1588 } else { 1589 dma->rx_size = RX_TRIGGER; 1590 dma->rxconf.src_maxburst = RX_TRIGGER; 1591 dma->txconf.dst_maxburst = TX_TRIGGER; 1592 } 1593 } 1594#endif 1595 1596 irq_set_status_flags(up.port.irq, IRQ_NOAUTOEN); 1597 ret = devm_request_irq(&pdev->dev, up.port.irq, omap8250_irq, 0, 1598 dev_name(&pdev->dev), priv); 1599 if (ret < 0) 1600 goto err; 1601 1602 priv->wakeirq = irq_of_parse_and_map(np, 1); 1603 1604 ret = serial8250_register_8250_port(&up); 1605 if (ret < 0) { 1606 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1607 goto err; 1608 } 1609 priv->line = ret; 1610 pm_runtime_mark_last_busy(&pdev->dev); 1611 pm_runtime_put_autosuspend(&pdev->dev); 1612 1613 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1614 if (!IS_ERR_OR_NULL(priv->pinctrl)) 1615 priv->pinctrl_wakeup = pinctrl_lookup_state(priv->pinctrl, "wakeup"); 1616 1617 return 0; 1618err: 1619 pm_runtime_dont_use_autosuspend(&pdev->dev); 1620 pm_runtime_put_sync(&pdev->dev); 1621 flush_work(&priv->qos_work); 1622 pm_runtime_disable(&pdev->dev); 1623 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1624 return ret; 1625} 1626 1627static void omap8250_remove(struct platform_device *pdev) 1628{ 1629 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1630 struct uart_8250_port *up; 1631 int err; 1632 1633 err = pm_runtime_resume_and_get(&pdev->dev); 1634 if (err) 1635 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1636 1637 up = serial8250_get_port(priv->line); 1638 omap_8250_shutdown(&up->port); 1639 serial8250_unregister_port(priv->line); 1640 priv->line = -ENODEV; 1641 pm_runtime_dont_use_autosuspend(&pdev->dev); 1642 pm_runtime_put_sync(&pdev->dev); 1643 flush_work(&priv->qos_work); 1644 pm_runtime_disable(&pdev->dev); 1645 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1646 device_set_wakeup_capable(&pdev->dev, false); 1647} 1648 1649static int omap8250_prepare(struct device *dev) 1650{ 1651 struct omap8250_priv *priv = dev_get_drvdata(dev); 1652 1653 if (!priv) 1654 return 0; 1655 priv->is_suspending = true; 1656 return 0; 1657} 1658 1659static void omap8250_complete(struct device *dev) 1660{ 1661 struct omap8250_priv *priv = dev_get_drvdata(dev); 1662 1663 if (!priv) 1664 return; 1665 priv->is_suspending = false; 1666} 1667 1668static int omap8250_suspend(struct device *dev) 1669{ 1670 struct omap8250_priv *priv = dev_get_drvdata(dev); 1671 struct uart_8250_port *up = serial8250_get_port(priv->line); 1672 int err = 0; 1673 1674 err = omap8250_select_wakeup_pinctrl(dev, priv); 1675 if (err) { 1676 dev_err(dev, "Failed to select wakeup pinctrl, aborting suspend %pe\n", 1677 ERR_PTR(err)); 1678 return err; 1679 } 1680 1681 serial8250_suspend_port(priv->line); 1682 1683 err = pm_runtime_resume_and_get(dev); 1684 if (err) 1685 return err; 1686 if (!device_may_wakeup(dev)) 1687 priv->wer = 0; 1688 serial_out(up, UART_OMAP_WER, priv->wer); 1689 if (uart_console(&up->port) && console_suspend_enabled) 1690 err = pm_runtime_force_suspend(dev); 1691 flush_work(&priv->qos_work); 1692 1693 return err; 1694} 1695 1696static int omap8250_resume(struct device *dev) 1697{ 1698 struct omap8250_priv *priv = dev_get_drvdata(dev); 1699 struct uart_8250_port *up = serial8250_get_port(priv->line); 1700 int err; 1701 1702 err = pinctrl_select_default_state(dev); 1703 if (err) { 1704 dev_err(dev, "Failed to select default pinctrl state on resume: %pe\n", 1705 ERR_PTR(err)); 1706 return err; 1707 } 1708 1709 if (uart_console(&up->port) && console_suspend_enabled) { 1710 err = pm_runtime_force_resume(dev); 1711 if (err) 1712 return err; 1713 } 1714 1715 serial8250_resume_port(priv->line); 1716 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1717 pm_runtime_mark_last_busy(dev); 1718 pm_runtime_put_autosuspend(dev); 1719 1720 return 0; 1721} 1722 1723static int omap8250_lost_context(struct uart_8250_port *up) 1724{ 1725 u32 val; 1726 1727 val = serial_in(up, UART_OMAP_SCR); 1728 /* 1729 * If we lose context, then SCR is set to its reset value of zero. 1730 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1731 * among other bits, to never set the register back to zero again. 1732 */ 1733 if (!val) 1734 return 1; 1735 return 0; 1736} 1737 1738static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1739{ 1740 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1741} 1742 1743/* TODO: in future, this should happen via API in drivers/reset/ */ 1744static int omap8250_soft_reset(struct device *dev) 1745{ 1746 struct omap8250_priv *priv = dev_get_drvdata(dev); 1747 int timeout = 100; 1748 int sysc; 1749 int syss; 1750 1751 /* 1752 * At least on omap4, unused uarts may not idle after reset without 1753 * a basic scr dma configuration even with no dma in use. The 1754 * module clkctrl status bits will be 1 instead of 3 blocking idle 1755 * for the whole clockdomain. The softreset below will clear scr, 1756 * and we restore it on resume so this is safe to do on all SoCs 1757 * needing omap8250_soft_reset() quirk. Do it in two writes as 1758 * recommended in the comment for omap8250_update_scr(). 1759 */ 1760 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1761 uart_write(priv, UART_OMAP_SCR, 1762 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1763 1764 sysc = uart_read(priv, UART_OMAP_SYSC); 1765 1766 /* softreset the UART */ 1767 sysc |= OMAP_UART_SYSC_SOFTRESET; 1768 uart_write(priv, UART_OMAP_SYSC, sysc); 1769 1770 /* By experiments, 1us enough for reset complete on AM335x */ 1771 do { 1772 udelay(1); 1773 syss = uart_read(priv, UART_OMAP_SYSS); 1774 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1775 1776 if (!timeout) { 1777 dev_err(dev, "timed out waiting for reset done\n"); 1778 return -ETIMEDOUT; 1779 } 1780 1781 return 0; 1782} 1783 1784static int omap8250_runtime_suspend(struct device *dev) 1785{ 1786 struct omap8250_priv *priv = dev_get_drvdata(dev); 1787 struct uart_8250_port *up = NULL; 1788 1789 if (priv->line >= 0) 1790 up = serial8250_get_port(priv->line); 1791 1792 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1793 int ret; 1794 1795 ret = omap8250_soft_reset(dev); 1796 if (ret) 1797 return ret; 1798 1799 if (up) { 1800 /* Restore to UART mode after reset (for wakeup) */ 1801 omap8250_update_mdr1(up, priv); 1802 /* Restore wakeup enable register */ 1803 serial_out(up, UART_OMAP_WER, priv->wer); 1804 } 1805 } 1806 1807 if (up && up->dma && up->dma->rxchan) 1808 omap_8250_rx_dma_flush(up); 1809 1810 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1811 schedule_work(&priv->qos_work); 1812 atomic_set(&priv->active, 0); 1813 1814 return 0; 1815} 1816 1817static int omap8250_runtime_resume(struct device *dev) 1818{ 1819 struct omap8250_priv *priv = dev_get_drvdata(dev); 1820 struct uart_8250_port *up = NULL; 1821 1822 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1823 if (atomic_read(&priv->active)) 1824 return 0; 1825 1826 if (priv->line >= 0) 1827 up = serial8250_get_port(priv->line); 1828 1829 if (up && omap8250_lost_context(up)) { 1830 guard(uart_port_lock_irq)(&up->port); 1831 omap8250_restore_regs(up); 1832 } 1833 1834 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1835 guard(uart_port_lock_irq)(&up->port); 1836 omap_8250_rx_dma(up); 1837 } 1838 1839 atomic_set(&priv->active, 1); 1840 priv->latency = priv->calc_latency; 1841 schedule_work(&priv->qos_work); 1842 1843 return 0; 1844} 1845 1846#ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1847static int __init omap8250_console_fixup(void) 1848{ 1849 char *omap_str; 1850 char *options; 1851 u8 idx; 1852 1853 if (strstr(boot_command_line, "console=ttyS")) 1854 /* user set a ttyS based name for the console */ 1855 return 0; 1856 1857 omap_str = strstr(boot_command_line, "console=ttyO"); 1858 if (!omap_str) 1859 /* user did not set ttyO based console, so we don't care */ 1860 return 0; 1861 1862 omap_str += 12; 1863 if ('0' <= *omap_str && *omap_str <= '9') 1864 idx = *omap_str - '0'; 1865 else 1866 return 0; 1867 1868 omap_str++; 1869 if (omap_str[0] == ',') { 1870 omap_str++; 1871 options = omap_str; 1872 } else { 1873 options = NULL; 1874 } 1875 1876 add_preferred_console("ttyS", idx, options); 1877 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1878 idx, idx); 1879 pr_err("This ensures that you still see kernel messages. Please\n"); 1880 pr_err("update your kernel commandline.\n"); 1881 return 0; 1882} 1883console_initcall(omap8250_console_fixup); 1884#endif 1885 1886static const struct dev_pm_ops omap8250_dev_pm_ops = { 1887 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1888 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1889 omap8250_runtime_resume, NULL) 1890 .prepare = pm_sleep_ptr(omap8250_prepare), 1891 .complete = pm_sleep_ptr(omap8250_complete), 1892}; 1893 1894static struct platform_driver omap8250_platform_driver = { 1895 .driver = { 1896 .name = "omap8250", 1897 .pm = pm_ptr(&omap8250_dev_pm_ops), 1898 .of_match_table = omap8250_dt_ids, 1899 }, 1900 .probe = omap8250_probe, 1901 .remove = omap8250_remove, 1902}; 1903module_platform_driver(omap8250_platform_driver); 1904 1905MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1906MODULE_DESCRIPTION("OMAP 8250 Driver"); 1907MODULE_LICENSE("GPL v2");
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