8250_fintek.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 *  Probe for F81216A LPC to 4 UART
  4 *
  5 *  Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
  6 */
  7#include <linux/module.h>
  8#include <linux/pci.h>
  9#include <linux/pnp.h>
 10#include <linux/kernel.h>
 11#include <linux/serial_core.h>
 12#include <linux/irq.h>
 13#include  "8250.h"
 14
 15#define ADDR_PORT 0
 16#define DATA_PORT 1
 17#define EXIT_KEY 0xAA
 18#define CHIP_ID1  0x20
 19#define CHIP_ID2  0x21
 20#define CHIP_ID_F81865 0x0407
 21#define CHIP_ID_F81866 0x1010
 22#define CHIP_ID_F81966 0x0215
 23#define CHIP_ID_F81216AD 0x1602
 24#define CHIP_ID_F81216E 0x1617
 25#define CHIP_ID_F81216H 0x0501
 26#define CHIP_ID_F81216 0x0802
 27#define VENDOR_ID1 0x23
 28#define VENDOR_ID1_VAL 0x19
 29#define VENDOR_ID2 0x24
 30#define VENDOR_ID2_VAL 0x34
 31#define IO_ADDR1 0x61
 32#define IO_ADDR2 0x60
 33#define LDN 0x7
 34
 35#define FINTEK_IRQ_MODE	0x70
 36#define IRQ_SHARE	BIT(4)
 37#define IRQ_MODE_MASK	(BIT(6) | BIT(5))
 38#define IRQ_LEVEL_LOW	0
 39#define IRQ_EDGE_HIGH	BIT(5)
 40
 41/*
 42 * F81216H clock source register, the value and mask is the same with F81866,
 43 * but it's on F0h.
 44 *
 45 * Clock speeds for UART (register F0h)
 46 * 00: 1.8432MHz.
 47 * 01: 18.432MHz.
 48 * 10: 24MHz.
 49 * 11: 14.769MHz.
 50 */
 51#define RS485  0xF0
 52#define RTS_INVERT BIT(5)
 53#define RS485_URA BIT(4)
 54#define RXW4C_IRA BIT(3)
 55#define TXW4C_IRA BIT(2)
 56
 57#define FIFO_CTRL		0xF6
 58#define FIFO_MODE_MASK		(BIT(1) | BIT(0))
 59#define FIFO_MODE_128		(BIT(1) | BIT(0))
 60#define RXFTHR_MODE_MASK	(BIT(5) | BIT(4))
 61#define RXFTHR_MODE_4X		BIT(5)
 62
 63#define F81216_LDN_LOW	0x0
 64#define F81216_LDN_HIGH	0x4
 65
 66/*
 67 * F81866/966 registers
 68 *
 69 * The IRQ setting mode of F81866/966 is not the same with F81216 series.
 70 *	Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
 71 *	Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
 72 *
 73 * Clock speeds for UART (register F2h)
 74 * 00: 1.8432MHz.
 75 * 01: 18.432MHz.
 76 * 10: 24MHz.
 77 * 11: 14.769MHz.
 78 */
 79#define F81866_IRQ_MODE		0xf0
 80#define F81866_IRQ_SHARE	BIT(0)
 81#define F81866_IRQ_MODE0	BIT(1)
 82
 83#define F81866_FIFO_CTRL	FIFO_CTRL
 84#define F81866_IRQ_MODE1	BIT(3)
 85
 86#define F81866_LDN_LOW		0x10
 87#define F81866_LDN_HIGH		0x16
 88
 89#define F81866_UART_CLK 0xF2
 90#define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
 91#define F81866_UART_CLK_1_8432MHZ 0
 92#define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
 93#define F81866_UART_CLK_18_432MHZ BIT(0)
 94#define F81866_UART_CLK_24MHZ BIT(1)
 95
 96struct fintek_8250 {
 97	u16 pid;
 98	u16 base_port;
 99	u8 index;
100	u8 key;
101};
102
103static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
104{
105	outb(reg, pdata->base_port + ADDR_PORT);
106	return inb(pdata->base_port + DATA_PORT);
107}
108
109static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
110{
111	outb(reg, pdata->base_port + ADDR_PORT);
112	outb(data, pdata->base_port + DATA_PORT);
113}
114
115static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
116			       u8 data)
117{
118	u8 tmp;
119
120	tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
121	sio_write_reg(pdata, reg, tmp);
122}
123
124static int fintek_8250_enter_key(u16 base_port, u8 key)
125{
126	if (!request_muxed_region(base_port, 2, "8250_fintek"))
127		return -EBUSY;
128
129	/* Force to deactivate all SuperIO in this base_port */
130	outb(EXIT_KEY, base_port + ADDR_PORT);
131
132	outb(key, base_port + ADDR_PORT);
133	outb(key, base_port + ADDR_PORT);
134	return 0;
135}
136
137static void fintek_8250_exit_key(u16 base_port)
138{
139
140	outb(EXIT_KEY, base_port + ADDR_PORT);
141	release_region(base_port + ADDR_PORT, 2);
142}
143
144static int fintek_8250_check_id(struct fintek_8250 *pdata)
145{
146	u16 chip;
147
148	if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
149		return -ENODEV;
150
151	if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
152		return -ENODEV;
153
154	chip = sio_read_reg(pdata, CHIP_ID1);
155	chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
156
157	switch (chip) {
158	case CHIP_ID_F81865:
159	case CHIP_ID_F81866:
160	case CHIP_ID_F81966:
161	case CHIP_ID_F81216AD:
162	case CHIP_ID_F81216E:
163	case CHIP_ID_F81216H:
164	case CHIP_ID_F81216:
165		break;
166	default:
167		return -ENODEV;
168	}
169
170	pdata->pid = chip;
171	return 0;
172}
173
174static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
175				     int *max)
176{
177	switch (pdata->pid) {
178	case CHIP_ID_F81966:
179	case CHIP_ID_F81865:
180	case CHIP_ID_F81866:
181		*min = F81866_LDN_LOW;
182		*max = F81866_LDN_HIGH;
183		return 0;
184
185	case CHIP_ID_F81216AD:
186	case CHIP_ID_F81216E:
187	case CHIP_ID_F81216H:
188	case CHIP_ID_F81216:
189		*min = F81216_LDN_LOW;
190		*max = F81216_LDN_HIGH;
191		return 0;
192	}
193
194	return -ENODEV;
195}
196
197static int fintek_8250_rs485_config(struct uart_port *port, struct ktermios *termios,
198			      struct serial_rs485 *rs485)
199{
200	uint8_t config = 0;
201	struct fintek_8250 *pdata = port->private_data;
202
203	if (!pdata)
204		return -EINVAL;
205
206
207	if (rs485->flags & SER_RS485_ENABLED) {
208		/* Hardware do not support same RTS level on send and receive */
209		if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
210		    !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
211			return -EINVAL;
212		config |= RS485_URA;
213	}
214
215	if (rs485->delay_rts_before_send) {
216		rs485->delay_rts_before_send = 1;
217		config |= TXW4C_IRA;
218	}
219
220	if (rs485->delay_rts_after_send) {
221		rs485->delay_rts_after_send = 1;
222		config |= RXW4C_IRA;
223	}
224
225	if (rs485->flags & SER_RS485_RTS_ON_SEND)
226		config |= RTS_INVERT;
227
228	if (fintek_8250_enter_key(pdata->base_port, pdata->key))
229		return -EBUSY;
230
231	sio_write_reg(pdata, LDN, pdata->index);
232	sio_write_reg(pdata, RS485, config);
233	fintek_8250_exit_key(pdata->base_port);
234
235	return 0;
236}
237
238static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
239{
240	sio_write_reg(pdata, LDN, pdata->index);
241
242	switch (pdata->pid) {
243	case CHIP_ID_F81966:
244	case CHIP_ID_F81866:
245		sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
246				   0);
247		fallthrough;
248	case CHIP_ID_F81865:
249		sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
250				   F81866_IRQ_SHARE);
251		sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
252				   is_level ? 0 : F81866_IRQ_MODE0);
253		break;
254
255	case CHIP_ID_F81216AD:
256	case CHIP_ID_F81216E:
257	case CHIP_ID_F81216H:
258	case CHIP_ID_F81216:
259		sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
260				   IRQ_SHARE);
261		sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
262				   is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
263		break;
264	}
265}
266
267static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
268{
269	switch (pdata->pid) {
270	case CHIP_ID_F81216E: /* 128Bytes FIFO */
271	case CHIP_ID_F81216H:
272	case CHIP_ID_F81966:
273	case CHIP_ID_F81866:
274		sio_write_mask_reg(pdata, FIFO_CTRL,
275				   FIFO_MODE_MASK | RXFTHR_MODE_MASK,
276				   FIFO_MODE_128 | RXFTHR_MODE_4X);
277		break;
278
279	default: /* Default 16Bytes FIFO */
280		break;
281	}
282}
283
284static void fintek_8250_set_termios(struct uart_port *port,
285				    struct ktermios *termios,
286				    const struct ktermios *old)
287{
288	struct fintek_8250 *pdata = port->private_data;
289	unsigned int baud = tty_termios_baud_rate(termios);
290	int i;
291	u8 reg;
292	static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
293	static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
294			F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
295			F81866_UART_CLK_24MHZ };
296
297	/*
298	 * We'll use serial8250_do_set_termios() for baud = 0, otherwise It'll
299	 * crash on baudrate_table[i] % baud with "division by zero".
300	 */
301	if (!baud)
302		goto exit;
303
304	switch (pdata->pid) {
305	case CHIP_ID_F81216E:
306	case CHIP_ID_F81216H:
307		reg = RS485;
308		break;
309	case CHIP_ID_F81966:
310	case CHIP_ID_F81866:
311		reg = F81866_UART_CLK;
312		break;
313	default:
314		/* Don't change clocksource with unknown PID */
315		dev_warn(port->dev,
316			"%s: pid: %x Not support. use default set_termios.\n",
317			__func__, pdata->pid);
318		goto exit;
319	}
320
321	for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
322		if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
323			continue;
324
325		if (port->uartclk == baudrate_table[i] * 16)
326			break;
327
328		if (fintek_8250_enter_key(pdata->base_port, pdata->key))
329			continue;
330
331		port->uartclk = baudrate_table[i] * 16;
332
333		sio_write_reg(pdata, LDN, pdata->index);
334		sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
335				clock_table[i]);
336
337		fintek_8250_exit_key(pdata->base_port);
338		break;
339	}
340
341	if (i == ARRAY_SIZE(baudrate_table)) {
342		baud = tty_termios_baud_rate(old);
343		tty_termios_encode_baud_rate(termios, baud, baud);
344	}
345
346exit:
347	serial8250_do_set_termios(port, termios, old);
348}
349
350static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
351{
352	struct fintek_8250 *pdata = uart->port.private_data;
353
354	switch (pdata->pid) {
355	case CHIP_ID_F81216E:
356	case CHIP_ID_F81216H:
357	case CHIP_ID_F81966:
358	case CHIP_ID_F81866:
359		uart->port.set_termios = fintek_8250_set_termios;
360		break;
361
362	default:
363		break;
364	}
365}
366
367static int probe_setup_port(struct fintek_8250 *pdata,
368					struct uart_8250_port *uart)
369{
370	static const u16 addr[] = {0x4e, 0x2e};
371	static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
372	struct irq_data *irq_data;
373	bool level_mode = false;
374	int i, j, k, min, max;
375
376	for (i = 0; i < ARRAY_SIZE(addr); i++) {
377		for (j = 0; j < ARRAY_SIZE(keys); j++) {
378			pdata->base_port = addr[i];
379			pdata->key = keys[j];
380
381			if (fintek_8250_enter_key(addr[i], keys[j]))
382				continue;
383			if (fintek_8250_check_id(pdata) ||
384			    fintek_8250_get_ldn_range(pdata, &min, &max)) {
385				fintek_8250_exit_key(addr[i]);
386				continue;
387			}
388
389			for (k = min; k < max; k++) {
390				u16 aux;
391
392				sio_write_reg(pdata, LDN, k);
393				aux = sio_read_reg(pdata, IO_ADDR1);
394				aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
395				if (aux != uart->port.iobase)
396					continue;
397
398				pdata->index = k;
399
400				irq_data = irq_get_irq_data(uart->port.irq);
401				if (irq_data)
402					level_mode =
403						irqd_is_level_type(irq_data);
404
405				fintek_8250_set_irq_mode(pdata, level_mode);
406				fintek_8250_set_max_fifo(pdata);
407
408				fintek_8250_exit_key(addr[i]);
409
410				return 0;
411			}
412
413			fintek_8250_exit_key(addr[i]);
414		}
415	}
416
417	return -ENODEV;
418}
419
420/* Only the first port supports delays */
421static const struct serial_rs485 fintek_8250_rs485_supported_port0 = {
422	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
423	.delay_rts_before_send = 1,
424	.delay_rts_after_send = 1,
425};
426
427static const struct serial_rs485 fintek_8250_rs485_supported = {
428	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
429};
430
431static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
432{
433	struct fintek_8250 *pdata = uart->port.private_data;
434
435	switch (pdata->pid) {
436	case CHIP_ID_F81216AD:
437	case CHIP_ID_F81216H:
438	case CHIP_ID_F81966:
439	case CHIP_ID_F81866:
440	case CHIP_ID_F81865:
441		uart->port.rs485_config = fintek_8250_rs485_config;
442		if (!pdata->index)
443			uart->port.rs485_supported = fintek_8250_rs485_supported_port0;
444		else
445			uart->port.rs485_supported = fintek_8250_rs485_supported;
446		break;
447
448	case CHIP_ID_F81216E: /* F81216E does not support RS485 delays */
449		uart->port.rs485_config = fintek_8250_rs485_config;
450		uart->port.rs485_supported = fintek_8250_rs485_supported;
451		break;
452
453	default: /* No RS485 Auto direction functional */
454		break;
455	}
456}
457
458int fintek_8250_probe(struct uart_8250_port *uart)
459{
460	struct fintek_8250 *pdata;
461	struct fintek_8250 probe_data;
462
463	if (probe_setup_port(&probe_data, uart))
464		return -ENODEV;
465
466	pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
467	if (!pdata)
468		return -ENOMEM;
469
470	memcpy(pdata, &probe_data, sizeof(probe_data));
471	uart->port.private_data = pdata;
472	fintek_8250_set_rs485_handler(uart);
473	fintek_8250_set_termios_handler(uart);
474
475	return 0;
476}