8250_dw.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Synopsys DesignWare 8250 driver.
   4 *
   5 * Copyright 2011 Picochip, Jamie Iles.
   6 * Copyright 2013 Intel Corporation
   7 *
   8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
   9 * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  10 * raised, the LCR needs to be rewritten and the uart status register read.
  11 */
  12#include <linux/bitfield.h>
  13#include <linux/bits.h>
  14#include <linux/cleanup.h>
  15#include <linux/clk.h>
  16#include <linux/delay.h>
  17#include <linux/device.h>
  18#include <linux/io.h>
  19#include <linux/lockdep.h>
  20#include <linux/mod_devicetable.h>
  21#include <linux/module.h>
  22#include <linux/notifier.h>
  23#include <linux/platform_device.h>
  24#include <linux/pm_runtime.h>
  25#include <linux/property.h>
  26#include <linux/reset.h>
  27#include <linux/slab.h>
  28#include <linux/workqueue.h>
  29
  30#include <asm/byteorder.h>
  31
  32#include <linux/serial_8250.h>
  33#include <linux/serial_reg.h>
  34
  35#include "8250_dwlib.h"
  36
  37/* Offsets for the DesignWare specific registers */
  38#define DW_UART_USR	0x1f /* UART Status Register */
  39#define DW_UART_DMASA	0xa8 /* DMA Software Ack */
  40
  41#define OCTEON_UART_USR	0x27 /* UART Status Register */
  42
  43#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
  44#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
  45
  46/* DesignWare specific register fields */
  47#define DW_UART_IIR_IID			GENMASK(3, 0)
  48
  49#define DW_UART_MCR_SIRE		BIT(6)
  50
  51#define DW_UART_USR_BUSY		BIT(0)
  52
  53/* Renesas specific register fields */
  54#define RZN1_UART_xDMACR_DMA_EN		BIT(0)
  55#define RZN1_UART_xDMACR_1_WORD_BURST	(0 << 1)
  56#define RZN1_UART_xDMACR_4_WORD_BURST	(1 << 1)
  57#define RZN1_UART_xDMACR_8_WORD_BURST	(2 << 1)
  58#define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
  59
  60/* Quirks */
  61#define DW_UART_QUIRK_OCTEON		BIT(0)
  62#define DW_UART_QUIRK_ARMADA_38X	BIT(1)
  63#define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
  64#define DW_UART_QUIRK_IS_DMA_FC		BIT(3)
  65#define DW_UART_QUIRK_APMC0D08		BIT(4)
  66#define DW_UART_QUIRK_CPR_VALUE		BIT(5)
  67#define DW_UART_QUIRK_IER_KICK		BIT(6)
  68
  69/*
  70 * Number of consecutive IIR_NO_INT interrupts required to trigger interrupt
  71 * storm prevention code.
  72 */
  73#define DW_UART_QUIRK_IER_KICK_THRES	4
  74
  75struct dw8250_platform_data {
  76	u8 usr_reg;
  77	u32 cpr_value;
  78	unsigned int quirks;
  79};
  80
  81struct dw8250_data {
  82	struct dw8250_port_data	data;
  83	const struct dw8250_platform_data *pdata;
  84
  85	u32			msr_mask_on;
  86	u32			msr_mask_off;
  87	struct clk		*clk;
  88	struct clk		*pclk;
  89	struct notifier_block	clk_notifier;
  90	struct work_struct	clk_work;
  91	struct reset_control	*rst;
  92
  93	unsigned int		skip_autocfg:1;
  94	unsigned int		uart_16550_compatible:1;
  95	unsigned int		in_idle:1;
  96
  97	u8			no_int_count;
  98};
  99
 100static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
 101{
 102	return container_of(data, struct dw8250_data, data);
 103}
 104
 105static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
 106{
 107	return container_of(nb, struct dw8250_data, clk_notifier);
 108}
 109
 110static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
 111{
 112	return container_of(work, struct dw8250_data, clk_work);
 113}
 114
 115static inline u32 dw8250_modify_msr(struct uart_port *p, unsigned int offset, u32 value)
 116{
 117	struct dw8250_data *d = to_dw8250_data(p->private_data);
 118
 119	/* Override any modem control signals if needed */
 120	if (offset == UART_MSR) {
 121		value |= d->msr_mask_on;
 122		value &= ~d->msr_mask_off;
 123	}
 124
 125	return value;
 126}
 127
 128static void dw8250_idle_exit(struct uart_port *p)
 129{
 130	struct dw8250_data *d = to_dw8250_data(p->private_data);
 131	struct uart_8250_port *up = up_to_u8250p(p);
 132
 133	if (d->uart_16550_compatible)
 134		return;
 135
 136	if (up->capabilities & UART_CAP_FIFO)
 137		serial_port_out(p, UART_FCR, up->fcr);
 138	serial_port_out(p, UART_MCR, up->mcr);
 139	serial_port_out(p, UART_IER, up->ier);
 140
 141	/* DMA Rx is restarted by IRQ handler as needed. */
 142	if (up->dma)
 143		serial8250_tx_dma_resume(up);
 144
 145	d->in_idle = 0;
 146}
 147
 148/*
 149 * Ensure BUSY is not asserted. If DW UART is configured with
 150 * !uart_16550_compatible, the writes to LCR, DLL, and DLH fail while
 151 * BUSY is asserted.
 152 *
 153 * Context: port's lock must be held
 154 */
 155static int dw8250_idle_enter(struct uart_port *p)
 156{
 157	struct dw8250_data *d = to_dw8250_data(p->private_data);
 158	unsigned int usr_reg = d->pdata ? d->pdata->usr_reg : DW_UART_USR;
 159	struct uart_8250_port *up = up_to_u8250p(p);
 160	int retries;
 161	u32 lsr;
 162
 163	lockdep_assert_held_once(&p->lock);
 164
 165	if (d->uart_16550_compatible)
 166		return 0;
 167
 168	d->in_idle = 1;
 169
 170	/* Prevent triggering interrupt from RBR filling */
 171	serial_port_out(p, UART_IER, 0);
 172
 173	if (up->dma) {
 174		serial8250_rx_dma_flush(up);
 175		if (serial8250_tx_dma_running(up))
 176			serial8250_tx_dma_pause(up);
 177	}
 178
 179	/*
 180	 * Wait until Tx becomes empty + one extra frame time to ensure all bits
 181	 * have been sent on the wire.
 182	 *
 183	 * FIXME: frame_time delay is too long with very low baudrates.
 184	 */
 185	serial8250_fifo_wait_for_lsr_thre(up, p->fifosize);
 186	ndelay(p->frame_time);
 187
 188	serial_port_out(p, UART_MCR, up->mcr | UART_MCR_LOOP);
 189
 190	retries = 4;	/* Arbitrary limit, 2 was always enough in tests */
 191	do {
 192		serial8250_clear_fifos(up);
 193		if (!(serial_port_in(p, usr_reg) & DW_UART_USR_BUSY))
 194			break;
 195		/* FIXME: frame_time delay is too long with very low baudrates. */
 196		ndelay(p->frame_time);
 197	} while (--retries);
 198
 199	lsr = serial_lsr_in(up);
 200	if (lsr & UART_LSR_DR) {
 201		serial_port_in(p, UART_RX);
 202		up->lsr_saved_flags = 0;
 203	}
 204
 205	/* Now guaranteed to have BUSY deasserted? Just sanity check */
 206	if (serial_port_in(p, usr_reg) & DW_UART_USR_BUSY) {
 207		dw8250_idle_exit(p);
 208		return -EBUSY;
 209	}
 210
 211	return 0;
 212}
 213
 214static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
 215			       unsigned int quot, unsigned int quot_frac)
 216{
 217	struct uart_8250_port *up = up_to_u8250p(p);
 218	int ret;
 219
 220	ret = dw8250_idle_enter(p);
 221	if (ret < 0)
 222		return;
 223
 224	serial_port_out(p, UART_LCR, up->lcr | UART_LCR_DLAB);
 225	if (!(serial_port_in(p, UART_LCR) & UART_LCR_DLAB))
 226		goto idle_failed;
 227
 228	serial_dl_write(up, quot);
 229	serial_port_out(p, UART_LCR, up->lcr);
 230
 231idle_failed:
 232	dw8250_idle_exit(p);
 233}
 234
 235/*
 236 * This function is being called as part of the uart_port::serial_out()
 237 * routine. Hence, special care must be taken when serial_port_out() or
 238 * serial_out() against the modified registers here, i.e. LCR (d->in_idle is
 239 * used to break recursion loop).
 240 */
 241static void dw8250_check_lcr(struct uart_port *p, unsigned int offset, u32 value)
 242{
 243	struct dw8250_data *d = to_dw8250_data(p->private_data);
 244	u32 lcr;
 245	int ret;
 246
 247	if (offset != UART_LCR || d->uart_16550_compatible)
 248		return;
 249
 250	lcr = serial_port_in(p, UART_LCR);
 251
 252	/* Make sure LCR write wasn't ignored */
 253	if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 254		return;
 255
 256	if (d->in_idle)
 257		goto write_err;
 258
 259	ret = dw8250_idle_enter(p);
 260	if (ret < 0)
 261		goto write_err;
 262
 263	serial_port_out(p, UART_LCR, value);
 264	dw8250_idle_exit(p);
 265	return;
 266
 267write_err:
 268	/*
 269	 * FIXME: this deadlocks if port->lock is already held
 270	 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 271	 */
 272	return;		/* Silences "label at the end of compound statement" */
 273}
 274
 275/*
 276 * With BUSY, LCR writes can be very expensive (IRQ + complex retry logic).
 277 * If the write does not change the value of the LCR register, skip it entirely.
 278 */
 279static bool dw8250_can_skip_reg_write(struct uart_port *p, unsigned int offset, u32 value)
 280{
 281	struct dw8250_data *d = to_dw8250_data(p->private_data);
 282	u32 lcr;
 283
 284	if (offset != UART_LCR || d->uart_16550_compatible)
 285		return false;
 286
 287	lcr = serial_port_in(p, offset);
 288	return lcr == value;
 289}
 290
 291/* Returns once the transmitter is empty or we run out of retries */
 292static void dw8250_tx_wait_empty(struct uart_port *p)
 293{
 294	struct uart_8250_port *up = up_to_u8250p(p);
 295	unsigned int tries = 20000;
 296	unsigned int delay_threshold = tries - 1000;
 297	unsigned int lsr;
 298
 299	while (tries--) {
 300		lsr = readb (p->membase + (UART_LSR << p->regshift));
 301		up->lsr_saved_flags |= lsr & up->lsr_save_mask;
 302
 303		if (lsr & UART_LSR_TEMT)
 304			break;
 305
 306		/* The device is first given a chance to empty without delay,
 307		 * to avoid slowdowns at high bitrates. If after 1000 tries
 308		 * the buffer has still not emptied, allow more time for low-
 309		 * speed links. */
 310		if (tries < delay_threshold)
 311			udelay (1);
 312	}
 313}
 314
 315static void dw8250_serial_out(struct uart_port *p, unsigned int offset, u32 value)
 316{
 317	if (dw8250_can_skip_reg_write(p, offset, value))
 318		return;
 319
 320	writeb(value, p->membase + (offset << p->regshift));
 321	dw8250_check_lcr(p, offset, value);
 322}
 323
 324static void dw8250_serial_out38x(struct uart_port *p, unsigned int offset, u32 value)
 325{
 326	if (dw8250_can_skip_reg_write(p, offset, value))
 327		return;
 328
 329	/* Allow the TX to drain before we reconfigure */
 330	if (offset == UART_LCR)
 331		dw8250_tx_wait_empty(p);
 332
 333	dw8250_serial_out(p, offset, value);
 334}
 335
 336static u32 dw8250_serial_in(struct uart_port *p, unsigned int offset)
 337{
 338	u32 value = readb(p->membase + (offset << p->regshift));
 339
 340	return dw8250_modify_msr(p, offset, value);
 341}
 342
 343#ifdef CONFIG_64BIT
 344static u32 dw8250_serial_inq(struct uart_port *p, unsigned int offset)
 345{
 346	u8 value = __raw_readq(p->membase + (offset << p->regshift));
 347
 348	return dw8250_modify_msr(p, offset, value);
 349}
 350
 351static void dw8250_serial_outq(struct uart_port *p, unsigned int offset, u32 value)
 352{
 353	if (dw8250_can_skip_reg_write(p, offset, value))
 354		return;
 355
 356	value &= 0xff;
 357	__raw_writeq(value, p->membase + (offset << p->regshift));
 358	/* Read back to ensure register write ordering. */
 359	__raw_readq(p->membase + (UART_LCR << p->regshift));
 360
 361	dw8250_check_lcr(p, offset, value);
 362}
 363#endif /* CONFIG_64BIT */
 364
 365static void dw8250_serial_out32(struct uart_port *p, unsigned int offset, u32 value)
 366{
 367	if (dw8250_can_skip_reg_write(p, offset, value))
 368		return;
 369
 370	writel(value, p->membase + (offset << p->regshift));
 371	dw8250_check_lcr(p, offset, value);
 372}
 373
 374static u32 dw8250_serial_in32(struct uart_port *p, unsigned int offset)
 375{
 376	u32 value = readl(p->membase + (offset << p->regshift));
 377
 378	return dw8250_modify_msr(p, offset, value);
 379}
 380
 381static void dw8250_serial_out32be(struct uart_port *p, unsigned int offset, u32 value)
 382{
 383	if (dw8250_can_skip_reg_write(p, offset, value))
 384		return;
 385
 386	iowrite32be(value, p->membase + (offset << p->regshift));
 387	dw8250_check_lcr(p, offset, value);
 388}
 389
 390static u32 dw8250_serial_in32be(struct uart_port *p, unsigned int offset)
 391{
 392       u32 value = ioread32be(p->membase + (offset << p->regshift));
 393
 394       return dw8250_modify_msr(p, offset, value);
 395}
 396
 397/*
 398 * INTC10EE UART can IRQ storm while reporting IIR_NO_INT. Inducing IIR value
 399 * change has been observed to break the storm.
 400 *
 401 * If Tx is empty (THRE asserted), we use here IER_THRI to cause IIR_NO_INT ->
 402 * IIR_THRI transition.
 403 */
 404static void dw8250_quirk_ier_kick(struct uart_port *p)
 405{
 406	struct uart_8250_port *up = up_to_u8250p(p);
 407	u32 lsr;
 408
 409	if (up->ier & UART_IER_THRI)
 410		return;
 411
 412	lsr = serial_lsr_in(up);
 413	if (!(lsr & UART_LSR_THRE))
 414		return;
 415
 416	serial_port_out(p, UART_IER, up->ier | UART_IER_THRI);
 417	serial_port_in(p, UART_LCR);		/* safe, no side-effects */
 418	serial_port_out(p, UART_IER, up->ier);
 419}
 420
 421static int dw8250_handle_irq(struct uart_port *p)
 422{
 423	struct uart_8250_port *up = up_to_u8250p(p);
 424	struct dw8250_data *d = to_dw8250_data(p->private_data);
 425	unsigned int iir = serial_port_in(p, UART_IIR);
 426	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
 427	unsigned int quirks = d->pdata->quirks;
 428	unsigned int status;
 429
 430	guard(uart_port_lock_irqsave)(p);
 431
 432	switch (FIELD_GET(DW_UART_IIR_IID, iir)) {
 433	case UART_IIR_NO_INT:
 434		if (d->uart_16550_compatible || up->dma)
 435			return 0;
 436
 437		if (quirks & DW_UART_QUIRK_IER_KICK &&
 438		    d->no_int_count == (DW_UART_QUIRK_IER_KICK_THRES - 1))
 439			dw8250_quirk_ier_kick(p);
 440		d->no_int_count = (d->no_int_count + 1) % DW_UART_QUIRK_IER_KICK_THRES;
 441
 442		return 0;
 443
 444	case UART_IIR_BUSY:
 445		/* Clear the USR */
 446		serial_port_in(p, d->pdata->usr_reg);
 447
 448		d->no_int_count = 0;
 449
 450		return 1;
 451	}
 452
 453	d->no_int_count = 0;
 454
 455	/*
 456	 * There are ways to get Designware-based UARTs into a state where
 457	 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
 458	 * data available.  If we see such a case then we'll do a bogus
 459	 * read.  If we don't do this then the "RX TIMEOUT" interrupt will
 460	 * fire forever.
 461	 *
 462	 * This problem has only been observed so far when not in DMA mode
 463	 * so we limit the workaround only to non-DMA mode.
 464	 */
 465	if (!up->dma && rx_timeout) {
 466		status = serial_lsr_in(up);
 467
 468		if (!(status & (UART_LSR_DR | UART_LSR_BI)))
 469			serial_port_in(p, UART_RX);
 470	}
 471
 472	/* Manually stop the Rx DMA transfer when acting as flow controller */
 473	if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
 474		status = serial_lsr_in(up);
 475
 476		if (status & (UART_LSR_DR | UART_LSR_BI)) {
 477			dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
 478			dw8250_writel_ext(p, DW_UART_DMASA, 1);
 479		}
 480	}
 481
 482	serial8250_handle_irq_locked(p, iir);
 483
 484	return 1;
 485}
 486
 487static void dw8250_clk_work_cb(struct work_struct *work)
 488{
 489	struct dw8250_data *d = work_to_dw8250_data(work);
 490	struct uart_8250_port *up;
 491	unsigned long rate;
 492
 493	rate = clk_get_rate(d->clk);
 494	if (rate <= 0)
 495		return;
 496
 497	up = serial8250_get_port(d->data.line);
 498
 499	serial8250_update_uartclk(&up->port, rate);
 500}
 501
 502static int dw8250_clk_notifier_cb(struct notifier_block *nb,
 503				  unsigned long event, void *data)
 504{
 505	struct dw8250_data *d = clk_to_dw8250_data(nb);
 506
 507	/*
 508	 * We have no choice but to defer the uartclk update due to two
 509	 * deadlocks. First one is caused by a recursive mutex lock which
 510	 * happens when clk_set_rate() is called from dw8250_set_termios().
 511	 * Second deadlock is more tricky and is caused by an inverted order of
 512	 * the clk and tty-port mutexes lock. It happens if clock rate change
 513	 * is requested asynchronously while set_termios() is executed between
 514	 * tty-port mutex lock and clk_set_rate() function invocation and
 515	 * vise-versa. Anyway if we didn't have the reference clock alteration
 516	 * in the dw8250_set_termios() method we wouldn't have needed this
 517	 * deferred event handling complication.
 518	 */
 519	if (event == POST_RATE_CHANGE) {
 520		queue_work(system_dfl_wq, &d->clk_work);
 521		return NOTIFY_OK;
 522	}
 523
 524	return NOTIFY_DONE;
 525}
 526
 527static void
 528dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 529{
 530	if (!state)
 531		pm_runtime_get_sync(port->dev);
 532
 533	serial8250_do_pm(port, state, old);
 534
 535	if (state)
 536		pm_runtime_put_sync_suspend(port->dev);
 537}
 538
 539static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
 540			       const struct ktermios *old)
 541{
 542	unsigned long newrate = tty_termios_baud_rate(termios) * 16;
 543	struct dw8250_data *d = to_dw8250_data(p->private_data);
 544	long rate;
 545	int ret;
 546
 547	clk_disable_unprepare(d->clk);
 548	rate = clk_round_rate(d->clk, newrate);
 549	if (rate > 0) {
 550		/*
 551		 * Note that any clock-notifier worker will block in
 552		 * serial8250_update_uartclk() until we are done.
 553		 */
 554		ret = clk_set_rate(d->clk, newrate);
 555		if (!ret)
 556			p->uartclk = rate;
 557	}
 558	clk_prepare_enable(d->clk);
 559
 560	dw8250_do_set_termios(p, termios, old);
 561}
 562
 563static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
 564{
 565	struct uart_8250_port *up = up_to_u8250p(p);
 566	unsigned int mcr = serial_port_in(p, UART_MCR);
 567
 568	if (up->capabilities & UART_CAP_IRDA) {
 569		if (termios->c_line == N_IRDA)
 570			mcr |= DW_UART_MCR_SIRE;
 571		else
 572			mcr &= ~DW_UART_MCR_SIRE;
 573
 574		serial_port_out(p, UART_MCR, mcr);
 575	}
 576	serial8250_do_set_ldisc(p, termios);
 577}
 578
 579/*
 580 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
 581 * channel on platforms that have DMA engines, but don't have any channels
 582 * assigned to the UART.
 583 *
 584 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
 585 * core problem is fixed, this function is no longer needed.
 586 */
 587static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
 588{
 589	return false;
 590}
 591
 592static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 593{
 594	return param == chan->device->dev;
 595}
 596
 597static void dw8250_setup_dma_filter(struct uart_port *p, struct dw8250_data *data)
 598{
 599	/* Platforms with iDMA 64-bit */
 600	if (platform_get_resource_byname(to_platform_device(p->dev), IORESOURCE_MEM, "lpss_priv")) {
 601		data->data.dma.rx_param = p->dev->parent;
 602		data->data.dma.tx_param = p->dev->parent;
 603		data->data.dma.fn = dw8250_idma_filter;
 604	} else {
 605		data->data.dma.fn = dw8250_fallback_dma_filter;
 606	}
 607}
 608
 609static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
 610{
 611	if (max_burst >= 8)
 612		return RZN1_UART_xDMACR_8_WORD_BURST;
 613	else if (max_burst >= 4)
 614		return RZN1_UART_xDMACR_4_WORD_BURST;
 615	else
 616		return RZN1_UART_xDMACR_1_WORD_BURST;
 617}
 618
 619static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
 620{
 621	struct uart_port *up = &p->port;
 622	struct uart_8250_dma *dma = p->dma;
 623	u32 val;
 624
 625	dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
 626	val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
 627	      RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
 628	      RZN1_UART_xDMACR_DMA_EN;
 629	dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
 630}
 631
 632static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
 633{
 634	struct uart_port *up = &p->port;
 635	struct uart_8250_dma *dma = p->dma;
 636	u32 val;
 637
 638	dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
 639	val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
 640	      RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
 641	      RZN1_UART_xDMACR_DMA_EN;
 642	dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
 643}
 644
 645static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 646{
 647	unsigned int quirks = data->pdata->quirks;
 648	u32 cpr_value = data->pdata->cpr_value;
 649
 650	if (quirks & DW_UART_QUIRK_CPR_VALUE)
 651		data->data.cpr_value = cpr_value;
 652
 653#ifdef CONFIG_64BIT
 654	if (quirks & DW_UART_QUIRK_OCTEON) {
 655		p->serial_in = dw8250_serial_inq;
 656		p->serial_out = dw8250_serial_outq;
 657		p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
 658		p->type = PORT_OCTEON;
 659		data->skip_autocfg = true;
 660	}
 661#endif
 662
 663	if (quirks & DW_UART_QUIRK_ARMADA_38X)
 664		p->serial_out = dw8250_serial_out38x;
 665	if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
 666		p->set_termios = dw8250_do_set_termios;
 667	if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
 668		data->data.dma.txconf.device_fc = 1;
 669		data->data.dma.rxconf.device_fc = 1;
 670		data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
 671		data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
 672	}
 673	if (quirks & DW_UART_QUIRK_APMC0D08) {
 674		p->iotype = UPIO_MEM32;
 675		p->regshift = 2;
 676		p->serial_in = dw8250_serial_in32;
 677		data->uart_16550_compatible = true;
 678	}
 679}
 680
 681static void dw8250_reset_control_assert(void *data)
 682{
 683	reset_control_assert(data);
 684}
 685
 686static void dw8250_shutdown(struct uart_port *port)
 687{
 688	struct dw8250_data *d = to_dw8250_data(port->private_data);
 689
 690	serial8250_do_shutdown(port);
 691	d->no_int_count = 0;
 692}
 693
 694static int dw8250_probe(struct platform_device *pdev)
 695{
 696	struct uart_8250_port uart = {}, *up = &uart;
 697	struct uart_port *p = &up->port;
 698	struct device *dev = &pdev->dev;
 699	struct dw8250_data *data;
 700	struct resource *regs;
 701	int err;
 702
 703	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 704	if (!regs)
 705		return dev_err_probe(dev, -EINVAL, "no registers defined\n");
 706
 707	spin_lock_init(&p->lock);
 708	p->pm		= dw8250_do_pm;
 709	p->type		= PORT_8250;
 710	p->flags	= UPF_FIXED_PORT;
 711	p->dev		= dev;
 712
 713	p->set_ldisc	= dw8250_set_ldisc;
 714	p->set_termios	= dw8250_set_termios;
 715	p->set_divisor	= dw8250_set_divisor;
 716
 717	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 718	if (!data)
 719		return -ENOMEM;
 720
 721	p->private_data = &data->data;
 722
 723	p->mapbase = regs->start;
 724	p->mapsize = resource_size(regs);
 725
 726	p->membase = devm_ioremap(dev, p->mapbase, p->mapsize);
 727	if (!p->membase)
 728		return -ENOMEM;
 729
 730	err = uart_read_port_properties(p);
 731	/* no interrupt -> fall back to polling */
 732	if (err == -ENXIO)
 733		err = 0;
 734	if (err)
 735		return err;
 736
 737	switch (p->iotype) {
 738	case UPIO_MEM:
 739		p->serial_in = dw8250_serial_in;
 740		p->serial_out = dw8250_serial_out;
 741		break;
 742	case UPIO_MEM32:
 743		p->serial_in = dw8250_serial_in32;
 744		p->serial_out = dw8250_serial_out32;
 745		break;
 746	case UPIO_MEM32BE:
 747		p->serial_in = dw8250_serial_in32be;
 748		p->serial_out = dw8250_serial_out32be;
 749		break;
 750	default:
 751		return -ENODEV;
 752	}
 753
 754	if (device_property_read_bool(dev, "dcd-override")) {
 755		/* Always report DCD as active */
 756		data->msr_mask_on |= UART_MSR_DCD;
 757		data->msr_mask_off |= UART_MSR_DDCD;
 758	}
 759
 760	if (device_property_read_bool(dev, "dsr-override")) {
 761		/* Always report DSR as active */
 762		data->msr_mask_on |= UART_MSR_DSR;
 763		data->msr_mask_off |= UART_MSR_DDSR;
 764	}
 765
 766	if (device_property_read_bool(dev, "cts-override")) {
 767		/* Always report CTS as active */
 768		data->msr_mask_on |= UART_MSR_CTS;
 769		data->msr_mask_off |= UART_MSR_DCTS;
 770	}
 771
 772	if (device_property_read_bool(dev, "ri-override")) {
 773		/* Always report Ring indicator as inactive */
 774		data->msr_mask_off |= UART_MSR_RI;
 775		data->msr_mask_off |= UART_MSR_TERI;
 776	}
 777
 778	/* If there is separate baudclk, get the rate from it. */
 779	data->clk = devm_clk_get_optional_enabled(dev, "baudclk");
 780	if (data->clk == NULL)
 781		data->clk = devm_clk_get_optional_enabled(dev, NULL);
 782	if (IS_ERR(data->clk))
 783		return dev_err_probe(dev, PTR_ERR(data->clk),
 784				     "failed to get baudclk\n");
 785
 786	INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
 787	data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
 788
 789	if (data->clk)
 790		p->uartclk = clk_get_rate(data->clk);
 791
 792	/* If no clock rate is defined, fail. */
 793	if (!p->uartclk)
 794		return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
 795
 796	data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk");
 797	if (IS_ERR(data->pclk))
 798		return PTR_ERR(data->pclk);
 799
 800	data->rst = devm_reset_control_array_get_optional_exclusive(dev);
 801	if (IS_ERR(data->rst))
 802		return PTR_ERR(data->rst);
 803
 804	err = reset_control_deassert(data->rst);
 805	if (err)
 806		return dev_err_probe(dev, err, "failed to deassert resets\n");
 807
 808	err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
 809	if (err)
 810		return err;
 811
 812	data->uart_16550_compatible = device_property_read_bool(dev, "snps,uart-16550-compatible");
 813
 814	data->pdata = device_get_match_data(p->dev);
 815	if (data->pdata)
 816		dw8250_quirks(p, data);
 817
 818	/* If the Busy Functionality is not implemented, don't handle it */
 819	if (data->uart_16550_compatible) {
 820		p->handle_irq = NULL;
 821	} else if (data->pdata) {
 822		p->handle_irq = dw8250_handle_irq;
 823		p->shutdown = dw8250_shutdown;
 824	}
 825
 826	dw8250_setup_dma_filter(p, data);
 827
 828	if (!data->skip_autocfg)
 829		dw8250_setup_port(p);
 830
 831	/* If we have a valid fifosize, try hooking up DMA */
 832	if (p->fifosize) {
 833		data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
 834		data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
 835		up->dma = &data->data.dma;
 836	}
 837
 838	data->data.line = serial8250_register_8250_port(up);
 839	if (data->data.line < 0)
 840		return data->data.line;
 841
 842	/*
 843	 * Some platforms may provide a reference clock shared between several
 844	 * devices. In this case any clock state change must be known to the
 845	 * UART port at least post factum.
 846	 */
 847	if (data->clk) {
 848		err = clk_notifier_register(data->clk, &data->clk_notifier);
 849		if (err)
 850			return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
 851		queue_work(system_dfl_wq, &data->clk_work);
 852	}
 853
 854	platform_set_drvdata(pdev, data);
 855
 856	pm_runtime_set_active(dev);
 857	pm_runtime_enable(dev);
 858
 859	return 0;
 860}
 861
 862static void dw8250_remove(struct platform_device *pdev)
 863{
 864	struct dw8250_data *data = platform_get_drvdata(pdev);
 865	struct device *dev = &pdev->dev;
 866
 867	pm_runtime_get_sync(dev);
 868
 869	if (data->clk) {
 870		clk_notifier_unregister(data->clk, &data->clk_notifier);
 871
 872		flush_work(&data->clk_work);
 873	}
 874
 875	serial8250_unregister_port(data->data.line);
 876
 877	pm_runtime_disable(dev);
 878	pm_runtime_put_noidle(dev);
 879}
 880
 881static int dw8250_suspend(struct device *dev)
 882{
 883	struct dw8250_data *data = dev_get_drvdata(dev);
 884
 885	serial8250_suspend_port(data->data.line);
 886
 887	return 0;
 888}
 889
 890static int dw8250_resume(struct device *dev)
 891{
 892	struct dw8250_data *data = dev_get_drvdata(dev);
 893
 894	serial8250_resume_port(data->data.line);
 895
 896	return 0;
 897}
 898
 899static int dw8250_runtime_suspend(struct device *dev)
 900{
 901	struct dw8250_data *data = dev_get_drvdata(dev);
 902
 903	clk_disable_unprepare(data->clk);
 904
 905	clk_disable_unprepare(data->pclk);
 906
 907	return 0;
 908}
 909
 910static int dw8250_runtime_resume(struct device *dev)
 911{
 912	int ret;
 913	struct dw8250_data *data = dev_get_drvdata(dev);
 914
 915	ret = clk_prepare_enable(data->pclk);
 916	if (ret)
 917		return ret;
 918
 919	ret = clk_prepare_enable(data->clk);
 920	if (ret) {
 921		clk_disable_unprepare(data->pclk);
 922		return ret;
 923	}
 924
 925	return 0;
 926}
 927
 928static const struct dev_pm_ops dw8250_pm_ops = {
 929	SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 930	RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 931};
 932
 933static const struct dw8250_platform_data dw8250_dw_apb = {
 934	.usr_reg = DW_UART_USR,
 935};
 936
 937static const struct dw8250_platform_data dw8250_octeon_3860_data = {
 938	.usr_reg = OCTEON_UART_USR,
 939	.quirks = DW_UART_QUIRK_OCTEON,
 940};
 941
 942static const struct dw8250_platform_data dw8250_armada_38x_data = {
 943	.usr_reg = DW_UART_USR,
 944	.quirks = DW_UART_QUIRK_ARMADA_38X,
 945};
 946
 947static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
 948	.usr_reg = DW_UART_USR,
 949	.cpr_value = 0x00012f32,
 950	.quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,
 951};
 952
 953static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
 954	.usr_reg = DW_UART_USR,
 955	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
 956};
 957
 958static const struct dw8250_platform_data dw8250_intc10ee = {
 959	.usr_reg = DW_UART_USR,
 960	.quirks = DW_UART_QUIRK_IER_KICK,
 961};
 962
 963static const struct of_device_id dw8250_of_match[] = {
 964	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
 965	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
 966	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
 967	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
 968	{ .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
 969	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
 970	{ /* Sentinel */ }
 971};
 972MODULE_DEVICE_TABLE(of, dw8250_of_match);
 973
 974static const struct dw8250_platform_data dw8250_apmc0d08 = {
 975	.usr_reg = DW_UART_USR,
 976	.quirks = DW_UART_QUIRK_APMC0D08,
 977};
 978
 979static const struct acpi_device_id dw8250_acpi_match[] = {
 980	{ "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
 981	{ "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
 982	{ "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
 983	{ "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
 984	{ "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
 985	{ "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 },
 986	{ "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
 987	{ "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
 988	{ "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
 989	{ "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
 990	{ "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
 991	{ "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
 992	{ "INTC10EE", (kernel_ulong_t)&dw8250_intc10ee },
 993	{ },
 994};
 995MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 996
 997static struct platform_driver dw8250_platform_driver = {
 998	.driver = {
 999		.name		= "dw-apb-uart",
1000		.pm		= pm_ptr(&dw8250_pm_ops),
1001		.of_match_table	= dw8250_of_match,
1002		.acpi_match_table = dw8250_acpi_match,
1003	},
1004	.probe			= dw8250_probe,
1005	.remove			= dw8250_remove,
1006};
1007
1008module_platform_driver(dw8250_platform_driver);
1009
1010MODULE_IMPORT_NS("SERIAL_8250");
1011MODULE_AUTHOR("Jamie Iles");
1012MODULE_LICENSE("GPL");
1013MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
1014MODULE_ALIAS("platform:dw-apb-uart");