lc.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Thunderbolt link controller support
  4 *
  5 * Copyright (C) 2019, Intel Corporation
  6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7 */
  8
  9#include <linux/delay.h>
 10
 11#include "tb.h"
 12
 13/**
 14 * tb_lc_read_uuid() - Read switch UUID from link controller common register
 15 * @sw: Switch whose UUID is read
 16 * @uuid: UUID is placed here
 17 *
 18 * Return: %0 on success, negative errno otherwise.
 19 */
 20int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid)
 21{
 22	if (!sw->cap_lc)
 23		return -EINVAL;
 24	return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);
 25}
 26
 27static int read_lc_desc(struct tb_switch *sw, u32 *desc)
 28{
 29	if (!sw->cap_lc)
 30		return -EINVAL;
 31	return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);
 32}
 33
 34static int find_port_lc_cap(struct tb_port *port)
 35{
 36	struct tb_switch *sw = port->sw;
 37	int start, phys, ret, size;
 38	u32 desc;
 39
 40	ret = read_lc_desc(sw, &desc);
 41	if (ret)
 42		return ret;
 43
 44	/* Start of port LC registers */
 45	start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
 46	size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
 47	phys = tb_phy_port_from_link(port->port);
 48
 49	return sw->cap_lc + start + phys * size;
 50}
 51
 52/**
 53 * tb_lc_reset_port() - Trigger downstream port reset through LC
 54 * @port: Port that is reset
 55 *
 56 * Triggers downstream port reset through link controller registers.
 57 * Only supports non-USB4 routers with link controller (that's
 58 * Thunderbolt 2 and Thunderbolt 3).
 59 *
 60 * Return: %0 on success, negative errno otherwise.
 61 */
 62int tb_lc_reset_port(struct tb_port *port)
 63{
 64	struct tb_switch *sw = port->sw;
 65	int cap, ret;
 66	u32 mode;
 67
 68	if (sw->generation < 2)
 69		return -EINVAL;
 70
 71	cap = find_port_lc_cap(port);
 72	if (cap < 0)
 73		return cap;
 74
 75	ret = tb_sw_read(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
 76	if (ret)
 77		return ret;
 78
 79	mode |= TB_LC_PORT_MODE_DPR;
 80
 81	ret = tb_sw_write(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
 82	if (ret)
 83		return ret;
 84
 85	fsleep(10000);
 86
 87	ret = tb_sw_read(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
 88	if (ret)
 89		return ret;
 90
 91	mode &= ~TB_LC_PORT_MODE_DPR;
 92
 93	return tb_sw_write(sw, &mode, TB_CFG_SWITCH, cap + TB_LC_PORT_MODE, 1);
 94}
 95
 96static int tb_lc_set_port_configured(struct tb_port *port, bool configured)
 97{
 98	bool upstream = tb_is_upstream_port(port);
 99	struct tb_switch *sw = port->sw;
100	u32 ctrl, lane;
101	int cap, ret;
102
103	if (sw->generation < 2)
104		return 0;
105
106	cap = find_port_lc_cap(port);
107	if (cap < 0)
108		return cap;
109
110	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
111	if (ret)
112		return ret;
113
114	/* Resolve correct lane */
115	if (port->port % 2)
116		lane = TB_LC_SX_CTRL_L1C;
117	else
118		lane = TB_LC_SX_CTRL_L2C;
119
120	if (configured) {
121		ctrl |= lane;
122		if (upstream)
123			ctrl |= TB_LC_SX_CTRL_UPSTREAM;
124	} else {
125		ctrl &= ~lane;
126		if (upstream)
127			ctrl &= ~TB_LC_SX_CTRL_UPSTREAM;
128	}
129
130	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
131}
132
133/**
134 * tb_lc_configure_port() - Let LC know about configured port
135 * @port: Port that is set as configured
136 *
137 * Sets the port configured for power management purposes.
138 *
139 * Return: %0 on success, negative errno otherwise.
140 */
141int tb_lc_configure_port(struct tb_port *port)
142{
143	return tb_lc_set_port_configured(port, true);
144}
145
146/**
147 * tb_lc_unconfigure_port() - Let LC know about unconfigured port
148 * @port: Port that is set as configured
149 *
150 * Sets the port unconfigured for power management purposes.
151 *
152 * Return: %0 on success, negative errno otherwise.
153 */
154void tb_lc_unconfigure_port(struct tb_port *port)
155{
156	tb_lc_set_port_configured(port, false);
157}
158
159static int tb_lc_set_xdomain_configured(struct tb_port *port, bool configure)
160{
161	struct tb_switch *sw = port->sw;
162	u32 ctrl, lane;
163	int cap, ret;
164
165	if (sw->generation < 2)
166		return 0;
167
168	cap = find_port_lc_cap(port);
169	if (cap < 0)
170		return cap;
171
172	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
173	if (ret)
174		return ret;
175
176	/* Resolve correct lane */
177	if (port->port % 2)
178		lane = TB_LC_SX_CTRL_L1D;
179	else
180		lane = TB_LC_SX_CTRL_L2D;
181
182	if (configure)
183		ctrl |= lane;
184	else
185		ctrl &= ~lane;
186
187	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
188}
189
190/**
191 * tb_lc_configure_xdomain() - Inform LC that the link is XDomain
192 * @port: Switch downstream port connected to another host
193 *
194 * Sets the lane configured for XDomain accordingly so that LC knows
195 * about this.
196 *
197 * Return: %0 on success, negative errno otherwise.
198 */
199int tb_lc_configure_xdomain(struct tb_port *port)
200{
201	return tb_lc_set_xdomain_configured(port, true);
202}
203
204/**
205 * tb_lc_unconfigure_xdomain() - Unconfigure XDomain from port
206 * @port: Switch downstream port that was connected to another host
207 *
208 * Unsets the lane XDomain configuration.
209 */
210void tb_lc_unconfigure_xdomain(struct tb_port *port)
211{
212	tb_lc_set_xdomain_configured(port, false);
213}
214
215/**
216 * tb_lc_start_lane_initialization() - Start lane initialization
217 * @port: Device router lane 0 adapter
218 *
219 * Starts lane initialization for @port after the router resumed from
220 * sleep. Should be called for those downstream lane adapters that were
221 * not connected (tb_lc_configure_port() was not called) before sleep.
222 *
223 * Return: %0 on success, negative errno otherwise.
224 */
225int tb_lc_start_lane_initialization(struct tb_port *port)
226{
227	struct tb_switch *sw = port->sw;
228	int ret, cap;
229	u32 ctrl;
230
231	if (!tb_route(sw))
232		return 0;
233
234	if (sw->generation < 2)
235		return 0;
236
237	cap = find_port_lc_cap(port);
238	if (cap < 0)
239		return cap;
240
241	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
242	if (ret)
243		return ret;
244
245	ctrl |= TB_LC_SX_CTRL_SLI;
246
247	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
248}
249
250/**
251 * tb_lc_is_clx_supported() - Check whether CLx is supported by the lane adapter
252 * @port: Lane adapter
253 *
254 * TB_LC_LINK_ATTR_CPS bit reflects if the link supports CLx including
255 * active cables (if connected on the link).
256 *
257 * Return: %true if CLx is supported, %false otherwise.
258 */
259bool tb_lc_is_clx_supported(struct tb_port *port)
260{
261	struct tb_switch *sw = port->sw;
262	int cap, ret;
263	u32 val;
264
265	cap = find_port_lc_cap(port);
266	if (cap < 0)
267		return false;
268
269	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_ATTR, 1);
270	if (ret)
271		return false;
272
273	return !!(val & TB_LC_LINK_ATTR_CPS);
274}
275
276/**
277 * tb_lc_is_usb_plugged() - Is there USB device connected to port
278 * @port: Device router lane 0 adapter
279 *
280 * Return: %true if the @port has USB Type-C device connected, %false
281 * otherwise.
282 */
283bool tb_lc_is_usb_plugged(struct tb_port *port)
284{
285	struct tb_switch *sw = port->sw;
286	int cap, ret;
287	u32 val;
288
289	if (sw->generation != 3)
290		return false;
291
292	cap = find_port_lc_cap(port);
293	if (cap < 0)
294		return false;
295
296	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_CS_42, 1);
297	if (ret)
298		return false;
299
300	return !!(val & TB_LC_CS_42_USB_PLUGGED);
301}
302
303/**
304 * tb_lc_is_xhci_connected() - Is the internal xHCI connected
305 * @port: Device router lane 0 adapter
306 *
307 * Return: %true if the internal xHCI has been connected to
308 * @port, %false otherwise.
309 */
310bool tb_lc_is_xhci_connected(struct tb_port *port)
311{
312	struct tb_switch *sw = port->sw;
313	int cap, ret;
314	u32 val;
315
316	if (sw->generation != 3)
317		return false;
318
319	cap = find_port_lc_cap(port);
320	if (cap < 0)
321		return false;
322
323	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1);
324	if (ret)
325		return false;
326
327	return !!(val & TB_LC_LINK_REQ_XHCI_CONNECT);
328}
329
330static int __tb_lc_xhci_connect(struct tb_port *port, bool connect)
331{
332	struct tb_switch *sw = port->sw;
333	int cap, ret;
334	u32 val;
335
336	if (sw->generation != 3)
337		return -EINVAL;
338
339	cap = find_port_lc_cap(port);
340	if (cap < 0)
341		return cap;
342
343	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1);
344	if (ret)
345		return ret;
346
347	if (connect)
348		val |= TB_LC_LINK_REQ_XHCI_CONNECT;
349	else
350		val &= ~TB_LC_LINK_REQ_XHCI_CONNECT;
351
352	return tb_sw_write(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1);
353}
354
355/**
356 * tb_lc_xhci_connect() - Connect internal xHCI
357 * @port: Device router lane 0 adapter
358 *
359 * Tells LC to connect the internal xHCI to @port. Can be called for
360 * Thunderbolt 3 routers only.
361 *
362 * Return: %0 on success, negative errno otherwise.
363 */
364int tb_lc_xhci_connect(struct tb_port *port)
365{
366	int ret;
367
368	ret = __tb_lc_xhci_connect(port, true);
369	if (ret)
370		return ret;
371
372	tb_port_dbg(port, "xHCI connected\n");
373	return 0;
374}
375
376/**
377 * tb_lc_xhci_disconnect() - Disconnect internal xHCI
378 * @port: Device router lane 0 adapter
379 *
380 * Tells LC to disconnect the internal xHCI from @port. Can be called
381 * for Thunderbolt 3 routers only.
382 */
383void tb_lc_xhci_disconnect(struct tb_port *port)
384{
385	__tb_lc_xhci_connect(port, false);
386	tb_port_dbg(port, "xHCI disconnected\n");
387}
388
389static int tb_lc_set_wake_one(struct tb_switch *sw, unsigned int offset,
390			      unsigned int flags)
391{
392	u32 ctrl;
393	int ret;
394
395	/*
396	 * Enable wake on PCIe and USB4 (wake coming from another
397	 * router).
398	 */
399	ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
400			 offset + TB_LC_SX_CTRL, 1);
401	if (ret)
402		return ret;
403
404	ctrl &= ~(TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD | TB_LC_SX_CTRL_WODPC |
405		  TB_LC_SX_CTRL_WODPD | TB_LC_SX_CTRL_WOP | TB_LC_SX_CTRL_WOU4);
406
407	if (flags & TB_WAKE_ON_CONNECT)
408		ctrl |= TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD;
409	if (flags & TB_WAKE_ON_USB4)
410		ctrl |= TB_LC_SX_CTRL_WOU4;
411	if (flags & TB_WAKE_ON_PCIE)
412		ctrl |= TB_LC_SX_CTRL_WOP;
413	if (flags & TB_WAKE_ON_DP)
414		ctrl |= TB_LC_SX_CTRL_WODPC | TB_LC_SX_CTRL_WODPD;
415
416	return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, offset + TB_LC_SX_CTRL, 1);
417}
418
419/**
420 * tb_lc_set_wake() - Enable/disable wake
421 * @sw: Switch whose wakes to configure
422 * @flags: Wakeup flags (%0 to disable)
423 *
424 * For each LC sets wake bits accordingly.
425 *
426 * Return: %0 on success, negative errno otherwise.
427 */
428int tb_lc_set_wake(struct tb_switch *sw, unsigned int flags)
429{
430	int start, size, nlc, ret, i;
431	u32 desc;
432
433	if (sw->generation < 2)
434		return 0;
435
436	if (!tb_route(sw))
437		return 0;
438
439	ret = read_lc_desc(sw, &desc);
440	if (ret)
441		return ret;
442
443	/* Figure out number of link controllers */
444	nlc = desc & TB_LC_DESC_NLC_MASK;
445	start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
446	size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
447
448	/* For each link controller set sleep bit */
449	for (i = 0; i < nlc; i++) {
450		unsigned int offset = sw->cap_lc + start + i * size;
451
452		ret = tb_lc_set_wake_one(sw, offset, flags);
453		if (ret)
454			return ret;
455	}
456
457	return 0;
458}
459
460/**
461 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep
462 * @sw: Switch to set sleep
463 *
464 * Let the switch link controllers know that the switch is going to
465 * sleep.
466 *
467 * Return: %0 on success, negative errno otherwise.
468 */
469int tb_lc_set_sleep(struct tb_switch *sw)
470{
471	int start, size, nlc, ret, i;
472	u32 desc;
473
474	if (sw->generation < 2)
475		return 0;
476
477	ret = read_lc_desc(sw, &desc);
478	if (ret)
479		return ret;
480
481	/* Figure out number of link controllers */
482	nlc = desc & TB_LC_DESC_NLC_MASK;
483	start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
484	size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
485
486	/* For each link controller set sleep bit */
487	for (i = 0; i < nlc; i++) {
488		unsigned int offset = sw->cap_lc + start + i * size;
489		u32 ctrl;
490
491		ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
492				 offset + TB_LC_SX_CTRL, 1);
493		if (ret)
494			return ret;
495
496		ctrl |= TB_LC_SX_CTRL_SLP;
497		ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH,
498				  offset + TB_LC_SX_CTRL, 1);
499		if (ret)
500			return ret;
501	}
502
503	return 0;
504}
505
506/**
507 * tb_lc_lane_bonding_possible() - Is lane bonding possible towards switch
508 * @sw: Switch to check
509 *
510 * Checks whether conditions for lane bonding from parent to @sw are
511 * possible.
512 *
513 * Return: %true if lane bonding is possible, %false otherwise.
514 */
515bool tb_lc_lane_bonding_possible(struct tb_switch *sw)
516{
517	struct tb_port *up;
518	int cap, ret;
519	u32 val;
520
521	if (sw->generation < 2)
522		return false;
523
524	up = tb_upstream_port(sw);
525	cap = find_port_lc_cap(up);
526	if (cap < 0)
527		return false;
528
529	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_PORT_ATTR, 1);
530	if (ret)
531		return false;
532
533	return !!(val & TB_LC_PORT_ATTR_BE);
534}
535
536static int tb_lc_dp_sink_from_port(const struct tb_switch *sw,
537				   struct tb_port *in)
538{
539	struct tb_port *port;
540
541	/* The first DP IN port is sink 0 and second is sink 1 */
542	tb_switch_for_each_port(sw, port) {
543		if (tb_port_is_dpin(port))
544			return in != port;
545	}
546
547	return -EINVAL;
548}
549
550static int tb_lc_dp_sink_available(struct tb_switch *sw, int sink)
551{
552	u32 val, alloc;
553	int ret;
554
555	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
556			 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
557	if (ret)
558		return ret;
559
560	/*
561	 * Sink is available for CM/SW to use if the allocation value is
562	 * either 0 or 1.
563	 */
564	if (!sink) {
565		alloc = val & TB_LC_SNK_ALLOCATION_SNK0_MASK;
566		if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK0_CM)
567			return 0;
568	} else {
569		alloc = (val & TB_LC_SNK_ALLOCATION_SNK1_MASK) >>
570			TB_LC_SNK_ALLOCATION_SNK1_SHIFT;
571		if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK1_CM)
572			return 0;
573	}
574
575	return -EBUSY;
576}
577
578/**
579 * tb_lc_dp_sink_query() - Is DP sink available for DP IN port
580 * @sw: Switch whose DP sink is queried
581 * @in: DP IN port to check
582 *
583 * Queries through LC SNK_ALLOCATION registers whether DP sink is available
584 * for the given DP IN port or not.
585 *
586 * Return: %true if DP sink is available, %false otherwise.
587 */
588bool tb_lc_dp_sink_query(struct tb_switch *sw, struct tb_port *in)
589{
590	int sink;
591
592	/*
593	 * For older generations sink is always available as there is no
594	 * allocation mechanism.
595	 */
596	if (sw->generation < 3)
597		return true;
598
599	sink = tb_lc_dp_sink_from_port(sw, in);
600	if (sink < 0)
601		return false;
602
603	return !tb_lc_dp_sink_available(sw, sink);
604}
605
606/**
607 * tb_lc_dp_sink_alloc() - Allocate DP sink
608 * @sw: Switch whose DP sink is allocated
609 * @in: DP IN port the DP sink is allocated for
610 *
611 * Allocate DP sink for @in via LC SNK_ALLOCATION registers.
612 *
613 * Return:
614 * * %0 - If the resource is available and allocation is successful.
615 * * %-EBUSY - If resource is not available.
616 * * Negative errno - Another error occurred.
617 */
618int tb_lc_dp_sink_alloc(struct tb_switch *sw, struct tb_port *in)
619{
620	int ret, sink;
621	u32 val;
622
623	if (sw->generation < 3)
624		return 0;
625
626	sink = tb_lc_dp_sink_from_port(sw, in);
627	if (sink < 0)
628		return sink;
629
630	ret = tb_lc_dp_sink_available(sw, sink);
631	if (ret)
632		return ret;
633
634	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
635			 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
636	if (ret)
637		return ret;
638
639	if (!sink) {
640		val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK;
641		val |= TB_LC_SNK_ALLOCATION_SNK0_CM;
642	} else {
643		val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK;
644		val |= TB_LC_SNK_ALLOCATION_SNK1_CM <<
645			TB_LC_SNK_ALLOCATION_SNK1_SHIFT;
646	}
647
648	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
649			  sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
650
651	if (ret)
652		return ret;
653
654	tb_port_dbg(in, "sink %d allocated\n", sink);
655	return 0;
656}
657
658/**
659 * tb_lc_dp_sink_dealloc() - De-allocate DP sink
660 * @sw: Switch whose DP sink is de-allocated
661 * @in: DP IN port whose DP sink is de-allocated
662 *
663 * De-allocate DP sink from @in using LC SNK_ALLOCATION registers.
664 *
665 * Return: %0 on success, negative errno otherwise.
666 */
667int tb_lc_dp_sink_dealloc(struct tb_switch *sw, struct tb_port *in)
668{
669	int ret, sink;
670	u32 val;
671
672	if (sw->generation < 3)
673		return 0;
674
675	sink = tb_lc_dp_sink_from_port(sw, in);
676	if (sink < 0)
677		return sink;
678
679	/* Needs to be owned by CM/SW */
680	ret = tb_lc_dp_sink_available(sw, sink);
681	if (ret)
682		return ret;
683
684	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
685			 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
686	if (ret)
687		return ret;
688
689	if (!sink)
690		val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK;
691	else
692		val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK;
693
694	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
695			  sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
696	if (ret)
697		return ret;
698
699	tb_port_dbg(in, "sink %d de-allocated\n", sink);
700	return 0;
701}
702
703/**
704 * tb_lc_force_power() - Forces LC to be powered on
705 * @sw: Thunderbolt switch
706 *
707 * This is useful to let authentication cycle pass even without
708 * a Thunderbolt link present.
709 *
710 * Return: %0 on success, negative errno otherwise.
711 */
712int tb_lc_force_power(struct tb_switch *sw)
713{
714	u32 in = 0xffff;
715
716	return tb_sw_write(sw, &in, TB_CFG_SWITCH, TB_LC_POWER, 1);
717}