rockchip_thermal.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
   4 * Caesar Wang <wxt@rock-chips.com>
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/delay.h>
   9#include <linux/interrupt.h>
  10#include <linux/io.h>
  11#include <linux/module.h>
  12#include <linux/nvmem-consumer.h>
  13#include <linux/of.h>
  14#include <linux/of_address.h>
  15#include <linux/of_irq.h>
  16#include <linux/platform_device.h>
  17#include <linux/regmap.h>
  18#include <linux/reset.h>
  19#include <linux/thermal.h>
  20#include <linux/mfd/syscon.h>
  21#include <linux/pinctrl/consumer.h>
  22
  23/*
  24 * If the temperature over a period of time High,
  25 * the resulting TSHUT gave CRU module,let it reset the entire chip,
  26 * or via GPIO give PMIC.
  27 */
  28enum tshut_mode {
  29	TSHUT_MODE_CRU = 0,
  30	TSHUT_MODE_GPIO,
  31};
  32
  33/*
  34 * The system Temperature Sensors tshut(tshut) polarity
  35 * the bit 8 is tshut polarity.
  36 * 0: low active, 1: high active
  37 */
  38enum tshut_polarity {
  39	TSHUT_LOW_ACTIVE = 0,
  40	TSHUT_HIGH_ACTIVE,
  41};
  42
  43/*
  44 * The conversion table has the adc value and temperature.
  45 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
  46 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
  47 */
  48enum adc_sort_mode {
  49	ADC_DECREMENT = 0,
  50	ADC_INCREMENT,
  51};
  52
  53#include "thermal_hwmon.h"
  54
  55/**
  56 * struct chip_tsadc_table - hold information about chip-specific differences
  57 * @id: conversion table
  58 * @length: size of conversion table
  59 * @data_mask: mask to apply on data inputs
  60 * @mode: sort mode of this adc variant (incrementing or decrementing)
  61 */
  62struct chip_tsadc_table {
  63	const struct tsadc_table *id;
  64	unsigned int length;
  65	u32 data_mask;
  66	enum adc_sort_mode mode;
  67};
  68
  69/**
  70 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
  71 * @chn_offset: the channel offset of the first channel
  72 * @chn_num: the channel number of tsadc chip
  73 * @trim_slope: used to convert the trim code to a temperature in millicelsius
  74 * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim
  75 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
  76 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
  77 * @grf_required: true, if a GRF is required for proper functionality
  78 * @initialize: SoC special initialize tsadc controller method
  79 * @irq_ack: clear the interrupt
  80 * @control: enable/disable method for the tsadc controller
  81 * @get_temp: get the raw temperature, unadjusted by trim
  82 * @set_alarm_temp: set the high temperature interrupt
  83 * @set_tshut_temp: set the hardware-controlled shutdown temperature
  84 * @set_tshut_mode: set the hardware-controlled shutdown mode
  85 * @get_trim_code: convert a hardware temperature code to one adjusted for by trim
  86 * @table: the chip-specific conversion table
  87 */
  88struct rockchip_tsadc_chip {
  89	/* The sensor id of chip correspond to the ADC channel */
  90	int chn_offset;
  91	int chn_num;
  92
  93	/* Used to convert trim code to trim temp */
  94	int trim_slope;
  95
  96	/* The hardware-controlled tshut property */
  97	int tshut_temp;
  98	enum tshut_mode tshut_mode;
  99	enum tshut_polarity tshut_polarity;
 100
 101	/* GRF availability */
 102	bool grf_required;
 103
 104	/* Chip-wide methods */
 105	void (*initialize)(struct regmap *grf,
 106			   void __iomem *reg, enum tshut_polarity p);
 107	void (*irq_ack)(void __iomem *reg);
 108	void (*control)(void __iomem *reg, bool on);
 109
 110	/* Per-sensor methods */
 111	int (*get_temp)(const struct chip_tsadc_table *table,
 112			int chn, void __iomem *reg, int *temp);
 113	int (*set_alarm_temp)(const struct chip_tsadc_table *table,
 114			      int chn, void __iomem *reg, int temp);
 115	int (*set_tshut_temp)(const struct chip_tsadc_table *table,
 116			      int chn, void __iomem *reg, int temp);
 117	void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
 118	int (*get_trim_code)(const struct chip_tsadc_table *table,
 119			     int code, int trim_base, int trim_base_frac);
 120
 121	/* Per-table methods */
 122	struct chip_tsadc_table table;
 123};
 124
 125/**
 126 * struct rockchip_thermal_sensor - hold the information of thermal sensor
 127 * @thermal:  pointer to the platform/configuration data
 128 * @tzd: pointer to a thermal zone
 129 * @of_node: pointer to the device_node representing this sensor, if any
 130 * @id: identifier of the thermal sensor
 131 * @trim_temp: per-sensor trim temperature value
 132 */
 133struct rockchip_thermal_sensor {
 134	struct rockchip_thermal_data *thermal;
 135	struct thermal_zone_device *tzd;
 136	struct device_node *of_node;
 137	int id;
 138	int trim_temp;
 139};
 140
 141/**
 142 * struct rockchip_thermal_data - hold the private data of thermal driver
 143 * @chip: pointer to the platform/configuration data
 144 * @pdev: platform device of thermal
 145 * @reset: the reset controller of tsadc
 146 * @sensors: array of thermal sensors
 147 * @clk: the controller clock is divided by the exteral 24MHz
 148 * @pclk: the advanced peripherals bus clock
 149 * @grf: the general register file will be used to do static set by software
 150 * @regs: the base address of tsadc controller
 151 * @trim_base: major component of sensor trim value, in Celsius
 152 * @trim_base_frac: minor component of sensor trim value, in Decicelsius
 153 * @trim: fallback thermal trim value for each channel
 154 * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim
 155 * @trim_temp: the fallback trim temperature for the whole sensor
 156 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
 157 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
 158 */
 159struct rockchip_thermal_data {
 160	const struct rockchip_tsadc_chip *chip;
 161	struct platform_device *pdev;
 162	struct reset_control *reset;
 163
 164	struct rockchip_thermal_sensor *sensors;
 165
 166	struct clk *clk;
 167	struct clk *pclk;
 168
 169	struct regmap *grf;
 170	void __iomem *regs;
 171
 172	int trim_base;
 173	int trim_base_frac;
 174	int trim;
 175
 176	int tshut_temp;
 177	int trim_temp;
 178	enum tshut_mode tshut_mode;
 179	enum tshut_polarity tshut_polarity;
 180};
 181
 182/*
 183 * TSADC Sensor Register description:
 184 *
 185 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
 186 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
 187 *
 188 */
 189#define TSADCV2_USER_CON			0x00
 190#define TSADCV2_AUTO_CON			0x04
 191#define TSADCV2_INT_EN				0x08
 192#define TSADCV2_INT_PD				0x0c
 193#define TSADCV3_AUTO_SRC_CON			0x0c
 194#define TSADCV3_HT_INT_EN			0x14
 195#define TSADCV3_HSHUT_GPIO_INT_EN		0x18
 196#define TSADCV3_HSHUT_CRU_INT_EN		0x1c
 197#define TSADCV3_INT_PD				0x24
 198#define TSADCV3_HSHUT_PD			0x28
 199#define TSADCV2_DATA(chn)			(0x20 + (chn) * 0x04)
 200#define TSADCV2_COMP_INT(chn)		        (0x30 + (chn) * 0x04)
 201#define TSADCV2_COMP_SHUT(chn)		        (0x40 + (chn) * 0x04)
 202#define TSADCV3_DATA(chn)			(0x2c + (chn) * 0x04)
 203#define TSADCV3_COMP_INT(chn)		        (0x6c + (chn) * 0x04)
 204#define TSADCV3_COMP_SHUT(chn)		        (0x10c + (chn) * 0x04)
 205#define TSADCV2_HIGHT_INT_DEBOUNCE		0x60
 206#define TSADCV2_HIGHT_TSHUT_DEBOUNCE		0x64
 207#define TSADCV3_HIGHT_INT_DEBOUNCE		0x14c
 208#define TSADCV3_HIGHT_TSHUT_DEBOUNCE		0x150
 209#define TSADCV2_AUTO_PERIOD			0x68
 210#define TSADCV2_AUTO_PERIOD_HT			0x6c
 211#define TSADCV3_AUTO_PERIOD			0x154
 212#define TSADCV3_AUTO_PERIOD_HT			0x158
 213
 214#define TSADCV2_AUTO_EN				BIT(0)
 215#define TSADCV2_AUTO_EN_MASK			BIT(16)
 216#define TSADCV2_AUTO_SRC_EN(chn)		BIT(4 + (chn))
 217#define TSADCV3_AUTO_SRC_EN(chn)		BIT(chn)
 218#define TSADCV3_AUTO_SRC_EN_MASK(chn)		BIT(16 + chn)
 219#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH	BIT(8)
 220#define TSADCV2_AUTO_TSHUT_POLARITY_MASK	BIT(24)
 221
 222#define TSADCV3_AUTO_Q_SEL_EN			BIT(1)
 223
 224#define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
 225#define TSADCV2_INT_SRC_EN_MASK(chn)		BIT(16 + (chn))
 226#define TSADCV2_SHUT_2GPIO_SRC_EN(chn)		BIT(4 + (chn))
 227#define TSADCV2_SHUT_2CRU_SRC_EN(chn)		BIT(8 + (chn))
 228
 229#define TSADCV2_INT_PD_CLEAR_MASK		~BIT(8)
 230#define TSADCV3_INT_PD_CLEAR_MASK		~BIT(16)
 231#define TSADCV4_INT_PD_CLEAR_MASK		0xffffffff
 232
 233#define TSADCV2_DATA_MASK			0xfff
 234#define TSADCV3_DATA_MASK			0x3ff
 235#define TSADCV4_DATA_MASK			0x1ff
 236
 237#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4
 238#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT	4
 239#define TSADCV2_AUTO_PERIOD_TIME		250 /* 250ms */
 240#define TSADCV2_AUTO_PERIOD_HT_TIME		50  /* 50ms */
 241#define TSADCV3_AUTO_PERIOD_TIME		1875 /* 2.5ms */
 242#define TSADCV3_AUTO_PERIOD_HT_TIME		1875 /* 2.5ms */
 243
 244#define TSADCV5_AUTO_PERIOD_TIME		1622 /* 2.5ms */
 245#define TSADCV5_AUTO_PERIOD_HT_TIME		1622 /* 2.5ms */
 246#define TSADCV6_AUTO_PERIOD_TIME		5000 /* 2.5ms */
 247#define TSADCV6_AUTO_PERIOD_HT_TIME		5000 /* 2.5ms */
 248
 249#define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
 250#define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
 251
 252#define GRF_SARADC_TESTBIT			0x0e644
 253#define GRF_TSADC_TESTBIT_L			0x0e648
 254#define GRF_TSADC_TESTBIT_H			0x0e64c
 255
 256#define PX30_GRF_SOC_CON2			0x0408
 257
 258#define RK3568_GRF_TSADC_CON			0x0600
 259#define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
 260#define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
 261#define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
 262#define RK3568_GRF_TSADC_TSEN			(0x10001 << 8)
 263
 264#define RK3588_GRF0_TSADC_CON			0x0100
 265
 266#define RK3588_GRF0_TSADC_TRM			(0xff0077 << 0)
 267#define RK3588_GRF0_TSADC_SHUT_2CRU		(0x30003 << 10)
 268#define RK3588_GRF0_TSADC_SHUT_2GPIO		(0x70007 << 12)
 269
 270#define GRF_SARADC_TESTBIT_ON			(0x10001 << 2)
 271#define GRF_TSADC_TESTBIT_H_ON			(0x10001 << 2)
 272#define GRF_TSADC_VCM_EN_L			(0x10001 << 7)
 273#define GRF_TSADC_VCM_EN_H			(0x10001 << 7)
 274
 275#define GRF_CON_TSADC_CH_INV			(0x10001 << 1)
 276
 277
 278#define RK_MAX_TEMP				(180000)
 279
 280/**
 281 * struct tsadc_table - code to temperature conversion table
 282 * @code: the value of adc channel
 283 * @temp: the temperature
 284 * Note:
 285 * code to temperature mapping of the temperature sensor is a piece wise linear
 286 * curve.Any temperature, code faling between to 2 give temperatures can be
 287 * linearly interpolated.
 288 * Code to Temperature mapping should be updated based on manufacturer results.
 289 */
 290struct tsadc_table {
 291	u32 code;
 292	int temp;
 293};
 294
 295static const struct tsadc_table rv1108_table[] = {
 296	{0, -40000},
 297	{374, -40000},
 298	{382, -35000},
 299	{389, -30000},
 300	{397, -25000},
 301	{405, -20000},
 302	{413, -15000},
 303	{421, -10000},
 304	{429, -5000},
 305	{436, 0},
 306	{444, 5000},
 307	{452, 10000},
 308	{460, 15000},
 309	{468, 20000},
 310	{476, 25000},
 311	{483, 30000},
 312	{491, 35000},
 313	{499, 40000},
 314	{507, 45000},
 315	{515, 50000},
 316	{523, 55000},
 317	{531, 60000},
 318	{539, 65000},
 319	{547, 70000},
 320	{555, 75000},
 321	{562, 80000},
 322	{570, 85000},
 323	{578, 90000},
 324	{586, 95000},
 325	{594, 100000},
 326	{602, 105000},
 327	{610, 110000},
 328	{618, 115000},
 329	{626, 120000},
 330	{634, 125000},
 331	{TSADCV2_DATA_MASK, 125000},
 332};
 333
 334static const struct tsadc_table rk3228_code_table[] = {
 335	{0, -40000},
 336	{588, -40000},
 337	{593, -35000},
 338	{598, -30000},
 339	{603, -25000},
 340	{608, -20000},
 341	{613, -15000},
 342	{618, -10000},
 343	{623, -5000},
 344	{629, 0},
 345	{634, 5000},
 346	{639, 10000},
 347	{644, 15000},
 348	{649, 20000},
 349	{654, 25000},
 350	{660, 30000},
 351	{665, 35000},
 352	{670, 40000},
 353	{675, 45000},
 354	{681, 50000},
 355	{686, 55000},
 356	{691, 60000},
 357	{696, 65000},
 358	{702, 70000},
 359	{707, 75000},
 360	{712, 80000},
 361	{717, 85000},
 362	{723, 90000},
 363	{728, 95000},
 364	{733, 100000},
 365	{738, 105000},
 366	{744, 110000},
 367	{749, 115000},
 368	{754, 120000},
 369	{760, 125000},
 370	{TSADCV2_DATA_MASK, 125000},
 371};
 372
 373static const struct tsadc_table rk3288_code_table[] = {
 374	{TSADCV2_DATA_MASK, -40000},
 375	{3800, -40000},
 376	{3792, -35000},
 377	{3783, -30000},
 378	{3774, -25000},
 379	{3765, -20000},
 380	{3756, -15000},
 381	{3747, -10000},
 382	{3737, -5000},
 383	{3728, 0},
 384	{3718, 5000},
 385	{3708, 10000},
 386	{3698, 15000},
 387	{3688, 20000},
 388	{3678, 25000},
 389	{3667, 30000},
 390	{3656, 35000},
 391	{3645, 40000},
 392	{3634, 45000},
 393	{3623, 50000},
 394	{3611, 55000},
 395	{3600, 60000},
 396	{3588, 65000},
 397	{3575, 70000},
 398	{3563, 75000},
 399	{3550, 80000},
 400	{3537, 85000},
 401	{3524, 90000},
 402	{3510, 95000},
 403	{3496, 100000},
 404	{3482, 105000},
 405	{3467, 110000},
 406	{3452, 115000},
 407	{3437, 120000},
 408	{3421, 125000},
 409	{0, 125000},
 410};
 411
 412static const struct tsadc_table rk3328_code_table[] = {
 413	{0, -40000},
 414	{296, -40000},
 415	{304, -35000},
 416	{313, -30000},
 417	{322, -25000},
 418	{331, -20000},
 419	{340, -15000},
 420	{349, -10000},
 421	{359, -5000},
 422	{368, 0},
 423	{378, 5000},
 424	{388, 10000},
 425	{398, 15000},
 426	{408, 20000},
 427	{418, 25000},
 428	{429, 30000},
 429	{440, 35000},
 430	{451, 40000},
 431	{462, 45000},
 432	{473, 50000},
 433	{485, 55000},
 434	{496, 60000},
 435	{508, 65000},
 436	{521, 70000},
 437	{533, 75000},
 438	{546, 80000},
 439	{559, 85000},
 440	{572, 90000},
 441	{586, 95000},
 442	{600, 100000},
 443	{614, 105000},
 444	{629, 110000},
 445	{644, 115000},
 446	{659, 120000},
 447	{675, 125000},
 448	{TSADCV2_DATA_MASK, 125000},
 449};
 450
 451static const struct tsadc_table rk3368_code_table[] = {
 452	{0, -40000},
 453	{106, -40000},
 454	{108, -35000},
 455	{110, -30000},
 456	{112, -25000},
 457	{114, -20000},
 458	{116, -15000},
 459	{118, -10000},
 460	{120, -5000},
 461	{122, 0},
 462	{124, 5000},
 463	{126, 10000},
 464	{128, 15000},
 465	{130, 20000},
 466	{132, 25000},
 467	{134, 30000},
 468	{136, 35000},
 469	{138, 40000},
 470	{140, 45000},
 471	{142, 50000},
 472	{144, 55000},
 473	{146, 60000},
 474	{148, 65000},
 475	{150, 70000},
 476	{152, 75000},
 477	{154, 80000},
 478	{156, 85000},
 479	{158, 90000},
 480	{160, 95000},
 481	{162, 100000},
 482	{163, 105000},
 483	{165, 110000},
 484	{167, 115000},
 485	{169, 120000},
 486	{171, 125000},
 487	{TSADCV3_DATA_MASK, 125000},
 488};
 489
 490static const struct tsadc_table rk3399_code_table[] = {
 491	{0, -40000},
 492	{402, -40000},
 493	{410, -35000},
 494	{419, -30000},
 495	{427, -25000},
 496	{436, -20000},
 497	{444, -15000},
 498	{453, -10000},
 499	{461, -5000},
 500	{470, 0},
 501	{478, 5000},
 502	{487, 10000},
 503	{496, 15000},
 504	{504, 20000},
 505	{513, 25000},
 506	{521, 30000},
 507	{530, 35000},
 508	{538, 40000},
 509	{547, 45000},
 510	{555, 50000},
 511	{564, 55000},
 512	{573, 60000},
 513	{581, 65000},
 514	{590, 70000},
 515	{599, 75000},
 516	{607, 80000},
 517	{616, 85000},
 518	{624, 90000},
 519	{633, 95000},
 520	{642, 100000},
 521	{650, 105000},
 522	{659, 110000},
 523	{668, 115000},
 524	{677, 120000},
 525	{685, 125000},
 526	{TSADCV3_DATA_MASK, 125000},
 527};
 528
 529static const struct tsadc_table rk3568_code_table[] = {
 530	{0, -40000},
 531	{1584, -40000},
 532	{1620, -35000},
 533	{1652, -30000},
 534	{1688, -25000},
 535	{1720, -20000},
 536	{1756, -15000},
 537	{1788, -10000},
 538	{1824, -5000},
 539	{1856, 0},
 540	{1892, 5000},
 541	{1924, 10000},
 542	{1956, 15000},
 543	{1992, 20000},
 544	{2024, 25000},
 545	{2060, 30000},
 546	{2092, 35000},
 547	{2128, 40000},
 548	{2160, 45000},
 549	{2196, 50000},
 550	{2228, 55000},
 551	{2264, 60000},
 552	{2300, 65000},
 553	{2332, 70000},
 554	{2368, 75000},
 555	{2400, 80000},
 556	{2436, 85000},
 557	{2468, 90000},
 558	{2500, 95000},
 559	{2536, 100000},
 560	{2572, 105000},
 561	{2604, 110000},
 562	{2636, 115000},
 563	{2672, 120000},
 564	{2704, 125000},
 565	{TSADCV2_DATA_MASK, 125000},
 566};
 567
 568static const struct tsadc_table rk3588_code_table[] = {
 569	{0, -40000},
 570	{215, -40000},
 571	{285, 25000},
 572	{350, 85000},
 573	{395, 125000},
 574	{TSADCV4_DATA_MASK, 125000},
 575};
 576
 577static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
 578				   int temp)
 579{
 580	int high, low, mid;
 581	unsigned long num;
 582	unsigned int denom;
 583	u32 error = table->data_mask;
 584
 585	low = 0;
 586	high = (table->length - 1) - 1; /* ignore the last check for table */
 587	mid = (high + low) / 2;
 588
 589	/* Return mask code data when the temp is over table range */
 590	if (temp < table->id[low].temp || temp > table->id[high].temp)
 591		goto exit;
 592
 593	while (low <= high) {
 594		if (temp == table->id[mid].temp)
 595			return table->id[mid].code;
 596		else if (temp < table->id[mid].temp)
 597			high = mid - 1;
 598		else
 599			low = mid + 1;
 600		mid = (low + high) / 2;
 601	}
 602
 603	/*
 604	 * The conversion code granularity provided by the table. Let's
 605	 * assume that the relationship between temperature and
 606	 * analog value between 2 table entries is linear and interpolate
 607	 * to produce less granular result.
 608	 */
 609	num = abs(table->id[mid + 1].code - table->id[mid].code);
 610	num *= temp - table->id[mid].temp;
 611	denom = table->id[mid + 1].temp - table->id[mid].temp;
 612
 613	switch (table->mode) {
 614	case ADC_DECREMENT:
 615		return table->id[mid].code - (num / denom);
 616	case ADC_INCREMENT:
 617		return table->id[mid].code + (num / denom);
 618	default:
 619		pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
 620		return error;
 621	}
 622
 623exit:
 624	pr_err("%s: invalid temperature, temp=%d error=%d\n",
 625	       __func__, temp, error);
 626	return error;
 627}
 628
 629static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
 630				   u32 code, int *temp)
 631{
 632	unsigned int low = 1;
 633	unsigned int high = table->length - 1;
 634	unsigned int mid = (low + high) / 2;
 635	unsigned int num;
 636	unsigned long denom;
 637
 638	WARN_ON(table->length < 2);
 639
 640	switch (table->mode) {
 641	case ADC_DECREMENT:
 642		code &= table->data_mask;
 643		if (code <= table->id[high].code)
 644			return -EAGAIN;		/* Incorrect reading */
 645
 646		while (low <= high) {
 647			if (code >= table->id[mid].code &&
 648			    code < table->id[mid - 1].code)
 649				break;
 650			else if (code < table->id[mid].code)
 651				low = mid + 1;
 652			else
 653				high = mid - 1;
 654
 655			mid = (low + high) / 2;
 656		}
 657		break;
 658	case ADC_INCREMENT:
 659		code &= table->data_mask;
 660		if (code < table->id[low].code)
 661			return -EAGAIN;		/* Incorrect reading */
 662
 663		while (low <= high) {
 664			if (code <= table->id[mid].code &&
 665			    code > table->id[mid - 1].code)
 666				break;
 667			else if (code > table->id[mid].code)
 668				low = mid + 1;
 669			else
 670				high = mid - 1;
 671
 672			mid = (low + high) / 2;
 673		}
 674		break;
 675	default:
 676		pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
 677		return -EINVAL;
 678	}
 679
 680	/*
 681	 * The 5C granularity provided by the table is too much. Let's
 682	 * assume that the relationship between sensor readings and
 683	 * temperature between 2 table entries is linear and interpolate
 684	 * to produce less granular result.
 685	 */
 686	num = table->id[mid].temp - table->id[mid - 1].temp;
 687	num *= abs(table->id[mid - 1].code - code);
 688	denom = abs(table->id[mid - 1].code - table->id[mid].code);
 689	*temp = table->id[mid - 1].temp + (num / denom);
 690
 691	return 0;
 692}
 693
 694/**
 695 * rk_tsadcv2_initialize - initialize TASDC Controller.
 696 * @grf: the general register file will be used to do static set by software
 697 * @regs: the base address of tsadc controller
 698 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
 699 *
 700 * (1) Set TSADC_V2_AUTO_PERIOD:
 701 *     Configure the interleave between every two accessing of
 702 *     TSADC in normal operation.
 703 *
 704 * (2) Set TSADCV2_AUTO_PERIOD_HT:
 705 *     Configure the interleave between every two accessing of
 706 *     TSADC after the temperature is higher than COM_SHUT or COM_INT.
 707 *
 708 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
 709 *     If the temperature is higher than COMP_INT or COMP_SHUT for
 710 *     "debounce" times, TSADC controller will generate interrupt or TSHUT.
 711 */
 712static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
 713				  enum tshut_polarity tshut_polarity)
 714{
 715	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
 716		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 717			       regs + TSADCV2_AUTO_CON);
 718	else
 719		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 720			       regs + TSADCV2_AUTO_CON);
 721
 722	writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
 723	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 724		       regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 725	writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
 726		       regs + TSADCV2_AUTO_PERIOD_HT);
 727	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 728		       regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 729}
 730
 731/**
 732 * rk_tsadcv3_initialize - initialize TASDC Controller.
 733 * @grf: the general register file will be used to do static set by software
 734 * @regs: the base address of tsadc controller
 735 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
 736 *
 737 * (1) The tsadc control power sequence.
 738 *
 739 * (2) Set TSADC_V2_AUTO_PERIOD:
 740 *     Configure the interleave between every two accessing of
 741 *     TSADC in normal operation.
 742 *
 743 * (2) Set TSADCV2_AUTO_PERIOD_HT:
 744 *     Configure the interleave between every two accessing of
 745 *     TSADC after the temperature is higher than COM_SHUT or COM_INT.
 746 *
 747 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
 748 *     If the temperature is higher than COMP_INT or COMP_SHUT for
 749 *     "debounce" times, TSADC controller will generate interrupt or TSHUT.
 750 */
 751static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
 752				  enum tshut_polarity tshut_polarity)
 753{
 754	/* The tsadc control power sequence */
 755	if (IS_ERR(grf)) {
 756		/* Set interleave value to workround ic time sync issue */
 757		writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
 758			       TSADCV2_USER_CON);
 759
 760		writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
 761			       regs + TSADCV2_AUTO_PERIOD);
 762		writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 763			       regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 764		writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
 765			       regs + TSADCV2_AUTO_PERIOD_HT);
 766		writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 767			       regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 768
 769	} else {
 770		/* Enable the voltage common mode feature */
 771		regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
 772		regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
 773
 774		usleep_range(15, 100); /* The spec note says at least 15 us */
 775		regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
 776		regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
 777		usleep_range(90, 200); /* The spec note says at least 90 us */
 778
 779		writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
 780			       regs + TSADCV2_AUTO_PERIOD);
 781		writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 782			       regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 783		writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
 784			       regs + TSADCV2_AUTO_PERIOD_HT);
 785		writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 786			       regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 787	}
 788
 789	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
 790		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 791			       regs + TSADCV2_AUTO_CON);
 792	else
 793		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 794			       regs + TSADCV2_AUTO_CON);
 795}
 796
 797static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
 798				  enum tshut_polarity tshut_polarity)
 799{
 800	rk_tsadcv2_initialize(grf, regs, tshut_polarity);
 801	regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
 802}
 803
 804static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
 805				  enum tshut_polarity tshut_polarity)
 806{
 807	writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
 808	writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
 809	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 810		       regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 811	writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
 812		       regs + TSADCV2_AUTO_PERIOD_HT);
 813	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 814		       regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 815
 816	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
 817		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 818			       regs + TSADCV2_AUTO_CON);
 819	else
 820		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 821			       regs + TSADCV2_AUTO_CON);
 822
 823	/*
 824	 * The general register file will is optional
 825	 * and might not be available.
 826	 */
 827	if (!IS_ERR(grf)) {
 828		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
 829		/*
 830		 * RK3568 TRM, section 18.5. requires a delay no less
 831		 * than 10us between the rising edge of tsadc_tsen_en
 832		 * and the rising edge of tsadc_ana_reg_0/1/2.
 833		 */
 834		udelay(15);
 835		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
 836		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
 837		regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
 838
 839		/*
 840		 * RK3568 TRM, section 18.5. requires a delay no less
 841		 * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
 842		 */
 843		usleep_range(100, 200);
 844	}
 845}
 846
 847static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
 848				  enum tshut_polarity tshut_polarity)
 849{
 850	writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
 851	writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
 852		       regs + TSADCV3_AUTO_PERIOD_HT);
 853	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 854		       regs + TSADCV3_HIGHT_INT_DEBOUNCE);
 855	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 856		       regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
 857	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
 858		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
 859			       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
 860			       regs + TSADCV2_AUTO_CON);
 861	else
 862		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
 863			       regs + TSADCV2_AUTO_CON);
 864}
 865
 866static void rk_tsadcv2_irq_ack(void __iomem *regs)
 867{
 868	u32 val;
 869
 870	val = readl_relaxed(regs + TSADCV2_INT_PD);
 871	writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
 872}
 873
 874static void rk_tsadcv3_irq_ack(void __iomem *regs)
 875{
 876	u32 val;
 877
 878	val = readl_relaxed(regs + TSADCV2_INT_PD);
 879	writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
 880}
 881
 882static void rk_tsadcv4_irq_ack(void __iomem *regs)
 883{
 884	u32 val;
 885
 886	val = readl_relaxed(regs + TSADCV3_INT_PD);
 887	writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
 888	val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
 889	writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
 890		       regs + TSADCV3_HSHUT_PD);
 891}
 892
 893static void rk_tsadcv2_control(void __iomem *regs, bool enable)
 894{
 895	u32 val;
 896
 897	val = readl_relaxed(regs + TSADCV2_AUTO_CON);
 898	if (enable)
 899		val |= TSADCV2_AUTO_EN;
 900	else
 901		val &= ~TSADCV2_AUTO_EN;
 902
 903	writel_relaxed(val, regs + TSADCV2_AUTO_CON);
 904}
 905
 906/**
 907 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
 908 * @regs: the base address of tsadc controller
 909 * @enable: boolean flag to enable the controller
 910 *
 911 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
 912 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
 913 * adc value if setting this bit to enable.
 914 */
 915static void rk_tsadcv3_control(void __iomem *regs, bool enable)
 916{
 917	u32 val;
 918
 919	val = readl_relaxed(regs + TSADCV2_AUTO_CON);
 920	if (enable)
 921		val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
 922	else
 923		val &= ~TSADCV2_AUTO_EN;
 924
 925	writel_relaxed(val, regs + TSADCV2_AUTO_CON);
 926}
 927
 928static void rk_tsadcv4_control(void __iomem *regs, bool enable)
 929{
 930	u32 val;
 931
 932	if (enable)
 933		val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
 934	else
 935		val = TSADCV2_AUTO_EN_MASK;
 936
 937	writel_relaxed(val, regs + TSADCV2_AUTO_CON);
 938}
 939
 940static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
 941			       int chn, void __iomem *regs, int *temp)
 942{
 943	u32 val;
 944
 945	val = readl_relaxed(regs + TSADCV2_DATA(chn));
 946
 947	return rk_tsadcv2_code_to_temp(table, val, temp);
 948}
 949
 950static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
 951			       int chn, void __iomem *regs, int *temp)
 952{
 953	u32 val;
 954
 955	val = readl_relaxed(regs + TSADCV3_DATA(chn));
 956
 957	return rk_tsadcv2_code_to_temp(table, val, temp);
 958}
 959
 960static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
 961				 int chn, void __iomem *regs, int temp)
 962{
 963	u32 alarm_value;
 964	u32 int_en, int_clr;
 965
 966	/*
 967	 * In some cases, some sensors didn't need the trip points, the
 968	 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
 969	 * in the end, ignore this case and disable the high temperature
 970	 * interrupt.
 971	 */
 972	if (temp == INT_MAX) {
 973		int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
 974		int_clr &= ~TSADCV2_INT_SRC_EN(chn);
 975		writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
 976		return 0;
 977	}
 978
 979	/* Make sure the value is valid */
 980	alarm_value = rk_tsadcv2_temp_to_code(table, temp);
 981	if (alarm_value == table->data_mask)
 982		return -ERANGE;
 983
 984	writel_relaxed(alarm_value & table->data_mask,
 985		       regs + TSADCV2_COMP_INT(chn));
 986
 987	int_en = readl_relaxed(regs + TSADCV2_INT_EN);
 988	int_en |= TSADCV2_INT_SRC_EN(chn);
 989	writel_relaxed(int_en, regs + TSADCV2_INT_EN);
 990
 991	return 0;
 992}
 993
 994static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
 995				 int chn, void __iomem *regs, int temp)
 996{
 997	u32 alarm_value;
 998
 999	/*
1000	 * In some cases, some sensors didn't need the trip points, the
1001	 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
1002	 * in the end, ignore this case and disable the high temperature
1003	 * interrupt.
1004	 */
1005	if (temp == INT_MAX) {
1006		writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
1007			       regs + TSADCV3_HT_INT_EN);
1008		return 0;
1009	}
1010	/* Make sure the value is valid */
1011	alarm_value = rk_tsadcv2_temp_to_code(table, temp);
1012	if (alarm_value == table->data_mask)
1013		return -ERANGE;
1014	writel_relaxed(alarm_value & table->data_mask,
1015		       regs + TSADCV3_COMP_INT(chn));
1016	writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
1017		       regs + TSADCV3_HT_INT_EN);
1018	return 0;
1019}
1020
1021static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
1022				 int chn, void __iomem *regs, int temp)
1023{
1024	u32 tshut_value, val;
1025
1026	/* Make sure the value is valid */
1027	tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1028	if (tshut_value == table->data_mask)
1029		return -ERANGE;
1030
1031	writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
1032
1033	/* TSHUT will be valid */
1034	val = readl_relaxed(regs + TSADCV2_AUTO_CON);
1035	writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
1036
1037	return 0;
1038}
1039
1040static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
1041				 int chn, void __iomem *regs, int temp)
1042{
1043	u32 tshut_value;
1044
1045	/* Make sure the value is valid */
1046	tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1047	if (tshut_value == table->data_mask)
1048		return -ERANGE;
1049
1050	writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
1051
1052	/* TSHUT will be valid */
1053	writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
1054		       regs + TSADCV3_AUTO_SRC_CON);
1055
1056	return 0;
1057}
1058
1059static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
1060				  enum tshut_mode mode)
1061{
1062	u32 val;
1063
1064	val = readl_relaxed(regs + TSADCV2_INT_EN);
1065	if (mode == TSHUT_MODE_GPIO) {
1066		val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
1067		val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1068	} else {
1069		val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1070		val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
1071	}
1072
1073	writel_relaxed(val, regs + TSADCV2_INT_EN);
1074}
1075
1076static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs,
1077				  enum tshut_mode mode)
1078{
1079	u32 val_gpio, val_cru;
1080
1081	if (mode == TSHUT_MODE_GPIO) {
1082		val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1083		val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
1084	} else {
1085		val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1086		val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
1087	}
1088	writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
1089	writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
1090}
1091
1092static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table,
1093				    int code, int trim_base, int trim_base_frac)
1094{
1095	int temp = trim_base * 1000 + trim_base_frac * 100;
1096	u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
1097
1098	return code - base_code;
1099}
1100
1101static const struct rockchip_tsadc_chip px30_tsadc_data = {
1102	/* cpu, gpu */
1103	.chn_offset = 0,
1104	.chn_num = 2, /* 2 channels for tsadc */
1105	.grf_required = true,
1106	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1107	.tshut_temp = 95000,
1108	.initialize = rk_tsadcv4_initialize,
1109	.irq_ack = rk_tsadcv3_irq_ack,
1110	.control = rk_tsadcv3_control,
1111	.get_temp = rk_tsadcv2_get_temp,
1112	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1113	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1114	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1115	.table = {
1116		.id = rk3328_code_table,
1117		.length = ARRAY_SIZE(rk3328_code_table),
1118		.data_mask = TSADCV2_DATA_MASK,
1119		.mode = ADC_INCREMENT,
1120	},
1121};
1122
1123static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
1124	/* cpu */
1125	.chn_offset = 0,
1126	.chn_num = 1, /* one channel for tsadc */
1127	.grf_required = false,
1128	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1129	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1130	.tshut_temp = 95000,
1131	.initialize = rk_tsadcv2_initialize,
1132	.irq_ack = rk_tsadcv3_irq_ack,
1133	.control = rk_tsadcv3_control,
1134	.get_temp = rk_tsadcv2_get_temp,
1135	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1136	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1137	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1138	.table = {
1139		.id = rv1108_table,
1140		.length = ARRAY_SIZE(rv1108_table),
1141		.data_mask = TSADCV2_DATA_MASK,
1142		.mode = ADC_INCREMENT,
1143	},
1144};
1145
1146static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
1147	/* cpu */
1148	.chn_offset = 0,
1149	.chn_num = 1, /* one channel for tsadc */
1150	.grf_required = false,
1151	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1152	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1153	.tshut_temp = 95000,
1154	.initialize = rk_tsadcv2_initialize,
1155	.irq_ack = rk_tsadcv3_irq_ack,
1156	.control = rk_tsadcv3_control,
1157	.get_temp = rk_tsadcv2_get_temp,
1158	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1159	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1160	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1161	.table = {
1162		.id = rk3228_code_table,
1163		.length = ARRAY_SIZE(rk3228_code_table),
1164		.data_mask = TSADCV3_DATA_MASK,
1165		.mode = ADC_INCREMENT,
1166	},
1167};
1168
1169static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1170	/* cpu, gpu */
1171	.chn_offset = 1,
1172	.chn_num = 2, /* two channels for tsadc */
1173	.grf_required = false,
1174	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1175	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1176	.tshut_temp = 95000,
1177	.initialize = rk_tsadcv2_initialize,
1178	.irq_ack = rk_tsadcv2_irq_ack,
1179	.control = rk_tsadcv2_control,
1180	.get_temp = rk_tsadcv2_get_temp,
1181	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1182	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1183	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1184	.table = {
1185		.id = rk3288_code_table,
1186		.length = ARRAY_SIZE(rk3288_code_table),
1187		.data_mask = TSADCV2_DATA_MASK,
1188		.mode = ADC_DECREMENT,
1189	},
1190};
1191
1192static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1193	/* cpu */
1194	.chn_offset = 0,
1195	.chn_num = 1, /* one channels for tsadc */
1196	.grf_required = false,
1197	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1198	.tshut_temp = 95000,
1199	.initialize = rk_tsadcv2_initialize,
1200	.irq_ack = rk_tsadcv3_irq_ack,
1201	.control = rk_tsadcv3_control,
1202	.get_temp = rk_tsadcv2_get_temp,
1203	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1204	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1205	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1206	.table = {
1207		.id = rk3328_code_table,
1208		.length = ARRAY_SIZE(rk3328_code_table),
1209		.data_mask = TSADCV2_DATA_MASK,
1210		.mode = ADC_INCREMENT,
1211	},
1212};
1213
1214static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1215	/* cpu, gpu */
1216	.chn_offset = 0,
1217	.chn_num = 2, /* two channels for tsadc */
1218	.grf_required = true,
1219	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1220	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1221	.tshut_temp = 95000,
1222	.initialize = rk_tsadcv3_initialize,
1223	.irq_ack = rk_tsadcv3_irq_ack,
1224	.control = rk_tsadcv3_control,
1225	.get_temp = rk_tsadcv2_get_temp,
1226	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1227	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1228	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1229	.table = {
1230		.id = rk3228_code_table,
1231		.length = ARRAY_SIZE(rk3228_code_table),
1232		.data_mask = TSADCV3_DATA_MASK,
1233		.mode = ADC_INCREMENT,
1234	},
1235};
1236
1237static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1238	/* cpu, gpu */
1239	.chn_offset = 0,
1240	.chn_num = 2, /* two channels for tsadc */
1241	.grf_required = false,
1242	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1243	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1244	.tshut_temp = 95000,
1245	.initialize = rk_tsadcv2_initialize,
1246	.irq_ack = rk_tsadcv2_irq_ack,
1247	.control = rk_tsadcv2_control,
1248	.get_temp = rk_tsadcv2_get_temp,
1249	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1250	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1251	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1252	.table = {
1253		.id = rk3368_code_table,
1254		.length = ARRAY_SIZE(rk3368_code_table),
1255		.data_mask = TSADCV3_DATA_MASK,
1256		.mode = ADC_INCREMENT,
1257	},
1258};
1259
1260static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1261	/* cpu, gpu */
1262	.chn_offset = 0,
1263	.chn_num = 2, /* two channels for tsadc */
1264	.grf_required = true,
1265	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1266	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1267	.tshut_temp = 95000,
1268	.initialize = rk_tsadcv3_initialize,
1269	.irq_ack = rk_tsadcv3_irq_ack,
1270	.control = rk_tsadcv3_control,
1271	.get_temp = rk_tsadcv2_get_temp,
1272	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1273	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1274	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1275	.table = {
1276		.id = rk3399_code_table,
1277		.length = ARRAY_SIZE(rk3399_code_table),
1278		.data_mask = TSADCV3_DATA_MASK,
1279		.mode = ADC_INCREMENT,
1280	},
1281};
1282
1283static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1284	/* cpu, gpu */
1285	.chn_offset = 0,
1286	.chn_num = 2, /* two channels for tsadc */
1287	.grf_required = true,
1288	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1289	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1290	.tshut_temp = 95000,
1291	.initialize = rk_tsadcv7_initialize,
1292	.irq_ack = rk_tsadcv3_irq_ack,
1293	.control = rk_tsadcv3_control,
1294	.get_temp = rk_tsadcv2_get_temp,
1295	.set_alarm_temp = rk_tsadcv2_alarm_temp,
1296	.set_tshut_temp = rk_tsadcv2_tshut_temp,
1297	.set_tshut_mode = rk_tsadcv2_tshut_mode,
1298	.table = {
1299		.id = rk3568_code_table,
1300		.length = ARRAY_SIZE(rk3568_code_table),
1301		.data_mask = TSADCV2_DATA_MASK,
1302		.mode = ADC_INCREMENT,
1303	},
1304};
1305
1306static const struct rockchip_tsadc_chip rk3576_tsadc_data = {
1307	/* top, big_core, little_core, ddr, npu, gpu */
1308	.chn_offset = 0,
1309	.chn_num = 6, /* six channels for tsadc */
1310	.grf_required = false,
1311	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1312	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1313	.tshut_temp = 95000,
1314	.initialize = rk_tsadcv8_initialize,
1315	.irq_ack = rk_tsadcv4_irq_ack,
1316	.control = rk_tsadcv4_control,
1317	.get_temp = rk_tsadcv4_get_temp,
1318	.set_alarm_temp = rk_tsadcv3_alarm_temp,
1319	.set_tshut_temp = rk_tsadcv3_tshut_temp,
1320	.set_tshut_mode = rk_tsadcv4_tshut_mode,
1321	.get_trim_code = rk_tsadcv2_get_trim_code,
1322	.trim_slope = 923,
1323	.table = {
1324		.id = rk3588_code_table,
1325		.length = ARRAY_SIZE(rk3588_code_table),
1326		.data_mask = TSADCV4_DATA_MASK,
1327		.mode = ADC_INCREMENT,
1328	},
1329};
1330
1331static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
1332	/* top, big_core0, big_core1, little_core, center, gpu, npu */
1333	.chn_offset = 0,
1334	.chn_num = 7, /* seven channels for tsadc */
1335	.grf_required = false,
1336	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1337	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1338	.tshut_temp = 95000,
1339	.initialize = rk_tsadcv8_initialize,
1340	.irq_ack = rk_tsadcv4_irq_ack,
1341	.control = rk_tsadcv4_control,
1342	.get_temp = rk_tsadcv4_get_temp,
1343	.set_alarm_temp = rk_tsadcv3_alarm_temp,
1344	.set_tshut_temp = rk_tsadcv3_tshut_temp,
1345	.set_tshut_mode = rk_tsadcv4_tshut_mode,
1346	.table = {
1347		.id = rk3588_code_table,
1348		.length = ARRAY_SIZE(rk3588_code_table),
1349		.data_mask = TSADCV4_DATA_MASK,
1350		.mode = ADC_INCREMENT,
1351	},
1352};
1353
1354static const struct of_device_id of_rockchip_thermal_match[] = {
1355	{	.compatible = "rockchip,px30-tsadc",
1356		.data = (void *)&px30_tsadc_data,
1357	},
1358	{
1359		.compatible = "rockchip,rv1108-tsadc",
1360		.data = (void *)&rv1108_tsadc_data,
1361	},
1362	{
1363		.compatible = "rockchip,rk3228-tsadc",
1364		.data = (void *)&rk3228_tsadc_data,
1365	},
1366	{
1367		.compatible = "rockchip,rk3288-tsadc",
1368		.data = (void *)&rk3288_tsadc_data,
1369	},
1370	{
1371		.compatible = "rockchip,rk3328-tsadc",
1372		.data = (void *)&rk3328_tsadc_data,
1373	},
1374	{
1375		.compatible = "rockchip,rk3366-tsadc",
1376		.data = (void *)&rk3366_tsadc_data,
1377	},
1378	{
1379		.compatible = "rockchip,rk3368-tsadc",
1380		.data = (void *)&rk3368_tsadc_data,
1381	},
1382	{
1383		.compatible = "rockchip,rk3399-tsadc",
1384		.data = (void *)&rk3399_tsadc_data,
1385	},
1386	{
1387		.compatible = "rockchip,rk3568-tsadc",
1388		.data = (void *)&rk3568_tsadc_data,
1389	},
1390	{
1391		.compatible = "rockchip,rk3576-tsadc",
1392		.data = (void *)&rk3576_tsadc_data,
1393	},
1394	{
1395		.compatible = "rockchip,rk3588-tsadc",
1396		.data = (void *)&rk3588_tsadc_data,
1397	},
1398	{ /* end */ },
1399};
1400MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1401
1402static void
1403rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1404{
1405	struct thermal_zone_device *tzd = sensor->tzd;
1406
1407	if (on)
1408		thermal_zone_device_enable(tzd);
1409	else
1410		thermal_zone_device_disable(tzd);
1411}
1412
1413static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1414{
1415	struct rockchip_thermal_data *thermal = dev;
1416	int i;
1417
1418	dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1419
1420	thermal->chip->irq_ack(thermal->regs);
1421
1422	for (i = 0; i < thermal->chip->chn_num; i++)
1423		thermal_zone_device_update(thermal->sensors[i].tzd,
1424					   THERMAL_EVENT_UNSPECIFIED);
1425
1426	return IRQ_HANDLED;
1427}
1428
1429static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, int high)
1430{
1431	struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
1432	struct rockchip_thermal_data *thermal = sensor->thermal;
1433	const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1434
1435	dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1436		__func__, sensor->id, low, high);
1437
1438	return tsadc->set_alarm_temp(&tsadc->table,
1439				     sensor->id, thermal->regs, high + sensor->trim_temp);
1440}
1441
1442static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp)
1443{
1444	struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
1445	struct rockchip_thermal_data *thermal = sensor->thermal;
1446	const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1447	int retval;
1448
1449	retval = tsadc->get_temp(&tsadc->table,
1450				 sensor->id, thermal->regs, out_temp);
1451	*out_temp -= sensor->trim_temp;
1452
1453	return retval;
1454}
1455
1456static const struct thermal_zone_device_ops rockchip_of_thermal_ops = {
1457	.get_temp = rockchip_thermal_get_temp,
1458	.set_trips = rockchip_thermal_set_trips,
1459};
1460
1461/**
1462 * rockchip_get_efuse_value - read an OTP cell from a device node
1463 * @np: pointer to the device node with the nvmem-cells property
1464 * @cell_name: name of cell that should be read
1465 * @value: pointer to where the read value will be placed
1466 *
1467 * Return: Negative errno on failure, during which *value will not be touched,
1468 * or 0 on success.
1469 */
1470static int rockchip_get_efuse_value(struct device_node *np, const char *cell_name,
1471				    int *value)
1472{
1473	struct nvmem_cell *cell;
1474	int ret = 0;
1475	size_t len;
1476	u8 *buf;
1477	int i;
1478
1479	cell = of_nvmem_cell_get(np, cell_name);
1480	if (IS_ERR(cell))
1481		return PTR_ERR(cell);
1482
1483	buf = nvmem_cell_read(cell, &len);
1484
1485	nvmem_cell_put(cell);
1486
1487	if (IS_ERR(buf))
1488		return PTR_ERR(buf);
1489
1490	if (len > sizeof(*value)) {
1491		ret = -ERANGE;
1492		goto exit;
1493	}
1494
1495	/* Copy with implicit endian conversion */
1496	*value = 0;
1497	for (i = 0; i < len; i++)
1498		*value |= (int) buf[i] << (8 * i);
1499
1500exit:
1501	kfree(buf);
1502	return ret;
1503}
1504
1505static int rockchip_get_trim_configuration(struct device *dev, struct device_node *np,
1506					   struct rockchip_thermal_data *thermal)
1507{
1508	const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1509	int trim_base = 0, trim_base_frac = 0, trim = 0;
1510	int trim_code;
1511	int ret;
1512
1513	thermal->trim_base = 0;
1514	thermal->trim_base_frac = 0;
1515	thermal->trim = 0;
1516
1517	if (!tsadc->get_trim_code)
1518		return 0;
1519
1520	ret = rockchip_get_efuse_value(np, "trim_base", &trim_base);
1521	if (ret < 0) {
1522		if (ret == -ENOENT) {
1523			trim_base = 30;
1524			dev_dbg(dev, "trim_base is absent, defaulting to 30\n");
1525		} else {
1526			dev_err(dev, "failed reading nvmem value of trim_base: %pe\n",
1527				ERR_PTR(ret));
1528			return ret;
1529		}
1530	}
1531	ret = rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac);
1532	if (ret < 0) {
1533		if (ret == -ENOENT) {
1534			dev_dbg(dev, "trim_base_frac is absent, defaulting to 0\n");
1535		} else {
1536			dev_err(dev, "failed reading nvmem value of trim_base_frac: %pe\n",
1537				ERR_PTR(ret));
1538			return ret;
1539		}
1540	}
1541	thermal->trim_base = trim_base;
1542	thermal->trim_base_frac = trim_base_frac;
1543
1544	/*
1545	 * If the tsadc node contains the trim property, then it is used in the
1546	 * absence of per-channel trim values
1547	 */
1548	if (!rockchip_get_efuse_value(np, "trim", &trim))
1549		thermal->trim = trim;
1550	if (trim) {
1551		trim_code = tsadc->get_trim_code(&tsadc->table, trim,
1552						 trim_base, trim_base_frac);
1553		thermal->trim_temp = thermal->chip->trim_slope * trim_code;
1554	}
1555
1556	return 0;
1557}
1558
1559static int rockchip_configure_from_dt(struct device *dev,
1560				      struct device_node *np,
1561				      struct rockchip_thermal_data *thermal)
1562{
1563	u32 shut_temp, tshut_mode, tshut_polarity;
1564
1565	if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1566		dev_warn(dev,
1567			 "Missing tshut temp property, using default %d\n",
1568			 thermal->chip->tshut_temp);
1569		thermal->tshut_temp = thermal->chip->tshut_temp;
1570	} else {
1571		if (shut_temp > INT_MAX) {
1572			dev_err(dev, "Invalid tshut temperature specified: %d\n",
1573				shut_temp);
1574			return -ERANGE;
1575		}
1576		thermal->tshut_temp = shut_temp;
1577	}
1578
1579	if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1580		dev_warn(dev,
1581			 "Missing tshut mode property, using default (%s)\n",
1582			 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1583				"gpio" : "cru");
1584		thermal->tshut_mode = thermal->chip->tshut_mode;
1585	} else {
1586		thermal->tshut_mode = tshut_mode;
1587	}
1588
1589	if (thermal->tshut_mode > 1) {
1590		dev_err(dev, "Invalid tshut mode specified: %d\n",
1591			thermal->tshut_mode);
1592		return -EINVAL;
1593	}
1594
1595	if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1596				 &tshut_polarity)) {
1597		dev_warn(dev,
1598			 "Missing tshut-polarity property, using default (%s)\n",
1599			 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1600				"low" : "high");
1601		thermal->tshut_polarity = thermal->chip->tshut_polarity;
1602	} else {
1603		thermal->tshut_polarity = tshut_polarity;
1604	}
1605
1606	if (thermal->tshut_polarity > 1) {
1607		dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1608			thermal->tshut_polarity);
1609		return -EINVAL;
1610	}
1611
1612	thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1613	if (IS_ERR(thermal->grf) && thermal->chip->grf_required)
1614		return dev_err_probe(dev, PTR_ERR(thermal->grf),
1615				     "Missing rockchip,grf property\n");
1616
1617	rockchip_get_trim_configuration(dev, np, thermal);
1618
1619	return 0;
1620}
1621
1622static int
1623rockchip_thermal_register_sensor(struct platform_device *pdev,
1624				 struct rockchip_thermal_data *thermal,
1625				 struct rockchip_thermal_sensor *sensor,
1626				 int id)
1627{
1628	const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1629	struct device *dev = &pdev->dev;
1630	int trim = thermal->trim;
1631	int trim_code, tshut_temp;
1632	int trim_temp = 0;
1633	int error;
1634
1635	if (thermal->trim_temp)
1636		trim_temp = thermal->trim_temp;
1637
1638	if (tsadc->get_trim_code && sensor->of_node) {
1639		error = rockchip_get_efuse_value(sensor->of_node, "trim", &trim);
1640		if (error < 0 && error != -ENOENT) {
1641			dev_err(dev, "failed reading trim of sensor %d: %pe\n",
1642				id, ERR_PTR(error));
1643			return error;
1644		}
1645		if (trim) {
1646			trim_code = tsadc->get_trim_code(&tsadc->table, trim,
1647							 thermal->trim_base,
1648							 thermal->trim_base_frac);
1649			trim_temp = thermal->chip->trim_slope * trim_code;
1650		}
1651	}
1652
1653	sensor->trim_temp = trim_temp;
1654
1655	dev_dbg(dev, "trim of sensor %d is %d\n", id, sensor->trim_temp);
1656
1657	tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, RK_MAX_TEMP);
1658
1659	tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1660
1661	error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, tshut_temp);
1662	if (error)
1663		dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1664			__func__, tshut_temp, error);
1665
1666	sensor->thermal = thermal;
1667	sensor->id = id;
1668	sensor->tzd = devm_thermal_of_zone_register(dev, id, sensor,
1669						    &rockchip_of_thermal_ops);
1670	if (IS_ERR(sensor->tzd)) {
1671		error = PTR_ERR(sensor->tzd);
1672		dev_err(dev, "failed to register sensor %d: %d\n",
1673			id, error);
1674		return error;
1675	}
1676
1677	return 0;
1678}
1679
1680/**
1681 * rockchip_thermal_reset_controller - Reset TSADC Controller, reset all tsadc registers.
1682 * @reset: the reset controller of tsadc
1683 */
1684static void rockchip_thermal_reset_controller(struct reset_control *reset)
1685{
1686	reset_control_assert(reset);
1687	usleep_range(10, 20);
1688	reset_control_deassert(reset);
1689}
1690
1691static int rockchip_thermal_probe(struct platform_device *pdev)
1692{
1693	struct device_node *np = pdev->dev.of_node;
1694	struct rockchip_thermal_data *thermal;
1695	struct device_node *child;
1696	int irq;
1697	int i;
1698	int error;
1699	u32 chn;
1700
1701	irq = platform_get_irq(pdev, 0);
1702	if (irq < 0)
1703		return -EINVAL;
1704
1705	thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1706			       GFP_KERNEL);
1707	if (!thermal)
1708		return -ENOMEM;
1709
1710	thermal->pdev = pdev;
1711
1712	thermal->chip = device_get_match_data(&pdev->dev);
1713	if (!thermal->chip)
1714		return -EINVAL;
1715
1716	thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num,
1717					sizeof(*thermal->sensors), GFP_KERNEL);
1718	if (!thermal->sensors)
1719		return -ENOMEM;
1720
1721	thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1722	if (IS_ERR(thermal->regs))
1723		return PTR_ERR(thermal->regs);
1724
1725	thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
1726	if (IS_ERR(thermal->reset))
1727		return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
1728				     "failed to get tsadc reset.\n");
1729
1730	thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
1731	if (IS_ERR(thermal->clk))
1732		return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk),
1733				     "failed to get tsadc clock.\n");
1734
1735	thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
1736	if (IS_ERR(thermal->pclk))
1737		return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk),
1738				     "failed to get apb_pclk clock.\n");
1739
1740	rockchip_thermal_reset_controller(thermal->reset);
1741
1742	error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1743	if (error)
1744		return dev_err_probe(&pdev->dev, error,
1745				"failed to parse device tree data\n");
1746
1747	thermal->chip->initialize(thermal->grf, thermal->regs,
1748				  thermal->tshut_polarity);
1749
1750	for_each_available_child_of_node(np, child) {
1751		if (!of_property_read_u32(child, "reg", &chn)) {
1752			if (chn < thermal->chip->chn_num)
1753				thermal->sensors[chn].of_node = child;
1754			else
1755				dev_warn(&pdev->dev,
1756					 "sensor address (%d) too large, ignoring its trim\n",
1757					 chn);
1758		}
1759
1760	}
1761
1762	for (i = 0; i < thermal->chip->chn_num; i++) {
1763		error = rockchip_thermal_register_sensor(pdev, thermal,
1764						&thermal->sensors[i],
1765						thermal->chip->chn_offset + i);
1766		if (error)
1767			return dev_err_probe(&pdev->dev, error,
1768				"failed to register sensor[%d].\n", i);
1769	}
1770
1771	error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1772					  &rockchip_thermal_alarm_irq_thread,
1773					  IRQF_ONESHOT,
1774					  "rockchip_thermal", thermal);
1775	if (error)
1776		return dev_err_probe(&pdev->dev, error,
1777				     "failed to request tsadc irq.\n");
1778
1779	thermal->chip->control(thermal->regs, true);
1780
1781	for (i = 0; i < thermal->chip->chn_num; i++) {
1782		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1783		error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1784		if (error)
1785			dev_warn(&pdev->dev,
1786				 "failed to register sensor %d with hwmon: %d\n",
1787				 i, error);
1788	}
1789
1790	platform_set_drvdata(pdev, thermal);
1791
1792	return 0;
1793}
1794
1795static void rockchip_thermal_remove(struct platform_device *pdev)
1796{
1797	struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1798	int i;
1799
1800	for (i = 0; i < thermal->chip->chn_num; i++) {
1801		struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1802
1803		thermal_remove_hwmon_sysfs(sensor->tzd);
1804		rockchip_thermal_toggle_sensor(sensor, false);
1805	}
1806
1807	thermal->chip->control(thermal->regs, false);
1808}
1809
1810static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1811{
1812	struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1813	int i;
1814
1815	for (i = 0; i < thermal->chip->chn_num; i++)
1816		rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1817
1818	thermal->chip->control(thermal->regs, false);
1819
1820	clk_disable(thermal->pclk);
1821	clk_disable(thermal->clk);
1822
1823	pinctrl_pm_select_sleep_state(dev);
1824
1825	return 0;
1826}
1827
1828static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1829{
1830	struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1831	const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1832	struct rockchip_thermal_sensor *sensor;
1833	int tshut_temp;
1834	int error;
1835	int i;
1836
1837	error = clk_enable(thermal->clk);
1838	if (error)
1839		return error;
1840
1841	error = clk_enable(thermal->pclk);
1842	if (error) {
1843		clk_disable(thermal->clk);
1844		return error;
1845	}
1846
1847	rockchip_thermal_reset_controller(thermal->reset);
1848
1849	tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity);
1850
1851	for (i = 0; i < thermal->chip->chn_num; i++) {
1852		sensor = &thermal->sensors[i];
1853
1854		tshut_temp = min(thermal->tshut_temp + sensor->trim_temp,
1855				 RK_MAX_TEMP);
1856
1857		tsadc->set_tshut_mode(sensor->id, thermal->regs,
1858					      thermal->tshut_mode);
1859
1860		error = tsadc->set_tshut_temp(&thermal->chip->table,
1861					      sensor->id, thermal->regs,
1862					      tshut_temp);
1863		if (error)
1864			dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1865				__func__, tshut_temp, error);
1866	}
1867
1868	thermal->chip->control(thermal->regs, true);
1869
1870	for (i = 0; i < thermal->chip->chn_num; i++)
1871		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1872
1873	pinctrl_pm_select_default_state(dev);
1874
1875	return 0;
1876}
1877
1878static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1879			 rockchip_thermal_suspend, rockchip_thermal_resume);
1880
1881static struct platform_driver rockchip_thermal_driver = {
1882	.driver = {
1883		.name = "rockchip-thermal",
1884		.pm = &rockchip_thermal_pm_ops,
1885		.of_match_table = of_rockchip_thermal_match,
1886	},
1887	.probe = rockchip_thermal_probe,
1888	.remove = rockchip_thermal_remove,
1889};
1890
1891module_platform_driver(rockchip_thermal_driver);
1892
1893MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1894MODULE_AUTHOR("Rockchip, Inc.");
1895MODULE_LICENSE("GPL v2");
1896MODULE_ALIAS("platform:rockchip-thermal");