tsens.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef __QCOM_TSENS_H__
  7#define __QCOM_TSENS_H__
  8
  9#define NO_PT_CALIB		0x0
 10#define ONE_PT_CALIB		0x1
 11#define ONE_PT_CALIB2		0x2
 12#define TWO_PT_CALIB		0x3
 13#define ONE_PT_CALIB2_NO_OFFSET	0x6
 14#define TWO_PT_CALIB_NO_OFFSET	0x7
 15#define CAL_DEGC_PT1		30
 16#define CAL_DEGC_PT2		120
 17#define SLOPE_FACTOR		1000
 18#define SLOPE_DEFAULT		3200
 19#define TIMEOUT_US		100
 20#define THRESHOLD_MAX_ADC_CODE	0x3ff
 21#define THRESHOLD_MIN_ADC_CODE	0x0
 22
 23#define MAX_SENSORS 16
 24
 25#include <linux/interrupt.h>
 26#include <linux/thermal.h>
 27#include <linux/regmap.h>
 28#include <linux/slab.h>
 29
 30struct tsens_priv;
 31
 32/* IP version numbers in ascending order */
 33enum tsens_ver {
 34	VER_0 = 0,
 35	VER_0_1,
 36	VER_1_X,
 37	VER_1_X_NO_RPM,
 38	VER_2_X,
 39	VER_2_X_NO_RPM,
 40};
 41
 42enum tsens_irq_type {
 43	LOWER,
 44	UPPER,
 45	CRITICAL,
 46};
 47
 48/**
 49 * struct tsens_sensor - data for each sensor connected to the tsens device
 50 * @priv: tsens device instance that this sensor is connected to
 51 * @tzd: pointer to the thermal zone that this sensor is in
 52 * @offset: offset of temperature adjustment curve
 53 * @hw_id: HW ID can be used in case of platform-specific IDs
 54 * @slope: slope of temperature adjustment curve
 55 * @status: 8960-specific variable to track 8960 and 8660 status register offset
 56 */
 57struct tsens_sensor {
 58	struct tsens_priv		*priv;
 59	struct thermal_zone_device	*tzd;
 60	int				offset;
 61	unsigned int			hw_id;
 62	int				slope;
 63	u32				status;
 64	int				p1_calib_offset;
 65	int				p2_calib_offset;
 66};
 67
 68/**
 69 * struct tsens_ops - operations as supported by the tsens device
 70 * @init: Function to initialize the tsens device
 71 * @calibrate: Function to calibrate the tsens device
 72 * @get_temp: Function which returns the temp in millidegC
 73 * @enable: Function to enable (clocks/power) tsens device
 74 * @disable: Function to disable the tsens device
 75 * @suspend: Function to suspend the tsens device
 76 * @resume: Function to resume the tsens device
 77 */
 78struct tsens_ops {
 79	/* mandatory callbacks */
 80	int (*init)(struct tsens_priv *priv);
 81	int (*calibrate)(struct tsens_priv *priv);
 82	int (*get_temp)(const struct tsens_sensor *s, int *temp);
 83	/* optional callbacks */
 84	int (*enable)(struct tsens_priv *priv, int i);
 85	void (*disable)(struct tsens_priv *priv);
 86	int (*suspend)(struct tsens_priv *priv);
 87	int (*resume)(struct tsens_priv *priv);
 88};
 89
 90#define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
 91	[_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),	\
 92	[_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
 93	[_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
 94	[_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
 95	[_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
 96	[_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
 97	[_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
 98	[_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
 99	[_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
100	[_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
101	[_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)
102
103#define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \
104	[_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),	\
105	[_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
106	[_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
107	[_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
108	[_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
109	[_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
110	[_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
111	[_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
112	[_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
113	[_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
114	[_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \
115	[_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \
116	[_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \
117	[_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \
118	[_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
119	[_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
120
121#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset)		\
122	[_name##_##0]  = REG_FIELD(_offset,  0,  0),		\
123	[_name##_##1]  = REG_FIELD(_offset,  1,  1),	\
124	[_name##_##2]  = REG_FIELD(_offset,  2,  2),	\
125	[_name##_##3]  = REG_FIELD(_offset,  3,  3),	\
126	[_name##_##4]  = REG_FIELD(_offset,  4,  4),	\
127	[_name##_##5]  = REG_FIELD(_offset,  5,  5),	\
128	[_name##_##6]  = REG_FIELD(_offset,  6,  6),	\
129	[_name##_##7]  = REG_FIELD(_offset,  7,  7),	\
130	[_name##_##8]  = REG_FIELD(_offset,  8,  8),	\
131	[_name##_##9]  = REG_FIELD(_offset,  9,  9),	\
132	[_name##_##10] = REG_FIELD(_offset, 10, 10),	\
133	[_name##_##11] = REG_FIELD(_offset, 11, 11),	\
134	[_name##_##12] = REG_FIELD(_offset, 12, 12),	\
135	[_name##_##13] = REG_FIELD(_offset, 13, 13),	\
136	[_name##_##14] = REG_FIELD(_offset, 14, 14),	\
137	[_name##_##15] = REG_FIELD(_offset, 15, 15)
138
139#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset)		\
140	[_name##_##0]  = REG_FIELD(_offset, 16, 16),		\
141	[_name##_##1]  = REG_FIELD(_offset, 17, 17),	\
142	[_name##_##2]  = REG_FIELD(_offset, 18, 18),	\
143	[_name##_##3]  = REG_FIELD(_offset, 19, 19),	\
144	[_name##_##4]  = REG_FIELD(_offset, 20, 20),	\
145	[_name##_##5]  = REG_FIELD(_offset, 21, 21),	\
146	[_name##_##6]  = REG_FIELD(_offset, 22, 22),	\
147	[_name##_##7]  = REG_FIELD(_offset, 23, 23),	\
148	[_name##_##8]  = REG_FIELD(_offset, 24, 24),	\
149	[_name##_##9]  = REG_FIELD(_offset, 25, 25),	\
150	[_name##_##10] = REG_FIELD(_offset, 26, 26),	\
151	[_name##_##11] = REG_FIELD(_offset, 27, 27),	\
152	[_name##_##12] = REG_FIELD(_offset, 28, 28),	\
153	[_name##_##13] = REG_FIELD(_offset, 29, 29),	\
154	[_name##_##14] = REG_FIELD(_offset, 30, 30),	\
155	[_name##_##15] = REG_FIELD(_offset, 31, 31)
156
157/*
158 * reg_field IDs to use as an index into an array
159 * If you change the order of the entries, check the devm_regmap_field_alloc()
160 * calls in init_common()
161 */
162enum regfield_ids {
163	/* ----- SROT ------ */
164	/* HW_VER */
165	VER_MAJOR,
166	VER_MINOR,
167	VER_STEP,
168	/* CTRL_OFFSET */
169	TSENS_EN,
170	TSENS_SW_RST,
171	SENSOR_EN,
172	CODE_OR_TEMP,
173	MAIN_MEASURE_PERIOD,
174
175	/* ----- TM ------ */
176	/* TRDY */
177	TRDY,
178	/* INTERRUPT ENABLE */
179	INT_EN,	/* v2+ has separate enables for crit, upper and lower irq */
180	/* STATUS */
181	LAST_TEMP_0,	/* Last temperature reading */
182	LAST_TEMP_1,
183	LAST_TEMP_2,
184	LAST_TEMP_3,
185	LAST_TEMP_4,
186	LAST_TEMP_5,
187	LAST_TEMP_6,
188	LAST_TEMP_7,
189	LAST_TEMP_8,
190	LAST_TEMP_9,
191	LAST_TEMP_10,
192	LAST_TEMP_11,
193	LAST_TEMP_12,
194	LAST_TEMP_13,
195	LAST_TEMP_14,
196	LAST_TEMP_15,
197	VALID_0,		/* VALID reading or not */
198	VALID_1,
199	VALID_2,
200	VALID_3,
201	VALID_4,
202	VALID_5,
203	VALID_6,
204	VALID_7,
205	VALID_8,
206	VALID_9,
207	VALID_10,
208	VALID_11,
209	VALID_12,
210	VALID_13,
211	VALID_14,
212	VALID_15,
213	LOWER_STATUS_0,	/* LOWER threshold violated */
214	LOWER_STATUS_1,
215	LOWER_STATUS_2,
216	LOWER_STATUS_3,
217	LOWER_STATUS_4,
218	LOWER_STATUS_5,
219	LOWER_STATUS_6,
220	LOWER_STATUS_7,
221	LOWER_STATUS_8,
222	LOWER_STATUS_9,
223	LOWER_STATUS_10,
224	LOWER_STATUS_11,
225	LOWER_STATUS_12,
226	LOWER_STATUS_13,
227	LOWER_STATUS_14,
228	LOWER_STATUS_15,
229	LOW_INT_STATUS_0,	/* LOWER interrupt status */
230	LOW_INT_STATUS_1,
231	LOW_INT_STATUS_2,
232	LOW_INT_STATUS_3,
233	LOW_INT_STATUS_4,
234	LOW_INT_STATUS_5,
235	LOW_INT_STATUS_6,
236	LOW_INT_STATUS_7,
237	LOW_INT_STATUS_8,
238	LOW_INT_STATUS_9,
239	LOW_INT_STATUS_10,
240	LOW_INT_STATUS_11,
241	LOW_INT_STATUS_12,
242	LOW_INT_STATUS_13,
243	LOW_INT_STATUS_14,
244	LOW_INT_STATUS_15,
245	LOW_INT_CLEAR_0,	/* LOWER interrupt clear */
246	LOW_INT_CLEAR_1,
247	LOW_INT_CLEAR_2,
248	LOW_INT_CLEAR_3,
249	LOW_INT_CLEAR_4,
250	LOW_INT_CLEAR_5,
251	LOW_INT_CLEAR_6,
252	LOW_INT_CLEAR_7,
253	LOW_INT_CLEAR_8,
254	LOW_INT_CLEAR_9,
255	LOW_INT_CLEAR_10,
256	LOW_INT_CLEAR_11,
257	LOW_INT_CLEAR_12,
258	LOW_INT_CLEAR_13,
259	LOW_INT_CLEAR_14,
260	LOW_INT_CLEAR_15,
261	LOW_INT_MASK_0,	/* LOWER interrupt mask */
262	LOW_INT_MASK_1,
263	LOW_INT_MASK_2,
264	LOW_INT_MASK_3,
265	LOW_INT_MASK_4,
266	LOW_INT_MASK_5,
267	LOW_INT_MASK_6,
268	LOW_INT_MASK_7,
269	LOW_INT_MASK_8,
270	LOW_INT_MASK_9,
271	LOW_INT_MASK_10,
272	LOW_INT_MASK_11,
273	LOW_INT_MASK_12,
274	LOW_INT_MASK_13,
275	LOW_INT_MASK_14,
276	LOW_INT_MASK_15,
277	LOW_THRESH_0,		/* LOWER threshold values */
278	LOW_THRESH_1,
279	LOW_THRESH_2,
280	LOW_THRESH_3,
281	LOW_THRESH_4,
282	LOW_THRESH_5,
283	LOW_THRESH_6,
284	LOW_THRESH_7,
285	LOW_THRESH_8,
286	LOW_THRESH_9,
287	LOW_THRESH_10,
288	LOW_THRESH_11,
289	LOW_THRESH_12,
290	LOW_THRESH_13,
291	LOW_THRESH_14,
292	LOW_THRESH_15,
293	UPPER_STATUS_0,	/* UPPER threshold violated */
294	UPPER_STATUS_1,
295	UPPER_STATUS_2,
296	UPPER_STATUS_3,
297	UPPER_STATUS_4,
298	UPPER_STATUS_5,
299	UPPER_STATUS_6,
300	UPPER_STATUS_7,
301	UPPER_STATUS_8,
302	UPPER_STATUS_9,
303	UPPER_STATUS_10,
304	UPPER_STATUS_11,
305	UPPER_STATUS_12,
306	UPPER_STATUS_13,
307	UPPER_STATUS_14,
308	UPPER_STATUS_15,
309	UP_INT_STATUS_0,	/* UPPER interrupt status */
310	UP_INT_STATUS_1,
311	UP_INT_STATUS_2,
312	UP_INT_STATUS_3,
313	UP_INT_STATUS_4,
314	UP_INT_STATUS_5,
315	UP_INT_STATUS_6,
316	UP_INT_STATUS_7,
317	UP_INT_STATUS_8,
318	UP_INT_STATUS_9,
319	UP_INT_STATUS_10,
320	UP_INT_STATUS_11,
321	UP_INT_STATUS_12,
322	UP_INT_STATUS_13,
323	UP_INT_STATUS_14,
324	UP_INT_STATUS_15,
325	UP_INT_CLEAR_0,	/* UPPER interrupt clear */
326	UP_INT_CLEAR_1,
327	UP_INT_CLEAR_2,
328	UP_INT_CLEAR_3,
329	UP_INT_CLEAR_4,
330	UP_INT_CLEAR_5,
331	UP_INT_CLEAR_6,
332	UP_INT_CLEAR_7,
333	UP_INT_CLEAR_8,
334	UP_INT_CLEAR_9,
335	UP_INT_CLEAR_10,
336	UP_INT_CLEAR_11,
337	UP_INT_CLEAR_12,
338	UP_INT_CLEAR_13,
339	UP_INT_CLEAR_14,
340	UP_INT_CLEAR_15,
341	UP_INT_MASK_0,		/* UPPER interrupt mask */
342	UP_INT_MASK_1,
343	UP_INT_MASK_2,
344	UP_INT_MASK_3,
345	UP_INT_MASK_4,
346	UP_INT_MASK_5,
347	UP_INT_MASK_6,
348	UP_INT_MASK_7,
349	UP_INT_MASK_8,
350	UP_INT_MASK_9,
351	UP_INT_MASK_10,
352	UP_INT_MASK_11,
353	UP_INT_MASK_12,
354	UP_INT_MASK_13,
355	UP_INT_MASK_14,
356	UP_INT_MASK_15,
357	UP_THRESH_0,		/* UPPER threshold values */
358	UP_THRESH_1,
359	UP_THRESH_2,
360	UP_THRESH_3,
361	UP_THRESH_4,
362	UP_THRESH_5,
363	UP_THRESH_6,
364	UP_THRESH_7,
365	UP_THRESH_8,
366	UP_THRESH_9,
367	UP_THRESH_10,
368	UP_THRESH_11,
369	UP_THRESH_12,
370	UP_THRESH_13,
371	UP_THRESH_14,
372	UP_THRESH_15,
373	CRITICAL_STATUS_0,	/* CRITICAL threshold violated */
374	CRITICAL_STATUS_1,
375	CRITICAL_STATUS_2,
376	CRITICAL_STATUS_3,
377	CRITICAL_STATUS_4,
378	CRITICAL_STATUS_5,
379	CRITICAL_STATUS_6,
380	CRITICAL_STATUS_7,
381	CRITICAL_STATUS_8,
382	CRITICAL_STATUS_9,
383	CRITICAL_STATUS_10,
384	CRITICAL_STATUS_11,
385	CRITICAL_STATUS_12,
386	CRITICAL_STATUS_13,
387	CRITICAL_STATUS_14,
388	CRITICAL_STATUS_15,
389	CRIT_INT_STATUS_0,	/* CRITICAL interrupt status */
390	CRIT_INT_STATUS_1,
391	CRIT_INT_STATUS_2,
392	CRIT_INT_STATUS_3,
393	CRIT_INT_STATUS_4,
394	CRIT_INT_STATUS_5,
395	CRIT_INT_STATUS_6,
396	CRIT_INT_STATUS_7,
397	CRIT_INT_STATUS_8,
398	CRIT_INT_STATUS_9,
399	CRIT_INT_STATUS_10,
400	CRIT_INT_STATUS_11,
401	CRIT_INT_STATUS_12,
402	CRIT_INT_STATUS_13,
403	CRIT_INT_STATUS_14,
404	CRIT_INT_STATUS_15,
405	CRIT_INT_CLEAR_0,	/* CRITICAL interrupt clear */
406	CRIT_INT_CLEAR_1,
407	CRIT_INT_CLEAR_2,
408	CRIT_INT_CLEAR_3,
409	CRIT_INT_CLEAR_4,
410	CRIT_INT_CLEAR_5,
411	CRIT_INT_CLEAR_6,
412	CRIT_INT_CLEAR_7,
413	CRIT_INT_CLEAR_8,
414	CRIT_INT_CLEAR_9,
415	CRIT_INT_CLEAR_10,
416	CRIT_INT_CLEAR_11,
417	CRIT_INT_CLEAR_12,
418	CRIT_INT_CLEAR_13,
419	CRIT_INT_CLEAR_14,
420	CRIT_INT_CLEAR_15,
421	CRIT_INT_MASK_0,	/* CRITICAL interrupt mask */
422	CRIT_INT_MASK_1,
423	CRIT_INT_MASK_2,
424	CRIT_INT_MASK_3,
425	CRIT_INT_MASK_4,
426	CRIT_INT_MASK_5,
427	CRIT_INT_MASK_6,
428	CRIT_INT_MASK_7,
429	CRIT_INT_MASK_8,
430	CRIT_INT_MASK_9,
431	CRIT_INT_MASK_10,
432	CRIT_INT_MASK_11,
433	CRIT_INT_MASK_12,
434	CRIT_INT_MASK_13,
435	CRIT_INT_MASK_14,
436	CRIT_INT_MASK_15,
437	CRIT_THRESH_0,		/* CRITICAL threshold values */
438	CRIT_THRESH_1,
439	CRIT_THRESH_2,
440	CRIT_THRESH_3,
441	CRIT_THRESH_4,
442	CRIT_THRESH_5,
443	CRIT_THRESH_6,
444	CRIT_THRESH_7,
445	CRIT_THRESH_8,
446	CRIT_THRESH_9,
447	CRIT_THRESH_10,
448	CRIT_THRESH_11,
449	CRIT_THRESH_12,
450	CRIT_THRESH_13,
451	CRIT_THRESH_14,
452	CRIT_THRESH_15,
453
454	/* WATCHDOG */
455	WDOG_BARK_STATUS,
456	WDOG_BARK_CLEAR,
457	WDOG_BARK_MASK,
458	WDOG_BARK_COUNT,
459
460	/* CYCLE COMPLETION MONITOR */
461	CC_MON_STATUS,
462	CC_MON_CLEAR,
463	CC_MON_MASK,
464
465	MIN_STATUS_0,		/* MIN threshold violated */
466	MIN_STATUS_1,
467	MIN_STATUS_2,
468	MIN_STATUS_3,
469	MIN_STATUS_4,
470	MIN_STATUS_5,
471	MIN_STATUS_6,
472	MIN_STATUS_7,
473	MIN_STATUS_8,
474	MIN_STATUS_9,
475	MIN_STATUS_10,
476	MIN_STATUS_11,
477	MIN_STATUS_12,
478	MIN_STATUS_13,
479	MIN_STATUS_14,
480	MIN_STATUS_15,
481	MAX_STATUS_0,		/* MAX threshold violated */
482	MAX_STATUS_1,
483	MAX_STATUS_2,
484	MAX_STATUS_3,
485	MAX_STATUS_4,
486	MAX_STATUS_5,
487	MAX_STATUS_6,
488	MAX_STATUS_7,
489	MAX_STATUS_8,
490	MAX_STATUS_9,
491	MAX_STATUS_10,
492	MAX_STATUS_11,
493	MAX_STATUS_12,
494	MAX_STATUS_13,
495	MAX_STATUS_14,
496	MAX_STATUS_15,
497
498	/* Keep last */
499	MAX_REGFIELDS
500};
501
502/**
503 * struct tsens_features - Features supported by the IP
504 * @ver_major: Major number of IP version
505 * @crit_int: does the IP support critical interrupts?
506 * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
507 * @adc:      do the sensors only output adc code (instead of temperature)?
508 * @srot_split: does the IP neatly splits the register space into SROT and TM,
509 *              with SROT only being available to secure boot firmware?
510 * @has_watchdog: does this IP support watchdog functionality?
511 * @max_sensors: maximum sensors supported by this version of the IP
512 * @trip_min_temp: minimum trip temperature supported by this version of the IP
513 * @trip_max_temp: maximum trip temperature supported by this version of the IP
514 */
515struct tsens_features {
516	unsigned int ver_major;
517	unsigned int crit_int:1;
518	unsigned int combo_int:1;
519	unsigned int adc:1;
520	unsigned int srot_split:1;
521	unsigned int has_watchdog:1;
522	unsigned int max_sensors;
523	int trip_min_temp;
524	int trip_max_temp;
525};
526
527/**
528 * struct tsens_plat_data - tsens compile-time platform data
529 * @num_sensors: Number of sensors supported by platform
530 * @ops: operations the tsens instance supports
531 * @hw_ids: Subset of sensors ids supported by platform, if not the first n
532 * @feat: features of the IP
533 * @fields: bitfield locations
534 */
535struct tsens_plat_data {
536	const u32		num_sensors;
537	const struct tsens_ops	*ops;
538	unsigned int		*hw_ids;
539	struct tsens_features	*feat;
540	const struct reg_field		*fields;
541};
542
543/**
544 * struct tsens_context - Registers to be saved/restored across a context loss
545 * @threshold: Threshold register value
546 * @control: Control register value
547 */
548struct tsens_context {
549	int	threshold;
550	int	control;
551};
552
553/**
554 * struct tsens_priv - private data for each instance of the tsens IP
555 * @dev: pointer to struct device
556 * @num_sensors: number of sensors enabled on this device
557 * @tm_map: pointer to TM register address space
558 * @srot_map: pointer to SROT register address space
559 * @tm_offset: deal with old device trees that don't address TM and SROT
560 *             address space separately
561 * @ul_lock: lock while processing upper/lower threshold interrupts
562 * @crit_lock: lock while processing critical threshold interrupts
563 * @rf: array of regmap_fields used to store value of the field
564 * @ctx: registers to be saved and restored during suspend/resume
565 * @feat: features of the IP
566 * @fields: bitfield locations
567 * @ops: pointer to list of callbacks supported by this device
568 * @debug_root: pointer to debugfs dentry for all tsens
569 * @debug: pointer to debugfs dentry for tsens controller
570 * @sensor: list of sensors attached to this device
571 */
572struct tsens_priv {
573	struct device			*dev;
574	u32				num_sensors;
575	struct regmap			*tm_map;
576	struct regmap			*srot_map;
577	u32				tm_offset;
578
579	/* lock for upper/lower threshold interrupts */
580	spinlock_t			ul_lock;
581
582	struct regmap_field		*rf[MAX_REGFIELDS];
583	struct tsens_context		ctx;
584	struct tsens_features		*feat;
585	const struct reg_field		*fields;
586	const struct tsens_ops		*ops;
587
588	struct dentry			*debug_root;
589	struct dentry			*debug;
590
591	struct tsens_sensor		sensor[] __counted_by(num_sensors);
592};
593
594/**
595 * struct tsens_single_value - internal representation of a single field inside nvmem calibration data
596 * @idx: index into the u32 data array
597 * @shift: the shift of the first bit in the value
598 * @blob: index of the data blob to use for this cell
599 */
600struct tsens_single_value {
601	u8 idx;
602	u8 shift;
603	u8 blob;
604};
605
606/**
607 * struct tsens_legacy_calibration_format - description of calibration data used when parsing the legacy nvmem blob
608 * @base_len: the length of the base fields inside calibration data
609 * @base_shift: the shift to be applied to base data
610 * @sp_len: the length of the sN_pM fields inside calibration data
611 * @mode: descriptor of the calibration mode field
612 * @invalid: descriptor of the calibration mode invalid field
613 * @base: descriptors of the base0 and base1 fields
614 * @sp: descriptors of the sN_pM fields
615 */
616struct tsens_legacy_calibration_format {
617	unsigned int base_len;
618	unsigned int base_shift;
619	unsigned int sp_len;
620	/* just two bits */
621	struct tsens_single_value mode;
622	/* on all platforms except 8974 invalid is the third bit of what downstream calls 'mode' */
623	struct tsens_single_value invalid;
624	struct tsens_single_value base[2];
625	struct tsens_single_value sp[][2];
626};
627
628char *qfprom_read(struct device *dev, const char *cname);
629int tsens_read_calibration_legacy(struct tsens_priv *priv,
630				  const struct tsens_legacy_calibration_format *format,
631				  u32 *p1, u32 *p2,
632				  u32 *cdata, u32 *csel);
633int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup);
634int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift);
635int tsens_calibrate_common(struct tsens_priv *priv);
636void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);
637int init_common(struct tsens_priv *priv);
638int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
639int get_temp_common(const struct tsens_sensor *s, int *temp);
640#ifdef CONFIG_SUSPEND
641int tsens_resume_common(struct tsens_priv *priv);
642#else
643#define tsens_resume_common            NULL
644#endif
645
646/* TSENS target */
647extern struct tsens_plat_data data_8960;
648
649/* TSENS v0.1 targets */
650extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8974, data_9607;
651
652/* TSENS v1 targets */
653extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_8956;
654
655/* TSENS v1 with no RPM targets */
656extern const struct tsens_plat_data data_ipq5018;
657
658/* TSENS v2 targets */
659extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2;
660extern const struct tsens_plat_data data_ipq5332, data_ipq5424;
661
662#endif /* __QCOM_TSENS_H__ */