qcom-spmi-temp-alarm.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
  4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  5 */
  6
  7#include <linux/bitfield.h>
  8#include <linux/bitops.h>
  9#include <linux/delay.h>
 10#include <linux/err.h>
 11#include <linux/iio/consumer.h>
 12#include <linux/interrupt.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/platform_device.h>
 16#include <linux/regmap.h>
 17#include <linux/thermal.h>
 18
 19#include "../thermal_hwmon.h"
 20
 21#define QPNP_TM_REG_DIG_MINOR		0x00
 22#define QPNP_TM_REG_DIG_MAJOR		0x01
 23#define QPNP_TM_REG_TYPE		0x04
 24#define QPNP_TM_REG_SUBTYPE		0x05
 25#define QPNP_TM_REG_STATUS		0x08
 26#define QPNP_TM_REG_IRQ_STATUS		0x10
 27#define QPNP_TM_REG_SHUTDOWN_CTRL1	0x40
 28#define QPNP_TM_REG_ALARM_CTRL		0x46
 29
 30/* TEMP_DAC_STGx registers are only present for TEMP_GEN2 v2.0 */
 31#define QPNP_TM_REG_TEMP_DAC_STG1	0x47
 32#define QPNP_TM_REG_TEMP_DAC_STG2	0x48
 33#define QPNP_TM_REG_TEMP_DAC_STG3	0x49
 34#define QPNP_TM_REG_LITE_TEMP_CFG1	0x50
 35#define QPNP_TM_REG_LITE_TEMP_CFG2	0x51
 36
 37#define QPNP_TM_TYPE			0x09
 38#define QPNP_TM_SUBTYPE_GEN1		0x08
 39#define QPNP_TM_SUBTYPE_GEN2		0x09
 40#define QPNP_TM_SUBTYPE_LITE		0xC0
 41
 42#define STATUS_GEN1_STAGE_MASK		GENMASK(1, 0)
 43#define STATUS_GEN2_STATE_MASK		GENMASK(6, 4)
 44
 45/* IRQ status only needed for TEMP_ALARM_LITE */
 46#define IRQ_STATUS_MASK			BIT(0)
 47
 48#define SHUTDOWN_CTRL1_OVERRIDE_STAGE2	BIT(6)
 49#define SHUTDOWN_CTRL1_THRESHOLD_MASK	GENMASK(1, 0)
 50
 51#define SHUTDOWN_CTRL1_RATE_25HZ	BIT(3)
 52
 53#define ALARM_CTRL_FORCE_ENABLE		BIT(7)
 54
 55#define LITE_TEMP_CFG_THRESHOLD_MASK	GENMASK(3, 2)
 56
 57#define THRESH_COUNT			4
 58#define STAGE_COUNT			3
 59
 60enum overtemp_stage {
 61	STAGE1 = 0,
 62	STAGE2,
 63	STAGE3,
 64};
 65
 66/* Over-temperature trip point values in mC */
 67static const long temp_map_gen1[THRESH_COUNT][STAGE_COUNT] = {
 68	{ 105000, 125000, 145000 },
 69	{ 110000, 130000, 150000 },
 70	{ 115000, 135000, 155000 },
 71	{ 120000, 140000, 160000 },
 72};
 73
 74static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = {
 75	{  90000, 110000, 140000 },
 76	{  95000, 115000, 145000 },
 77	{ 100000, 120000, 150000 },
 78	{ 105000, 125000, 155000 },
 79};
 80
 81#define TEMP_THRESH_STEP		5000 /* Threshold step: 5 C */
 82
 83#define THRESH_MIN			0
 84#define THRESH_MAX			3
 85
 86#define TEMP_STAGE_HYSTERESIS		2000
 87
 88/*
 89 * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the threshold
 90 * for each stage independently.
 91 * TEMP_DAC_STG* = 0 --> 80 C
 92 * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC).
 93 */
 94#define TEMP_DAC_MIN			80000
 95#define TEMP_DAC_SCALE_NUM		8
 96#define TEMP_DAC_SCALE_DEN		5000
 97
 98#define TEMP_DAC_TEMP_TO_REG(temp) \
 99	(((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN)
100#define TEMP_DAC_REG_TO_TEMP(reg) \
101	(TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM)
102
103static const long temp_dac_max[STAGE_COUNT] = {
104	119375, 159375, 159375
105};
106
107/*
108 * TEMP_ALARM_LITE has two stages: warning and shutdown with independently
109 * configured threshold temperatures.
110 */
111
112static const long temp_lite_warning_map[THRESH_COUNT] = {
113	115000, 125000, 135000, 145000
114};
115
116static const long temp_lite_shutdown_map[THRESH_COUNT] = {
117	135000, 145000, 160000, 175000
118};
119
120/* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
121#define DEFAULT_TEMP			37000
122
123struct qpnp_tm_chip;
124
125struct spmi_temp_alarm_data {
126	const struct thermal_zone_device_ops *ops;
127	const long (*temp_map)[THRESH_COUNT][STAGE_COUNT];
128	int (*sync_thresholds)(struct qpnp_tm_chip *chip);
129	int (*get_temp_stage)(struct qpnp_tm_chip *chip);
130	int (*configure_trip_temps)(struct qpnp_tm_chip *chip);
131};
132
133struct qpnp_tm_chip {
134	struct regmap			*map;
135	struct device			*dev;
136	struct thermal_zone_device	*tz_dev;
137	const struct spmi_temp_alarm_data *data;
138	unsigned int			subtype;
139	long				temp;
140	unsigned int			stage;
141	unsigned int			base;
142	unsigned int			ntrips;
143	/* protects .thresh, .stage and chip registers */
144	struct mutex			lock;
145	bool				initialized;
146	bool				require_stage2_shutdown;
147	long				temp_thresh_map[STAGE_COUNT];
148
149	struct iio_channel		*adc;
150};
151
152/* This array maps from GEN2 alarm state to GEN1 alarm stage */
153static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
154
155static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
156{
157	unsigned int val;
158	int ret;
159
160	ret = regmap_read(chip->map, chip->base + addr, &val);
161	if (ret < 0)
162		return ret;
163
164	*data = val;
165	return 0;
166}
167
168static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
169{
170	return regmap_write(chip->map, chip->base + addr, data);
171}
172
173/**
174 * qpnp_tm_decode_temp() - return temperature in mC corresponding to the
175 *		specified over-temperature stage
176 * @chip:		Pointer to the qpnp_tm chip
177 * @stage:		Over-temperature stage
178 *
179 * Return: temperature in mC
180 */
181static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage)
182{
183	if (stage == 0 || stage > STAGE_COUNT)
184		return 0;
185
186	return chip->temp_thresh_map[stage - 1];
187}
188
189/**
190 * qpnp_tm_gen1_get_temp_stage() - return over-temperature stage
191 * @chip:		Pointer to the qpnp_tm chip
192 *
193 * Return: stage on success, or errno on failure.
194 */
195static int qpnp_tm_gen1_get_temp_stage(struct qpnp_tm_chip *chip)
196{
197	int ret;
198	u8 reg;
199
200	ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg);
201	if (ret < 0)
202		return ret;
203
204	return FIELD_GET(STATUS_GEN1_STAGE_MASK, reg);
205}
206
207/**
208 * qpnp_tm_gen2_get_temp_stage() - return over-temperature stage
209 * @chip:		Pointer to the qpnp_tm chip
210 *
211 * Return: stage on success, or errno on failure.
212 */
213static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip)
214{
215	int ret;
216	u8 reg;
217
218	ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg);
219	if (ret < 0)
220		return ret;
221
222	ret = FIELD_GET(STATUS_GEN2_STATE_MASK, reg);
223
224	return alarm_state_map[ret];
225}
226
227/**
228 * qpnp_tm_lite_get_temp_stage() - return over-temperature stage
229 * @chip:		Pointer to the qpnp_tm chip
230 *
231 * Return: alarm interrupt state on success, or errno on failure.
232 */
233static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip)
234{
235	u8 reg = 0;
236	int ret;
237
238	ret = qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, &reg);
239	if (ret < 0)
240		return ret;
241
242	return FIELD_GET(IRQ_STATUS_MASK, reg);
243}
244
245/*
246 * This function updates the internal temp value based on the
247 * current thermal stage and threshold as well as the previous stage
248 */
249static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
250{
251	unsigned int stage_new, stage_old;
252	int ret;
253
254	WARN_ON(!mutex_is_locked(&chip->lock));
255
256	ret = chip->data->get_temp_stage(chip);
257	if (ret < 0)
258		return ret;
259	stage_new = ret;
260	stage_old = chip->stage;
261
262	if (stage_new > stage_old) {
263		/* increasing stage, use lower bound */
264		chip->temp = qpnp_tm_decode_temp(chip, stage_new)
265				+ TEMP_STAGE_HYSTERESIS;
266	} else if (stage_new < stage_old) {
267		/* decreasing stage, use upper bound */
268		chip->temp = qpnp_tm_decode_temp(chip, stage_new + 1)
269				- TEMP_STAGE_HYSTERESIS;
270	}
271
272	chip->stage = stage_new;
273
274	return 0;
275}
276
277static int qpnp_tm_get_temp(struct thermal_zone_device *tz, int *temp)
278{
279	struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz);
280	int ret, mili_celsius;
281
282	if (!temp)
283		return -EINVAL;
284
285	if (!chip->initialized) {
286		*temp = DEFAULT_TEMP;
287		return 0;
288	}
289
290	if (!chip->adc) {
291		mutex_lock(&chip->lock);
292		ret = qpnp_tm_update_temp_no_adc(chip);
293		mutex_unlock(&chip->lock);
294		if (ret < 0)
295			return ret;
296	} else {
297		ret = iio_read_channel_processed(chip->adc, &mili_celsius);
298		if (ret < 0)
299			return ret;
300
301		chip->temp = mili_celsius;
302	}
303
304	*temp = chip->temp;
305
306	return 0;
307}
308
309static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
310					     int temp)
311{
312	long stage2_threshold_min = (*chip->data->temp_map)[THRESH_MIN][STAGE2];
313	long stage2_threshold_max = (*chip->data->temp_map)[THRESH_MAX][STAGE2];
314	bool disable_stage2_shutdown = false;
315	u8 reg, threshold;
316
317	WARN_ON(!mutex_is_locked(&chip->lock));
318
319	/*
320	 * Default: Stage 2 and Stage 3 shutdown enabled, thresholds at
321	 * lowest threshold set, monitoring at 25Hz
322	 */
323	reg = SHUTDOWN_CTRL1_RATE_25HZ;
324
325	if (temp == THERMAL_TEMP_INVALID ||
326	    temp < stage2_threshold_min) {
327		threshold = THRESH_MIN;
328		goto skip;
329	}
330
331	if (temp <= stage2_threshold_max) {
332		threshold = THRESH_MAX -
333			((stage2_threshold_max - temp) /
334			 TEMP_THRESH_STEP);
335		disable_stage2_shutdown = true;
336	} else {
337		threshold = THRESH_MAX;
338
339		if (chip->adc)
340			disable_stage2_shutdown = true;
341		else
342			dev_warn(chip->dev,
343				 "No ADC is configured and critical temperature %d mC is above the maximum stage 2 threshold of %ld mC! Configuring stage 2 shutdown at %ld mC.\n",
344				 temp, stage2_threshold_max, stage2_threshold_max);
345	}
346
347skip:
348	memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold],
349		sizeof(chip->temp_thresh_map));
350	reg |= threshold;
351	if (disable_stage2_shutdown && !chip->require_stage2_shutdown)
352		reg |= SHUTDOWN_CTRL1_OVERRIDE_STAGE2;
353
354	return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
355}
356
357static int qpnp_tm_set_trip_temp(struct thermal_zone_device *tz,
358				 const struct thermal_trip *trip, int temp)
359{
360	struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz);
361	int ret;
362
363	if (trip->type != THERMAL_TRIP_CRITICAL)
364		return 0;
365
366	mutex_lock(&chip->lock);
367	ret = qpnp_tm_update_critical_trip_temp(chip, temp);
368	mutex_unlock(&chip->lock);
369
370	return ret;
371}
372
373static const struct thermal_zone_device_ops qpnp_tm_sensor_ops = {
374	.get_temp = qpnp_tm_get_temp,
375	.set_trip_temp = qpnp_tm_set_trip_temp,
376};
377
378static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, unsigned int trip, int temp)
379{
380	int ret, temp_cfg;
381	u8 reg;
382
383	WARN_ON(!mutex_is_locked(&chip->lock));
384
385	if (trip >= STAGE_COUNT) {
386		dev_err(chip->dev, "invalid TEMP_DAC trip = %d\n", trip);
387		return -EINVAL;
388	} else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) {
389		dev_err(chip->dev, "invalid TEMP_DAC temp = %d\n", temp);
390		return -EINVAL;
391	}
392
393	reg = TEMP_DAC_TEMP_TO_REG(temp);
394	temp_cfg = TEMP_DAC_REG_TO_TEMP(reg);
395
396	ret = qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg);
397	if (ret < 0) {
398		dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=%d\n", ret);
399		return ret;
400	}
401
402	chip->temp_thresh_map[trip] = temp_cfg;
403
404	return 0;
405}
406
407static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz,
408					   const struct thermal_trip *trip, int temp)
409{
410	unsigned int trip_index = THERMAL_TRIP_PRIV_TO_INT(trip->priv);
411	struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz);
412	int ret;
413
414	mutex_lock(&chip->lock);
415	ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip_index, temp);
416	mutex_unlock(&chip->lock);
417
418	return ret;
419}
420
421static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = {
422	.get_temp = qpnp_tm_get_temp,
423	.set_trip_temp = qpnp_tm_gen2_rev2_set_trip_temp,
424};
425
426static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, unsigned int trip, int temp)
427{
428	int ret, temp_cfg, i;
429	const long *temp_map;
430	u8 reg, thresh;
431	u16 addr;
432
433	WARN_ON(!mutex_is_locked(&chip->lock));
434
435	if (trip >= STAGE_COUNT) {
436		dev_err(chip->dev, "invalid TEMP_LITE trip = %d\n", trip);
437		return -EINVAL;
438	}
439
440	switch (trip) {
441	case 0:
442		temp_map = temp_lite_warning_map;
443		addr = QPNP_TM_REG_LITE_TEMP_CFG1;
444		break;
445	case 1:
446		/*
447		 * The second trip point is purely in software to facilitate
448		 * a controlled shutdown after the warning threshold is crossed
449		 * but before the automatic hardware shutdown threshold is
450		 * crossed.
451		 */
452		return 0;
453	case 2:
454		temp_map = temp_lite_shutdown_map;
455		addr = QPNP_TM_REG_LITE_TEMP_CFG2;
456		break;
457	default:
458		return 0;
459	}
460
461	if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) {
462		dev_err(chip->dev, "invalid TEMP_LITE temp = %d\n", temp);
463		return -EINVAL;
464	}
465
466	thresh = 0;
467	temp_cfg = temp_map[thresh];
468	for (i = THRESH_MAX; i >= THRESH_MIN; i--) {
469		if (temp >= temp_map[i]) {
470			thresh = i;
471			temp_cfg = temp_map[i];
472			break;
473		}
474	}
475
476	if (temp_cfg == chip->temp_thresh_map[trip])
477		return 0;
478
479	ret = qpnp_tm_read(chip, addr, &reg);
480	if (ret < 0) {
481		dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=%d\n", ret);
482		return ret;
483	}
484
485	reg &= ~LITE_TEMP_CFG_THRESHOLD_MASK;
486	reg |= FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh);
487
488	ret = qpnp_tm_write(chip, addr, reg);
489	if (ret < 0) {
490		dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=%d\n", ret);
491		return ret;
492	}
493
494	chip->temp_thresh_map[trip] = temp_cfg;
495
496	return 0;
497}
498
499static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz,
500				      const struct thermal_trip *trip, int temp)
501{
502	unsigned int trip_index = THERMAL_TRIP_PRIV_TO_INT(trip->priv);
503	struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz);
504	int ret;
505
506	mutex_lock(&chip->lock);
507	ret = qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp);
508	mutex_unlock(&chip->lock);
509
510	return ret;
511}
512
513static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops = {
514	.get_temp = qpnp_tm_get_temp,
515	.set_trip_temp = qpnp_tm_lite_set_trip_temp,
516};
517
518static irqreturn_t qpnp_tm_isr(int irq, void *data)
519{
520	struct qpnp_tm_chip *chip = data;
521
522	thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
523
524	return IRQ_HANDLED;
525}
526
527/* Read the hardware default stage threshold temperatures */
528static int qpnp_tm_sync_thresholds(struct qpnp_tm_chip *chip)
529{
530	u8 reg, threshold;
531	int ret;
532
533	ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, &reg);
534	if (ret < 0)
535		return ret;
536
537	threshold = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
538	memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold],
539		sizeof(chip->temp_thresh_map));
540
541	return ret;
542}
543
544static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip)
545{
546	int crit_temp, ret;
547
548	ret = thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp);
549	if (ret)
550		crit_temp = THERMAL_TEMP_INVALID;
551
552	mutex_lock(&chip->lock);
553	ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp);
554	mutex_unlock(&chip->lock);
555
556	return ret;
557}
558
559/* Configure TEMP_DAC registers based on DT thermal_zone trips */
560static int qpnp_tm_gen2_rev2_configure_trip_temps_cb(struct thermal_trip *trip, void *data)
561{
562	struct qpnp_tm_chip *chip = data;
563	int ret;
564
565	mutex_lock(&chip->lock);
566	trip->priv = THERMAL_INT_TO_TRIP_PRIV(chip->ntrips);
567	ret = qpnp_tm_gen2_rev2_set_temp_thresh(chip, chip->ntrips, trip->temperature);
568	chip->ntrips++;
569	mutex_unlock(&chip->lock);
570
571	return ret;
572}
573
574static int qpnp_tm_gen2_rev2_configure_trip_temps(struct qpnp_tm_chip *chip)
575{
576	int ret, i;
577
578	ret = thermal_zone_for_each_trip(chip->tz_dev,
579					 qpnp_tm_gen2_rev2_configure_trip_temps_cb, chip);
580	if (ret < 0)
581		return ret;
582
583	/* Verify that trips are strictly increasing. */
584	for (i = 1; i < STAGE_COUNT; i++) {
585		if (chip->temp_thresh_map[i] <= chip->temp_thresh_map[i - 1]) {
586			dev_err(chip->dev, "Threshold %d=%ld <= threshold %d=%ld\n",
587				i, chip->temp_thresh_map[i], i - 1,
588				chip->temp_thresh_map[i - 1]);
589			return -EINVAL;
590		}
591	}
592
593	return 0;
594}
595
596/* Read the hardware default TEMP_DAC stage threshold temperatures */
597static int qpnp_tm_gen2_rev2_sync_thresholds(struct qpnp_tm_chip *chip)
598{
599	int ret, i;
600	u8 reg = 0;
601
602	for (i = 0; i < STAGE_COUNT; i++) {
603		ret = qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, &reg);
604		if (ret < 0)
605			return ret;
606
607		chip->temp_thresh_map[i] = TEMP_DAC_REG_TO_TEMP(reg);
608	}
609
610	return 0;
611}
612
613/* Configure TEMP_LITE registers based on DT thermal_zone trips */
614static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip, void *data)
615{
616	struct qpnp_tm_chip *chip = data;
617	int ret;
618
619	mutex_lock(&chip->lock);
620	trip->priv = THERMAL_INT_TO_TRIP_PRIV(chip->ntrips);
621	ret = qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperature);
622	chip->ntrips++;
623	mutex_unlock(&chip->lock);
624
625	return ret;
626}
627
628static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip)
629{
630	int ret;
631
632	ret = thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_trip_temps_cb, chip);
633	if (ret < 0)
634		return ret;
635
636	/* Verify that trips are strictly increasing. */
637	if (chip->temp_thresh_map[2] <= chip->temp_thresh_map[0]) {
638		dev_err(chip->dev, "Threshold 2=%ld <= threshold 0=%ld\n",
639			chip->temp_thresh_map[2], chip->temp_thresh_map[0]);
640		return -EINVAL;
641	}
642
643	return 0;
644}
645
646/* Read the hardware default TEMP_LITE stage threshold temperatures */
647static int qpnp_tm_lite_sync_thresholds(struct qpnp_tm_chip *chip)
648{
649	int ret, thresh;
650	u8 reg = 0;
651
652	/*
653	 * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip
654	 * temp in temp_thresh_map[2].  The second trip point is purely in software
655	 * to facilitate a controlled shutdown after the warning threshold is
656	 * crossed but before the automatic hardware shutdown threshold is
657	 * crossed.  Thus, there is no register to read for the second trip
658	 * point.
659	 */
660	ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, &reg);
661	if (ret < 0)
662		return ret;
663
664	thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg);
665	chip->temp_thresh_map[0] = temp_lite_warning_map[thresh];
666
667	ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, &reg);
668	if (ret < 0)
669		return ret;
670
671	thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg);
672	chip->temp_thresh_map[2] = temp_lite_shutdown_map[thresh];
673
674	return 0;
675}
676
677static const struct spmi_temp_alarm_data spmi_temp_alarm_data = {
678	.ops = &qpnp_tm_sensor_ops,
679	.temp_map = &temp_map_gen1,
680	.sync_thresholds = qpnp_tm_sync_thresholds,
681	.configure_trip_temps = qpnp_tm_configure_trip_temp,
682	.get_temp_stage = qpnp_tm_gen1_get_temp_stage,
683};
684
685static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data = {
686	.ops = &qpnp_tm_sensor_ops,
687	.temp_map = &temp_map_gen1,
688	.sync_thresholds = qpnp_tm_sync_thresholds,
689	.configure_trip_temps = qpnp_tm_configure_trip_temp,
690	.get_temp_stage = qpnp_tm_gen2_get_temp_stage,
691};
692
693static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = {
694	.ops = &qpnp_tm_sensor_ops,
695	.temp_map = &temp_map_gen2_v1,
696	.sync_thresholds = qpnp_tm_sync_thresholds,
697	.configure_trip_temps = qpnp_tm_configure_trip_temp,
698	.get_temp_stage = qpnp_tm_gen2_get_temp_stage,
699};
700
701static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = {
702	.ops = &qpnp_tm_gen2_rev2_sensor_ops,
703	.sync_thresholds = qpnp_tm_gen2_rev2_sync_thresholds,
704	.configure_trip_temps = qpnp_tm_gen2_rev2_configure_trip_temps,
705	.get_temp_stage = qpnp_tm_gen2_get_temp_stage,
706};
707
708static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data = {
709	.ops = &qpnp_tm_lite_sensor_ops,
710	.sync_thresholds = qpnp_tm_lite_sync_thresholds,
711	.configure_trip_temps = qpnp_tm_lite_configure_trip_temps,
712	.get_temp_stage = qpnp_tm_lite_get_temp_stage,
713};
714
715/*
716 * This function initializes the internal temp value based on only the
717 * current thermal stage and threshold.
718 */
719static int qpnp_tm_threshold_init(struct qpnp_tm_chip *chip)
720{
721	int ret;
722
723	ret = chip->data->sync_thresholds(chip);
724	if (ret < 0)
725		return ret;
726
727	ret = chip->data->get_temp_stage(chip);
728	if (ret < 0)
729		return ret;
730	chip->stage = ret;
731	chip->temp = DEFAULT_TEMP;
732
733	if (chip->stage)
734		chip->temp = qpnp_tm_decode_temp(chip, chip->stage);
735
736	return ret;
737}
738
739/* This function initializes threshold control and disables shutdown override. */
740static int qpnp_tm_init(struct qpnp_tm_chip *chip)
741{
742	int ret;
743	u8 reg;
744
745	ret = chip->data->configure_trip_temps(chip);
746	if (ret < 0)
747		return ret;
748
749	/* Enable the thermal alarm PMIC module in always-on mode. */
750	reg = ALARM_CTRL_FORCE_ENABLE;
751	ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
752
753	chip->initialized = true;
754
755	return ret;
756}
757
758static int qpnp_tm_probe(struct platform_device *pdev)
759{
760	struct qpnp_tm_chip *chip;
761	struct device_node *node;
762	u8 type, subtype, dig_major, dig_minor;
763	u32 res, dig_revision;
764	int ret, irq;
765
766	node = pdev->dev.of_node;
767
768	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
769	if (!chip)
770		return -ENOMEM;
771
772	chip->dev = &pdev->dev;
773
774	mutex_init(&chip->lock);
775
776	chip->map = dev_get_regmap(pdev->dev.parent, NULL);
777	if (!chip->map)
778		return -ENXIO;
779
780	ret = of_property_read_u32(node, "reg", &res);
781	if (ret < 0)
782		return ret;
783
784	irq = platform_get_irq(pdev, 0);
785	if (irq < 0)
786		return irq;
787
788	/* ADC based measurements are optional */
789	chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
790	if (IS_ERR(chip->adc)) {
791		ret = PTR_ERR(chip->adc);
792		chip->adc = NULL;
793		if (ret == -EPROBE_DEFER)
794			return ret;
795	}
796
797	chip->base = res;
798
799	ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
800	if (ret < 0)
801		return dev_err_probe(&pdev->dev, ret,
802				     "could not read type\n");
803
804	ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
805	if (ret < 0)
806		return dev_err_probe(&pdev->dev, ret,
807				     "could not read subtype\n");
808
809	ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MAJOR, &dig_major);
810	if (ret < 0)
811		return dev_err_probe(&pdev->dev, ret,
812				     "could not read dig_major\n");
813
814	ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor);
815	if (ret < 0)
816		return dev_err_probe(&pdev->dev, ret,
817				     "could not read dig_minor\n");
818
819	if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
820				     && subtype != QPNP_TM_SUBTYPE_GEN2
821				     && subtype != QPNP_TM_SUBTYPE_LITE)) {
822		dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
823			type, subtype);
824		return -ENODEV;
825	}
826
827	chip->subtype = subtype;
828	if (subtype == QPNP_TM_SUBTYPE_GEN1)
829		chip->data = &spmi_temp_alarm_data;
830	else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major == 0)
831		chip->data = &spmi_temp_alarm_gen2_data;
832	else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major == 1)
833		chip->data = &spmi_temp_alarm_gen2_rev1_data;
834	else if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 2)
835		chip->data = &spmi_temp_alarm_gen2_rev2_data;
836	else if (subtype == QPNP_TM_SUBTYPE_LITE)
837		chip->data = &spmi_temp_alarm_lite_data;
838	else
839		return -ENODEV;
840
841	if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) {
842		dig_revision = (dig_major << 8) | dig_minor;
843		/*
844		 * Check if stage 2 automatic partial shutdown must remain
845		 * enabled to avoid potential repeated faults upon reaching
846		 * over-temperature stage 3.
847		 */
848		switch (dig_revision) {
849		case 0x0001:
850		case 0x0002:
851		case 0x0100:
852		case 0x0101:
853			chip->require_stage2_shutdown = true;
854			break;
855		}
856	}
857
858	ret = qpnp_tm_threshold_init(chip);
859	if (ret < 0)
860		return dev_err_probe(&pdev->dev, ret, "threshold init failed\n");
861
862	/*
863	 * Register the sensor before initializing the hardware to be able to
864	 * read the trip points. get_temp() returns the default temperature
865	 * before the hardware initialization is completed.
866	 */
867	chip->tz_dev = devm_thermal_of_zone_register(
868		&pdev->dev, 0, chip, chip->data->ops);
869	if (IS_ERR(chip->tz_dev))
870		return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev),
871				     "failed to register sensor\n");
872
873	ret = qpnp_tm_init(chip);
874	if (ret < 0)
875		return dev_err_probe(&pdev->dev, ret, "init failed\n");
876
877	devm_thermal_add_hwmon_sysfs(&pdev->dev, chip->tz_dev);
878
879	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
880					IRQF_ONESHOT, node->name, chip);
881	if (ret < 0)
882		return ret;
883
884	thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
885
886	return 0;
887}
888
889static const struct of_device_id qpnp_tm_match_table[] = {
890	{ .compatible = "qcom,spmi-temp-alarm" },
891	{ }
892};
893MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
894
895static struct platform_driver qpnp_tm_driver = {
896	.driver = {
897		.name = "spmi-temp-alarm",
898		.of_match_table = qpnp_tm_match_table,
899	},
900	.probe  = qpnp_tm_probe,
901};
902module_platform_driver(qpnp_tm_driver);
903
904MODULE_ALIAS("platform:spmi-temp-alarm");
905MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
906MODULE_LICENSE("GPL v2");