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lvts_thermal.c
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linux-6.19.14/drivers/thermal/mediatek/lvts_thermal.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/delay.h> 10#include <linux/debugfs.h> 11#include <linux/init.h> 12#include <linux/interrupt.h> 13#include <linux/iopoll.h> 14#include <linux/kernel.h> 15#include <linux/nvmem-consumer.h> 16#include <linux/of.h> 17#include <linux/platform_device.h> 18#include <linux/reset.h> 19#include <linux/thermal.h> 20#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22#include "../thermal_hwmon.h" 23 24#define LVTS_MONCTL0(__base) (__base + 0x0000) 25#define LVTS_MONCTL1(__base) (__base + 0x0004) 26#define LVTS_MONCTL2(__base) (__base + 0x0008) 27#define LVTS_MONINT(__base) (__base + 0x000C) 28#define LVTS_MONINTSTS(__base) (__base + 0x0010) 29#define LVTS_MONIDET0(__base) (__base + 0x0014) 30#define LVTS_MONIDET1(__base) (__base + 0x0018) 31#define LVTS_MONIDET2(__base) (__base + 0x001C) 32#define LVTS_MONIDET3(__base) (__base + 0x0020) 33#define LVTS_H2NTHRE(__base) (__base + 0x0024) 34#define LVTS_HTHRE(__base) (__base + 0x0028) 35#define LVTS_OFFSETH(__base) (__base + 0x0030) 36#define LVTS_OFFSETL(__base) (__base + 0x0034) 37#define LVTS_MSRCTL0(__base) (__base + 0x0038) 38#define LVTS_MSRCTL1(__base) (__base + 0x003C) 39#define LVTS_TSSEL(__base) (__base + 0x0040) 40#define LVTS_CALSCALE(__base) (__base + 0x0048) 41#define LVTS_ID(__base) (__base + 0x004C) 42#define LVTS_CONFIG(__base) (__base + 0x0050) 43#define LVTS_EDATA00(__base) (__base + 0x0054) 44#define LVTS_EDATA01(__base) (__base + 0x0058) 45#define LVTS_EDATA02(__base) (__base + 0x005C) 46#define LVTS_EDATA03(__base) (__base + 0x0060) 47#define LVTS_MSR0(__base) (__base + 0x0090) 48#define LVTS_MSR1(__base) (__base + 0x0094) 49#define LVTS_MSR2(__base) (__base + 0x0098) 50#define LVTS_MSR3(__base) (__base + 0x009C) 51#define LVTS_IMMD0(__base) (__base + 0x00A0) 52#define LVTS_IMMD1(__base) (__base + 0x00A4) 53#define LVTS_IMMD2(__base) (__base + 0x00A8) 54#define LVTS_IMMD3(__base) (__base + 0x00AC) 55#define LVTS_PROTCTL(__base) (__base + 0x00C0) 56#define LVTS_PROTTA(__base) (__base + 0x00C4) 57#define LVTS_PROTTB(__base) (__base + 0x00C8) 58#define LVTS_PROTTC(__base) (__base + 0x00CC) 59#define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61#define LVTS_PERIOD_UNIT 0 62#define LVTS_GROUP_INTERVAL 0 63#define LVTS_FILTER_INTERVAL 0 64#define LVTS_SENSOR_INTERVAL 0 65#define LVTS_HW_FILTER 0x0 66#define LVTS_TSSEL_CONF 0x13121110 67#define LVTS_CALSCALE_CONF 0x300 68 69#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0 BIT(3) 70#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1 BIT(8) 71#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2 BIT(13) 72#define LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3 BIT(25) 73#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0 BIT(2) 74#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1 BIT(7) 75#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2 BIT(12) 76#define LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3 BIT(24) 77 78#define LVTS_INT_SENSOR0 0x0009001F 79#define LVTS_INT_SENSOR1 0x001203E0 80#define LVTS_INT_SENSOR2 0x00247C00 81#define LVTS_INT_SENSOR3 0x1FC00000 82 83#define LVTS_SENSOR_MAX 4 84#define LVTS_GOLDEN_TEMP_MAX 62 85#define LVTS_GOLDEN_TEMP_DEFAULT 50 86#define LVTS_COEFF_A_MT8195 -250460 87#define LVTS_COEFF_B_MT8195 250460 88#define LVTS_COEFF_A_MT7988 -204650 89#define LVTS_COEFF_B_MT7988 204650 90 91#define LVTS_MSR_IMMEDIATE_MODE 0 92#define LVTS_MSR_FILTERED_MODE 1 93 94#define LVTS_MSR_READ_TIMEOUT_US 400 95#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 96 97#define LVTS_MINIMUM_THRESHOLD 20000 98 99static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 100static int golden_temp_offset; 101 102struct lvts_sensor_data { 103 int dt_id; 104 u8 cal_offsets[3]; 105}; 106 107struct lvts_ctrl_data { 108 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 109 u8 valid_sensor_mask; 110 int offset; 111 int mode; 112}; 113 114#define VALID_SENSOR_MAP(s0, s1, s2, s3) \ 115 .valid_sensor_mask = (((s0) ? BIT(0) : 0) | \ 116 ((s1) ? BIT(1) : 0) | \ 117 ((s2) ? BIT(2) : 0) | \ 118 ((s3) ? BIT(3) : 0)) 119 120#define lvts_for_each_valid_sensor(i, lvts_ctrl) \ 121 for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \ 122 if (!((lvts_ctrl)->valid_sensor_mask & BIT(i))) \ 123 continue; \ 124 else 125 126struct lvts_data { 127 const struct lvts_ctrl_data *lvts_ctrl; 128 const u32 *conn_cmd; 129 const u32 *init_cmd; 130 int num_lvts_ctrl; 131 int num_conn_cmd; 132 int num_init_cmd; 133 int temp_factor; 134 int temp_offset; 135 int gt_calib_bit_offset; 136 unsigned int def_calibration; 137}; 138 139struct lvts_sensor { 140 struct thermal_zone_device *tz; 141 void __iomem *msr; 142 void __iomem *base; 143 int id; 144 int dt_id; 145 int low_thresh; 146 int high_thresh; 147}; 148 149struct lvts_ctrl { 150 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 151 const struct lvts_data *lvts_data; 152 u32 calibration[LVTS_SENSOR_MAX]; 153 u8 valid_sensor_mask; 154 int mode; 155 void __iomem *base; 156 int low_thresh; 157 int high_thresh; 158}; 159 160struct lvts_domain { 161 struct lvts_ctrl *lvts_ctrl; 162 struct reset_control *reset; 163 struct clk *clk; 164 int num_lvts_ctrl; 165 void __iomem *base; 166 size_t calib_len; 167 u8 *calib; 168#ifdef CONFIG_DEBUG_FS 169 struct dentry *dom_dentry; 170#endif 171}; 172 173#ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 174 175#define LVTS_DEBUG_FS_REGS(__reg) \ 176{ \ 177 .name = __stringify(__reg), \ 178 .offset = __reg(0), \ 179} 180 181static const struct debugfs_reg32 lvts_regs[] = { 182 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 183 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 184 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 185 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 186 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 187 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 188 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 189 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 190 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 191 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 192 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 193 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 194 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 195 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 196 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 197 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 198 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 199 LVTS_DEBUG_FS_REGS(LVTS_ID), 200 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 201 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 202 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 203 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 204 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 205 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 206 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 207 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 208 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 209 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 210 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 211 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 212 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 213 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 214 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 215 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 216 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 217 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 218}; 219 220static void lvts_debugfs_exit(void *data) 221{ 222 struct lvts_domain *lvts_td = data; 223 224 debugfs_remove_recursive(lvts_td->dom_dentry); 225} 226 227static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 228{ 229 struct debugfs_regset32 *regset; 230 struct lvts_ctrl *lvts_ctrl; 231 struct dentry *dentry; 232 char name[64]; 233 int i; 234 235 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 236 if (IS_ERR(lvts_td->dom_dentry)) 237 return 0; 238 239 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 240 241 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 242 243 sprintf(name, "controller%d", i); 244 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 245 if (IS_ERR(dentry)) 246 continue; 247 248 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 249 if (!regset) 250 continue; 251 252 regset->base = lvts_ctrl->base; 253 regset->regs = lvts_regs; 254 regset->nregs = ARRAY_SIZE(lvts_regs); 255 256 debugfs_create_regset32("registers", 0400, dentry, regset); 257 } 258 259 return devm_add_action_or_reset(dev, lvts_debugfs_exit, lvts_td); 260} 261 262#else 263 264static inline int lvts_debugfs_init(struct device *dev, 265 struct lvts_domain *lvts_td) 266{ 267 return 0; 268} 269 270#endif 271 272static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 273{ 274 int temperature; 275 276 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 277 temperature += golden_temp_offset; 278 279 return temperature; 280} 281 282static u32 lvts_temp_to_raw(int temperature, int temp_factor) 283{ 284 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 285 286 raw_temp = div_s64(raw_temp, -temp_factor); 287 288 return raw_temp; 289} 290 291static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 292{ 293 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 294 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 295 sensors[lvts_sensor->id]); 296 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 297 void __iomem *msr = lvts_sensor->msr; 298 u32 value; 299 int rc; 300 301 /* 302 * Measurement registers: 303 * 304 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 305 * 306 * Bits: 307 * 308 * 32-17: Unused 309 * 16 : Valid temperature 310 * 15-0 : Raw temperature 311 */ 312 rc = readl_poll_timeout(msr, value, value & BIT(16), 313 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 314 315 /* 316 * As the thermal zone temperature will read before the 317 * hardware sensor is fully initialized, we have to check the 318 * validity of the temperature returned when reading the 319 * measurement register. The thermal controller will set the 320 * valid bit temperature only when it is totally initialized. 321 * 322 * Otherwise, we may end up with garbage values out of the 323 * functionning temperature and directly jump to a system 324 * shutdown. 325 */ 326 if (rc) 327 return -EAGAIN; 328 329 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 330 331 return 0; 332} 333 334static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 335{ 336 static const u32 high_offset_inten_masks[] = { 337 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR0, 338 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR1, 339 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR2, 340 LVTS_MONINT_OFFSET_HIGH_INTEN_SENSOR3, 341 }; 342 static const u32 low_offset_inten_masks[] = { 343 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR0, 344 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR1, 345 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR2, 346 LVTS_MONINT_OFFSET_LOW_INTEN_SENSOR3, 347 }; 348 u32 value = 0; 349 int i; 350 351 value = readl(LVTS_MONINT(lvts_ctrl->base)); 352 353 lvts_for_each_valid_sensor(i, lvts_ctrl) { 354 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 355 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) { 356 /* 357 * The minimum threshold needs to be configured in the 358 * OFFSETL register to get working interrupts, but we 359 * don't actually want to generate interrupts when 360 * crossing it. 361 */ 362 if (lvts_ctrl->low_thresh == -INT_MAX) { 363 value &= ~low_offset_inten_masks[i]; 364 value |= high_offset_inten_masks[i]; 365 } else { 366 value |= low_offset_inten_masks[i] | high_offset_inten_masks[i]; 367 } 368 } else { 369 value &= ~(low_offset_inten_masks[i] | high_offset_inten_masks[i]); 370 } 371 } 372 373 writel(value, LVTS_MONINT(lvts_ctrl->base)); 374} 375 376static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 377{ 378 int i; 379 380 if (high > lvts_ctrl->high_thresh) 381 return true; 382 383 lvts_for_each_valid_sensor(i, lvts_ctrl) 384 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 385 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 386 return false; 387 388 return true; 389} 390 391static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 392{ 393 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 394 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 395 sensors[lvts_sensor->id]); 396 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 397 void __iomem *base = lvts_sensor->base; 398 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 399 lvts_data->temp_factor); 400 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 401 bool should_update_thresh; 402 403 lvts_sensor->low_thresh = low; 404 lvts_sensor->high_thresh = high; 405 406 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 407 if (should_update_thresh) { 408 lvts_ctrl->high_thresh = high; 409 lvts_ctrl->low_thresh = low; 410 } 411 lvts_update_irq_mask(lvts_ctrl); 412 413 if (!should_update_thresh) 414 return 0; 415 416 /* 417 * Low offset temperature threshold 418 * 419 * LVTS_OFFSETL 420 * 421 * Bits: 422 * 423 * 14-0 : Raw temperature for threshold 424 */ 425 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 426 thermal_zone_device_type(tz), low); 427 writel(raw_low, LVTS_OFFSETL(base)); 428 429 /* 430 * High offset temperature threshold 431 * 432 * LVTS_OFFSETH 433 * 434 * Bits: 435 * 436 * 14-0 : Raw temperature for threshold 437 */ 438 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 439 thermal_zone_device_type(tz), high); 440 writel(raw_high, LVTS_OFFSETH(base)); 441 442 return 0; 443} 444 445static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 446{ 447 irqreturn_t iret = IRQ_NONE; 448 u32 value; 449 static const u32 masks[] = { 450 LVTS_INT_SENSOR0, 451 LVTS_INT_SENSOR1, 452 LVTS_INT_SENSOR2, 453 LVTS_INT_SENSOR3 454 }; 455 int i; 456 457 /* 458 * Interrupt monitoring status 459 * 460 * LVTS_MONINTST 461 * 462 * Bits: 463 * 464 * 31 : Interrupt for stage 3 465 * 30 : Interrupt for stage 2 466 * 29 : Interrupt for state 1 467 * 28 : Interrupt using filter on sensor 3 468 * 469 * 27 : Interrupt using immediate on sensor 3 470 * 26 : Interrupt normal to hot on sensor 3 471 * 25 : Interrupt high offset on sensor 3 472 * 24 : Interrupt low offset on sensor 3 473 * 474 * 23 : Interrupt hot threshold on sensor 3 475 * 22 : Interrupt cold threshold on sensor 3 476 * 21 : Interrupt using filter on sensor 2 477 * 20 : Interrupt using filter on sensor 1 478 * 479 * 19 : Interrupt using filter on sensor 0 480 * 18 : Interrupt using immediate on sensor 2 481 * 17 : Interrupt using immediate on sensor 1 482 * 16 : Interrupt using immediate on sensor 0 483 * 484 * 15 : Interrupt device access timeout interrupt 485 * 14 : Interrupt normal to hot on sensor 2 486 * 13 : Interrupt high offset interrupt on sensor 2 487 * 12 : Interrupt low offset interrupt on sensor 2 488 * 489 * 11 : Interrupt hot threshold on sensor 2 490 * 10 : Interrupt cold threshold on sensor 2 491 * 9 : Interrupt normal to hot on sensor 1 492 * 8 : Interrupt high offset interrupt on sensor 1 493 * 494 * 7 : Interrupt low offset interrupt on sensor 1 495 * 6 : Interrupt hot threshold on sensor 1 496 * 5 : Interrupt cold threshold on sensor 1 497 * 4 : Interrupt normal to hot on sensor 0 498 * 499 * 3 : Interrupt high offset interrupt on sensor 0 500 * 2 : Interrupt low offset interrupt on sensor 0 501 * 1 : Interrupt hot threshold on sensor 0 502 * 0 : Interrupt cold threshold on sensor 0 503 * 504 * We are interested in the sensor(s) responsible of the 505 * interrupt event. We update the thermal framework with the 506 * thermal zone associated with the sensor. The framework will 507 * take care of the rest whatever the kind of interrupt, we 508 * are only interested in which sensor raised the interrupt. 509 * 510 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 511 * => 0x1FC00000 512 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 513 * => 0x00247C00 514 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 515 * => 0X001203E0 516 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 517 * => 0x0009001F 518 */ 519 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 520 521 /* 522 * Let's figure out which sensors raised the interrupt 523 * 524 * NOTE: the masks array must be ordered with the index 525 * corresponding to the sensor id eg. index=0, mask for 526 * sensor0. 527 */ 528 for (i = 0; i < ARRAY_SIZE(masks); i++) { 529 530 if (!(value & masks[i])) 531 continue; 532 533 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 534 THERMAL_TRIP_VIOLATED); 535 iret = IRQ_HANDLED; 536 } 537 538 /* 539 * Write back to clear the interrupt status (W1C) 540 */ 541 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 542 543 return iret; 544} 545 546/* 547 * Temperature interrupt handler. Even if the driver supports more 548 * interrupt modes, we use the interrupt when the temperature crosses 549 * the hot threshold the way up and the way down (modulo the 550 * hysteresis). 551 * 552 * Each thermal domain has a couple of interrupts, one for hardware 553 * reset and another one for all the thermal events happening on the 554 * different sensors. 555 * 556 * The interrupt is configured for thermal events when crossing the 557 * hot temperature limit. At each interrupt, we check in every 558 * controller if there is an interrupt pending. 559 */ 560static irqreturn_t lvts_irq_handler(int irq, void *data) 561{ 562 struct lvts_domain *lvts_td = data; 563 irqreturn_t aux, iret = IRQ_NONE; 564 int i; 565 566 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 567 568 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 569 if (aux != IRQ_HANDLED) 570 continue; 571 572 iret = IRQ_HANDLED; 573 } 574 575 return iret; 576} 577 578static const struct thermal_zone_device_ops lvts_ops = { 579 .get_temp = lvts_get_temp, 580 .set_trips = lvts_set_trips, 581}; 582 583static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 584 const struct lvts_ctrl_data *lvts_ctrl_data) 585{ 586 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 587 588 void __iomem *msr_regs[] = { 589 LVTS_MSR0(lvts_ctrl->base), 590 LVTS_MSR1(lvts_ctrl->base), 591 LVTS_MSR2(lvts_ctrl->base), 592 LVTS_MSR3(lvts_ctrl->base) 593 }; 594 595 void __iomem *imm_regs[] = { 596 LVTS_IMMD0(lvts_ctrl->base), 597 LVTS_IMMD1(lvts_ctrl->base), 598 LVTS_IMMD2(lvts_ctrl->base), 599 LVTS_IMMD3(lvts_ctrl->base) 600 }; 601 602 int i; 603 604 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 605 606 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 607 608 /* 609 * At this point, we don't know which id matches which 610 * sensor. Let's set arbitrally the id from the index. 611 */ 612 lvts_sensor[i].id = i; 613 614 /* 615 * The thermal zone registration will set the trip 616 * point interrupt in the thermal controller 617 * register. But this one will be reset in the 618 * initialization after. So we need to post pone the 619 * thermal zone creation after the controller is 620 * setup. For this reason, we store the device tree 621 * node id from the data in the sensor structure 622 */ 623 lvts_sensor[i].dt_id = dt_id; 624 625 /* 626 * We assign the base address of the thermal 627 * controller as a back pointer. So it will be 628 * accessible from the different thermal framework ops 629 * as we pass the lvts_sensor pointer as thermal zone 630 * private data. 631 */ 632 lvts_sensor[i].base = lvts_ctrl->base; 633 634 /* 635 * Each sensor has its own register address to read from. 636 */ 637 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 638 imm_regs[i] : msr_regs[i]; 639 640 lvts_sensor[i].low_thresh = INT_MIN; 641 lvts_sensor[i].high_thresh = INT_MIN; 642 } 643 644 lvts_ctrl->valid_sensor_mask = lvts_ctrl_data->valid_sensor_mask; 645 646 return 0; 647} 648 649/* 650 * The efuse blob values follows the sensor enumeration per thermal 651 * controller. The decoding of the stream is as follow: 652 * 653 * MT8192 : 654 * Stream index map for MCU Domain mt8192 : 655 * 656 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 657 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 658 * 659 * <-----sensor#2-----> <-----sensor#3-----> 660 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 661 * 662 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 663 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 664 * 665 * Stream index map for AP Domain mt8192 : 666 * 667 * <-----sensor#0-----> <-----sensor#1-----> 668 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 669 * 670 * <-----sensor#2-----> <-----sensor#3-----> 671 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 672 * 673 * <-----sensor#4-----> <-----sensor#5-----> 674 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 675 * 676 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 677 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 678 * 679 * MT8195 : 680 * Stream index map for MCU Domain mt8195 : 681 * 682 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 683 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 684 * 685 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 686 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 687 * 688 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 689 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 690 * 691 * Stream index map for AP Domain mt8195 : 692 * 693 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 694 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 695 * 696 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 697 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 698 * 699 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 700 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 701 * 702 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 703 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 704 * 705 * Note: In some cases, values don't strictly follow a little endian ordering. 706 * The data description gives byte offsets constituting each calibration value 707 * for each sensor. 708 */ 709static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 710 const struct lvts_ctrl_data *lvts_ctrl_data, 711 u8 *efuse_calibration, 712 size_t calib_len) 713{ 714 int i; 715 u32 gt; 716 717 /* A zero value for gt means that device has invalid efuse data */ 718 gt = (((u32 *)efuse_calibration)[0] >> lvts_ctrl->lvts_data->gt_calib_bit_offset) & 0xff; 719 720 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 721 const struct lvts_sensor_data *sensor = 722 &lvts_ctrl_data->lvts_sensor[i]; 723 724 if (sensor->cal_offsets[0] >= calib_len || 725 sensor->cal_offsets[1] >= calib_len || 726 sensor->cal_offsets[2] >= calib_len) 727 return -EINVAL; 728 729 if (gt) { 730 lvts_ctrl->calibration[i] = 731 (efuse_calibration[sensor->cal_offsets[0]] << 0) + 732 (efuse_calibration[sensor->cal_offsets[1]] << 8) + 733 (efuse_calibration[sensor->cal_offsets[2]] << 16); 734 } else if (lvts_ctrl->lvts_data->def_calibration) { 735 lvts_ctrl->calibration[i] = lvts_ctrl->lvts_data->def_calibration; 736 } else { 737 dev_err(dev, "efuse contains invalid calibration data and no default given.\n"); 738 return -ENODATA; 739 } 740 } 741 742 return 0; 743} 744 745/* 746 * The efuse bytes stream can be split into different chunk of 747 * nvmems. This function reads and concatenate those into a single 748 * buffer so it can be read sequentially when initializing the 749 * calibration data. 750 */ 751static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 752 const struct lvts_data *lvts_data) 753{ 754 struct device_node *np = dev_of_node(dev); 755 struct nvmem_cell *cell; 756 struct property *prop; 757 const char *cell_name; 758 759 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 760 size_t len; 761 u8 *efuse; 762 763 cell = of_nvmem_cell_get(np, cell_name); 764 if (IS_ERR(cell)) { 765 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 766 return PTR_ERR(cell); 767 } 768 769 efuse = nvmem_cell_read(cell, &len); 770 771 nvmem_cell_put(cell); 772 773 if (IS_ERR(efuse)) { 774 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 775 return PTR_ERR(efuse); 776 } 777 778 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 779 lvts_td->calib_len + len, GFP_KERNEL); 780 if (!lvts_td->calib) { 781 kfree(efuse); 782 return -ENOMEM; 783 } 784 785 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 786 787 lvts_td->calib_len += len; 788 789 kfree(efuse); 790 } 791 792 return 0; 793} 794 795static int lvts_golden_temp_init(struct device *dev, u8 *calib, 796 const struct lvts_data *lvts_data) 797{ 798 u32 gt; 799 800 /* 801 * The golden temp information is contained in the first 32-bit 802 * word of efuse data at a specific bit offset. 803 */ 804 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff; 805 806 /* A zero value for gt means that device has invalid efuse data */ 807 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 808 golden_temp = gt; 809 810 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset; 811 812 dev_info(dev, "%sgolden temp=%d\n", gt ? "" : "fake ", golden_temp); 813 814 return 0; 815} 816 817static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 818 const struct lvts_data *lvts_data) 819{ 820 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 821 struct lvts_ctrl *lvts_ctrl; 822 int i, ret; 823 824 /* 825 * Create the calibration bytes stream from efuse data 826 */ 827 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 828 if (ret) 829 return ret; 830 831 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data); 832 if (ret) 833 return ret; 834 835 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 836 if (!lvts_ctrl) 837 return -ENOMEM; 838 839 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 840 841 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 842 lvts_ctrl[i].lvts_data = lvts_data; 843 844 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 845 &lvts_data->lvts_ctrl[i]); 846 if (ret) 847 return ret; 848 849 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 850 &lvts_data->lvts_ctrl[i], 851 lvts_td->calib, 852 lvts_td->calib_len); 853 if (ret) 854 return ret; 855 856 /* 857 * The mode the ctrl will use to read the temperature 858 * (filtered or immediate) 859 */ 860 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 861 862 lvts_ctrl[i].low_thresh = INT_MIN; 863 lvts_ctrl[i].high_thresh = INT_MIN; 864 } 865 866 /* 867 * We no longer need the efuse bytes stream, let's free it 868 */ 869 devm_kfree(dev, lvts_td->calib); 870 871 lvts_td->lvts_ctrl = lvts_ctrl; 872 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 873 874 return 0; 875} 876 877static void lvts_ctrl_monitor_enable(struct device *dev, struct lvts_ctrl *lvts_ctrl, bool enable) 878{ 879 /* 880 * Bitmaps to enable each sensor on filtered mode in the MONCTL0 881 * register. 882 */ 883 static const u8 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 884 u32 sensor_map = 0; 885 int i; 886 887 if (lvts_ctrl->mode != LVTS_MSR_FILTERED_MODE) 888 return; 889 890 if (enable) { 891 lvts_for_each_valid_sensor(i, lvts_ctrl) 892 sensor_map |= sensor_filt_bitmap[i]; 893 } 894 895 /* 896 * Bits: 897 * 9: Single point access flow 898 * 0-3: Enable sensing point 0-3 899 */ 900 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 901} 902 903/* 904 * At this point the configuration register is the only place in the 905 * driver where we write multiple values. Per hardware constraint, 906 * each write in the configuration register must be separated by a 907 * delay of 2 us. 908 */ 909static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, const u32 *cmds, int nr_cmds) 910{ 911 int i; 912 913 /* 914 * Configuration register 915 */ 916 for (i = 0; i < nr_cmds; i++) { 917 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 918 usleep_range(2, 4); 919 } 920} 921 922static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 923{ 924 /* 925 * LVTS_PROTCTL : Thermal Protection Sensor Selection 926 * 927 * Bits: 928 * 929 * 19-18 : Sensor to base the protection on 930 * 17-16 : Strategy: 931 * 00 : Average of 4 sensors 932 * 01 : Max of 4 sensors 933 * 10 : Selected sensor with bits 19-18 934 * 11 : Reserved 935 */ 936 937 /* 938 * LVTS_PROTTA : Stage 1 temperature threshold 939 * LVTS_PROTTB : Stage 2 temperature threshold 940 * LVTS_PROTTC : Stage 3 temperature threshold 941 * 942 * Bits: 943 * 944 * 14-0: Raw temperature threshold 945 * 946 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 947 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 948 * writel(0x0, LVTS_PROTTC(lvts_ctrl->base)); 949 */ 950 951 /* 952 * LVTS_MONINT : Interrupt configuration register 953 * 954 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 955 * register, except we set the bits to enable the interrupt. 956 */ 957 writel(0, LVTS_MONINT(lvts_ctrl->base)); 958 959 return 0; 960} 961 962static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 963{ 964 int ret; 965 966 ret = reset_control_assert(reset); 967 if (ret) 968 return ret; 969 970 return reset_control_deassert(reset); 971} 972 973/* 974 * Enable or disable the clocks of a specified thermal controller 975 */ 976static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 977{ 978 /* 979 * LVTS_CLKEN : Internal LVTS clock 980 * 981 * Bits: 982 * 983 * 0 : enable / disable clock 984 */ 985 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 986 987 return 0; 988} 989 990static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 991{ 992 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 993 u32 id; 994 995 lvts_write_config(lvts_ctrl, lvts_data->conn_cmd, lvts_data->num_conn_cmd); 996 997 /* 998 * LVTS_ID : Get ID and status of the thermal controller 999 * 1000 * Bits: 1001 * 1002 * 0-5 : thermal controller id 1003 * 7 : thermal controller connection is valid 1004 */ 1005 id = readl(LVTS_ID(lvts_ctrl->base)); 1006 if (!(id & BIT(7))) 1007 return -EIO; 1008 1009 return 0; 1010} 1011 1012static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1013{ 1014 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 1015 1016 lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd); 1017 1018 return 0; 1019} 1020 1021static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1022{ 1023 int i; 1024 void __iomem *lvts_edata[] = { 1025 LVTS_EDATA00(lvts_ctrl->base), 1026 LVTS_EDATA01(lvts_ctrl->base), 1027 LVTS_EDATA02(lvts_ctrl->base), 1028 LVTS_EDATA03(lvts_ctrl->base) 1029 }; 1030 1031 /* 1032 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 1033 * 1034 * Bits: 1035 * 1036 * 20-0 : Efuse value for normalization data 1037 */ 1038 for (i = 0; i < LVTS_SENSOR_MAX; i++) 1039 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 1040 1041 return 0; 1042} 1043 1044static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1045{ 1046 u32 value; 1047 1048 /* 1049 * LVTS_TSSEL : Sensing point index numbering 1050 * 1051 * Bits: 1052 * 1053 * 31-24: ADC Sense 3 1054 * 23-16: ADC Sense 2 1055 * 15-8 : ADC Sense 1 1056 * 7-0 : ADC Sense 0 1057 */ 1058 value = LVTS_TSSEL_CONF; 1059 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 1060 1061 /* 1062 * LVTS_CALSCALE : ADC voltage round 1063 */ 1064 value = 0x300; 1065 value = LVTS_CALSCALE_CONF; 1066 1067 /* 1068 * LVTS_MSRCTL0 : Sensor filtering strategy 1069 * 1070 * Filters: 1071 * 1072 * 000 : One sample 1073 * 001 : Avg 2 samples 1074 * 010 : 4 samples, drop min and max, avg 2 samples 1075 * 011 : 6 samples, drop min and max, avg 4 samples 1076 * 100 : 10 samples, drop min and max, avg 8 samples 1077 * 101 : 18 samples, drop min and max, avg 16 samples 1078 * 1079 * Bits: 1080 * 1081 * 0-2 : Sensor0 filter 1082 * 3-5 : Sensor1 filter 1083 * 6-8 : Sensor2 filter 1084 * 9-11 : Sensor3 filter 1085 */ 1086 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1087 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1088 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1089 1090 /* 1091 * LVTS_MONCTL1 : Period unit and group interval configuration 1092 * 1093 * The clock source of LVTS thermal controller is 26MHz. 1094 * 1095 * The period unit is a time base for all the interval delays 1096 * specified in the registers. By default we use 12. The time 1097 * conversion is done by multiplying by 256 and 1/26.10^6 1098 * 1099 * An interval delay multiplied by the period unit gives the 1100 * duration in seconds. 1101 * 1102 * - Filter interval delay is a delay between two samples of 1103 * the same sensor. 1104 * 1105 * - Sensor interval delay is a delay between two samples of 1106 * different sensors. 1107 * 1108 * - Group interval delay is a delay between different rounds. 1109 * 1110 * For example: 1111 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1112 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1113 * and then 1114 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1115 * Filter interval delay = 1 * Period unit = 118.149us 1116 * Sensor interval delay = 2 * Period unit = 236.298us 1117 * Group interval delay = 1 * Period unit = 118.149us 1118 * 1119 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1120 * <--> Filter interval delay 1121 * <--> Sensor interval delay 1122 * <--> Group interval delay 1123 * Bits: 1124 * 29 - 20 : Group interval 1125 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1126 * or an interrupt everytime the hot threshold is crossed (0) 1127 * 9 - 0 : Period unit 1128 * 1129 */ 1130 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1131 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1132 1133 /* 1134 * LVTS_MONCTL2 : Filtering and sensor interval 1135 * 1136 * Bits: 1137 * 1138 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1139 * the same sensor, filter interval 1140 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1141 * 1142 */ 1143 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1144 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1145 1146 return lvts_irq_init(lvts_ctrl); 1147} 1148 1149static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1150{ 1151 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1152 struct thermal_zone_device *tz; 1153 u32 sensor_map = 0; 1154 int i; 1155 /* 1156 * Bitmaps to enable each sensor on immediate and filtered modes, as 1157 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1158 */ 1159 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1160 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1161 1162 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1163 sensor_imm_bitmap : sensor_filt_bitmap; 1164 1165 lvts_for_each_valid_sensor(i, lvts_ctrl) { 1166 1167 int dt_id = lvts_sensors[i].dt_id; 1168 1169 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1170 &lvts_ops); 1171 if (IS_ERR(tz)) { 1172 /* 1173 * This thermal zone is not described in the 1174 * device tree. It is not an error from the 1175 * thermal OF code POV, we just continue. 1176 */ 1177 if (PTR_ERR(tz) == -ENODEV) 1178 continue; 1179 1180 return PTR_ERR(tz); 1181 } 1182 1183 devm_thermal_add_hwmon_sysfs(dev, tz); 1184 1185 /* 1186 * The thermal zone pointer will be needed in the 1187 * interrupt handler, we store it in the sensor 1188 * structure. The thermal domain structure will be 1189 * passed to the interrupt handler private data as the 1190 * interrupt is shared for all the controller 1191 * belonging to the thermal domain. 1192 */ 1193 lvts_sensors[i].tz = tz; 1194 1195 /* 1196 * This sensor was correctly associated with a thermal 1197 * zone, let's set the corresponding bit in the sensor 1198 * map, so we can enable the temperature monitoring in 1199 * the hardware thermal controller. 1200 */ 1201 sensor_map |= sensor_bitmap[i]; 1202 } 1203 1204 /* 1205 * The initialization of the thermal zones give us 1206 * which sensor point to enable. If any thermal zone 1207 * was not described in the device tree, it won't be 1208 * enabled here in the sensor map. 1209 */ 1210 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1211 /* 1212 * LVTS_MSRCTL1 : Measurement control 1213 * 1214 * Bits: 1215 * 1216 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1217 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1218 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1219 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1220 * 1221 * That configuration will ignore the filtering and the delays 1222 * introduced in MONCTL1 and MONCTL2 1223 */ 1224 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1225 } else { 1226 /* 1227 * Bits: 1228 * 9: Single point access flow 1229 * 0-3: Enable sensing point 0-3 1230 */ 1231 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1232 } 1233 1234 return 0; 1235} 1236 1237static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1238 const struct lvts_data *lvts_data) 1239{ 1240 struct lvts_ctrl *lvts_ctrl; 1241 int i, ret; 1242 1243 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1244 if (ret) 1245 return ret; 1246 1247 ret = lvts_domain_reset(dev, lvts_td->reset); 1248 if (ret) { 1249 dev_dbg(dev, "Failed to reset domain"); 1250 return ret; 1251 } 1252 1253 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1254 1255 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1256 1257 /* 1258 * Initialization steps: 1259 * 1260 * - Enable the clock 1261 * - Connect to the LVTS 1262 * - Initialize the LVTS 1263 * - Prepare the calibration data 1264 * - Select monitored sensors 1265 * [ Configure sampling ] 1266 * [ Configure the interrupt ] 1267 * - Start measurement 1268 */ 1269 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1270 if (ret) { 1271 dev_dbg(dev, "Failed to enable LVTS clock"); 1272 return ret; 1273 } 1274 1275 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1276 if (ret) { 1277 dev_dbg(dev, "Failed to connect to LVTS controller"); 1278 return ret; 1279 } 1280 1281 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1282 if (ret) { 1283 dev_dbg(dev, "Failed to initialize controller"); 1284 return ret; 1285 } 1286 1287 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1288 if (ret) { 1289 dev_dbg(dev, "Failed to calibrate controller"); 1290 return ret; 1291 } 1292 1293 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1294 if (ret) { 1295 dev_dbg(dev, "Failed to configure controller"); 1296 return ret; 1297 } 1298 1299 ret = lvts_ctrl_start(dev, lvts_ctrl); 1300 if (ret) { 1301 dev_dbg(dev, "Failed to start controller"); 1302 return ret; 1303 } 1304 } 1305 1306 return lvts_debugfs_init(dev, lvts_td); 1307} 1308 1309static int lvts_probe(struct platform_device *pdev) 1310{ 1311 const struct lvts_data *lvts_data; 1312 struct lvts_domain *lvts_td; 1313 struct device *dev = &pdev->dev; 1314 struct resource *res; 1315 int irq, ret; 1316 1317 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1318 if (!lvts_td) 1319 return -ENOMEM; 1320 1321 lvts_data = of_device_get_match_data(dev); 1322 if (!lvts_data) 1323 return -ENODEV; 1324 1325 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1326 if (IS_ERR(lvts_td->clk)) 1327 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1328 1329 res = platform_get_mem_or_io(pdev, 0); 1330 if (!res) 1331 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1332 1333 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1334 if (IS_ERR(lvts_td->base)) 1335 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1336 1337 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1338 if (IS_ERR(lvts_td->reset)) 1339 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1340 1341 irq = platform_get_irq(pdev, 0); 1342 if (irq < 0) 1343 return irq; 1344 1345 golden_temp_offset = lvts_data->temp_offset; 1346 1347 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1348 if (ret) 1349 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1350 1351 /* 1352 * At this point the LVTS is initialized and enabled. We can 1353 * safely enable the interrupt. 1354 */ 1355 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1356 IRQF_ONESHOT, dev_name(dev), lvts_td); 1357 if (ret) 1358 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1359 1360 platform_set_drvdata(pdev, lvts_td); 1361 1362 return 0; 1363} 1364 1365static void lvts_remove(struct platform_device *pdev) 1366{ 1367 struct lvts_domain *lvts_td; 1368 int i; 1369 1370 lvts_td = platform_get_drvdata(pdev); 1371 1372 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1373 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1374} 1375 1376static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1377 { 1378 .lvts_sensor = { 1379 { .dt_id = MT7988_CPU_0, 1380 .cal_offsets = { 0x00, 0x01, 0x02 } }, 1381 { .dt_id = MT7988_CPU_1, 1382 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1383 { .dt_id = MT7988_ETH2P5G_0, 1384 .cal_offsets = { 0x08, 0x09, 0x0a } }, 1385 { .dt_id = MT7988_ETH2P5G_1, 1386 .cal_offsets = { 0x0c, 0x0d, 0x0e } } 1387 }, 1388 VALID_SENSOR_MAP(1, 1, 1, 1), 1389 .offset = 0x0, 1390 }, 1391 { 1392 .lvts_sensor = { 1393 { .dt_id = MT7988_TOPS_0, 1394 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1395 { .dt_id = MT7988_TOPS_1, 1396 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1397 { .dt_id = MT7988_ETHWARP_0, 1398 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1399 { .dt_id = MT7988_ETHWARP_1, 1400 .cal_offsets = { 0x20, 0x21, 0x22 } } 1401 }, 1402 VALID_SENSOR_MAP(1, 1, 1, 1), 1403 .offset = 0x100, 1404 } 1405}; 1406 1407static int lvts_suspend(struct device *dev) 1408{ 1409 struct lvts_domain *lvts_td; 1410 int i; 1411 1412 lvts_td = dev_get_drvdata(dev); 1413 1414 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1415 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], false); 1416 usleep_range(100, 200); 1417 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1418 } 1419 1420 clk_disable_unprepare(lvts_td->clk); 1421 1422 return 0; 1423} 1424 1425static int lvts_resume(struct device *dev) 1426{ 1427 struct lvts_domain *lvts_td; 1428 int i, ret; 1429 1430 lvts_td = dev_get_drvdata(dev); 1431 1432 ret = clk_prepare_enable(lvts_td->clk); 1433 if (ret) 1434 return ret; 1435 1436 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1437 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1438 usleep_range(100, 200); 1439 lvts_ctrl_monitor_enable(dev, &lvts_td->lvts_ctrl[i], true); 1440 } 1441 1442 return 0; 1443} 1444 1445static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 }; 1446static const u32 mt7988_conn_cmds[] = { 0xC103FFFF, 0xC502FC55 }; 1447 1448/* 1449 * Write device mask: 0xC1030000 1450 */ 1451static const u32 default_init_cmds[] = { 1452 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 1453 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 1454 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 1455 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 1456}; 1457 1458static const u32 mt7988_init_cmds[] = { 1459 0xC1030300, 0xC1030420, 0xC1030500, 0xC10307A6, 0xC1030CFC, 1460 0xC1030A8C, 0xC103098D, 0xC10308F1, 0xC1030B04, 0xC1030E01, 1461 0xC10306B8 1462}; 1463 1464/* 1465 * The MT8186 calibration data is stored as packed 3-byte little-endian 1466 * values using a weird layout that makes sense only when viewed as a 32-bit 1467 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and 1468 * y = byte number where the LSB is y=0. We then have: 1469 * 1470 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0] 1471 * 1472 * However, when considering a byte stream, those appear as follows: 1473 * 1474 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0] 1475 * 1476 * Hence the rather confusing offsets provided below. 1477 */ 1478static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { 1479 { 1480 .lvts_sensor = { 1481 { .dt_id = MT8186_LITTLE_CPU0, 1482 .cal_offsets = { 5, 6, 7 } }, 1483 { .dt_id = MT8186_LITTLE_CPU1, 1484 .cal_offsets = { 10, 11, 4 } }, 1485 { .dt_id = MT8186_LITTLE_CPU2, 1486 .cal_offsets = { 15, 8, 9 } }, 1487 { .dt_id = MT8186_CAM, 1488 .cal_offsets = { 12, 13, 14 } } 1489 }, 1490 VALID_SENSOR_MAP(1, 1, 1, 1), 1491 .offset = 0x0, 1492 }, 1493 { 1494 .lvts_sensor = { 1495 { .dt_id = MT8186_BIG_CPU0, 1496 .cal_offsets = { 22, 23, 16 } }, 1497 { .dt_id = MT8186_BIG_CPU1, 1498 .cal_offsets = { 27, 20, 21 } } 1499 }, 1500 VALID_SENSOR_MAP(1, 1, 0, 0), 1501 .offset = 0x100, 1502 }, 1503 { 1504 .lvts_sensor = { 1505 { .dt_id = MT8186_NNA, 1506 .cal_offsets = { 29, 30, 31 } }, 1507 { .dt_id = MT8186_ADSP, 1508 .cal_offsets = { 34, 35, 28 } }, 1509 { .dt_id = MT8186_GPU, 1510 .cal_offsets = { 39, 32, 33 } } 1511 }, 1512 VALID_SENSOR_MAP(1, 1, 1, 0), 1513 .offset = 0x200, 1514 } 1515}; 1516 1517static const struct lvts_ctrl_data mt8188_lvts_mcu_data_ctrl[] = { 1518 { 1519 .lvts_sensor = { 1520 { .dt_id = MT8188_MCU_LITTLE_CPU0, 1521 .cal_offsets = { 22, 23, 24 } }, 1522 { .dt_id = MT8188_MCU_LITTLE_CPU1, 1523 .cal_offsets = { 25, 26, 27 } }, 1524 { .dt_id = MT8188_MCU_LITTLE_CPU2, 1525 .cal_offsets = { 28, 29, 30 } }, 1526 { .dt_id = MT8188_MCU_LITTLE_CPU3, 1527 .cal_offsets = { 31, 32, 33 } }, 1528 }, 1529 VALID_SENSOR_MAP(1, 1, 1, 1), 1530 .offset = 0x0, 1531 }, 1532 { 1533 .lvts_sensor = { 1534 { .dt_id = MT8188_MCU_BIG_CPU0, 1535 .cal_offsets = { 34, 35, 36 } }, 1536 { .dt_id = MT8188_MCU_BIG_CPU1, 1537 .cal_offsets = { 37, 38, 39 } }, 1538 }, 1539 VALID_SENSOR_MAP(1, 1, 0, 0), 1540 .offset = 0x100, 1541 } 1542}; 1543 1544static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { 1545 { 1546 .lvts_sensor = { 1547 1548 { /* unused */ }, 1549 { .dt_id = MT8188_AP_APU, 1550 .cal_offsets = { 40, 41, 42 } }, 1551 }, 1552 VALID_SENSOR_MAP(0, 1, 0, 0), 1553 .offset = 0x0, 1554 }, 1555 { 1556 .lvts_sensor = { 1557 { .dt_id = MT8188_AP_GPU0, 1558 .cal_offsets = { 43, 44, 45 } }, 1559 { .dt_id = MT8188_AP_GPU1, 1560 .cal_offsets = { 46, 47, 48 } }, 1561 { .dt_id = MT8188_AP_ADSP, 1562 .cal_offsets = { 49, 50, 51 } }, 1563 }, 1564 VALID_SENSOR_MAP(1, 1, 1, 0), 1565 .offset = 0x100, 1566 }, 1567 { 1568 .lvts_sensor = { 1569 { .dt_id = MT8188_AP_VDO, 1570 .cal_offsets = { 52, 53, 54 } }, 1571 { .dt_id = MT8188_AP_INFRA, 1572 .cal_offsets = { 55, 56, 57 } }, 1573 }, 1574 VALID_SENSOR_MAP(1, 1, 0, 0), 1575 .offset = 0x200, 1576 }, 1577 { 1578 .lvts_sensor = { 1579 { .dt_id = MT8188_AP_CAM1, 1580 .cal_offsets = { 58, 59, 60 } }, 1581 { .dt_id = MT8188_AP_CAM2, 1582 .cal_offsets = { 61, 62, 63 } }, 1583 }, 1584 VALID_SENSOR_MAP(1, 1, 0, 0), 1585 .offset = 0x300, 1586 } 1587}; 1588 1589static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1590 { 1591 .lvts_sensor = { 1592 { .dt_id = MT8192_MCU_BIG_CPU0, 1593 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1594 { .dt_id = MT8192_MCU_BIG_CPU1, 1595 .cal_offsets = { 0x08, 0x09, 0x0a } } 1596 }, 1597 VALID_SENSOR_MAP(1, 1, 0, 0), 1598 .offset = 0x0, 1599 .mode = LVTS_MSR_FILTERED_MODE, 1600 }, 1601 { 1602 .lvts_sensor = { 1603 { .dt_id = MT8192_MCU_BIG_CPU2, 1604 .cal_offsets = { 0x0c, 0x0d, 0x0e } }, 1605 { .dt_id = MT8192_MCU_BIG_CPU3, 1606 .cal_offsets = { 0x10, 0x11, 0x12 } } 1607 }, 1608 VALID_SENSOR_MAP(1, 1, 0, 0), 1609 .offset = 0x100, 1610 .mode = LVTS_MSR_FILTERED_MODE, 1611 }, 1612 { 1613 .lvts_sensor = { 1614 { .dt_id = MT8192_MCU_LITTLE_CPU0, 1615 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1616 { .dt_id = MT8192_MCU_LITTLE_CPU1, 1617 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1618 { .dt_id = MT8192_MCU_LITTLE_CPU2, 1619 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1620 { .dt_id = MT8192_MCU_LITTLE_CPU3, 1621 .cal_offsets = { 0x20, 0x21, 0x22 } } 1622 }, 1623 VALID_SENSOR_MAP(1, 1, 1, 1), 1624 .offset = 0x200, 1625 .mode = LVTS_MSR_FILTERED_MODE, 1626 } 1627}; 1628 1629static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1630 { 1631 .lvts_sensor = { 1632 { .dt_id = MT8192_AP_VPU0, 1633 .cal_offsets = { 0x24, 0x25, 0x26 } }, 1634 { .dt_id = MT8192_AP_VPU1, 1635 .cal_offsets = { 0x28, 0x29, 0x2a } } 1636 }, 1637 VALID_SENSOR_MAP(1, 1, 0, 0), 1638 .offset = 0x0, 1639 }, 1640 { 1641 .lvts_sensor = { 1642 { .dt_id = MT8192_AP_GPU0, 1643 .cal_offsets = { 0x2c, 0x2d, 0x2e } }, 1644 { .dt_id = MT8192_AP_GPU1, 1645 .cal_offsets = { 0x30, 0x31, 0x32 } } 1646 }, 1647 VALID_SENSOR_MAP(1, 1, 0, 0), 1648 .offset = 0x100, 1649 }, 1650 { 1651 .lvts_sensor = { 1652 { .dt_id = MT8192_AP_INFRA, 1653 .cal_offsets = { 0x34, 0x35, 0x36 } }, 1654 { .dt_id = MT8192_AP_CAM, 1655 .cal_offsets = { 0x38, 0x39, 0x3a } }, 1656 }, 1657 VALID_SENSOR_MAP(1, 1, 0, 0), 1658 .offset = 0x200, 1659 }, 1660 { 1661 .lvts_sensor = { 1662 { .dt_id = MT8192_AP_MD0, 1663 .cal_offsets = { 0x3c, 0x3d, 0x3e } }, 1664 { .dt_id = MT8192_AP_MD1, 1665 .cal_offsets = { 0x40, 0x41, 0x42 } }, 1666 { .dt_id = MT8192_AP_MD2, 1667 .cal_offsets = { 0x44, 0x45, 0x46 } } 1668 }, 1669 VALID_SENSOR_MAP(1, 1, 1, 0), 1670 .offset = 0x300, 1671 } 1672}; 1673 1674static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1675 { 1676 .lvts_sensor = { 1677 { .dt_id = MT8195_MCU_BIG_CPU0, 1678 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1679 { .dt_id = MT8195_MCU_BIG_CPU1, 1680 .cal_offsets = { 0x07, 0x08, 0x09 } } 1681 }, 1682 VALID_SENSOR_MAP(1, 1, 0, 0), 1683 .offset = 0x0, 1684 }, 1685 { 1686 .lvts_sensor = { 1687 { .dt_id = MT8195_MCU_BIG_CPU2, 1688 .cal_offsets = { 0x0d, 0x0e, 0x0f } }, 1689 { .dt_id = MT8195_MCU_BIG_CPU3, 1690 .cal_offsets = { 0x10, 0x11, 0x12 } } 1691 }, 1692 VALID_SENSOR_MAP(1, 1, 0, 0), 1693 .offset = 0x100, 1694 }, 1695 { 1696 .lvts_sensor = { 1697 { .dt_id = MT8195_MCU_LITTLE_CPU0, 1698 .cal_offsets = { 0x16, 0x17, 0x18 } }, 1699 { .dt_id = MT8195_MCU_LITTLE_CPU1, 1700 .cal_offsets = { 0x19, 0x1a, 0x1b } }, 1701 { .dt_id = MT8195_MCU_LITTLE_CPU2, 1702 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1703 { .dt_id = MT8195_MCU_LITTLE_CPU3, 1704 .cal_offsets = { 0x1f, 0x20, 0x21 } } 1705 }, 1706 VALID_SENSOR_MAP(1, 1, 1, 1), 1707 .offset = 0x200, 1708 } 1709}; 1710 1711static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1712 { 1713 .lvts_sensor = { 1714 { .dt_id = MT8195_AP_VPU0, 1715 .cal_offsets = { 0x25, 0x26, 0x27 } }, 1716 { .dt_id = MT8195_AP_VPU1, 1717 .cal_offsets = { 0x28, 0x29, 0x2a } } 1718 }, 1719 VALID_SENSOR_MAP(1, 1, 0, 0), 1720 .offset = 0x0, 1721 }, 1722 { 1723 .lvts_sensor = { 1724 { .dt_id = MT8195_AP_GPU0, 1725 .cal_offsets = { 0x2e, 0x2f, 0x30 } }, 1726 { .dt_id = MT8195_AP_GPU1, 1727 .cal_offsets = { 0x31, 0x32, 0x33 } } 1728 }, 1729 VALID_SENSOR_MAP(1, 1, 0, 0), 1730 .offset = 0x100, 1731 }, 1732 { 1733 .lvts_sensor = { 1734 { .dt_id = MT8195_AP_VDEC, 1735 .cal_offsets = { 0x37, 0x38, 0x39 } }, 1736 { .dt_id = MT8195_AP_IMG, 1737 .cal_offsets = { 0x3a, 0x3b, 0x3c } }, 1738 { .dt_id = MT8195_AP_INFRA, 1739 .cal_offsets = { 0x3d, 0x3e, 0x3f } } 1740 }, 1741 VALID_SENSOR_MAP(1, 1, 1, 0), 1742 .offset = 0x200, 1743 }, 1744 { 1745 .lvts_sensor = { 1746 { .dt_id = MT8195_AP_CAM0, 1747 .cal_offsets = { 0x43, 0x44, 0x45 } }, 1748 { .dt_id = MT8195_AP_CAM1, 1749 .cal_offsets = { 0x46, 0x47, 0x48 } } 1750 }, 1751 VALID_SENSOR_MAP(1, 1, 0, 0), 1752 .offset = 0x300, 1753 } 1754}; 1755 1756static const struct lvts_data mt7988_lvts_ap_data = { 1757 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1758 .conn_cmd = mt7988_conn_cmds, 1759 .init_cmd = mt7988_init_cmds, 1760 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1761 .num_conn_cmd = ARRAY_SIZE(mt7988_conn_cmds), 1762 .num_init_cmd = ARRAY_SIZE(mt7988_init_cmds), 1763 .temp_factor = LVTS_COEFF_A_MT7988, 1764 .temp_offset = LVTS_COEFF_B_MT7988, 1765 .gt_calib_bit_offset = 24, 1766}; 1767 1768static const struct lvts_data mt8186_lvts_data = { 1769 .lvts_ctrl = mt8186_lvts_data_ctrl, 1770 .conn_cmd = default_conn_cmds, 1771 .init_cmd = default_init_cmds, 1772 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), 1773 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), 1774 .num_init_cmd = ARRAY_SIZE(default_init_cmds), 1775 .temp_factor = LVTS_COEFF_A_MT7988, 1776 .temp_offset = LVTS_COEFF_B_MT7988, 1777 .gt_calib_bit_offset = 24, 1778 .def_calibration = 19000, 1779}; 1780 1781static const struct lvts_data mt8188_lvts_mcu_data = { 1782 .lvts_ctrl = mt8188_lvts_mcu_data_ctrl, 1783 .conn_cmd = default_conn_cmds, 1784 .init_cmd = default_init_cmds, 1785 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl), 1786 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), 1787 .num_init_cmd = ARRAY_SIZE(default_init_cmds), 1788 .temp_factor = LVTS_COEFF_A_MT8195, 1789 .temp_offset = LVTS_COEFF_B_MT8195, 1790 .gt_calib_bit_offset = 20, 1791 .def_calibration = 35000, 1792}; 1793 1794static const struct lvts_data mt8188_lvts_ap_data = { 1795 .lvts_ctrl = mt8188_lvts_ap_data_ctrl, 1796 .conn_cmd = default_conn_cmds, 1797 .init_cmd = default_init_cmds, 1798 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl), 1799 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), 1800 .num_init_cmd = ARRAY_SIZE(default_init_cmds), 1801 .temp_factor = LVTS_COEFF_A_MT8195, 1802 .temp_offset = LVTS_COEFF_B_MT8195, 1803 .gt_calib_bit_offset = 20, 1804 .def_calibration = 35000, 1805}; 1806 1807static const struct lvts_data mt8192_lvts_mcu_data = { 1808 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1809 .conn_cmd = default_conn_cmds, 1810 .init_cmd = default_init_cmds, 1811 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1812 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), 1813 .num_init_cmd = ARRAY_SIZE(default_init_cmds), 1814 .temp_factor = LVTS_COEFF_A_MT8195, 1815 .temp_offset = LVTS_COEFF_B_MT8195, 1816 .gt_calib_bit_offset = 24, 1817 .def_calibration = 35000, 1818}; 1819 1820static const struct lvts_data mt8192_lvts_ap_data = { 1821 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1822 .conn_cmd = default_conn_cmds, 1823 .init_cmd = default_init_cmds, 1824 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1825 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), 1826 .num_init_cmd = ARRAY_SIZE(default_init_cmds), 1827 .temp_factor = LVTS_COEFF_A_MT8195, 1828 .temp_offset = LVTS_COEFF_B_MT8195, 1829 .gt_calib_bit_offset = 24, 1830 .def_calibration = 35000, 1831}; 1832 1833static const struct lvts_data mt8195_lvts_mcu_data = { 1834 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1835 .conn_cmd = default_conn_cmds, 1836 .init_cmd = default_init_cmds, 1837 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1838 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), 1839 .num_init_cmd = ARRAY_SIZE(default_init_cmds), 1840 .temp_factor = LVTS_COEFF_A_MT8195, 1841 .temp_offset = LVTS_COEFF_B_MT8195, 1842 .gt_calib_bit_offset = 24, 1843 .def_calibration = 35000, 1844}; 1845 1846static const struct lvts_data mt8195_lvts_ap_data = { 1847 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1848 .conn_cmd = default_conn_cmds, 1849 .init_cmd = default_init_cmds, 1850 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1851 .num_conn_cmd = ARRAY_SIZE(default_conn_cmds), 1852 .num_init_cmd = ARRAY_SIZE(default_init_cmds), 1853 .temp_factor = LVTS_COEFF_A_MT8195, 1854 .temp_offset = LVTS_COEFF_B_MT8195, 1855 .gt_calib_bit_offset = 24, 1856 .def_calibration = 35000, 1857}; 1858 1859static const struct of_device_id lvts_of_match[] = { 1860 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1861 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, 1862 { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, 1863 { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data }, 1864 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1865 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1866 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1867 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1868 {}, 1869}; 1870MODULE_DEVICE_TABLE(of, lvts_of_match); 1871 1872static const struct dev_pm_ops lvts_pm_ops = { 1873 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1874}; 1875 1876static struct platform_driver lvts_driver = { 1877 .probe = lvts_probe, 1878 .remove = lvts_remove, 1879 .driver = { 1880 .name = "mtk-lvts-thermal", 1881 .of_match_table = lvts_of_match, 1882 .pm = &lvts_pm_ops, 1883 }, 1884}; 1885module_platform_driver(lvts_driver); 1886 1887MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1888MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1889MODULE_LICENSE("GPL");
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