HalPwrSeqCmd.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/******************************************************************************
  3 *
  4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  5 *
  6 ******************************************************************************/
  7#ifndef __HALPWRSEQCMD_H__
  8#define __HALPWRSEQCMD_H__
  9
 10#include <drv_types.h>
 11
 12/*---------------------------------------------*/
 13/* 3 The value of cmd: 4 bits */
 14/*---------------------------------------------*/
 15#define PWR_CMD_READ			0x00
 16     /*  offset: the read register offset */
 17     /*  msk: the mask of the read value */
 18     /*  value: N/A, left by 0 */
 19     /*  note: dirver shall implement this function by read & msk */
 20
 21#define PWR_CMD_WRITE			0x01
 22     /*  offset: the read register offset */
 23     /*  msk: the mask of the write bits */
 24     /*  value: write value */
 25     /*  note: driver shall implement this cmd by read & msk after write */
 26
 27#define PWR_CMD_POLLING			0x02
 28     /*  offset: the read register offset */
 29     /*  msk: the mask of the polled value */
 30     /*  value: the value to be polled, masked by the msd field. */
 31     /*  note: driver shall implement this cmd by */
 32     /*  do{ */
 33     /*  if ((Read(offset) & msk) == (value & msk)) */
 34     /*  break; */
 35     /*  } while (not timeout); */
 36
 37#define PWR_CMD_DELAY			0x03
 38     /*  offset: the value to delay */
 39     /*  msk: N/A */
 40     /*  value: the unit of delay, 0: us, 1: ms */
 41
 42#define PWR_CMD_END				0x04
 43     /*  offset: N/A */
 44     /*  msk: N/A */
 45     /*  value: N/A */
 46
 47/*---------------------------------------------*/
 48/* 3 The value of base: 4 bits */
 49/*---------------------------------------------*/
 50   /*  define the base address of each block */
 51#define PWR_BASEADDR_MAC		0x00
 52#define PWR_BASEADDR_SDIO		0x03
 53
 54/*---------------------------------------------*/
 55/* 3 The value of interface_msk: 4 bits */
 56/*---------------------------------------------*/
 57#define	PWR_INTF_SDIO_MSK		BIT(0)
 58#define	PWR_INTF_USB_MSK		BIT(1)
 59#define	PWR_INTF_PCI_MSK		BIT(2)
 60#define	PWR_INTF_ALL_MSK		(BIT(0)|BIT(1)|BIT(2)|BIT(3))
 61
 62/*---------------------------------------------*/
 63/* 3 The value of fab_msk: 4 bits */
 64/*---------------------------------------------*/
 65#define	PWR_FAB_ALL_MSK			(BIT(0)|BIT(1)|BIT(2)|BIT(3))
 66
 67/*---------------------------------------------*/
 68/* 3 The value of cut_msk: 8 bits */
 69/*---------------------------------------------*/
 70#define	PWR_CUT_TESTCHIP_MSK	BIT(0)
 71#define	PWR_CUT_ALL_MSK			0xFF
 72
 73
 74enum {
 75	PWRSEQ_DELAY_US,
 76	PWRSEQ_DELAY_MS,
 77};
 78
 79struct wlan_pwr_cfg {
 80	u16 offset;
 81	u8 cut_msk;
 82	u8 fab_msk:4;
 83	u8 interface_msk:4;
 84	u8 base:4;
 85	u8 cmd:4;
 86	u8 msk;
 87	u8 value;
 88};
 89
 90
 91#define GET_PWR_CFG_OFFSET(__PWR_CMD)		__PWR_CMD.offset
 92#define GET_PWR_CFG_CUT_MASK(__PWR_CMD)		__PWR_CMD.cut_msk
 93#define GET_PWR_CFG_FAB_MASK(__PWR_CMD)		__PWR_CMD.fab_msk
 94#define GET_PWR_CFG_INTF_MASK(__PWR_CMD)	__PWR_CMD.interface_msk
 95#define GET_PWR_CFG_BASE(__PWR_CMD)			__PWR_CMD.base
 96#define GET_PWR_CFG_CMD(__PWR_CMD)			__PWR_CMD.cmd
 97#define GET_PWR_CFG_MASK(__PWR_CMD)			__PWR_CMD.msk
 98#define GET_PWR_CFG_VALUE(__PWR_CMD)		__PWR_CMD.value
 99
100
101/*  */
102/* 	Prototype of protected function. */
103/*  */
104u8 HalPwrSeqCmdParsing(
105	struct adapter *padapter,
106	u8 		CutVersion,
107	u8 		FabVersion,
108	u8 		InterfaceType,
109	struct wlan_pwr_cfg	PwrCfgCmd[]);
110
111#endif