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sdio_halinit.c

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linux-6.19.14/drivers/staging/rtl8723bs/hal/sdio_halinit.c C 
   1// SPDX-License-Identifier: GPL-2.0
   2/******************************************************************************
   3 *
   4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   5 *
   6 ******************************************************************************/
   7#include <drv_types.h>
   8#include <rtl8723b_hal.h>
   9
  10#include "hal_com_h2c.h"
  11/*
  12 * Description:
  13 *Call power on sequence to enable card
  14 *
  15 * Return:
  16 *_SUCCESS	enable success
  17 *_FAIL		enable fail
  18 */
  19static u8 CardEnable(struct adapter *padapter)
  20{
  21	u8 bMacPwrCtrlOn;
  22	u8 ret = _FAIL;
  23
  24
  25	rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  26	if (!bMacPwrCtrlOn) {
  27		/*  RSV_CTRL 0x1C[7:0] = 0x00 */
  28		/*  unlock ISO/CLK/Power control register */
  29		rtw_write8(padapter, REG_RSV_CTRL, 0x0);
  30
  31		ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
  32		if (ret == _SUCCESS) {
  33			u8 bMacPwrCtrlOn = true;
  34			rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  35		}
  36	} else
  37		ret = _SUCCESS;
  38
  39	return ret;
  40}
  41
  42static
  43u8 _InitPowerOn_8723BS(struct adapter *padapter)
  44{
  45	u8 value8;
  46	u16 value16;
  47	u32 value32;
  48	u8 ret;
  49/* 	u8 bMacPwrCtrlOn; */
  50
  51
  52	/*  all of these MUST be configured before power on */
  53
  54	/*  only cmd52 can be used before power on(card enable) */
  55	ret = CardEnable(padapter);
  56	if (!ret)
  57		return _FAIL;
  58
  59	/*  Radio-Off Pin Trigger */
  60	value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
  61	value8 |= BIT(1); /*  Enable falling edge triggering interrupt */
  62	rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
  63	value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
  64	value8 |= BIT(1);
  65	rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
  66
  67	/*  Enable power down and GPIO interrupt */
  68	value16 = rtw_read16(padapter, REG_APS_FSMCO);
  69	value16 |= EnPDN; /*  Enable HW power down and RF on */
  70	rtw_write16(padapter, REG_APS_FSMCO, value16);
  71
  72	/*  Enable CMD53 R/W Operation */
  73/* 	bMacPwrCtrlOn = true; */
  74/* 	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
  75
  76	rtw_write8(padapter, REG_CR, 0x00);
  77	/*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
  78	value16 = rtw_read16(padapter, REG_CR);
  79	value16 |= (
  80		HCI_TXDMA_EN |
  81		HCI_RXDMA_EN |
  82		TXDMA_EN |
  83		RXDMA_EN |
  84		PROTOCOL_EN |
  85		SCHEDULE_EN |
  86		ENSEC |
  87		CALTMR_EN
  88	);
  89	rtw_write16(padapter, REG_CR, value16);
  90
  91	hal_btcoex_PowerOnSetting(padapter);
  92
  93	/*  external switch to S1 */
  94	/*  0x38[11] = 0x1 */
  95	/*  0x4c[23] = 0x1 */
  96	/*  0x64[0] = 0 */
  97	value16 = rtw_read16(padapter, REG_PWR_DATA);
  98	/*  Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */
  99	value16 |= BIT(11); /*  BIT_EEPRPAD_RFE_CTRL_EN */
 100	rtw_write16(padapter, REG_PWR_DATA, value16);
 101
 102	value32 = rtw_read32(padapter, REG_LEDCFG0);
 103	value32 |= BIT(23); /*  DPDT_SEL_EN, 1 for SW control */
 104	rtw_write32(padapter, REG_LEDCFG0, value32);
 105
 106	value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
 107	value8 &= ~BIT(0); /*  BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */
 108	rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
 109
 110	return _SUCCESS;
 111}
 112
 113/* Tx Page FIFO threshold */
 114static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
 115{
 116	u16 HQ_threshold, NQ_threshold, LQ_threshold;
 117
 118	HQ_threshold = (numPubQ + numHQ + 1) >> 1;
 119	HQ_threshold |= (HQ_threshold << 8);
 120
 121	NQ_threshold = (numPubQ + numNQ + 1) >> 1;
 122	NQ_threshold |= (NQ_threshold << 8);
 123
 124	LQ_threshold = (numPubQ + numLQ + 1) >> 1;
 125	LQ_threshold |= (LQ_threshold << 8);
 126
 127	rtw_write16(padapter, 0x218, HQ_threshold);
 128	rtw_write16(padapter, 0x21A, NQ_threshold);
 129	rtw_write16(padapter, 0x21C, LQ_threshold);
 130}
 131
 132static void _InitQueueReservedPage(struct adapter *padapter)
 133{
 134	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 135	struct registry_priv *pregistrypriv = &padapter->registrypriv;
 136	u32 numHQ = 0;
 137	u32 numLQ = 0;
 138	u32 numNQ = 0;
 139	u32 numPubQ;
 140	u32 value32;
 141	u8 value8;
 142	bool bWiFiConfig	= pregistrypriv->wifi_spec;
 143
 144	if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 145		numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
 146
 147	if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 148		numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
 149
 150	/*  NOTE: This step shall be proceed before writing REG_RQPN. */
 151	if (pHalData->OutEpQueueSel & TX_SELE_NQ)
 152		numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
 153
 154	numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
 155
 156	value8 = (u8)_NPQ(numNQ);
 157	rtw_write8(padapter, REG_RQPN_NPQ, value8);
 158
 159	/*  TX DMA */
 160	value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 161	rtw_write32(padapter, REG_RQPN, value32);
 162
 163	rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
 164
 165	_init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
 166}
 167
 168static void _InitTxBufferBoundary(struct adapter *padapter)
 169{
 170	struct registry_priv *pregistrypriv = &padapter->registrypriv;
 171
 172	/* u16 txdmactrl; */
 173	u8 txpktbuf_bndy;
 174
 175	if (!pregistrypriv->wifi_spec) {
 176		txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
 177	} else {
 178		/* for WMM */
 179		txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
 180	}
 181
 182	rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
 183	rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
 184	rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
 185	rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 186	rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
 187}
 188
 189static void _InitNormalChipRegPriority(
 190	struct adapter *Adapter,
 191	u16 beQ,
 192	u16 bkQ,
 193	u16 viQ,
 194	u16 voQ,
 195	u16 mgtQ,
 196	u16 hiQ
 197)
 198{
 199	u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 200
 201	value16 |=
 202		_TXDMA_BEQ_MAP(beQ)  |
 203		_TXDMA_BKQ_MAP(bkQ)  |
 204		_TXDMA_VIQ_MAP(viQ)  |
 205		_TXDMA_VOQ_MAP(voQ)  |
 206		_TXDMA_MGQ_MAP(mgtQ) |
 207		_TXDMA_HIQ_MAP(hiQ);
 208
 209	rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 210}
 211
 212static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
 213{
 214	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 215
 216	u16 value = 0;
 217	switch (pHalData->OutEpQueueSel) {
 218	case TX_SELE_HQ:
 219		value = QUEUE_HIGH;
 220		break;
 221	case TX_SELE_LQ:
 222		value = QUEUE_LOW;
 223		break;
 224	case TX_SELE_NQ:
 225		value = QUEUE_NORMAL;
 226		break;
 227	default:
 228		break;
 229	}
 230
 231	_InitNormalChipRegPriority(
 232		Adapter, value, value, value, value, value, value
 233	);
 234
 235}
 236
 237static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
 238{
 239	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 240	struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 241	u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 242
 243
 244	u16 valueHi = 0;
 245	u16 valueLow = 0;
 246
 247	switch (pHalData->OutEpQueueSel) {
 248	case (TX_SELE_HQ | TX_SELE_LQ):
 249		valueHi = QUEUE_HIGH;
 250		valueLow = QUEUE_LOW;
 251		break;
 252	case (TX_SELE_NQ | TX_SELE_LQ):
 253		valueHi = QUEUE_NORMAL;
 254		valueLow = QUEUE_LOW;
 255		break;
 256	case (TX_SELE_HQ | TX_SELE_NQ):
 257		valueHi = QUEUE_HIGH;
 258		valueLow = QUEUE_NORMAL;
 259		break;
 260	default:
 261		break;
 262	}
 263
 264	if (!pregistrypriv->wifi_spec) {
 265		beQ = valueLow;
 266		bkQ = valueLow;
 267		viQ = valueHi;
 268		voQ = valueHi;
 269		mgtQ = valueHi;
 270		hiQ = valueHi;
 271	} else {
 272		/* for WMM , CONFIG_OUT_EP_WIFI_MODE */
 273		beQ = valueLow;
 274		bkQ = valueHi;
 275		viQ = valueHi;
 276		voQ = valueLow;
 277		mgtQ = valueHi;
 278		hiQ = valueHi;
 279	}
 280
 281	_InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 282
 283}
 284
 285static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter)
 286{
 287	struct registry_priv *pregistrypriv = &padapter->registrypriv;
 288	u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 289
 290	if (!pregistrypriv->wifi_spec) {
 291		/*  typical setting */
 292		beQ = QUEUE_LOW;
 293		bkQ = QUEUE_LOW;
 294		viQ = QUEUE_NORMAL;
 295		voQ = QUEUE_HIGH;
 296		mgtQ = QUEUE_HIGH;
 297		hiQ = QUEUE_HIGH;
 298	} else {
 299		/*  for WMM */
 300		beQ = QUEUE_LOW;
 301		bkQ = QUEUE_NORMAL;
 302		viQ = QUEUE_NORMAL;
 303		voQ = QUEUE_HIGH;
 304		mgtQ = QUEUE_HIGH;
 305		hiQ = QUEUE_HIGH;
 306	}
 307	_InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 308}
 309
 310static void _InitQueuePriority(struct adapter *Adapter)
 311{
 312	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 313
 314	switch (pHalData->OutEpNumber) {
 315	case 1:
 316		_InitNormalChipOneOutEpPriority(Adapter);
 317		break;
 318	case 2:
 319		_InitNormalChipTwoOutEpPriority(Adapter);
 320		break;
 321	case 3:
 322		_InitNormalChipThreeOutEpPriority(Adapter);
 323		break;
 324	default:
 325		break;
 326	}
 327
 328
 329}
 330
 331static void _InitPageBoundary(struct adapter *padapter)
 332{
 333	/*  RX Page Boundary */
 334	u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
 335
 336	rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 337}
 338
 339static void _InitTransferPageSize(struct adapter *padapter)
 340{
 341	/*  Tx page size is always 128. */
 342
 343	u8 value8;
 344	value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 345	rtw_write8(padapter, REG_PBP, value8);
 346}
 347
 348static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize)
 349{
 350	rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 351}
 352
 353static void _InitNetworkType(struct adapter *padapter)
 354{
 355	u32 value32;
 356
 357	value32 = rtw_read32(padapter, REG_CR);
 358
 359	/*  TODO: use the other function to set network type */
 360/* 	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
 361	value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 362
 363	rtw_write32(padapter, REG_CR, value32);
 364}
 365
 366static void _InitWMACSetting(struct adapter *padapter)
 367{
 368	struct hal_com_data *pHalData;
 369	u16 value16;
 370
 371
 372	pHalData = GET_HAL_DATA(padapter);
 373
 374	pHalData->ReceiveConfig = 0;
 375	pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
 376	pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
 377	pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
 378	pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
 379	rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
 380
 381	/*  Accept all multicast address */
 382	rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);	/* Offset 0x0620-0x0623 */
 383	rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);	/* Offset 0x0624-0x0627 */
 384
 385	/*  Accept all data frames */
 386	value16 = 0xFFFF;
 387	rtw_write16(padapter, REG_RXFLTMAP2, value16);
 388
 389	/*  2010.09.08 hpfan */
 390	/*  Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
 391	/*  RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
 392	value16 = 0x400;
 393	rtw_write16(padapter, REG_RXFLTMAP1, value16);
 394
 395	/*  Accept all management frames */
 396	value16 = 0xFFFF;
 397	rtw_write16(padapter, REG_RXFLTMAP0, value16);
 398}
 399
 400static void _InitAdaptiveCtrl(struct adapter *padapter)
 401{
 402	u16 value16;
 403	u32 value32;
 404
 405	/*  Response Rate Set */
 406	value32 = rtw_read32(padapter, REG_RRSR);
 407	value32 &= ~RATE_BITMAP_ALL;
 408	value32 |= RATE_RRSR_CCK_ONLY_1M;
 409	rtw_write32(padapter, REG_RRSR, value32);
 410
 411	/*  CF-END Threshold */
 412	/* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
 413
 414	/*  SIFS (used in NAV) */
 415	value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 416	rtw_write16(padapter, REG_SPEC_SIFS, value16);
 417
 418	/*  Retry Limit */
 419	value16 = _LRL(0x30) | _SRL(0x30);
 420	rtw_write16(padapter, REG_RL, value16);
 421}
 422
 423static void _InitEDCA(struct adapter *padapter)
 424{
 425	/*  Set Spec SIFS (used in NAV) */
 426	rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
 427	rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
 428
 429	/*  Set SIFS for CCK */
 430	rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
 431
 432	/*  Set SIFS for OFDM */
 433	rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
 434
 435	/*  TXOP */
 436	rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 437	rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 438	rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
 439	rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
 440}
 441
 442static void _InitRetryFunction(struct adapter *padapter)
 443{
 444	u8 value8;
 445
 446	value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
 447	value8 |= EN_AMPDU_RTY_NEW;
 448	rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
 449
 450	/*  Set ACK timeout */
 451	rtw_write8(padapter, REG_ACKTO, 0x40);
 452}
 453
 454static void HalRxAggr8723BSdio(struct adapter *padapter)
 455{
 456	u8 valueDMATimeout;
 457	u8 valueDMAPageCount;
 458
 459	valueDMATimeout = 0x06;
 460	valueDMAPageCount = 0x06;
 461
 462	rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
 463	rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
 464}
 465
 466static void sdio_AggSettingRxUpdate(struct adapter *padapter)
 467{
 468	u8 valueDMA;
 469	u8 valueRxAggCtrl = 0;
 470	u8 aggBurstNum = 3;  /* 0:1, 1:2, 2:3, 3:4 */
 471	u8 aggBurstSize = 0;  /* 0:1K, 1:512Byte, 2:256Byte... */
 472
 473	valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
 474	valueDMA |= RXDMA_AGG_EN;
 475	rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
 476
 477	valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
 478	valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
 479	valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
 480	rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
 481}
 482
 483static void _initSdioAggregationSetting(struct adapter *padapter)
 484{
 485	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
 486
 487	/*  Tx aggregation setting */
 488/* 	sdio_AggSettingTxUpdate(padapter); */
 489
 490	/*  Rx aggregation setting */
 491	HalRxAggr8723BSdio(padapter);
 492
 493	sdio_AggSettingRxUpdate(padapter);
 494
 495	/*  201/12/10 MH Add for USB agg mode dynamic switch. */
 496	pHalData->UsbRxHighSpeedMode = false;
 497}
 498
 499static void _InitOperationMode(struct adapter *padapter)
 500{
 501	struct mlme_ext_priv *pmlmeext;
 502	u8 regBwOpMode = 0;
 503
 504	pmlmeext = &padapter->mlmeextpriv;
 505
 506	/* 1 This part need to modified according to the rate set we filtered!! */
 507	/*  */
 508	/*  Set RRSR, RATR, and REG_BWOPMODE registers */
 509	/*  */
 510	switch (pmlmeext->cur_wireless_mode) {
 511	case WIRELESS_MODE_B:
 512		regBwOpMode = BW_OPMODE_20MHZ;
 513		break;
 514	case WIRELESS_MODE_G:
 515		regBwOpMode = BW_OPMODE_20MHZ;
 516		break;
 517	case WIRELESS_MODE_AUTO:
 518		regBwOpMode = BW_OPMODE_20MHZ;
 519		break;
 520	case WIRELESS_MODE_N_24G:
 521		/*  It support CCK rate by default. */
 522		/*  CCK rate will be filtered out only when associated AP does not support it. */
 523		regBwOpMode = BW_OPMODE_20MHZ;
 524		break;
 525
 526	default: /* for MacOSX compiler warning. */
 527		break;
 528	}
 529
 530	rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
 531
 532}
 533
 534static void _InitInterrupt(struct adapter *padapter)
 535{
 536	/*  HISR - turn all off */
 537	rtw_write32(padapter, REG_HISR, 0);
 538
 539	/*  HIMR - turn all off */
 540	rtw_write32(padapter, REG_HIMR, 0);
 541
 542	/*  */
 543	/*  Initialize and enable SDIO Host Interrupt. */
 544	/*  */
 545	InitInterrupt8723BSdio(padapter);
 546
 547	/*  */
 548	/*  Initialize system Host Interrupt. */
 549	/*  */
 550	InitSysInterrupt8723BSdio(padapter);
 551}
 552
 553static void _InitRFType(struct adapter *padapter)
 554{
 555	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 556
 557	pHalData->rf_chip	= RF_6052;
 558}
 559
 560static void _RfPowerSave(struct adapter *padapter)
 561{
 562/* YJ, TODO */
 563}
 564
 565/*  */
 566/*  2010/08/09 MH Add for power down check. */
 567/*  */
 568static bool HalDetectPwrDownMode(struct adapter *Adapter)
 569{
 570	u8 tmpvalue;
 571	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 572	struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
 573
 574
 575	EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
 576
 577	/*  2010/08/25 MH INF priority > PDN Efuse value. */
 578	if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
 579		pHalData->pwrdown = true;
 580	else
 581		pHalData->pwrdown = false;
 582
 583	return pHalData->pwrdown;
 584}	/*  HalDetectPwrDownMode */
 585
 586u32 rtl8723bs_hal_init(struct adapter *padapter)
 587{
 588	s32 ret;
 589	struct hal_com_data *pHalData;
 590	struct pwrctrl_priv *pwrctrlpriv;
 591	u32 NavUpper = WiFiNavUpperUs;
 592	u8 u1bTmp;
 593
 594	pHalData = GET_HAL_DATA(padapter);
 595	pwrctrlpriv = adapter_to_pwrctl(padapter);
 596
 597	if (
 598		adapter_to_pwrctl(padapter)->bips_processing == true &&
 599		adapter_to_pwrctl(padapter)->pre_ips_type == 0
 600	) {
 601		unsigned long start_time;
 602		u8 cpwm_orig, cpwm_now;
 603		u8 val8, bMacPwrCtrlOn = true;
 604
 605		/* for polling cpwm */
 606		cpwm_orig = 0;
 607		rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
 608
 609		/* ser rpwm */
 610		val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
 611		val8 &= 0x80;
 612		val8 += 0x80;
 613		val8 |= BIT(6);
 614		rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
 615		adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
 616
 617		/* do polling cpwm */
 618		start_time = jiffies;
 619		do {
 620
 621			mdelay(1);
 622
 623			rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
 624			if ((cpwm_orig ^ cpwm_now) & 0x80)
 625				break;
 626
 627			if (jiffies_to_msecs(jiffies - start_time) > 100)
 628				break;
 629
 630		} while (1);
 631
 632		rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
 633
 634		rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 635
 636		hal_btcoex_InitHwConfig(padapter, false);
 637
 638		return _SUCCESS;
 639	}
 640
 641	/*  Disable Interrupt first. */
 642/* 	rtw_hal_disable_interrupt(padapter); */
 643
 644	ret = _InitPowerOn_8723BS(padapter);
 645	if (ret == _FAIL)
 646		return _FAIL;
 647
 648	rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
 649
 650	ret = rtl8723b_FirmwareDownload(padapter, false);
 651	if (ret != _SUCCESS) {
 652		padapter->bFWReady = false;
 653		pHalData->fw_ractrl = false;
 654		return ret;
 655	} else {
 656		padapter->bFWReady = true;
 657		pHalData->fw_ractrl = true;
 658	}
 659
 660	rtl8723b_InitializeFirmwareVars(padapter);
 661
 662/* 	SIC_Init(padapter); */
 663
 664	if (pwrctrlpriv->reg_rfoff)
 665		pwrctrlpriv->rf_pwrstate = rf_off;
 666
 667	/*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 668	/*  HW GPIO pin. Before PHY_RFConfig8192C. */
 669	HalDetectPwrDownMode(padapter);
 670
 671	/*  Set RF type for BB/RF configuration */
 672	_InitRFType(padapter);
 673
 674	/*  Save target channel */
 675	/*  <Roger_Notes> Current Channel will be updated again later. */
 676	pHalData->CurrentChannel = 6;
 677
 678	ret = PHY_MACConfig8723B(padapter);
 679	if (ret != _SUCCESS)
 680		return ret;
 681	/*  */
 682	/* d. Initialize BB related configurations. */
 683	/*  */
 684	ret = PHY_BBConfig8723B(padapter);
 685	if (ret != _SUCCESS)
 686		return ret;
 687
 688	/*  If RF is on, we need to init RF. Otherwise, skip the procedure. */
 689	/*  We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
 690	/* if (pHalData->eRFPowerState == eRfOn) */
 691	{
 692		ret = PHY_RFConfig8723B(padapter);
 693		if (ret != _SUCCESS)
 694			return ret;
 695	}
 696
 697	/*  */
 698	/*  Joseph Note: Keep RfRegChnlVal for later use. */
 699	/*  */
 700	pHalData->RfRegChnlVal[0] =
 701		PHY_QueryRFReg(padapter, (enum rf_path)0, RF_CHNLBW, bRFRegOffsetMask);
 702	pHalData->RfRegChnlVal[1] =
 703		PHY_QueryRFReg(padapter, (enum rf_path)1, RF_CHNLBW, bRFRegOffsetMask);
 704
 705
 706	/* if (!pHalData->bMACFuncEnable) { */
 707	_InitQueueReservedPage(padapter);
 708	_InitTxBufferBoundary(padapter);
 709
 710	/*  init LLT after tx buffer boundary is defined */
 711	ret = rtl8723b_InitLLTTable(padapter);
 712	if (ret != _SUCCESS)
 713		return _FAIL;
 714
 715	/*  */
 716	_InitQueuePriority(padapter);
 717	_InitPageBoundary(padapter);
 718	_InitTransferPageSize(padapter);
 719
 720	/*  Get Rx PHY status in order to report RSSI and others. */
 721	_InitDriverInfoSize(padapter, DRVINFO_SZ);
 722	hal_init_macaddr(padapter);
 723	_InitNetworkType(padapter);
 724	_InitWMACSetting(padapter);
 725	_InitAdaptiveCtrl(padapter);
 726	_InitEDCA(padapter);
 727	_InitRetryFunction(padapter);
 728	_initSdioAggregationSetting(padapter);
 729	_InitOperationMode(padapter);
 730	rtl8723b_InitBeaconParameters(padapter);
 731	_InitInterrupt(padapter);
 732	_InitBurstPktLen_8723BS(padapter);
 733
 734	/* YJ, TODO */
 735	rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3);	/*  CCA */
 736	rtw_write8(padapter, 0x976, 0);	/*  hpfan_todo: 2nd CCA related */
 737
 738	rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400);	/*  unit: 256us. 256ms */
 739	rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400);	/*  unit: 256us. 256ms */
 740
 741	invalidate_cam_all(padapter);
 742
 743	rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
 744		CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
 745
 746	/*  Record original value for template. This is arough data, we can only use the data */
 747	/*  for power adjust. The value can not be adjustde according to different power!!! */
 748/* 	pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */
 749/* 	pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */
 750
 751	rtl8723b_InitAntenna_Selection(padapter);
 752
 753	/*  */
 754	/*  Disable BAR, suggested by Scott */
 755	/*  2010.04.09 add by hpfan */
 756	/*  */
 757	rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 758
 759	/*  HW SEQ CTRL */
 760	/*  set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 761	rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
 762
 763
 764	/*  */
 765	/*  Configure SDIO TxRx Control to enable Rx DMA timer masking. */
 766	/*  2010.02.24. */
 767	/*  */
 768	rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
 769
 770	_RfPowerSave(padapter);
 771
 772
 773	rtl8723b_InitHalDm(padapter);
 774
 775	/*  */
 776	/*  Update current Tx FIFO page status. */
 777	/*  */
 778	HalQueryTxBufferStatus8723BSdio(padapter);
 779	HalQueryTxOQTBufferStatus8723BSdio(padapter);
 780	pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
 781
 782	/*  Enable MACTXEN/MACRXEN block */
 783	u1bTmp = rtw_read8(padapter, REG_CR);
 784	u1bTmp |= (MACTXEN | MACRXEN);
 785	rtw_write8(padapter, REG_CR, u1bTmp);
 786
 787	rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
 788
 789	/* ack for xmit mgmt frames. */
 790	rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
 791
 792/* 	pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
 793
 794	{
 795		pwrctrlpriv->rf_pwrstate = rf_on;
 796
 797		if (pwrctrlpriv->rf_pwrstate == rf_on) {
 798			struct pwrctrl_priv *pwrpriv;
 799			unsigned long start_time;
 800			u8 restore_iqk_rst;
 801			u8 b2Ant;
 802			u8 h2cCmdBuf;
 803
 804			pwrpriv = adapter_to_pwrctl(padapter);
 805
 806			PHY_LCCalibrate_8723B(&pHalData->odmpriv);
 807
 808			/* Inform WiFi FW that it is the beginning of IQK */
 809			h2cCmdBuf = 1;
 810			FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
 811
 812			start_time = jiffies;
 813			do {
 814				if (rtw_read8(padapter, 0x1e7) & 0x01)
 815					break;
 816
 817				msleep(50);
 818			} while (jiffies_to_msecs(jiffies - start_time) <= 400);
 819
 820			hal_btcoex_IQKNotify(padapter, true);
 821
 822			restore_iqk_rst = pwrpriv->bips_processing;
 823			b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2;
 824			PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path);
 825			pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 826
 827			hal_btcoex_IQKNotify(padapter, false);
 828
 829			/* Inform WiFi FW that it is the finish of IQK */
 830			h2cCmdBuf = 0;
 831			FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
 832
 833			ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
 834		}
 835	}
 836
 837	/*  Init BT hw config. */
 838	hal_btcoex_InitHwConfig(padapter, false);
 839
 840	return _SUCCESS;
 841}
 842
 843/*  */
 844/*  Description: */
 845/* 	RTL8723e card disable power sequence v003 which suggested by Scott. */
 846/*  */
 847/*  First created by tynli. 2011.01.28. */
 848/*  */
 849static void CardDisableRTL8723BSdio(struct adapter *padapter)
 850{
 851	u8 u1bTmp;
 852	u8 bMacPwrCtrlOn;
 853
 854	/*  Run LPS WL RFOFF flow */
 855	HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
 856
 857	/* 	==== Reset digital sequence   ====== */
 858
 859	u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
 860	if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */
 861		rtl8723b_FirmwareSelfReset(padapter);
 862
 863	/*  Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */
 864	u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
 865	u1bTmp &= ~BIT(2);	/*  0x2[10], FEN_CPUEN */
 866	rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
 867
 868	/*  MCUFWDL 0x80[1:0]= 0 */
 869	/*  reset MCU ready status */
 870	rtw_write8(padapter, REG_MCUFWDL, 0);
 871
 872	/*  Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
 873	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
 874	u1bTmp &= ~BIT(0);
 875	rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
 876	u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
 877	u1bTmp |= BIT(0);
 878	rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
 879
 880	/* 	==== Reset digital sequence end ====== */
 881
 882	bMacPwrCtrlOn = false;	/*  Disable CMD53 R/W */
 883	rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 884	HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
 885}
 886
 887u32 rtl8723bs_hal_deinit(struct adapter *padapter)
 888{
 889	struct dvobj_priv *psdpriv = padapter->dvobj;
 890	struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
 891
 892	if (padapter->hw_init_completed) {
 893		if (adapter_to_pwrctl(padapter)->bips_processing) {
 894			if (padapter->netif_up) {
 895				int cnt = 0;
 896				u8 val8 = 0;
 897
 898				rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3);
 899				/* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */
 900				do {
 901					val8 = rtw_read8(padapter, REG_HMETFR);
 902					cnt++;
 903					mdelay(10);
 904				} while (cnt < 100 && (val8 != 0));
 905				/* H2C done, enter 32k */
 906				if (val8 == 0) {
 907					/* ser rpwm to enter 32k */
 908					val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
 909					val8 += 0x80;
 910					val8 |= BIT(0);
 911					rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
 912					adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
 913					cnt = val8 = 0;
 914					do {
 915						val8 = rtw_read8(padapter, REG_CR);
 916						cnt++;
 917						mdelay(10);
 918					} while (cnt < 100 && (val8 != 0xEA));
 919				}
 920
 921				adapter_to_pwrctl(padapter)->pre_ips_type = 0;
 922
 923			} else {
 924				pdbgpriv->dbg_carddisable_cnt++;
 925				CardDisableRTL8723BSdio(padapter);
 926
 927				adapter_to_pwrctl(padapter)->pre_ips_type = 1;
 928			}
 929
 930		} else {
 931			pdbgpriv->dbg_carddisable_cnt++;
 932			CardDisableRTL8723BSdio(padapter);
 933		}
 934	} else
 935		pdbgpriv->dbg_deinit_fail_cnt++;
 936
 937	return _SUCCESS;
 938}
 939
 940void rtl8723bs_init_default_value(struct adapter *padapter)
 941{
 942	struct hal_com_data *pHalData;
 943
 944
 945	pHalData = GET_HAL_DATA(padapter);
 946
 947	rtl8723b_init_default_value(padapter);
 948
 949	/*  interface related variable */
 950	pHalData->SdioRxFIFOCnt = 0;
 951}
 952
 953void rtl8723bs_interface_configure(struct adapter *padapter)
 954{
 955	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 956	struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 957	struct registry_priv *pregistrypriv = &padapter->registrypriv;
 958	bool bWiFiConfig = pregistrypriv->wifi_spec;
 959
 960
 961	pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
 962	pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
 963	pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
 964
 965	if (bWiFiConfig)
 966		pHalData->OutEpNumber = 2;
 967	else
 968		pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
 969
 970	switch (pHalData->OutEpNumber) {
 971	case 3:
 972		pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
 973		break;
 974	case 2:
 975		pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
 976		break;
 977	case 1:
 978		pHalData->OutEpQueueSel = TX_SELE_HQ;
 979		break;
 980	default:
 981		break;
 982	}
 983
 984	Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
 985}
 986
 987/*  */
 988/* 	Description: */
 989/* 		We should set Efuse cell selection to WiFi cell in default. */
 990/*  */
 991/* 	Assumption: */
 992/* 		PASSIVE_LEVEL */
 993/*  */
 994/* 	Added by Roger, 2010.11.23. */
 995/*  */
 996static void _EfuseCellSel(struct adapter *padapter)
 997{
 998	u32 value32;
 999
1000	value32 = rtw_read32(padapter, EFUSE_TEST);
1001	value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1002	rtw_write32(padapter, EFUSE_TEST, value32);
1003}
1004
1005static void _ReadRFType(struct adapter *Adapter)
1006{
1007	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1008
1009	pHalData->rf_chip = RF_6052;
1010}
1011
1012
1013static void Hal_EfuseParseMACAddr_8723BS(
1014	struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1015)
1016{
1017	struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1018
1019	if (AutoLoadFail) {
1020		eth_random_addr(pEEPROM->mac_addr);
1021	} else {
1022		/* Read Permanent MAC address */
1023		memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN);
1024	}
1025}
1026
1027static void Hal_EfuseParseBoardType_8723BS(
1028	struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1029)
1030{
1031	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1032
1033	if (!AutoLoadFail) {
1034		pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
1035		if (pHalData->BoardType == 0xFF)
1036			pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
1037	} else
1038		pHalData->BoardType = 0;
1039}
1040
1041static void _ReadEfuseInfo8723BS(struct adapter *padapter)
1042{
1043	struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1044	u8 *hwinfo = NULL;
1045
1046	/*  */
1047	/*  This part read and parse the eeprom/efuse content */
1048	/*  */
1049
1050	hwinfo = pEEPROM->efuse_eeprom_data;
1051
1052	Hal_InitPGData(padapter, hwinfo);
1053
1054	Hal_EfuseParseIDCode(padapter, hwinfo);
1055	Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1056
1057	Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1058
1059	Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1060	Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1061
1062	/*  */
1063	/*  Read Bluetooth co-exist and initialize */
1064	/*  */
1065	Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1066	Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1067	Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1068	Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1069	Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1070	Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1071
1072	Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1073
1074	Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1075}
1076
1077static void _ReadPROMContent(struct adapter *padapter)
1078{
1079	struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1080	u8 	eeValue;
1081
1082	eeValue = rtw_read8(padapter, REG_9346CR);
1083	/*  To check system boot selection. */
1084	pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1085	pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1086
1087/* 	pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1088
1089	_ReadEfuseInfo8723BS(padapter);
1090}
1091
1092/*  */
1093/* 	Description: */
1094/* 		Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */
1095/*  */
1096/* 	Assumption: */
1097/* 		PASSIVE_LEVEL (SDIO interface) */
1098/*  */
1099/*  */
1100static s32 _ReadAdapterInfo8723BS(struct adapter *padapter)
1101{
1102	u8 val8;
1103
1104	/*  before access eFuse, make sure card enable has been called */
1105	if (!padapter->hw_init_completed)
1106		_InitPowerOn_8723BS(padapter);
1107
1108
1109	val8 = rtw_read8(padapter, 0x4e);
1110	val8 |= BIT(6);
1111	rtw_write8(padapter, 0x4e, val8);
1112
1113	_EfuseCellSel(padapter);
1114	_ReadRFType(padapter);
1115	_ReadPROMContent(padapter);
1116
1117	if (!padapter->hw_init_completed) {
1118		rtw_write8(padapter, 0x67, 0x00); /*  for BT, Switch Ant control to BT */
1119		CardDisableRTL8723BSdio(padapter);/* for the power consumption issue,  wifi ko module is loaded during booting, but wifi GUI is off */
1120	}
1121
1122	return _SUCCESS;
1123}
1124
1125void ReadAdapterInfo8723BS(struct adapter *padapter)
1126{
1127	/*  Read EEPROM size before call any EEPROM function */
1128	padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
1129
1130	_ReadAdapterInfo8723BS(padapter);
1131}
1132
1133/*
1134 * If variable not handled here,
1135 * some variables will be processed in SetHwReg8723B()
1136 */
1137void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1138{
1139	u8 val8;
1140
1141	switch (variable) {
1142	case HW_VAR_SET_RPWM:
1143		/*  rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */
1144		/*  BIT0 value - 1: 32k, 0:40MHz. */
1145		/*  BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1146		/*  BIT7 value - Toggle bit change. */
1147		{
1148			val8 = *val;
1149			val8 &= 0xC1;
1150			rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1151		}
1152		break;
1153	case HW_VAR_SET_REQ_FW_PS:
1154		{
1155			u8 req_fw_ps = 0;
1156			req_fw_ps = rtw_read8(padapter, 0x8f);
1157			req_fw_ps |= 0x10;
1158			rtw_write8(padapter, 0x8f, req_fw_ps);
1159		}
1160		break;
1161	case HW_VAR_RXDMA_AGG_PG_TH:
1162		val8 = *val;
1163		break;
1164
1165	case HW_VAR_DM_IN_LPS:
1166		rtl8723b_hal_dm_in_lps(padapter);
1167		break;
1168	default:
1169		SetHwReg8723B(padapter, variable, val);
1170		break;
1171	}
1172}
1173
1174/*
1175 * If variable not handled here,
1176 * some variables will be processed in GetHwReg8723B()
1177 */
1178void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1179{
1180	switch (variable) {
1181	case HW_VAR_CPWM:
1182		*val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B);
1183		break;
1184
1185	case HW_VAR_FW_PS_STATE:
1186		{
1187			/* 3. read dword 0x88               driver read fw ps state */
1188			*((u16 *)val) = rtw_read16(padapter, 0x88);
1189		}
1190		break;
1191	default:
1192		GetHwReg8723B(padapter, variable, val);
1193		break;
1194	}
1195}
1196
1197void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len)
1198{
1199	switch (variable) {
1200	case HW_VAR_C2H_HANDLE:
1201		C2HPacketHandler_8723B(padapter, pbuf, len);
1202		break;
1203	default:
1204		break;
1205	}
1206}
1207
1208/*  */
1209/* 	Description: */
1210/* 		Query setting of specified variable. */
1211/*  */
1212u8 GetHalDefVar8723BSDIO(
1213	struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue
1214)
1215{
1216	u8 	bResult = _SUCCESS;
1217
1218	switch (eVariable) {
1219	case HAL_DEF_IS_SUPPORT_ANT_DIV:
1220		break;
1221	case HAL_DEF_CURRENT_ANTENNA:
1222		break;
1223	case HW_VAR_MAX_RX_AMPDU_FACTOR:
1224		/*  Stanley@BB.SD3 suggests 16K can get stable performance */
1225		/*  coding by Lucas@20130730 */
1226		*(u32 *)pValue = IEEE80211_HT_MAX_AMPDU_16K;
1227		break;
1228	default:
1229		bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
1230		break;
1231	}
1232
1233	return bResult;
1234}
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