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odm.h
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linux-6.19.14/drivers/staging/rtl8723bs/hal/odm.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9#ifndef __HALDMOUTSRC_H__ 10#define __HALDMOUTSRC_H__ 11 12#include "odm_EdcaTurboCheck.h" 13#include "odm_DIG.h" 14#include "odm_DynamicBBPowerSaving.h" 15#include "odm_DynamicTxPower.h" 16#include "odm_CfoTracking.h" 17 18#define TP_MODE 0 19#define RSSI_MODE 1 20#define TRAFFIC_LOW 0 21#define TRAFFIC_HIGH 1 22#define NONE 0 23 24/* 3 Tx Power Tracking */ 25/* 3 ============================================================ */ 26#define DPK_DELTA_MAPPING_NUM 13 27#define index_mapping_HP_NUM 15 28#define OFDM_TABLE_SIZE 43 29#define CCK_TABLE_SIZE 33 30#define TXSCALE_TABLE_SIZE 37 31#define TXPWR_TRACK_TABLE_SIZE 30 32#define DELTA_SWINGIDX_SIZE 30 33#define BAND_NUM 4 34 35/* 3 PSD Handler */ 36/* 3 ============================================================ */ 37 38#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 39#define MODE_40M 0 /* 0:20M, 1:40M */ 40#define PSD_TH2 3 41#define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 42#define SIR_STEP_SIZE 3 43#define Smooth_Size_1 5 44#define Smooth_TH_1 3 45#define Smooth_Size_2 10 46#define Smooth_TH_2 4 47#define Smooth_Size_3 20 48#define Smooth_TH_3 4 49#define Smooth_Step_Size 5 50#define Adaptive_SIR 1 51#define PSD_RESCAN 4 52#define PSD_SCAN_INTERVAL 700 /* ms */ 53 54/* 8723A High Power IGI Setting */ 55#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 56#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 57#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 58#define DM_DIG_LOW_PWR_THRESHOLD 0x14 59 60/* ANT Test */ 61#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 62#define ANTTESTA 0x01 /* Ant A will be Testing */ 63#define ANTTESTB 0x02 /* Ant B will be testing */ 64 65#define PS_MODE_ACTIVE 0x01 66 67/* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 68#define MAIN_ANT 1 /* Ant A or Ant Main */ 69#define AUX_ANT 2 /* AntB or Ant Aux */ 70#define MAX_ANT 3 /* 3 for AP using */ 71 72/* Antenna Diversity Type */ 73#define SW_ANTDIV 0 74#define HW_ANTDIV 1 75/* structure and define */ 76 77/* Remove DIG by Yuchen */ 78 79/* Remove BB power saving by Yuchn */ 80 81/* Remove DIG by yuchen */ 82 83struct dynamic_primary_CCA { 84 u8 PriCCA_flag; 85 u8 intf_flag; 86 u8 intf_type; 87 u8 DupRTS_flag; 88 u8 Monitor_flag; 89 u8 CH_offset; 90 u8 MF_state; 91}; 92 93struct ra_t { 94 u8 firstconnect; 95}; 96 97struct rxhp_t { 98 u8 RXHP_flag; 99 u8 PSD_func_trigger; 100 u8 PSD_bitmap_RXHP[80]; 101 u8 Pre_IGI; 102 u8 Cur_IGI; 103 u8 Pre_pw_th; 104 u8 Cur_pw_th; 105 bool First_time_enter; 106 bool RXHP_enable; 107 u8 TP_Mode; 108 struct timer_list PSDTimer; 109}; 110 111#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 112#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 113 114/* This indicates two different the steps. */ 115/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 116/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 117/* with original RSSI to determine if it is necessary to switch antenna. */ 118#define SWAW_STEP_PEAK 0 119#define SWAW_STEP_DETERMINE 1 120 121#define TP_MODE 0 122#define RSSI_MODE 1 123#define TRAFFIC_LOW 0 124#define TRAFFIC_HIGH 1 125#define TRAFFIC_UltraLOW 2 126 127struct swat_t { /* _SW_Antenna_Switch_ */ 128 u8 Double_chk_flag; 129 u8 try_flag; 130 s32 PreRSSI; 131 u8 CurAntenna; 132 u8 PreAntenna; 133 u8 RSSI_Trying; 134 u8 TestMode; 135 u8 bTriggerAntennaSwitch; 136 u8 SelectAntennaMap; 137 u8 RSSI_target; 138 u8 reset_idx; 139 u16 Single_Ant_Counter; 140 u16 Dual_Ant_Counter; 141 u16 Aux_FailDetec_Counter; 142 u16 Retry_Counter; 143 144 /* Before link Antenna Switch check */ 145 u8 SWAS_NoLink_State; 146 u32 SWAS_NoLink_BK_Reg860; 147 u32 SWAS_NoLink_BK_Reg92c; 148 u32 SWAS_NoLink_BK_Reg948; 149 bool ANTA_ON; /* To indicate Ant A is or not */ 150 bool ANTB_ON; /* To indicate Ant B is on or not */ 151 bool Pre_Aux_FailDetec; 152 bool RSSI_AntDect_bResult; 153 u8 Ant2G; 154 155 s32 RSSI_sum_A; 156 s32 RSSI_sum_B; 157 s32 RSSI_cnt_A; 158 s32 RSSI_cnt_B; 159 160 u64 lastTxOkCnt; 161 u64 lastRxOkCnt; 162 u64 TXByteCnt_A; 163 u64 TXByteCnt_B; 164 u64 RXByteCnt_A; 165 u64 RXByteCnt_B; 166 u8 TrafficLoad; 167 u8 Train_time; 168 u8 Train_time_flag; 169 struct timer_list SwAntennaSwitchTimer; 170 struct timer_list SwAntennaSwitchTimer_8723B; 171 u32 PktCnt_SWAntDivByCtrlFrame; 172 bool bSWAntDivByCtrlFrame; 173}; 174 175/* Remove Edca by YuChen */ 176 177 178struct odm_rate_adaptive { 179 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 180 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 181 bool bUseLdpc; 182 bool bLowerRtsRate; 183 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 184 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 185 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 186 187}; 188 189#define IQK_MAC_REG_NUM 4 190#define IQK_ADDA_REG_NUM 16 191#define IQK_BB_REG_NUM_MAX 10 192#define IQK_BB_REG_NUM 9 193#define HP_THERMAL_NUM 8 194 195#define AVG_THERMAL_NUM 8 196#define IQK_MATRIX_REG_NUM 8 197#define IQK_MATRIX_SETTINGS_NUM 14 /* Channels_2_4G_NUM */ 198 199#define DM_Type_ByFW 0 200#define DM_Type_ByDriver 1 201 202/* */ 203/* Declare for common info */ 204/* */ 205#define MAX_PATH_NUM_92CS 2 206#define MAX_PATH_NUM_8188E 1 207#define MAX_PATH_NUM_8192E 2 208#define MAX_PATH_NUM_8723B 1 209#define MAX_PATH_NUM_8812A 2 210#define MAX_PATH_NUM_8821A 1 211#define MAX_PATH_NUM_8814A 4 212#define MAX_PATH_NUM_8822B 2 213 214#define IQK_THRESHOLD 8 215#define DPK_THRESHOLD 4 216 217struct odm_phy_info { 218 /* 219 * Be care, if you want to add any element, please insert it between 220 * rx_pwd_ball and signal_strength. 221 */ 222 u8 rx_pwd_ba11; 223 224 u8 signal_quality; /* in 0-100 index. */ 225 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 226 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 227 228 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 229 230 u16 cfo_short[4]; /* per-path's Cfo_short */ 231 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 232 233 s8 rx_power; /* in dBm Translate from PWdB */ 234 235 /* 236 * Real power in dBm for this packet, no beautification and 237 * aggregation. Keep this raw info to be used for the other procedures. 238 */ 239 s8 recv_signal_power; 240 u8 bt_rx_rssi_percentage; 241 u8 signal_strength; /* in 0-100 index. */ 242 243 s8 rx_pwr[4]; /* per-path's pwdb */ 244 245 u8 rx_snr[4]; /* per-path's SNR */ 246 u8 band_width; 247 u8 bt_coex_pwr_adjust; 248}; 249 250struct odm_packet_info { 251 u8 data_rate; 252 u8 station_id; 253 bool bssid_match; 254 bool to_self; 255 bool is_beacon; 256}; 257 258struct odm_phy_dbg_info { 259 /* ODM Write, debug info */ 260 s8 RxSNRdB[4]; 261 u32 NumQryPhyStatus; 262 u32 NumQryPhyStatusCCK; 263 u32 NumQryPhyStatusOFDM; 264 u8 NumQryBeaconPkt; 265 /* Others */ 266 s32 RxEVM[4]; 267 268}; 269 270struct odm_mac_status_info { 271 u8 test; 272}; 273 274/* */ 275/* 2011/10/20 MH Define Common info enum for all team. */ 276/* */ 277enum odm_cmninfo_e { 278 /* Fixed value: */ 279 280 /* HOOK BEFORE REG INIT----------- */ 281 ODM_CMNINFO_PLATFORM = 0, 282 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 283 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 284 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 285 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 286 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 287 ODM_CMNINFO_RFE_TYPE, 288 ODM_CMNINFO_PACKAGE_TYPE, 289 ODM_CMNINFO_EXT_LNA, /* true */ 290 ODM_CMNINFO_EXT_PA, 291 ODM_CMNINFO_GPA, 292 ODM_CMNINFO_APA, 293 ODM_CMNINFO_GLNA, 294 ODM_CMNINFO_ALNA, 295 ODM_CMNINFO_EXT_TRSW, 296 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 297 ODM_CMNINFO_BINHCT_TEST, 298 ODM_CMNINFO_BWIFI_TEST, 299 ODM_CMNINFO_SMART_CONCURRENT, 300 /* HOOK BEFORE REG INIT----------- */ 301 302 /* Dynamic value: */ 303/* POINTER REFERENCE----------- */ 304 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 305 ODM_CMNINFO_TX_UNI, 306 ODM_CMNINFO_RX_UNI, 307 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 308 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 309 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 310 ODM_CMNINFO_BW, /* ODM_BW_E */ 311 ODM_CMNINFO_CHNL, 312 ODM_CMNINFO_FORCED_RATE, 313 314 ODM_CMNINFO_DMSP_GET_VALUE, 315 ODM_CMNINFO_BUDDY_ADAPTOR, 316 ODM_CMNINFO_DMSP_IS_MASTER, 317 ODM_CMNINFO_SCAN, 318 ODM_CMNINFO_POWER_SAVING, 319 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 320 ODM_CMNINFO_DRV_STOP, 321 ODM_CMNINFO_PNP_IN, 322 ODM_CMNINFO_INIT_ON, 323 ODM_CMNINFO_ANT_TEST, 324 ODM_CMNINFO_NET_CLOSED, 325 ODM_CMNINFO_MP_MODE, 326 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 327 ODM_CMNINFO_FORCED_IGI_LB, 328 ODM_CMNINFO_IS1ANTENNA, 329 ODM_CMNINFO_RFDEFAULTPATH, 330/* POINTER REFERENCE----------- */ 331 332/* CALL BY VALUE------------- */ 333 ODM_CMNINFO_WIFI_DIRECT, 334 ODM_CMNINFO_WIFI_DISPLAY, 335 ODM_CMNINFO_LINK_IN_PROGRESS, 336 ODM_CMNINFO_LINK, 337 ODM_CMNINFO_STATION_STATE, 338 ODM_CMNINFO_RSSI_MIN, 339 ODM_CMNINFO_DBG_COMP, /* u64 */ 340 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 341 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 342 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 343 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 344 ODM_CMNINFO_BT_ENABLED, 345 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 346 ODM_CMNINFO_BT_HS_RSSI, 347 ODM_CMNINFO_BT_OPERATION, 348 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 349 ODM_CMNINFO_BT_DISABLE_EDCA, 350/* CALL BY VALUE------------- */ 351 352 /* Dynamic ptr array hook itms. */ 353 ODM_CMNINFO_STA_STATUS, 354 ODM_CMNINFO_PHY_STATUS, 355 ODM_CMNINFO_MAC_STATUS, 356 357 ODM_CMNINFO_MAX, 358}; 359 360/* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 361enum { /* _ODM_Support_Ability_Definition */ 362 /* */ 363 /* BB ODM section BIT 0-15 */ 364 /* */ 365 ODM_BB_DIG = BIT0, 366 ODM_BB_RA_MASK = BIT1, 367 ODM_BB_DYNAMIC_TXPWR = BIT2, 368 ODM_BB_FA_CNT = BIT3, 369 ODM_BB_RSSI_MONITOR = BIT4, 370 ODM_BB_CCK_PD = BIT5, 371 ODM_BB_ANT_DIV = BIT6, 372 ODM_BB_PWR_SAVE = BIT7, 373 ODM_BB_PWR_TRAIN = BIT8, 374 ODM_BB_RATE_ADAPTIVE = BIT9, 375 ODM_BB_PATH_DIV = BIT10, 376 ODM_BB_PSD = BIT11, 377 ODM_BB_RXHP = BIT12, 378 ODM_BB_ADAPTIVITY = BIT13, 379 ODM_BB_CFO_TRACKING = BIT14, 380 381 /* MAC DM section BIT 16-23 */ 382 ODM_MAC_EDCA_TURBO = BIT16, 383 ODM_MAC_EARLY_MODE = BIT17, 384 385 /* RF ODM section BIT 24-31 */ 386 ODM_RF_TX_PWR_TRACK = BIT24, 387 ODM_RF_RX_GAIN_TRACK = BIT25, 388 ODM_RF_CALIBRATION = BIT26, 389}; 390 391/* ODM_CMNINFO_INTERFACE */ 392enum { /* tag_ODM_Support_Interface_Definition */ 393 ODM_ITRF_SDIO = 0x4, 394 ODM_ITRF_ALL = 0x7, 395}; 396 397/* ODM_CMNINFO_IC_TYPE */ 398enum { /* tag_ODM_Support_IC_Type_Definition */ 399 ODM_RTL8723B = BIT8, 400}; 401 402/* ODM_CMNINFO_CUT_VER */ 403enum { /* tag_ODM_Cut_Version_Definition */ 404 ODM_CUT_A = 0, 405 ODM_CUT_B = 1, 406 ODM_CUT_C = 2, 407 ODM_CUT_D = 3, 408 ODM_CUT_E = 4, 409 ODM_CUT_F = 5, 410 411 ODM_CUT_I = 8, 412 ODM_CUT_J = 9, 413 ODM_CUT_K = 10, 414 ODM_CUT_TEST = 15, 415}; 416 417/* ODM_CMNINFO_FAB_VER */ 418enum { /* tag_ODM_Fab_Version_Definition */ 419 ODM_TSMC = 0, 420 ODM_UMC = 1, 421}; 422 423/* */ 424/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 425/* */ 426enum { /* tag_ODM_RF_Type_Definition */ 427 ODM_1T1R = 0, 428 ODM_1T2R = 1, 429 ODM_2T2R = 2, 430 ODM_2T3R = 3, 431 ODM_2T4R = 4, 432 ODM_3T3R = 5, 433 ODM_3T4R = 6, 434 ODM_4T4R = 7, 435}; 436 437/* */ 438/* ODM Dynamic common info value definition */ 439/* */ 440 441/* ODM_CMNINFO_WM_MODE */ 442enum { /* tag_Wireless_Mode_Definition */ 443 ODM_WM_UNKNOWN = 0x0, 444 ODM_WM_B = BIT0, 445 ODM_WM_G = BIT1, 446 ODM_WM_N24G = BIT3, 447 ODM_WM_AUTO = BIT5, 448}; 449 450/* ODM_CMNINFO_BW */ 451enum { /* tag_Bandwidth_Definition */ 452 ODM_BW20M = 0, 453 ODM_BW40M = 1, 454}; 455 456/* For AC-series IC, external PA & LNA can be individually added on 2.4G */ 457 458enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */ 459 TYPE_GPA0 = 0, 460 TYPE_GPA1 = BIT(1)|BIT(0) 461}; 462 463enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */ 464 TYPE_APA0 = 0, 465 TYPE_APA1 = BIT(1)|BIT(0) 466}; 467 468enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */ 469 TYPE_GLNA0 = 0, 470 TYPE_GLNA1 = BIT(2)|BIT(0), 471 TYPE_GLNA2 = BIT(3)|BIT(1), 472 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 473}; 474 475enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */ 476 TYPE_ALNA0 = 0, 477 TYPE_ALNA1 = BIT(2)|BIT(0), 478 TYPE_ALNA2 = BIT(3)|BIT(1), 479 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 480}; 481 482/* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 483 484struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */ 485 /* for tx power tracking */ 486 487 u32 RegA24; /* for TempCCK */ 488 s32 RegE94; 489 s32 RegE9C; 490 s32 RegEB4; 491 s32 RegEBC; 492 493 u8 TXPowercount; 494 bool bTXPowerTrackingInit; 495 bool bTXPowerTracking; 496 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 497 u8 TM_Trigger; 498 499 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 500 u8 ThermalValue; 501 u8 ThermalValue_LCK; 502 u8 ThermalValue_IQK; 503 u8 ThermalValue_DPK; 504 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 505 u8 ThermalValue_AVG_index; 506 u8 ThermalValue_RxGain; 507 u8 ThermalValue_Crystal; 508 u8 ThermalValue_DPKstore; 509 u8 ThermalValue_DPKtrack; 510 bool TxPowerTrackingInProgress; 511 512 bool bReloadtxpowerindex; 513 u8 bRfPiEnable; 514 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 515 516 /* Tx power Tracking ------------------------- */ 517 u8 bCCKinCH14; 518 u8 CCK_index; 519 u8 OFDM_index[MAX_RF_PATH]; 520 s8 PowerIndexOffset[MAX_RF_PATH]; 521 s8 DeltaPowerIndex[MAX_RF_PATH]; 522 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 523 bool bTxPowerChanged; 524 525 u8 ThermalValue_HP[HP_THERMAL_NUM]; 526 u8 ThermalValue_HP_index; 527 s32 iqk_matrix_regs_setting_value[IQK_MATRIX_SETTINGS_NUM][IQK_MATRIX_REG_NUM]; 528 bool bNeedIQK; 529 bool bIQKInProgress; 530 u8 Delta_IQK; 531 u8 Delta_LCK; 532 s8 BBSwingDiff2G; /* Unit: dB */ 533 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 534 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 535 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 536 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 537 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 538 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 539 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 540 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 541 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 542 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 543 544 /* */ 545 546 /* for IQK */ 547 u32 RegC04; 548 u32 Reg874; 549 u32 RegC08; 550 u32 RegB68; 551 u32 RegB6C; 552 u32 Reg870; 553 u32 Reg860; 554 u32 Reg864; 555 556 bool bIQKInitialized; 557 bool bLCKInProgress; 558 bool bAntennaDetected; 559 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 560 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 561 u32 IQK_BB_backup_recover[9]; 562 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 563 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 564 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 565 566 /* for APK */ 567 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 568 u8 bAPKdone; 569 u8 bAPKThermalMeterIgnore; 570 571 /* DPK */ 572 bool bDPKFail; 573 u8 bDPdone; 574 u8 bDPPathAOK; 575 u8 bDPPathBOK; 576 577 u32 TxLOK[2]; 578 579}; 580/* */ 581/* ODM Dynamic common info value definition */ 582/* */ 583 584struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */ 585 u8 Bssid[6]; 586 u8 antsel_rx_keep_0; 587 u8 antsel_rx_keep_1; 588 u8 antsel_rx_keep_2; 589 u8 antsel_rx_keep_3; 590 u32 antSumRSSI[7]; 591 u32 antRSSIcnt[7]; 592 u32 antAveRSSI[7]; 593 u8 FAT_State; 594 u32 TrainIdx; 595 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 596 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 597 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 598 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 599 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 600 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 601 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 602 u8 RxIdleAnt; 603 bool bBecomeLinked; 604 u32 MinMaxRSSI; 605 u8 idx_AntDiv_counter_2G; 606 u32 CCK_counter_main; 607 u32 CCK_counter_aux; 608 u32 OFDM_counter_main; 609 u32 OFDM_counter_aux; 610 611 u32 CCK_CtrlFrame_Cnt_main; 612 u32 CCK_CtrlFrame_Cnt_aux; 613 u32 OFDM_CtrlFrame_Cnt_main; 614 u32 OFDM_CtrlFrame_Cnt_aux; 615 u32 MainAnt_CtrlFrame_Sum; 616 u32 AuxAnt_CtrlFrame_Sum; 617 u32 MainAnt_CtrlFrame_Cnt; 618 u32 AuxAnt_CtrlFrame_Cnt; 619 620}; 621 622enum { 623 NO_ANTDIV = 0xFF, 624 CG_TRX_HW_ANTDIV = 0x01, 625 CGCS_RX_HW_ANTDIV = 0x02, 626 FIXED_HW_ANTDIV = 0x03, 627 CG_TRX_SMART_ANTDIV = 0x04, 628 CGCS_RX_SW_ANTDIV = 0x05, 629 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 630}; 631 632struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */ 633 u8 RespTxPath; 634 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 635 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 636 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 637 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 638 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 639}; 640 641enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */ 642 PHY_REG_PG_RELATIVE_VALUE = 0, 643 PHY_REG_PG_EXACT_VALUE = 1 644}; 645 646/* */ 647/* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 648/* */ 649struct ant_detected_info { 650 bool bAntDetected; 651 u32 dBForAntA; 652 u32 dBForAntB; 653 u32 dBForAntO; 654}; 655 656/* */ 657/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 658/* */ 659struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */ 660 /* struct timer_list FastAntTrainingTimer; */ 661 /* */ 662 /* Add for different team use temporarily */ 663 /* */ 664 struct adapter *Adapter; /* For CE/NIC team */ 665 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 666 bool odm_ready; 667 668 enum phy_reg_pg_type PhyRegPgValueType; 669 u8 PhyRegPgVersion; 670 671 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 672 u32 LastNumQryPhyStatusAll; 673 u32 RxPWDBAve; 674 bool MPDIG_2G; /* off MPDIG */ 675 u8 Times_2G; 676 677/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 678 bool bCckHighPower; 679 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 680 u8 ControlChannel; 681/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 682 683/* REMOVED COMMON INFO---------- */ 684 /* u8 PseudoMacPhyMode; */ 685 /* bool *BTCoexist; */ 686 /* bool PseudoBtCoexist; */ 687 /* u8 OPMode; */ 688 /* bool bAPMode; */ 689 /* bool bClientMode; */ 690 /* bool bAdHocMode; */ 691 /* bool bSlaveOfDMSP; */ 692/* REMOVED COMMON INFO---------- */ 693 694/* 1 COMMON INFORMATION */ 695 696 /* */ 697 /* Init Value */ 698 /* */ 699/* HOOK BEFORE REG INIT----------- */ 700 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 701 u8 SupportPlatform; 702 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 703 u32 SupportAbility; 704 /* ODM PCIE/USB/SDIO = 1/2/3 */ 705 u8 SupportInterface; 706 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 707 u32 SupportICType; 708 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 709 u8 CutVersion; 710 /* Fab Version TSMC/UMC = 0/1 */ 711 u8 FabVersion; 712 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 713 u8 RFEType; 714 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 715 u8 BoardType; 716 u8 PackageType; 717 u8 TypeGLNA; 718 u8 TypeGPA; 719 u8 TypeALNA; 720 u8 TypeAPA; 721 /* with external LNA NO/Yes = 0/1 */ 722 u8 ExtLNA; 723 /* with external PA NO/Yes = 0/1 */ 724 u8 ExtPA; 725 /* with external TRSW NO/Yes = 0/1 */ 726 u8 ExtTRSW; 727 u8 PatchID; /* Customer ID */ 728 bool bInHctTest; 729 bool bWIFITest; 730 731 bool bDualMacSmartConcurrent; 732 u32 BK_SupportAbility; 733 u8 AntDivType; 734/* HOOK BEFORE REG INIT----------- */ 735 736 /* */ 737 /* Dynamic Value */ 738 /* */ 739/* POINTER REFERENCE----------- */ 740 741 u8 u8_temp; 742 bool bool_temp; 743 struct adapter *adapter_temp; 744 745 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 746 u8 *pMacPhyMode; 747 /* TX Unicast byte count */ 748 u64 *pNumTxBytesUnicast; 749 /* RX Unicast byte count */ 750 u64 *pNumRxBytesUnicast; 751 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 752 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 753 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 754 u8 *pSecChOffset; 755 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 756 u8 *pSecurity; 757 /* BW info 20M/40M/80M = 0/1/2 */ 758 u8 *pBandWidth; 759 /* Central channel location Ch1/Ch2/.... */ 760 u8 *pChannel; /* central channel number */ 761 bool DPK_Done; 762 /* Common info for 92D DMSP */ 763 764 bool *pbGetValueFromOtherMac; 765 struct adapter **pBuddyAdapter; 766 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 767 /* Common info for Status */ 768 bool *pbScanInProcess; 769 bool *pbPowerSaving; 770 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 771 u8 *pOnePathCCA; 772 /* pMgntInfo->AntennaTest */ 773 u8 *pAntennaTest; 774 bool *pbNet_closed; 775 u8 *mp_mode; 776 /* u8 *pAidMap; */ 777 u8 *pu1ForcedIgiLb; 778/* For 8723B IQK----------- */ 779 bool *pIs1Antenna; 780 u8 *pRFDefaultPath; 781 /* 0:S1, 1:S0 */ 782 783/* POINTER REFERENCE----------- */ 784 u16 *pForcedDataRate; 785/* CALL BY VALUE------------- */ 786 bool bLinkInProcess; 787 bool bWIFI_Direct; 788 bool bWIFI_Display; 789 bool bLinked; 790 791 bool bsta_state; 792 u8 RSSI_Min; 793 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 794 bool bOneEntryOnly; 795 /* Common info for BTDM */ 796 bool bBtEnabled; /* BT is disabled */ 797 bool bBtConnectProcess; /* BT HS is under connection progress. */ 798 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 799 bool bBtHsOperation; /* BT HS mode is under progress */ 800 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 801 bool bBtLimitedDig; /* BT is busy. */ 802/* CALL BY VALUE------------- */ 803 u8 RSSI_A; 804 u8 RSSI_B; 805 u64 RSSI_TRSW; 806 u64 RSSI_TRSW_H; 807 u64 RSSI_TRSW_L; 808 u64 RSSI_TRSW_iso; 809 810 u8 RxRate; 811 bool bNoisyState; 812 u8 TxRate; 813 u8 LinkedInterval; 814 u8 preChannel; 815 u32 TxagcOffsetValueA; 816 bool IsTxagcOffsetPositiveA; 817 u32 TxagcOffsetValueB; 818 bool IsTxagcOffsetPositiveB; 819 u64 lastTxOkCnt; 820 u64 lastRxOkCnt; 821 u32 BbSwingOffsetA; 822 bool IsBbSwingOffsetPositiveA; 823 u32 BbSwingOffsetB; 824 bool IsBbSwingOffsetPositiveB; 825 s8 TH_L2H_ini; 826 s8 TH_EDCCA_HL_diff; 827 s8 IGI_Base; 828 u8 IGI_target; 829 bool ForceEDCCA; 830 u8 AdapEn_RSSI; 831 s8 Force_TH_H; 832 s8 Force_TH_L; 833 u8 IGI_LowerBound; 834 u8 antdiv_rssi; 835 u8 AntType; 836 u8 pre_AntType; 837 u8 antdiv_period; 838 u8 antdiv_select; 839 u8 NdpaPeriod; 840 bool H2C_RARpt_connect; 841 842 /* add by Yu Cehn for adaptivtiy */ 843 bool adaptivity_flag; 844 bool NHM_disable; 845 bool TxHangFlg; 846 bool Carrier_Sense_enable; 847 u8 tolerance_cnt; 848 u64 NHMCurTxOkcnt; 849 u64 NHMCurRxOkcnt; 850 u64 NHMLastTxOkcnt; 851 u64 NHMLastRxOkcnt; 852 u8 txEdcca1; 853 u8 txEdcca0; 854 s8 H2L_lb; 855 s8 L2H_lb; 856 u8 Adaptivity_IGI_upper; 857 u8 NHM_cnt_0; 858 859 /* */ 860 /* 2 Define STA info. */ 861 /* _ODM_STA_INFO */ 862 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 863 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 864 865 /* */ 866 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 867 /* We need to colelct all support abilit to a proper area. */ 868 /* */ 869 bool RaSupport88E; 870 871 /* Define ........... */ 872 873 /* Latest packet phy info (ODM write) */ 874 struct odm_phy_dbg_info PhyDbgInfo; 875 /* PHY_INFO_88E PhyInfo; */ 876 877 /* Latest packet phy info (ODM write) */ 878 struct odm_mac_status_info *pMacInfo; 879 /* MAC_INFO_88E MacInfo; */ 880 881 /* Different Team independent structure?? */ 882 883 /* */ 884 /* TX_RTP_CMN TX_retrpo; */ 885 /* TX_RTP_88E TX_retrpo; */ 886 /* TX_RTP_8195 TX_retrpo; */ 887 888 /* */ 889 /* ODM Structure */ 890 /* */ 891 struct fat_t DM_FatTable; 892 struct dig_t DM_DigTable; 893 struct ps_t DM_PSTable; 894 struct dynamic_primary_CCA DM_PriCCA; 895 struct rxhp_t dM_RXHP_Table; 896 struct ra_t DM_RA_Table; 897 struct false_ALARM_STATISTICS FalseAlmCnt; 898 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 899 struct swat_t DM_SWAT_Table; 900 bool RSSI_test; 901 struct cfo_tracking DM_CfoTrack; 902 903 struct edca_t DM_EDCA_Table; 904 u32 WMMEDCA_BE; 905 struct pathdiv_t DM_PathDiv; 906 /* Copy from SD4 structure */ 907 /* */ 908 /* ================================================== */ 909 /* */ 910 911 /* common */ 912 /* u8 DM_Type; */ 913 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 914 /* u8 PSD_func_flag; Add By Gary */ 915 /* for DIG */ 916 /* u8 bDMInitialGainEnable; */ 917 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 918 /* for Antenna diversity */ 919 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 920 /* PSTA_INFO_T RSSI_target; */ 921 922 bool *pbDriverStopped; 923 bool *pbDriverIsGoingToPnpSetPowerSleep; 924 bool *pinit_adpt_in_progress; 925 926 /* PSD */ 927 bool bUserAssignLevel; 928 struct timer_list PSDTimer; 929 u8 RSSI_BT; /* come from BT */ 930 bool bPSDinProcess; 931 bool bPSDactive; 932 bool bDMInitialGainEnable; 933 934 /* MPT DIG */ 935 struct timer_list MPT_DIGTimer; 936 937 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 938 u8 bUseRAMask; 939 940 struct odm_rate_adaptive RateAdaptive; 941 942 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */ 943 944 struct odm_rf_cal_t RFCalibrateInfo; 945 946 /* */ 947 /* TX power tracking */ 948 /* */ 949 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 950 u8 BbSwingIdxOfdmCurrent; 951 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 952 bool BbSwingFlagOfdm; 953 u8 BbSwingIdxCck; 954 u8 BbSwingIdxCckCurrent; 955 u8 BbSwingIdxCckBase; 956 u8 DefaultOfdmIndex; 957 u8 DefaultCckIndex; 958 bool BbSwingFlagCck; 959 960 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 961 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 962 s8 Remnant_CCKSwingIdx; 963 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 964 bool Modify_TxAGC_Flag_PathA; 965 bool Modify_TxAGC_Flag_PathB; 966 bool Modify_TxAGC_Flag_PathC; 967 bool Modify_TxAGC_Flag_PathD; 968 bool Modify_TxAGC_Flag_PathA_CCK; 969 970 s8 KfreeOffset[MAX_RF_PATH]; 971 /* */ 972 /* ODM system resource. */ 973 /* */ 974 975 /* ODM relative time. */ 976 struct timer_list PathDivSwitchTimer; 977 /* 2011.09.27 add for Path Diversity */ 978 struct timer_list CCKPathDiversityTimer; 979 struct timer_list FastAntTrainingTimer; 980 981 /* ODM relative workitem. */ 982 983 #if (BEAMFORMING_SUPPORT == 1) 984 RT_BEAMFORMING_INFO BeamformingInfo; 985 #endif 986}; 987 988 enum odm_rf_content { 989 odm_radioa_txt = 0x1000, 990 odm_radiob_txt = 0x1001, 991 odm_radioc_txt = 0x1002, 992 odm_radiod_txt = 0x1003 993}; 994 995enum ODM_BB_Config_Type { 996 CONFIG_BB_PHY_REG, 997 CONFIG_BB_AGC_TAB, 998 CONFIG_BB_AGC_TAB_2G, 999 CONFIG_BB_PHY_REG_PG, 1000 CONFIG_BB_PHY_REG_MP, 1001 CONFIG_BB_AGC_TAB_DIFF, 1002}; 1003 1004enum ODM_RF_Config_Type { 1005 CONFIG_RF_RADIO, 1006 CONFIG_RF_TXPWR_LMT, 1007}; 1008 1009enum ODM_FW_Config_Type { 1010 CONFIG_FW_NIC, 1011 CONFIG_FW_NIC_2, 1012 CONFIG_FW_AP, 1013 CONFIG_FW_WoWLAN, 1014 CONFIG_FW_WoWLAN_2, 1015 CONFIG_FW_AP_WoWLAN, 1016 CONFIG_FW_BT, 1017}; 1018 1019#ifdef REMOVE_PACK 1020#pragma pack() 1021#endif 1022 1023/* include "odm_function.h" */ 1024 1025/* 3 =========================================================== */ 1026/* 3 DIG */ 1027/* 3 =========================================================== */ 1028 1029/* Remove DIG by Yuchen */ 1030 1031/* 3 =========================================================== */ 1032/* 3 AGC RX High Power Mode */ 1033/* 3 =========================================================== */ 1034#define LNA_Low_Gain_1 0x64 1035#define LNA_Low_Gain_2 0x5A 1036#define LNA_Low_Gain_3 0x58 1037 1038#define FA_RXHP_TH1 5000 1039#define FA_RXHP_TH2 1500 1040#define FA_RXHP_TH3 800 1041#define FA_RXHP_TH4 600 1042#define FA_RXHP_TH5 500 1043 1044/* 3 =========================================================== */ 1045/* 3 EDCA */ 1046/* 3 =========================================================== */ 1047 1048/* 3 =========================================================== */ 1049/* 3 Dynamic Tx Power */ 1050/* 3 =========================================================== */ 1051/* Dynamic Tx Power Control Threshold */ 1052 1053/* 3 =========================================================== */ 1054/* 3 Rate Adaptive */ 1055/* 3 =========================================================== */ 1056#define DM_RATR_STA_INIT 0 1057#define DM_RATR_STA_HIGH 1 1058#define DM_RATR_STA_MIDDLE 2 1059#define DM_RATR_STA_LOW 3 1060 1061/* 3 =========================================================== */ 1062/* 3 BB Power Save */ 1063/* 3 =========================================================== */ 1064 1065enum { /* tag_1R_CCA_Type_Definition */ 1066 CCA_1R = 0, 1067 CCA_2R = 1, 1068 CCA_MAX = 2, 1069}; 1070 1071enum { /* tag_RF_Type_Definition */ 1072 RF_Save = 0, 1073 RF_Normal = 1, 1074 RF_MAX = 2, 1075}; 1076 1077/* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1078#define MAX_ANTENNA_DETECTION_CNT 10 1079 1080/* */ 1081/* Extern Global Variables. */ 1082/* */ 1083extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1084extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1085extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1086 1087/* */ 1088/* check Sta pointer valid or not */ 1089/* */ 1090#define IS_STA_VALID(pSta) (pSta) 1091/* 20100514 Joseph: Add definition for antenna switching test after link. */ 1092/* This indicates two different the steps. */ 1093/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1094/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1095/* with original RSSI to determine if it is necessary to switch antenna. */ 1096#define SWAW_STEP_PEAK 0 1097#define SWAW_STEP_DETERMINE 1 1098 1099/* Remove BB power saving by Yuchen */ 1100 1101#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1102void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm); 1103 1104bool ODM_RAStateCheck( 1105 struct dm_odm_t *pDM_Odm, 1106 s32 RSSI, 1107 bool bForceUpdate, 1108 u8 *pRATRState 1109); 1110 1111#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1112void ODM_SwAntDivChkPerPktRssi( 1113 struct dm_odm_t *pDM_Odm, 1114 u8 StationID, 1115 struct odm_phy_info *pPhyInfo 1116); 1117 1118u32 ODM_Get_Rate_Bitmap( 1119 struct dm_odm_t *pDM_Odm, 1120 u32 macid, 1121 u32 ra_mask, 1122 u8 rssi_level 1123); 1124 1125#if (BEAMFORMING_SUPPORT == 1) 1126BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1127#endif 1128 1129void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm); 1130 1131void ODM_DMInit(struct dm_odm_t *pDM_Odm); 1132 1133void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1134 1135void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value); 1136 1137void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue); 1138 1139void ODM_CmnInfoPtrArrayHook( 1140 struct dm_odm_t *pDM_Odm, 1141 enum odm_cmninfo_e CmnInfo, 1142 u16 Index, 1143 void *pValue 1144); 1145 1146void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1147 1148void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); 1149 1150void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); 1151 1152void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); 1153 1154void ODM_AntselStatistics_88C( 1155 struct dm_odm_t *pDM_Odm, 1156 u8 MacId, 1157 u32 PWDBAll, 1158 bool isCCKrate 1159); 1160 1161void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State); 1162 1163#endif
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