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hal_com_phycfg.c

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linux-6.19.14/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c C 
  1// SPDX-License-Identifier: GPL-2.0
  2/******************************************************************************
  3 *
  4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  5 *
  6 ******************************************************************************/
  7
  8#include <drv_types.h>
  9#include <hal_data.h>
 10#include <linux/kernel.h>
 11
 12u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
 13			    enum rate_section RateSection)
 14{
 15	struct hal_com_data	*pHalData = GET_HAL_DATA(Adapter);
 16	u8	value = 0;
 17
 18	if (RfPath >= RF_PATH_MAX)
 19		return 0;
 20
 21	switch (RateSection) {
 22	case CCK:
 23		value = pHalData->TxPwrByRateBase2_4G[RfPath][0];
 24		break;
 25	case OFDM:
 26		value = pHalData->TxPwrByRateBase2_4G[RfPath][1];
 27		break;
 28	case HT_MCS0_MCS7:
 29		value = pHalData->TxPwrByRateBase2_4G[RfPath][2];
 30		break;
 31	default:
 32		break;
 33	}
 34
 35	return value;
 36}
 37
 38static void
 39phy_SetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath,
 40			 enum rate_section RateSection, u8 Value)
 41{
 42	struct hal_com_data	*pHalData = GET_HAL_DATA(Adapter);
 43
 44	if (RfPath >= RF_PATH_MAX)
 45		return;
 46
 47	switch (RateSection) {
 48	case CCK:
 49		pHalData->TxPwrByRateBase2_4G[RfPath][0] = Value;
 50		break;
 51	case OFDM:
 52		pHalData->TxPwrByRateBase2_4G[RfPath][1] = Value;
 53		break;
 54	case HT_MCS0_MCS7:
 55		pHalData->TxPwrByRateBase2_4G[RfPath][2] = Value;
 56		break;
 57	default:
 58		break;
 59	}
 60}
 61
 62static void phy_StoreTxPowerByRateBase(struct adapter *padapter)
 63{
 64	u8 path, base;
 65
 66	for (path = RF_PATH_A; path <= RF_PATH_B; ++path) {
 67		base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
 68		phy_SetTxPowerByRateBase(padapter, path, CCK, base);
 69
 70		base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
 71		phy_SetTxPowerByRateBase(padapter, path, OFDM, base);
 72
 73		base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
 74		phy_SetTxPowerByRateBase(padapter, path, HT_MCS0_MCS7, base);
 75	}
 76}
 77
 78u8 PHY_GetRateSectionIndexOfTxPowerByRate(
 79	struct adapter *padapter, u32 RegAddr, u32 BitMask
 80)
 81{
 82	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
 83	struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 84	u8	index = 0;
 85
 86	if (pDM_Odm->PhyRegPgVersion == 0) {
 87		switch (RegAddr) {
 88		case rTxAGC_A_Rate18_06:
 89			index = 0;
 90			break;
 91		case rTxAGC_A_Rate54_24:
 92			index = 1;
 93			break;
 94		case rTxAGC_A_CCK1_Mcs32:
 95			index = 6;
 96			break;
 97		case rTxAGC_B_CCK11_A_CCK2_11:
 98			if (BitMask == bMaskH3Bytes)
 99				index = 7;
100			else if (BitMask == 0x000000ff)
101				index = 15;
102			break;
103
104		case rTxAGC_A_Mcs03_Mcs00:
105			index = 2;
106			break;
107		case rTxAGC_A_Mcs07_Mcs04:
108			index = 3;
109			break;
110		case rTxAGC_B_Rate18_06:
111			index = 8;
112			break;
113		case rTxAGC_B_Rate54_24:
114			index = 9;
115			break;
116		case rTxAGC_B_CCK1_55_Mcs32:
117			index = 14;
118			break;
119		case rTxAGC_B_Mcs03_Mcs00:
120			index = 10;
121			break;
122		case rTxAGC_B_Mcs07_Mcs04:
123			index = 11;
124			break;
125		default:
126			break;
127		}
128	}
129
130	return index;
131}
132
133void
134PHY_GetRateValuesOfTxPowerByRate(
135	struct adapter *padapter,
136	u32	RegAddr,
137	u32	BitMask,
138	u32	Value,
139	u8 *RateIndex,
140	s8 *PwrByRateVal,
141	u8 *RateNum
142)
143{
144	u8 i = 0;
145
146	switch (RegAddr) {
147	case rTxAGC_A_Rate18_06:
148	case rTxAGC_B_Rate18_06:
149		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
150		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
151		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
152		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
153		for (i = 0; i < 4; ++i) {
154			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
155											((Value >> (i * 8)) & 0xF));
156		}
157		*RateNum = 4;
158		break;
159
160	case rTxAGC_A_Rate54_24:
161	case rTxAGC_B_Rate54_24:
162		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
163		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
164		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
165		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
166		for (i = 0; i < 4; ++i) {
167			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
168											((Value >> (i * 8)) & 0xF));
169		}
170		*RateNum = 4;
171		break;
172
173	case rTxAGC_A_CCK1_Mcs32:
174		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
175		PwrByRateVal[0] = (s8) ((((Value >> (8 + 4)) & 0xF)) * 10 +
176										((Value >> 8) & 0xF));
177		*RateNum = 1;
178		break;
179
180	case rTxAGC_B_CCK11_A_CCK2_11:
181		if (BitMask == 0xffffff00) {
182			RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
183			RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
184			RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
185			for (i = 1; i < 4; ++i) {
186				PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
187												((Value >> (i * 8)) & 0xF));
188			}
189			*RateNum = 3;
190		} else if (BitMask == 0x000000ff) {
191			RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
192			PwrByRateVal[0] = (s8) ((((Value >> 4) & 0xF)) * 10 + (Value & 0xF));
193			*RateNum = 1;
194		}
195		break;
196
197	case rTxAGC_A_Mcs03_Mcs00:
198	case rTxAGC_B_Mcs03_Mcs00:
199		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
200		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
201		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
202		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
203		for (i = 0; i < 4; ++i) {
204			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
205											((Value >> (i * 8)) & 0xF));
206		}
207		*RateNum = 4;
208		break;
209
210	case rTxAGC_A_Mcs07_Mcs04:
211	case rTxAGC_B_Mcs07_Mcs04:
212		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
213		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
214		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
215		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
216		for (i = 0; i < 4; ++i) {
217			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
218											((Value >> (i * 8)) & 0xF));
219		}
220		*RateNum = 4;
221		break;
222
223	case rTxAGC_B_CCK1_55_Mcs32:
224		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
225		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
226		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
227		for (i = 1; i < 4; ++i) {
228			PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
229											((Value >> (i * 8)) & 0xF));
230		}
231		*RateNum = 3;
232		break;
233
234	case 0xC20:
235	case 0xE20:
236	case 0x1820:
237	case 0x1a20:
238		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
239		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
240		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
241		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
242		for (i = 0; i < 4; ++i) {
243			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
244											((Value >> (i * 8)) & 0xF));
245		}
246		*RateNum = 4;
247		break;
248
249	case 0xC24:
250	case 0xE24:
251	case 0x1824:
252	case 0x1a24:
253		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
254		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
255		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
256		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
257		for (i = 0; i < 4; ++i) {
258			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
259											((Value >> (i * 8)) & 0xF));
260		}
261		*RateNum = 4;
262		break;
263
264	case 0xC28:
265	case 0xE28:
266	case 0x1828:
267	case 0x1a28:
268		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
269		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
270		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
271		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
272		for (i = 0; i < 4; ++i) {
273			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
274											((Value >> (i * 8)) & 0xF));
275		}
276		*RateNum = 4;
277		break;
278
279	case 0xC2C:
280	case 0xE2C:
281	case 0x182C:
282	case 0x1a2C:
283		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
284		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
285		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
286		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
287		for (i = 0; i < 4; ++i) {
288			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
289											((Value >> (i * 8)) & 0xF));
290		}
291		*RateNum = 4;
292		break;
293
294	case 0xC30:
295	case 0xE30:
296	case 0x1830:
297	case 0x1a30:
298		RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
299		RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
300		RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
301		RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
302		for (i = 0; i < 4; ++i) {
303			PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
304											((Value >> (i * 8)) & 0xF));
305		}
306		*RateNum = 4;
307		break;
308
309	default:
310		break;
311	}
312}
313
314static void PHY_StoreTxPowerByRateNew(struct adapter *padapter,	u32 RfPath,
315				      u32 RegAddr, u32 BitMask, u32 Data)
316{
317	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
318	u8 i = 0, rateIndex[4] = {0}, rateNum = 0;
319	s8	PwrByRateVal[4] = {0};
320
321	PHY_GetRateValuesOfTxPowerByRate(padapter, RegAddr, BitMask, Data, rateIndex, PwrByRateVal, &rateNum);
322
323	if (RfPath >= RF_PATH_MAX)
324		return;
325
326	for (i = 0; i < rateNum; ++i) {
327		pHalData->TxPwrByRateOffset[RfPath][rateIndex[i]] = PwrByRateVal[i];
328	}
329}
330
331static void PHY_StoreTxPowerByRateOld(
332	struct adapter *padapter, u32	RegAddr, u32 BitMask, u32 Data
333)
334{
335	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
336	u8	index = PHY_GetRateSectionIndexOfTxPowerByRate(padapter, RegAddr, BitMask);
337
338	pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data;
339}
340
341void PHY_InitTxPowerByRate(struct adapter *padapter)
342{
343	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
344	u8 rfPath, rate;
345
346	for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath)
347		for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
348			pHalData->TxPwrByRateOffset[rfPath][rate] = 0;
349}
350
351void PHY_StoreTxPowerByRate(
352	struct adapter *padapter,
353	u32	RfPath,
354	u32	RegAddr,
355	u32	BitMask,
356	u32	Data
357)
358{
359	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
360	struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
361
362	if (pDM_Odm->PhyRegPgVersion > 0)
363		PHY_StoreTxPowerByRateNew(padapter, RfPath, RegAddr, BitMask, Data);
364	else if (pDM_Odm->PhyRegPgVersion == 0) {
365		PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data);
366	}
367}
368
369static void
370phy_ConvertTxPowerByRateInDbmToRelativeValues(
371struct adapter *padapter
372	)
373{
374	u8	base = 0, i = 0, value = 0, path = 0;
375	u8	cckRates[4] = {
376		MGN_1M, MGN_2M, MGN_5_5M, MGN_11M
377	};
378	u8	ofdmRates[8] = {
379		MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M
380	};
381	u8 mcs0_7Rates[8] = {
382		MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7
383	};
384	for (path = RF_PATH_A; path < RF_PATH_MAX; ++path) {
385		/*  CCK */
386		base = PHY_GetTxPowerByRate(padapter, path, MGN_11M);
387		for (i = 0; i < ARRAY_SIZE(cckRates); ++i) {
388			value = PHY_GetTxPowerByRate(padapter, path, cckRates[i]);
389			PHY_SetTxPowerByRate(padapter, path, cckRates[i], value - base);
390		}
391
392		/*  OFDM */
393		base = PHY_GetTxPowerByRate(padapter, path, MGN_54M);
394		for (i = 0; i < sizeof(ofdmRates); ++i) {
395			value = PHY_GetTxPowerByRate(padapter, path, ofdmRates[i]);
396			PHY_SetTxPowerByRate(padapter, path, ofdmRates[i], value - base);
397		}
398
399		/*  HT MCS0~7 */
400		base = PHY_GetTxPowerByRate(padapter, path, MGN_MCS7);
401		for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
402			value = PHY_GetTxPowerByRate(padapter, path, mcs0_7Rates[i]);
403			PHY_SetTxPowerByRate(padapter, path, mcs0_7Rates[i], value - base);
404		}
405	}
406}
407
408/*
409  * This function must be called if the value in the PHY_REG_PG.txt(or header)
410  * is exact dBm values
411  */
412void PHY_TxPowerByRateConfiguration(struct adapter *padapter)
413{
414	phy_StoreTxPowerByRateBase(padapter);
415	phy_ConvertTxPowerByRateInDbmToRelativeValues(padapter);
416}
417
418void PHY_SetTxPowerIndexByRateSection(
419	struct adapter *padapter, u8 RFPath, u8 Channel, u8 RateSection
420)
421{
422	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
423
424	if (RateSection == CCK) {
425		u8 cckRates[]   = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
426		PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
427					     pHalData->CurrentChannelBW,
428					     Channel, cckRates,
429					     ARRAY_SIZE(cckRates));
430
431	} else if (RateSection == OFDM) {
432		u8 ofdmRates[]  = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
433		PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
434					       pHalData->CurrentChannelBW,
435					       Channel, ofdmRates,
436					       ARRAY_SIZE(ofdmRates));
437
438	} else if (RateSection == HT_MCS0_MCS7) {
439		u8 htRates1T[]  = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
440		PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
441					       pHalData->CurrentChannelBW,
442					       Channel, htRates1T,
443					       ARRAY_SIZE(htRates1T));
444
445	}
446}
447
448u8 PHY_GetTxPowerIndexBase(
449	struct adapter *padapter,
450	u8 RFPath,
451	u8 Rate,
452	enum channel_width	BandWidth,
453	u8 Channel
454)
455{
456	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
457	u8 txPower = 0;
458	u8 chnlIdx = (Channel-1);
459
460	if (HAL_IsLegalChannel(padapter, Channel) == false)
461		chnlIdx = 0;
462
463	if (IS_CCK_RATE(Rate))
464		txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
465	else if (MGN_6M <= Rate)
466		txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
467
468	/*  OFDM-1T */
469	if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate))
470		txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S];
471
472	if (BandWidth == CHANNEL_WIDTH_20) { /*  BW20-1S, BW20-2S */
473		if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
474			txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S];
475	} else if (BandWidth == CHANNEL_WIDTH_40) { /*  BW40-1S, BW40-2S */
476		if (MGN_MCS0 <= Rate && Rate <= MGN_MCS7)
477			txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
478	}
479
480	return txPower;
481}
482
483s8 PHY_GetTxPowerTrackingOffset(struct adapter *padapter, u8 RFPath, u8 Rate)
484{
485	struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
486	struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
487	s8 offset = 0;
488
489	if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl  == false)
490		return offset;
491
492	if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M))
493		offset = pDM_Odm->Remnant_CCKSwingIdx;
494	else
495		offset = pDM_Odm->Remnant_OFDMSwingIdx[RFPath];
496
497	return offset;
498}
499
500u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate)
501{
502	u8 index = 0;
503	switch (Rate) {
504	case MGN_1M:
505		index = 0;
506		break;
507	case MGN_2M:
508		index = 1;
509		break;
510	case MGN_5_5M:
511		index = 2;
512		break;
513	case MGN_11M:
514		index = 3;
515		break;
516	case MGN_6M:
517		index = 4;
518		break;
519	case MGN_9M:
520		index = 5;
521		break;
522	case MGN_12M:
523		index = 6;
524		break;
525	case MGN_18M:
526		index = 7;
527		break;
528	case MGN_24M:
529		index = 8;
530		break;
531	case MGN_36M:
532		index = 9;
533		break;
534	case MGN_48M:
535		index = 10;
536		break;
537	case MGN_54M:
538		index = 11;
539		break;
540	case MGN_MCS0:
541		index = 12;
542		break;
543	case MGN_MCS1:
544		index = 13;
545		break;
546	case MGN_MCS2:
547		index = 14;
548		break;
549	case MGN_MCS3:
550		index = 15;
551		break;
552	case MGN_MCS4:
553		index = 16;
554		break;
555	case MGN_MCS5:
556		index = 17;
557		break;
558	case MGN_MCS6:
559		index = 18;
560		break;
561	case MGN_MCS7:
562		index = 19;
563		break;
564	default:
565		break;
566	}
567	return index;
568}
569
570s8 PHY_GetTxPowerByRate(struct adapter *padapter, u8 RFPath, u8 Rate)
571{
572	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
573	s8 value = 0;
574	u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
575
576	if ((padapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) ||
577		   padapter->registrypriv.RegEnableTxPowerByRate == 0)
578		return 0;
579
580	if (RFPath >= RF_PATH_MAX)
581		return value;
582
583	if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
584		return value;
585
586	return pHalData->TxPwrByRateOffset[RFPath][rateIndex];
587
588}
589
590void PHY_SetTxPowerByRate(
591	struct adapter *padapter,
592	u8 RFPath,
593	u8 Rate,
594	s8 Value
595)
596{
597	struct hal_com_data	*pHalData = GET_HAL_DATA(padapter);
598	u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
599
600	if (RFPath >= RF_PATH_MAX)
601		return;
602
603	if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
604		return;
605
606	pHalData->TxPwrByRateOffset[RFPath][rateIndex] = Value;
607}
608
609void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path)
610{
611	PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK);
612
613	PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM);
614	PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7);
615}
616
617void PHY_SetTxPowerIndexByRateArray(
618	struct adapter *padapter,
619	u8 RFPath,
620	enum channel_width BandWidth,
621	u8 Channel,
622	u8 *Rates,
623	u8 RateArraySize
624)
625{
626	u32 powerIndex = 0;
627	int	i = 0;
628
629	for (i = 0; i < RateArraySize; ++i) {
630		powerIndex = PHY_GetTxPowerIndex(padapter, RFPath, Rates[i], BandWidth, Channel);
631		PHY_SetTxPowerIndex(padapter, powerIndex, RFPath, Rates[i]);
632	}
633}
634
635static s8 phy_GetWorldWideLimit(s8 *LimitTable)
636{
637	s8	min = LimitTable[0];
638	u8 i = 0;
639
640	for (i = 0; i < MAX_REGULATION_NUM; ++i) {
641		if (LimitTable[i] < min)
642			min = LimitTable[i];
643	}
644
645	return min;
646}
647
648static s8 phy_GetChannelIndexOfTxPowerLimit(u8 Channel)
649{
650	return Channel - 1;
651}
652
653static s16 get_bandwidth_idx(const enum channel_width bandwidth)
654{
655	switch (bandwidth) {
656	case CHANNEL_WIDTH_20:
657		return 0;
658	case CHANNEL_WIDTH_40:
659		return 1;
660	default:
661		return -1;
662	}
663}
664
665static s16 get_rate_sctn_idx(const u8 rate)
666{
667	switch (rate) {
668	case MGN_1M: case MGN_2M: case MGN_5_5M: case MGN_11M:
669		return 0;
670	case MGN_6M: case MGN_9M: case MGN_12M: case MGN_18M:
671	case MGN_24M: case MGN_36M: case MGN_48M: case MGN_54M:
672		return 1;
673	case MGN_MCS0: case MGN_MCS1: case MGN_MCS2: case MGN_MCS3:
674	case MGN_MCS4: case MGN_MCS5: case MGN_MCS6: case MGN_MCS7:
675		return 2;
676	default:
677		return -1;
678	}
679}
680
681s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 reg_pwr_tbl_sel,
682		      enum channel_width bandwidth,
683		      u8 rf_path, u8 data_rate, u8 channel)
684{
685	s16 idx_regulation = -1;
686	s16 idx_bandwidth  = -1;
687	s16 idx_rate_sctn  = -1;
688	s16 idx_channel    = -1;
689	s8 pwr_lmt = MAX_POWER_INDEX;
690	struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
691	s8 limits[10] = {0}; u8 i = 0;
692
693	if (((adapter->registrypriv.RegEnableTxPowerLimit == 2) &&
694	     (hal_data->EEPROMRegulatory != 1)) ||
695	    (adapter->registrypriv.RegEnableTxPowerLimit == 0))
696		return MAX_POWER_INDEX;
697
698	switch (adapter->registrypriv.RegPwrTblSel) {
699	case 1:
700		idx_regulation = TXPWR_LMT_ETSI;
701		break;
702	case 2:
703		idx_regulation = TXPWR_LMT_MKK;
704		break;
705	case 3:
706		idx_regulation = TXPWR_LMT_FCC;
707		break;
708	case 4:
709		idx_regulation = TXPWR_LMT_WW;
710		break;
711	default:
712		idx_regulation = hal_data->Regulation2_4G;
713		break;
714	}
715
716	idx_bandwidth = get_bandwidth_idx(bandwidth);
717	idx_rate_sctn = get_rate_sctn_idx(data_rate);
718
719	/*  workaround for wrong index combination to obtain tx power limit, */
720	/*  OFDM only exists in BW 20M */
721	/*  CCK table will only be given in BW 20M */
722	/*  HT on 80M will reference to HT on 40M */
723	if (idx_rate_sctn == 0 || idx_rate_sctn == 1)
724		idx_bandwidth = 0;
725
726	channel = phy_GetChannelIndexOfTxPowerLimit(channel);
727
728	if (idx_regulation == -1 || idx_bandwidth == -1 ||
729	    idx_rate_sctn == -1 || idx_channel == -1)
730		return MAX_POWER_INDEX;
731
732
733	for (i = 0; i < MAX_REGULATION_NUM; i++)
734		limits[i] = hal_data->TxPwrLimit_2_4G[i]
735						     [idx_bandwidth]
736						     [idx_rate_sctn]
737						     [idx_channel]
738						     [rf_path];
739
740	pwr_lmt = (idx_regulation == TXPWR_LMT_WW) ?
741		phy_GetWorldWideLimit(limits) :
742		hal_data->TxPwrLimit_2_4G[idx_regulation]
743					 [idx_bandwidth]
744					 [idx_rate_sctn]
745					 [idx_channel]
746					 [rf_path];
747
748	return pwr_lmt;
749}
750
751void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter)
752{
753	struct hal_com_data	*pHalData = GET_HAL_DATA(Adapter);
754	u8 BW40PwrBasedBm2_4G = 0x2E;
755	u8 regulation, bw, channel, rateSection;
756	s8 tempValue = 0, tempPwrLmt = 0;
757	u8 rfPath = 0;
758
759	for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
760		for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
761			for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
762				for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
763					tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A];
764
765					for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) {
766						if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
767							if (rateSection == 2) /*  HT 1T */
768								BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, HT_MCS0_MCS7);
769							else if (rateSection == 1) /*  OFDM */
770								BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, OFDM);
771							else if (rateSection == 0) /*  CCK */
772								BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, CCK);
773						} else
774							BW40PwrBasedBm2_4G = Adapter->registrypriv.RegPowerBase * 2;
775
776						if (tempPwrLmt != MAX_POWER_INDEX) {
777							tempValue = tempPwrLmt - BW40PwrBasedBm2_4G;
778							pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
779						}
780					}
781				}
782			}
783		}
784	}
785}
786
787void PHY_InitTxPowerLimit(struct adapter *Adapter)
788{
789	struct hal_com_data	*pHalData = GET_HAL_DATA(Adapter);
790	u8 i, j, k, l, m;
791
792	for (i = 0; i < MAX_REGULATION_NUM; ++i) {
793		for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
794			for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
795				for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
796					for (l = 0; l < MAX_RF_PATH_NUM; ++l)
797						pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
798	}
799}
800
801void PHY_SetTxPowerLimit(
802	struct adapter *Adapter,
803	u8 *Regulation,
804	u8 *Bandwidth,
805	u8 *RateSection,
806	u8 *RfPath,
807	u8 *Channel,
808	u8 *PowerLimit
809)
810{
811	struct hal_com_data	*pHalData = GET_HAL_DATA(Adapter);
812	u8 regulation = 0, bandwidth = 0, rateSection = 0, channel;
813	s8 powerLimit = 0, prevPowerLimit, channelIndex;
814
815	GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel);
816	GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit);
817
818	powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit;
819
820	if (eqNByte(Regulation, (u8 *)("FCC"), 3))
821		regulation = 0;
822	else if (eqNByte(Regulation, (u8 *)("MKK"), 3))
823		regulation = 1;
824	else if (eqNByte(Regulation, (u8 *)("ETSI"), 4))
825		regulation = 2;
826	else if (eqNByte(Regulation, (u8 *)("WW13"), 4))
827		regulation = 3;
828
829	if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
830		rateSection = 0;
831	else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2))
832		rateSection = 1;
833	else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2))
834		rateSection = 2;
835	else
836		return;
837
838	if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
839		bandwidth = 0;
840	else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
841		bandwidth = 1;
842
843	channelIndex = phy_GetChannelIndexOfTxPowerLimit(channel);
844
845	if (channelIndex == -1)
846		return;
847
848	prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A];
849
850	if (powerLimit < prevPowerLimit)
851		pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit;
852}
853
854void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan)
855{
856	struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
857	pHalData->Regulation2_4G = TXPWR_LMT_WW;
858
859	switch (ChannelPlan) {
860	case RT_CHANNEL_DOMAIN_WORLD_NULL:
861		pHalData->Regulation2_4G = TXPWR_LMT_WW;
862		break;
863	case RT_CHANNEL_DOMAIN_ETSI1_NULL:
864		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
865		break;
866	case RT_CHANNEL_DOMAIN_FCC1_NULL:
867		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
868		break;
869	case RT_CHANNEL_DOMAIN_MKK1_NULL:
870		pHalData->Regulation2_4G = TXPWR_LMT_MKK;
871		break;
872	case RT_CHANNEL_DOMAIN_ETSI2_NULL:
873		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
874		break;
875	case RT_CHANNEL_DOMAIN_FCC1_FCC1:
876		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
877		break;
878	case RT_CHANNEL_DOMAIN_WORLD_ETSI1:
879		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
880		break;
881	case RT_CHANNEL_DOMAIN_MKK1_MKK1:
882		pHalData->Regulation2_4G = TXPWR_LMT_MKK;
883		break;
884	case RT_CHANNEL_DOMAIN_WORLD_KCC1:
885		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
886		break;
887	case RT_CHANNEL_DOMAIN_WORLD_FCC2:
888		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
889		break;
890	case RT_CHANNEL_DOMAIN_WORLD_FCC3:
891		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
892		break;
893	case RT_CHANNEL_DOMAIN_WORLD_FCC4:
894		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
895		break;
896	case RT_CHANNEL_DOMAIN_WORLD_FCC5:
897		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
898		break;
899	case RT_CHANNEL_DOMAIN_WORLD_FCC6:
900		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
901		break;
902	case RT_CHANNEL_DOMAIN_FCC1_FCC7:
903		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
904		break;
905	case RT_CHANNEL_DOMAIN_WORLD_ETSI2:
906		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
907		break;
908	case RT_CHANNEL_DOMAIN_WORLD_ETSI3:
909		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
910		break;
911	case RT_CHANNEL_DOMAIN_MKK1_MKK2:
912		pHalData->Regulation2_4G = TXPWR_LMT_MKK;
913		break;
914	case RT_CHANNEL_DOMAIN_MKK1_MKK3:
915		pHalData->Regulation2_4G = TXPWR_LMT_MKK;
916		break;
917	case RT_CHANNEL_DOMAIN_FCC1_NCC1:
918		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
919		break;
920	case RT_CHANNEL_DOMAIN_FCC1_NCC2:
921		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
922		break;
923	case RT_CHANNEL_DOMAIN_GLOBAL_NULL:
924		pHalData->Regulation2_4G = TXPWR_LMT_WW;
925		break;
926	case RT_CHANNEL_DOMAIN_ETSI1_ETSI4:
927		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
928		break;
929	case RT_CHANNEL_DOMAIN_FCC1_FCC2:
930		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
931		break;
932	case RT_CHANNEL_DOMAIN_FCC1_NCC3:
933		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
934		break;
935	case RT_CHANNEL_DOMAIN_WORLD_ETSI5:
936		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
937		break;
938	case RT_CHANNEL_DOMAIN_FCC1_FCC8:
939		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
940		break;
941	case RT_CHANNEL_DOMAIN_WORLD_ETSI6:
942		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
943		break;
944	case RT_CHANNEL_DOMAIN_WORLD_ETSI7:
945		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
946		break;
947	case RT_CHANNEL_DOMAIN_WORLD_ETSI8:
948		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
949		break;
950	case RT_CHANNEL_DOMAIN_WORLD_ETSI9:
951		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
952		break;
953	case RT_CHANNEL_DOMAIN_WORLD_ETSI10:
954		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
955		break;
956	case RT_CHANNEL_DOMAIN_WORLD_ETSI11:
957		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
958		break;
959	case RT_CHANNEL_DOMAIN_FCC1_NCC4:
960		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
961		break;
962	case RT_CHANNEL_DOMAIN_WORLD_ETSI12:
963		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
964		break;
965	case RT_CHANNEL_DOMAIN_FCC1_FCC9:
966		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
967		break;
968	case RT_CHANNEL_DOMAIN_WORLD_ETSI13:
969		pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
970		break;
971	case RT_CHANNEL_DOMAIN_FCC1_FCC10:
972		pHalData->Regulation2_4G = TXPWR_LMT_FCC;
973		break;
974	case RT_CHANNEL_DOMAIN_REALTEK_DEFINE: /* Realtek Reserve */
975		pHalData->Regulation2_4G = TXPWR_LMT_WW;
976		break;
977	default:
978		break;
979	}
980}
~/ Read-only file preview.