FILE
HalPwrSeqCmd.c
File preview with syntax highlighting.
linux-6.19.14/drivers/staging/rtl8723bs/hal/HalPwrSeqCmd.c
1// SPDX-License-Identifier: GPL-2.0 2/****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7/*++ 8Copyright (c) Realtek Semiconductor Corp. All rights reserved. 9 10Module Name: 11 HalPwrSeqCmd.c 12 13Abstract: 14 Implement HW Power sequence configuration CMD handling routine for Realtek devices. 15 16Major Change History: 17 When Who What 18 ---------- --------------- ------------------------------- 19 2011-10-26 Lucas Modify to be compatible with SD4-CE driver. 20 2011-07-07 Roger Create. 21 22--*/ 23#include <drv_types.h> 24#include <HalPwrSeqCmd.h> 25 26 27/* */ 28/* Description: */ 29/* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */ 30/* */ 31/* Assumption: */ 32/* We should follow specific format which was released from HW SD. */ 33/* */ 34/* 2011.07.07, added by Roger. */ 35/* */ 36u8 HalPwrSeqCmdParsing( 37 struct adapter *padapter, 38 u8 CutVersion, 39 u8 FabVersion, 40 u8 InterfaceType, 41 struct wlan_pwr_cfg PwrSeqCmd[] 42) 43{ 44 struct wlan_pwr_cfg PwrCfgCmd; 45 u8 bPollingBit = false; 46 u32 AryIdx = 0; 47 u8 value = 0; 48 u32 offset = 0; 49 u32 pollingCount = 0; /* polling autoload done. */ 50 u32 maxPollingCnt = 5000; 51 52 do { 53 PwrCfgCmd = PwrSeqCmd[AryIdx]; 54 55 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */ 56 if ( 57 (GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) && 58 (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) && 59 (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType) 60 ) { 61 switch (GET_PWR_CFG_CMD(PwrCfgCmd)) { 62 case PWR_CMD_READ: 63 break; 64 65 case PWR_CMD_WRITE: 66 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); 67 68 /* */ 69 /* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */ 70 /* 2011.07.07. */ 71 /* */ 72 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) { 73 /* Read Back SDIO Local value */ 74 value = SdioLocalCmd52Read1Byte(padapter, offset); 75 76 value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); 77 value |= ( 78 GET_PWR_CFG_VALUE(PwrCfgCmd) & 79 GET_PWR_CFG_MASK(PwrCfgCmd) 80 ); 81 82 /* Write Back SDIO Local value */ 83 SdioLocalCmd52Write1Byte(padapter, offset, value); 84 } else { 85 /* Read the value from system register */ 86 value = rtw_read8(padapter, offset); 87 88 value &= (~(GET_PWR_CFG_MASK(PwrCfgCmd))); 89 value |= ( 90 GET_PWR_CFG_VALUE(PwrCfgCmd) 91 &GET_PWR_CFG_MASK(PwrCfgCmd) 92 ); 93 94 /* Write the value back to system register */ 95 rtw_write8(padapter, offset, value); 96 } 97 break; 98 99 case PWR_CMD_POLLING: 100 101 bPollingBit = false; 102 offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); 103 do { 104 if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) 105 value = SdioLocalCmd52Read1Byte(padapter, offset); 106 else 107 value = rtw_read8(padapter, offset); 108 109 value = value&GET_PWR_CFG_MASK(PwrCfgCmd); 110 if ( 111 value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & 112 GET_PWR_CFG_MASK(PwrCfgCmd)) 113 ) 114 bPollingBit = true; 115 else 116 udelay(10); 117 118 if (pollingCount++ > maxPollingCnt) 119 return false; 120 121 } while (!bPollingBit); 122 123 break; 124 125 case PWR_CMD_DELAY: 126 if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) 127 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)); 128 else 129 udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000); 130 break; 131 132 case PWR_CMD_END: 133 /* When this command is parsed, end the process */ 134 return true; 135 136 default: 137 break; 138 } 139 } 140 141 AryIdx++;/* Add Array Index */ 142 } while (1); 143 144 return true; 145}
~/
Read-only file preview.