cedrus_regs.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Cedrus VPU driver
  4 *
  5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
  6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
  7 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
  8 */
  9
 10#ifndef _CEDRUS_REGS_H_
 11#define _CEDRUS_REGS_H_
 12
 13#define SHIFT_AND_MASK_BITS(v, h, l) \
 14	(((unsigned long)(v) << (l)) & GENMASK(h, l))
 15
 16/*
 17 * Common acronyms and contractions used in register descriptions:
 18 * * VLD : Variable-Length Decoder
 19 * * IQ: Inverse Quantization
 20 * * IDCT: Inverse Discrete Cosine Transform
 21 * * MC: Motion Compensation
 22 * * STCD: Start Code Detect
 23 * * SDRT: Scale Down and Rotate
 24 * * WB: Writeback
 25 * * BITS/BS: Bitstream
 26 * * MB: Macroblock
 27 * * CTU: Coding Tree Unit
 28 * * CTB: Coding Tree Block
 29 * * IDX: Index
 30 */
 31
 32#define VE_ENGINE_DEC_MPEG			0x100
 33#define VE_ENGINE_DEC_H264			0x200
 34#define VE_ENGINE_DEC_H265			0x500
 35
 36#define VE_MODE					0x00
 37
 38#define VE_MODE_PIC_WIDTH_IS_4096		BIT(22)
 39#define VE_MODE_PIC_WIDTH_MORE_2048		BIT(21)
 40#define VE_MODE_REC_WR_MODE_2MB			(0x01 << 20)
 41#define VE_MODE_REC_WR_MODE_1MB			(0x00 << 20)
 42#define VE_MODE_DDR_MODE_BW_128			(0x03 << 16)
 43#define VE_MODE_DDR_MODE_BW_256			(0x02 << 16)
 44#define VE_MODE_DISABLED			(0x07 << 0)
 45#define VE_MODE_DEC_H265			(0x04 << 0)
 46#define VE_MODE_DEC_H264			(0x01 << 0)
 47#define VE_MODE_DEC_MPEG			(0x00 << 0)
 48
 49#define VE_BUF_CTRL				0x50
 50
 51#define VE_BUF_CTRL_INTRAPRED_EXT_RAM		(0x02 << 2)
 52#define VE_BUF_CTRL_INTRAPRED_MIXED_RAM		(0x01 << 2)
 53#define VE_BUF_CTRL_INTRAPRED_INT_SRAM		(0x00 << 2)
 54#define VE_BUF_CTRL_DBLK_EXT_RAM		(0x02 << 0)
 55#define VE_BUF_CTRL_DBLK_MIXED_RAM		(0x01 << 0)
 56#define VE_BUF_CTRL_DBLK_INT_SRAM		(0x00 << 0)
 57
 58#define VE_DBLK_DRAM_BUF_ADDR			0x54
 59#define VE_INTRAPRED_DRAM_BUF_ADDR		0x58
 60#define VE_PRIMARY_CHROMA_BUF_LEN		0xc4
 61#define VE_PRIMARY_FB_LINE_STRIDE		0xc8
 62
 63#define VE_PRIMARY_FB_LINE_STRIDE_CHROMA(s)	SHIFT_AND_MASK_BITS(s, 31, 16)
 64#define VE_PRIMARY_FB_LINE_STRIDE_LUMA(s)	SHIFT_AND_MASK_BITS(s, 15, 0)
 65
 66#define VE_CHROMA_BUF_LEN			0xe8
 67
 68#define VE_SECONDARY_OUT_FMT_TILED_32_NV12	(0x00 << 30)
 69#define VE_SECONDARY_OUT_FMT_EXT		(0x01 << 30)
 70#define VE_SECONDARY_OUT_FMT_YU12		(0x02 << 30)
 71#define VE_SECONDARY_OUT_FMT_YV12		(0x03 << 30)
 72#define VE_CHROMA_BUF_LEN_SDRT(l)		SHIFT_AND_MASK_BITS(l, 27, 0)
 73
 74#define VE_PRIMARY_OUT_FMT			0xec
 75
 76#define VE_PRIMARY_OUT_FMT_TILED_32_NV12	(0x00 << 4)
 77#define VE_PRIMARY_OUT_FMT_TILED_128_NV12	(0x01 << 4)
 78#define VE_PRIMARY_OUT_FMT_YU12			(0x02 << 4)
 79#define VE_PRIMARY_OUT_FMT_YV12			(0x03 << 4)
 80#define VE_PRIMARY_OUT_FMT_NV12			(0x04 << 4)
 81#define VE_PRIMARY_OUT_FMT_NV21			(0x05 << 4)
 82#define VE_SECONDARY_OUT_FMT_EXT_TILED_32_NV12	(0x00 << 0)
 83#define VE_SECONDARY_OUT_FMT_EXT_TILED_128_NV12	(0x01 << 0)
 84#define VE_SECONDARY_OUT_FMT_EXT_YU12		(0x02 << 0)
 85#define VE_SECONDARY_OUT_FMT_EXT_YV12		(0x03 << 0)
 86#define VE_SECONDARY_OUT_FMT_EXT_NV12		(0x04 << 0)
 87#define VE_SECONDARY_OUT_FMT_EXT_NV21		(0x05 << 0)
 88
 89#define VE_VERSION				0xf0
 90
 91#define VE_VERSION_SHIFT			16
 92
 93#define VE_DEC_MPEG_MP12HDR			(VE_ENGINE_DEC_MPEG + 0x00)
 94
 95#define VE_DEC_MPEG_MP12HDR_SLICE_TYPE(t)	SHIFT_AND_MASK_BITS(t, 30, 28)
 96#define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y)	(24 - 4 * (y) - 8 * (x))
 97#define VE_DEC_MPEG_MP12HDR_F_CODE(__x, __y, __v) \
 98	(((unsigned long)(__v) & GENMASK(3, 0)) << VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(__x, __y))
 99
100#define VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION(p) \
101	SHIFT_AND_MASK_BITS(p, 11, 10)
102#define VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE(s) \
103	SHIFT_AND_MASK_BITS(s, 9, 8)
104#define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \
105	((v) ? BIT(7) : 0)
106#define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \
107	((v) ? BIT(6) : 0)
108#define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \
109	((v) ? BIT(5) : 0)
110#define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \
111	((v) ? BIT(4) : 0)
112#define VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT(v) \
113	((v) ? BIT(3) : 0)
114#define VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN(v) \
115	((v) ? BIT(2) : 0)
116#define VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR(v) \
117	((v) ? BIT(1) : 0)
118#define VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR(v) \
119	((v) ? BIT(0) : 0)
120
121#define VE_DEC_MPEG_PICCODEDSIZE		(VE_ENGINE_DEC_MPEG + 0x08)
122
123#define VE_DEC_MPEG_PICCODEDSIZE_WIDTH(w) \
124	SHIFT_AND_MASK_BITS(DIV_ROUND_UP(w, 16), 15, 8)
125#define VE_DEC_MPEG_PICCODEDSIZE_HEIGHT(h) \
126	SHIFT_AND_MASK_BITS(DIV_ROUND_UP(h, 16), 7, 0)
127
128#define VE_DEC_MPEG_PICBOUNDSIZE		(VE_ENGINE_DEC_MPEG + 0x0c)
129
130#define VE_DEC_MPEG_PICBOUNDSIZE_WIDTH(w)	SHIFT_AND_MASK_BITS(w, 27, 16)
131#define VE_DEC_MPEG_PICBOUNDSIZE_HEIGHT(h)	SHIFT_AND_MASK_BITS(h, 11, 0)
132
133#define VE_DEC_MPEG_MBADDR			(VE_ENGINE_DEC_MPEG + 0x10)
134
135#define VE_DEC_MPEG_MBADDR_X(w)			SHIFT_AND_MASK_BITS(w, 15, 8)
136#define VE_DEC_MPEG_MBADDR_Y(h)			SHIFT_AND_MASK_BITS(h, 7, 0)
137
138#define VE_DEC_MPEG_CTRL			(VE_ENGINE_DEC_MPEG + 0x14)
139
140#define VE_DEC_MPEG_CTRL_MC_CACHE_EN		BIT(31)
141#define VE_DEC_MPEG_CTRL_SW_VLD			BIT(27)
142#define VE_DEC_MPEG_CTRL_SW_IQ_IS		BIT(17)
143#define VE_DEC_MPEG_CTRL_QP_AC_DC_OUT_EN	BIT(14)
144#define VE_DEC_MPEG_CTRL_ROTATE_SCALE_OUT_EN	BIT(8)
145#define VE_DEC_MPEG_CTRL_MC_NO_WRITEBACK	BIT(7)
146#define VE_DEC_MPEG_CTRL_ROTATE_IRQ_EN		BIT(6)
147#define VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN	BIT(5)
148#define VE_DEC_MPEG_CTRL_ERROR_IRQ_EN		BIT(4)
149#define VE_DEC_MPEG_CTRL_FINISH_IRQ_EN		BIT(3)
150#define VE_DEC_MPEG_CTRL_IRQ_MASK \
151	(VE_DEC_MPEG_CTRL_FINISH_IRQ_EN | VE_DEC_MPEG_CTRL_ERROR_IRQ_EN | \
152	 VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN)
153
154#define VE_DEC_MPEG_TRIGGER			(VE_ENGINE_DEC_MPEG + 0x18)
155
156#define VE_DEC_MPEG_TRIGGER_MB_BOUNDARY		BIT(31)
157
158#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_420	(0x00 << 27)
159#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_411	(0x01 << 27)
160#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422	(0x02 << 27)
161#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_444	(0x03 << 27)
162#define VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422T	(0x04 << 27)
163
164#define VE_DEC_MPEG_TRIGGER_MPEG1		(0x01 << 24)
165#define VE_DEC_MPEG_TRIGGER_MPEG2		(0x02 << 24)
166#define VE_DEC_MPEG_TRIGGER_JPEG		(0x03 << 24)
167#define VE_DEC_MPEG_TRIGGER_MPEG4		(0x04 << 24)
168#define VE_DEC_MPEG_TRIGGER_VP62		(0x05 << 24)
169
170#define VE_DEC_MPEG_TRIGGER_VP62_AC_GET_BITS	BIT(7)
171
172#define VE_DEC_MPEG_TRIGGER_STCD_VC1		(0x02 << 4)
173#define VE_DEC_MPEG_TRIGGER_STCD_MPEG2		(0x01 << 4)
174#define VE_DEC_MPEG_TRIGGER_STCD_AVC		(0x00 << 4)
175
176#define VE_DEC_MPEG_TRIGGER_HW_MPEG_VLD		(0x0f << 0)
177#define VE_DEC_MPEG_TRIGGER_HW_JPEG_VLD		(0x0e << 0)
178#define VE_DEC_MPEG_TRIGGER_HW_MB		(0x0d << 0)
179#define VE_DEC_MPEG_TRIGGER_HW_ROTATE		(0x0c << 0)
180#define VE_DEC_MPEG_TRIGGER_HW_VP6_VLD		(0x0b << 0)
181#define VE_DEC_MPEG_TRIGGER_HW_MAF		(0x0a << 0)
182#define VE_DEC_MPEG_TRIGGER_HW_STCD_END		(0x09 << 0)
183#define VE_DEC_MPEG_TRIGGER_HW_STCD_BEGIN	(0x08 << 0)
184#define VE_DEC_MPEG_TRIGGER_SW_MC		(0x07 << 0)
185#define VE_DEC_MPEG_TRIGGER_SW_IQ		(0x06 << 0)
186#define VE_DEC_MPEG_TRIGGER_SW_IDCT		(0x05 << 0)
187#define VE_DEC_MPEG_TRIGGER_SW_SCALE		(0x04 << 0)
188#define VE_DEC_MPEG_TRIGGER_SW_VP6		(0x03 << 0)
189#define VE_DEC_MPEG_TRIGGER_SW_VP62_AC_GET_BITS	(0x02 << 0)
190
191#define VE_DEC_MPEG_STATUS			(VE_ENGINE_DEC_MPEG + 0x1c)
192
193#define VE_DEC_MPEG_STATUS_START_DETECT_BUSY	BIT(27)
194#define VE_DEC_MPEG_STATUS_VP6_BIT		BIT(26)
195#define VE_DEC_MPEG_STATUS_VP6_BIT_BUSY		BIT(25)
196#define VE_DEC_MPEG_STATUS_MAF_BUSY		BIT(23)
197#define VE_DEC_MPEG_STATUS_VP6_MVP_BUSY		BIT(22)
198#define VE_DEC_MPEG_STATUS_JPEG_BIT_END		BIT(21)
199#define VE_DEC_MPEG_STATUS_JPEG_RESTART_ERROR	BIT(20)
200#define VE_DEC_MPEG_STATUS_JPEG_MARKER		BIT(19)
201#define VE_DEC_MPEG_STATUS_ROTATE_BUSY		BIT(18)
202#define VE_DEC_MPEG_STATUS_DEBLOCKING_BUSY	BIT(17)
203#define VE_DEC_MPEG_STATUS_SCALE_DOWN_BUSY	BIT(16)
204#define VE_DEC_MPEG_STATUS_IQIS_BUF_EMPTY	BIT(15)
205#define VE_DEC_MPEG_STATUS_IDCT_BUF_EMPTY	BIT(14)
206#define VE_DEC_MPEG_STATUS_VE_BUSY		BIT(13)
207#define VE_DEC_MPEG_STATUS_MC_BUSY		BIT(12)
208#define VE_DEC_MPEG_STATUS_IDCT_BUSY		BIT(11)
209#define VE_DEC_MPEG_STATUS_IQIS_BUSY		BIT(10)
210#define VE_DEC_MPEG_STATUS_DCAC_BUSY		BIT(9)
211#define VE_DEC_MPEG_STATUS_VLD_BUSY		BIT(8)
212#define VE_DEC_MPEG_STATUS_ROTATE_SUCCESS	BIT(3)
213#define VE_DEC_MPEG_STATUS_VLD_DATA_REQ		BIT(2)
214#define VE_DEC_MPEG_STATUS_ERROR		BIT(1)
215#define VE_DEC_MPEG_STATUS_SUCCESS		BIT(0)
216#define VE_DEC_MPEG_STATUS_CHECK_MASK \
217	(VE_DEC_MPEG_STATUS_SUCCESS | VE_DEC_MPEG_STATUS_ERROR | \
218	 VE_DEC_MPEG_STATUS_VLD_DATA_REQ)
219#define VE_DEC_MPEG_STATUS_CHECK_ERROR \
220	(VE_DEC_MPEG_STATUS_ERROR | VE_DEC_MPEG_STATUS_VLD_DATA_REQ)
221
222#define VE_DEC_MPEG_VLD_ADDR			(VE_ENGINE_DEC_MPEG + 0x28)
223
224#define VE_DEC_MPEG_VLD_ADDR_FIRST_PIC_DATA	BIT(30)
225#define VE_DEC_MPEG_VLD_ADDR_LAST_PIC_DATA	BIT(29)
226#define VE_DEC_MPEG_VLD_ADDR_VALID_PIC_DATA	BIT(28)
227#define VE_DEC_MPEG_VLD_ADDR_BASE(a)					\
228	({								\
229		u32 _tmp = (a);						\
230		u32 _lo = _tmp & GENMASK(27, 4);			\
231		u32 _hi = (_tmp >> 28) & GENMASK(3, 0);			\
232		(_lo | _hi);						\
233	})
234
235#define VE_DEC_MPEG_VLD_OFFSET			(VE_ENGINE_DEC_MPEG + 0x2c)
236#define VE_DEC_MPEG_VLD_LEN			(VE_ENGINE_DEC_MPEG + 0x30)
237#define VE_DEC_MPEG_VLD_END_ADDR		(VE_ENGINE_DEC_MPEG + 0x34)
238
239#define VE_DEC_MPEG_REC_LUMA			(VE_ENGINE_DEC_MPEG + 0x48)
240#define VE_DEC_MPEG_REC_CHROMA			(VE_ENGINE_DEC_MPEG + 0x4c)
241#define VE_DEC_MPEG_FWD_REF_LUMA_ADDR		(VE_ENGINE_DEC_MPEG + 0x50)
242#define VE_DEC_MPEG_FWD_REF_CHROMA_ADDR		(VE_ENGINE_DEC_MPEG + 0x54)
243#define VE_DEC_MPEG_BWD_REF_LUMA_ADDR		(VE_ENGINE_DEC_MPEG + 0x58)
244#define VE_DEC_MPEG_BWD_REF_CHROMA_ADDR		(VE_ENGINE_DEC_MPEG + 0x5c)
245
246#define VE_DEC_MPEG_IQMINPUT			(VE_ENGINE_DEC_MPEG + 0x80)
247
248#define VE_DEC_MPEG_IQMINPUT_FLAG_INTRA		(0x01 << 14)
249#define VE_DEC_MPEG_IQMINPUT_FLAG_NON_INTRA	(0x00 << 14)
250#define VE_DEC_MPEG_IQMINPUT_WEIGHT(i, v) \
251	(SHIFT_AND_MASK_BITS(i, 13, 8) | SHIFT_AND_MASK_BITS(v, 7, 0))
252
253#define VE_DEC_MPEG_ERROR			(VE_ENGINE_DEC_MPEG + 0xc4)
254#define VE_DEC_MPEG_CRTMBADDR			(VE_ENGINE_DEC_MPEG + 0xc8)
255#define VE_DEC_MPEG_ROT_LUMA			(VE_ENGINE_DEC_MPEG + 0xcc)
256#define VE_DEC_MPEG_ROT_CHROMA			(VE_ENGINE_DEC_MPEG + 0xd0)
257
258#define VE_DEC_H265_DEC_NAL_HDR			(VE_ENGINE_DEC_H265 + 0x00)
259
260#define VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \
261	SHIFT_AND_MASK_BITS(v, 8, 6)
262#define VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \
263	SHIFT_AND_MASK_BITS(v, 5, 0)
264
265#define VE_DEC_H265_FLAG(reg_flag, ctrl_flag, flags) \
266	(((flags) & (ctrl_flag)) ? reg_flag : 0)
267
268#define VE_DEC_H265_DEC_SPS_HDR			(VE_ENGINE_DEC_H265 + 0x04)
269
270#define VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE	BIT(26)
271#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED		BIT(25)
272#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED	BIT(24)
273#define VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED			BIT(23)
274#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE		BIT(2)
275
276#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \
277	SHIFT_AND_MASK_BITS(v, 22, 20)
278#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \
279	SHIFT_AND_MASK_BITS(v, 19, 17)
280#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \
281	SHIFT_AND_MASK_BITS(v, 16, 15)
282#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \
283	SHIFT_AND_MASK_BITS(v, 14, 13)
284#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \
285	SHIFT_AND_MASK_BITS(v, 12, 11)
286#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
287	SHIFT_AND_MASK_BITS(v, 10, 9)
288#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \
289	SHIFT_AND_MASK_BITS(v, 8, 6)
290#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \
291	SHIFT_AND_MASK_BITS(v, 5, 3)
292#define VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \
293	SHIFT_AND_MASK_BITS(v, 1, 0)
294
295#define VE_DEC_H265_DEC_PIC_SIZE		(VE_ENGINE_DEC_H265 + 0x08)
296
297#define VE_DEC_H265_DEC_PIC_SIZE_WIDTH(w)	(((w) << 0) & GENMASK(13, 0))
298#define VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(h)	(((h) << 16) & GENMASK(29, 16))
299
300#define VE_DEC_H265_DEC_PCM_CTRL		(VE_ENGINE_DEC_H265 + 0x0c)
301
302#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED		BIT(15)
303#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED	BIT(14)
304
305#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \
306	SHIFT_AND_MASK_BITS(v, 11, 10)
307#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
308	SHIFT_AND_MASK_BITS(v, 9, 8)
309#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \
310	SHIFT_AND_MASK_BITS(v, 7, 4)
311#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \
312	SHIFT_AND_MASK_BITS(v, 3, 0)
313
314#define VE_DEC_H265_DEC_PPS_CTRL0		(VE_ENGINE_DEC_H265 + 0x10)
315
316#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED	BIT(3)
317#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED	BIT(2)
318#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED	BIT(1)
319#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED	BIT(0)
320
321#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \
322	SHIFT_AND_MASK_BITS(v, 29, 24)
323#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \
324	SHIFT_AND_MASK_BITS(v, 21, 16)
325#define VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \
326	SHIFT_AND_MASK_BITS(v, 14, 8)
327#define VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \
328	SHIFT_AND_MASK_BITS(v, 5, 4)
329
330#define VE_DEC_H265_DEC_PPS_CTRL1		(VE_ENGINE_DEC_H265 + 0x14)
331
332#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(6)
333#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED	BIT(5)
334#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED	BIT(4)
335#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED			BIT(3)
336#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED	BIT(2)
337#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED			BIT(1)
338#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED			BIT(0)
339
340#define VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \
341	SHIFT_AND_MASK_BITS(v, 10, 8)
342
343#define VE_DEC_H265_SCALING_LIST_CTRL0		(VE_ENGINE_DEC_H265 + 0x18)
344
345#define VE_DEC_H265_SCALING_LIST_CTRL0_FLAG_ENABLED			BIT(31)
346
347#define VE_DEC_H265_SCALING_LIST_CTRL0_SRAM	(0 << 30)
348#define VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT	(1 << 30)
349
350#define VE_DEC_H265_DEC_SLICE_HDR_INFO0		(VE_ENGINE_DEC_H265 + 0x20)
351
352#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0		BIT(11)
353#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT			BIT(10)
354#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO		BIT(9)
355#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA		BIT(8)
356#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA		BIT(7)
357#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE	BIT(6)
358#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT	BIT(1)
359#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC	BIT(0)
360
361#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \
362	SHIFT_AND_MASK_BITS(v, 29, 28)
363#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \
364	SHIFT_AND_MASK_BITS(v, 26, 24)
365#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \
366	SHIFT_AND_MASK_BITS(v, 23, 20)
367#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \
368	SHIFT_AND_MASK_BITS(v, 19, 16)
369#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \
370	SHIFT_AND_MASK_BITS(v, 15, 12)
371#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \
372	SHIFT_AND_MASK_BITS(v, 5, 4)
373#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \
374	SHIFT_AND_MASK_BITS(v, 3, 2)
375
376#define VE_DEC_H265_DEC_SLICE_HDR_INFO1		(VE_ENGINE_DEC_H265 + 0x24)
377
378#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED BIT(23)
379#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(22)
380#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_NOT_LOW_DELAY BIT(21)
381
382#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \
383	SHIFT_AND_MASK_BITS(v, 31, 28)
384#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \
385	SHIFT_AND_MASK_BITS(v, 27, 24)
386#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \
387	SHIFT_AND_MASK_BITS(v, 20, 16)
388#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \
389	SHIFT_AND_MASK_BITS(v, 12, 8)
390#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \
391	SHIFT_AND_MASK_BITS(v, 6, 0)
392
393#define VE_DEC_H265_DEC_SLICE_HDR_INFO2		(VE_ENGINE_DEC_H265 + 0x28)
394
395#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \
396	SHIFT_AND_MASK_BITS(v, 21, 8)
397#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \
398	SHIFT_AND_MASK_BITS(v, 6, 4)
399#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \
400	SHIFT_AND_MASK_BITS(v, 2, 0)
401
402#define VE_DEC_H265_DEC_CTB_ADDR		(VE_ENGINE_DEC_H265 + 0x2c)
403
404#define VE_DEC_H265_DEC_CTB_ADDR_Y(y)		SHIFT_AND_MASK_BITS(y, 25, 16)
405#define VE_DEC_H265_DEC_CTB_ADDR_X(x)		SHIFT_AND_MASK_BITS(x, 9, 0)
406
407#define VE_DEC_H265_CTRL			(VE_ENGINE_DEC_H265 + 0x30)
408
409#define VE_DEC_H265_CTRL_DDR_CONSISTENCY_EN	BIT(31)
410#define VE_DEC_H265_CTRL_STCD_EN		BIT(25)
411#define VE_DEC_H265_CTRL_EPTB_DEC_BYPASS_EN	BIT(24)
412#define VE_DEC_H265_CTRL_TQ_BYPASS_EN		BIT(12)
413#define VE_DEC_H265_CTRL_VLD_BYPASS_EN		BIT(11)
414#define VE_DEC_H265_CTRL_NCRI_CACHE_DISABLE	BIT(10)
415#define VE_DEC_H265_CTRL_ROTATE_SCALE_OUT_EN	BIT(9)
416#define VE_DEC_H265_CTRL_MC_NO_WRITEBACK	BIT(8)
417#define VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN	BIT(2)
418#define VE_DEC_H265_CTRL_ERROR_IRQ_EN		BIT(1)
419#define VE_DEC_H265_CTRL_FINISH_IRQ_EN		BIT(0)
420#define VE_DEC_H265_CTRL_IRQ_MASK \
421	(VE_DEC_H265_CTRL_FINISH_IRQ_EN | VE_DEC_H265_CTRL_ERROR_IRQ_EN | \
422	 VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN)
423
424#define VE_DEC_H265_TRIGGER			(VE_ENGINE_DEC_H265 + 0x34)
425
426#define VE_DEC_H265_TRIGGER_TYPE_N_BITS(x)	(((x) & 0x3f) << 8)
427#define VE_DEC_H265_TRIGGER_STCD_VC1		(0x02 << 4)
428#define VE_DEC_H265_TRIGGER_STCD_AVS		(0x01 << 4)
429#define VE_DEC_H265_TRIGGER_STCD_HEVC		(0x00 << 4)
430#define VE_DEC_H265_TRIGGER_DEC_SLICE		(0x08 << 0)
431#define VE_DEC_H265_TRIGGER_INIT_SWDEC		(0x07 << 0)
432#define VE_DEC_H265_TRIGGER_BYTE_ALIGN		(0x06 << 0)
433#define VE_DEC_H265_TRIGGER_GET_VLCUE		(0x05 << 0)
434#define VE_DEC_H265_TRIGGER_GET_VLCSE		(0x04 << 0)
435#define VE_DEC_H265_TRIGGER_FLUSH_BITS		(0x03 << 0)
436#define VE_DEC_H265_TRIGGER_GET_BITS		(0x02 << 0)
437#define VE_DEC_H265_TRIGGER_SHOW_BITS		(0x01 << 0)
438
439#define VE_DEC_H265_STATUS			(VE_ENGINE_DEC_H265 + 0x38)
440
441#define VE_DEC_H265_STATUS_STCD			BIT(24)
442#define VE_DEC_H265_STATUS_STCD_BUSY		BIT(21)
443#define VE_DEC_H265_STATUS_WB_BUSY		BIT(20)
444#define VE_DEC_H265_STATUS_BS_DMA_BUSY		BIT(19)
445#define VE_DEC_H265_STATUS_IT_BUSY		BIT(18)
446#define VE_DEC_H265_STATUS_INTER_BUSY		BIT(17)
447#define VE_DEC_H265_STATUS_MORE_DATA		BIT(16)
448#define VE_DEC_H265_STATUS_DBLK_BUSY		BIT(15)
449#define VE_DEC_H265_STATUS_IREC_BUSY		BIT(14)
450#define VE_DEC_H265_STATUS_INTRA_BUSY		BIT(13)
451#define VE_DEC_H265_STATUS_MCRI_BUSY		BIT(12)
452#define VE_DEC_H265_STATUS_IQIT_BUSY		BIT(11)
453#define VE_DEC_H265_STATUS_MVP_BUSY		BIT(10)
454#define VE_DEC_H265_STATUS_IS_BUSY		BIT(9)
455#define VE_DEC_H265_STATUS_VLD_BUSY		BIT(8)
456#define VE_DEC_H265_STATUS_OVER_TIME		BIT(3)
457#define VE_DEC_H265_STATUS_VLD_DATA_REQ		BIT(2)
458#define VE_DEC_H265_STATUS_ERROR		BIT(1)
459#define VE_DEC_H265_STATUS_SUCCESS		BIT(0)
460#define VE_DEC_H265_STATUS_STCD_TYPE_MASK	GENMASK(23, 22)
461#define VE_DEC_H265_STATUS_CHECK_MASK \
462	(VE_DEC_H265_STATUS_SUCCESS | VE_DEC_H265_STATUS_ERROR | \
463	 VE_DEC_H265_STATUS_VLD_DATA_REQ)
464#define VE_DEC_H265_STATUS_CHECK_ERROR \
465	(VE_DEC_H265_STATUS_ERROR | VE_DEC_H265_STATUS_VLD_DATA_REQ)
466
467#define VE_DEC_H265_DEC_CTB_NUM			(VE_ENGINE_DEC_H265 + 0x3c)
468
469#define VE_DEC_H265_BITS_ADDR			(VE_ENGINE_DEC_H265 + 0x40)
470
471#define VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA	BIT(30)
472#define VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA	BIT(29)
473#define VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA	BIT(28)
474#define VE_DEC_H265_BITS_ADDR_BASE(a)		(((a) >> 8) & GENMASK(27, 0))
475
476#define VE_DEC_H265_BITS_OFFSET			(VE_ENGINE_DEC_H265 + 0x44)
477#define VE_DEC_H265_BITS_LEN			(VE_ENGINE_DEC_H265 + 0x48)
478
479#define VE_DEC_H265_BITS_END_ADDR		(VE_ENGINE_DEC_H265 + 0x4c)
480
481#define VE_DEC_H265_BITS_END_ADDR_BASE(a)	((a) >> 8)
482
483#define VE_DEC_H265_SDRT_CTRL			(VE_ENGINE_DEC_H265 + 0x50)
484#define VE_DEC_H265_SDRT_LUMA_ADDR		(VE_ENGINE_DEC_H265 + 0x54)
485#define VE_DEC_H265_SDRT_CHROMA_ADDR		(VE_ENGINE_DEC_H265 + 0x58)
486
487#define VE_DEC_H265_OUTPUT_FRAME_IDX		(VE_ENGINE_DEC_H265 + 0x5c)
488
489#define VE_DEC_H265_NEIGHBOR_INFO_ADDR		(VE_ENGINE_DEC_H265 + 0x60)
490
491#define VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(a)	((a) >> 8)
492
493#define VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR	(VE_ENGINE_DEC_H265 + 0x64)
494#define VE_DEC_H265_TILE_START_CTB		(VE_ENGINE_DEC_H265 + 0x68)
495#define VE_DEC_H265_TILE_END_CTB		(VE_ENGINE_DEC_H265 + 0x6c)
496#define VE_DEC_H265_SCALING_LIST_DC_COEF0	(VE_ENGINE_DEC_H265 + 0x78)
497#define VE_DEC_H265_SCALING_LIST_DC_COEF1	(VE_ENGINE_DEC_H265 + 0x7c)
498
499#define VE_DEC_H265_LOW_ADDR			(VE_ENGINE_DEC_H265 + 0x80)
500
501#define VE_DEC_H265_OFFSET_ADDR_FIRST_OUT	(VE_ENGINE_DEC_H265 + 0x84)
502#define VE_DEC_H265_OFFSET_ADDR_SECOND_OUT	(VE_ENGINE_DEC_H265 + 0x88)
503
504#define VE_DEC_H265_SECOND_OUT_FMT_8BIT_PLUS_2BIT	0
505#define VE_DEC_H265_SECOND_OUT_FMT_P010			1
506#define VE_DEC_H265_SECOND_OUT_FMT_10BIT_4x4_TILED	2
507
508#define VE_DEC_H265_10BIT_CONFIGURE_SECOND_OUT_FMT(v) \
509	SHIFT_AND_MASK_BITS(v, 24, 23)
510#define VE_DEC_H265_10BIT_CONFIGURE_SECOND_2BIT_ENABLE	BIT(22)
511#define VE_DEC_H265_10BIT_CONFIGURE_SECOND_2BIT_STRIDE(v) \
512	SHIFT_AND_MASK_BITS(v, 21, 11)
513#define VE_DEC_H265_10BIT_CONFIGURE_FIRST_2BIT_STRIDE(v) \
514	SHIFT_AND_MASK_BITS(v, 10, 0)
515#define VE_DEC_H265_10BIT_CONFIGURE		(VE_ENGINE_DEC_H265 + 0x8c)
516
517#define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \
518	SHIFT_AND_MASK_BITS(a, 31, 24)
519#define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \
520	SHIFT_AND_MASK_BITS(a, 23, 16)
521#define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \
522	SHIFT_AND_MASK_BITS(a, 7, 0)
523
524#define VE_DEC_H265_BITS_READ			(VE_ENGINE_DEC_H265 + 0xdc)
525
526#define VE_DEC_H265_SRAM_OFFSET			(VE_ENGINE_DEC_H265 + 0xe0)
527
528#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0	0x00
529#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0	0x20
530#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1	0x60
531#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1	0x80
532#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO		0x400
533#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT		0x20
534#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS		0x800
535#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0		0xc00
536#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1		0xc10
537
538#define VE_DEC_H265_SRAM_DATA			(VE_ENGINE_DEC_H265 + 0xe4)
539
540#define VE_DEC_H265_SRAM_DATA_ADDR_BASE(a)	((a) >> 8)
541#define VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF	BIT(7)
542
543#define VE_H264_SPS			0x200
544#define VE_H264_SPS_MBS_ONLY			BIT(18)
545#define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD	BIT(17)
546#define VE_H264_SPS_DIRECT_8X8_INFERENCE	BIT(16)
547
548#define VE_H264_PPS			0x204
549#define VE_H264_PPS_ENTROPY_CODING_MODE		BIT(15)
550#define VE_H264_PPS_WEIGHTED_PRED		BIT(4)
551#define VE_H264_PPS_CONSTRAINED_INTRA_PRED	BIT(1)
552#define VE_H264_PPS_TRANSFORM_8X8_MODE		BIT(0)
553
554#define VE_H264_SHS			0x208
555#define VE_H264_SHS_FIRST_SLICE_IN_PIC		BIT(5)
556#define VE_H264_SHS_FIELD_PIC			BIT(4)
557#define VE_H264_SHS_BOTTOM_FIELD		BIT(3)
558#define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED	BIT(2)
559
560#define VE_H264_SHS2			0x20c
561#define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD	BIT(12)
562
563#define VE_H264_SHS_WP			0x210
564
565#define VE_H264_SHS_QP			0x21c
566#define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT	BIT(24)
567
568#define VE_H264_CTRL			0x220
569#define VE_H264_CTRL_VP8			BIT(29)
570#define VE_H264_CTRL_VLD_DATA_REQ_INT		BIT(2)
571#define VE_H264_CTRL_DECODE_ERR_INT		BIT(1)
572#define VE_H264_CTRL_SLICE_DECODE_INT		BIT(0)
573
574#define VE_H264_CTRL_INT_MASK		(VE_H264_CTRL_VLD_DATA_REQ_INT | \
575					 VE_H264_CTRL_DECODE_ERR_INT | \
576					 VE_H264_CTRL_SLICE_DECODE_INT)
577
578#define VE_H264_TRIGGER_TYPE		0x224
579#define VE_H264_TRIGGER_TYPE_PROBABILITY(x)	SHIFT_AND_MASK_BITS(x, 31, 24)
580#define VE_H264_TRIGGER_TYPE_BIN_LENS(x)	SHIFT_AND_MASK_BITS((x) - 1, 18, 16)
581#define VE_H264_TRIGGER_TYPE_N_BITS(x)		(((x) & 0x3f) << 8)
582#define VE_H264_TRIGGER_TYPE_VP8_GET_BITS	(15 << 0)
583#define VE_H264_TRIGGER_TYPE_VP8_UPDATE_COEF	(14 << 0)
584#define VE_H264_TRIGGER_TYPE_VP8_SLICE_DECODE	(10 << 0)
585#define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE	(8 << 0)
586#define VE_H264_TRIGGER_TYPE_INIT_SWDEC		(7 << 0)
587#define VE_H264_TRIGGER_TYPE_FLUSH_BITS		(3 << 0)
588
589#define VE_H264_STATUS			0x228
590#define VE_H264_STATUS_VLD_DATA_REQ_INT		VE_H264_CTRL_VLD_DATA_REQ_INT
591#define VE_H264_STATUS_DECODE_ERR_INT		VE_H264_CTRL_DECODE_ERR_INT
592#define VE_H264_STATUS_SLICE_DECODE_INT		VE_H264_CTRL_SLICE_DECODE_INT
593#define VE_H264_STATUS_VLD_BUSY			BIT(8)
594#define VE_H264_STATUS_VP8_UPPROB_BUSY		BIT(17)
595
596#define VE_H264_STATUS_INT_MASK			VE_H264_CTRL_INT_MASK
597
598#define VE_H264_CUR_MB_NUM		0x22c
599
600#define VE_H264_VLD_ADDR		0x230
601#define VE_H264_VLD_ADDR_FIRST			BIT(30)
602#define VE_H264_VLD_ADDR_LAST			BIT(29)
603#define VE_H264_VLD_ADDR_VALID			BIT(28)
604#define VE_H264_VLD_ADDR_VAL(x)			(((x) & 0x0ffffff0) | ((x) >> 28))
605
606#define VE_H264_VLD_OFFSET		0x234
607#define VE_H264_VLD_LEN			0x238
608#define VE_H264_VLD_END			0x23c
609#define VE_H264_SDROT_CTRL		0x240
610#define VE_H264_OUTPUT_FRAME_IDX	0x24c
611#define VE_H264_EXTRA_BUFFER1		0x250
612#define VE_H264_EXTRA_BUFFER2		0x254
613#define VE_H264_MB_ADDR			0x260
614#define VE_H264_ERROR_CASE		0x2b8
615#define VE_H264_BASIC_BITS		0x2dc
616#define VE_AVC_SRAM_PORT_OFFSET		0x2e0
617#define VE_AVC_SRAM_PORT_DATA		0x2e4
618
619#define VE_VP8_PPS			0x214
620#define VE_VP8_PPS_PIC_TYPE_P_FRAME		BIT(31)
621#define VE_VP8_PPS_LAST_SHARPNESS_LEVEL(v)	SHIFT_AND_MASK_BITS(v, 30, 28)
622#define VE_VP8_PPS_LAST_PIC_TYPE_P_FRAME	BIT(27)
623#define VE_VP8_PPS_ALTREF_SIGN_BIAS		BIT(26)
624#define VE_VP8_PPS_GOLDEN_SIGN_BIAS		BIT(25)
625#define VE_VP8_PPS_RELOAD_ENTROPY_PROBS		BIT(24)
626#define VE_VP8_PPS_REFRESH_ENTROPY_PROBS	BIT(23)
627#define VE_VP8_PPS_MB_NO_COEFF_SKIP		BIT(22)
628#define VE_VP8_PPS_TOKEN_PARTITION(v)		SHIFT_AND_MASK_BITS(v, 21, 20)
629#define VE_VP8_PPS_MODE_REF_LF_DELTA_UPDATE	BIT(19)
630#define VE_VP8_PPS_MODE_REF_LF_DELTA_ENABLE	BIT(18)
631#define VE_VP8_PPS_LOOP_FILTER_LEVEL(v)		SHIFT_AND_MASK_BITS(v, 17, 12)
632#define VE_VP8_PPS_LOOP_FILTER_SIMPLE		BIT(11)
633#define VE_VP8_PPS_SHARPNESS_LEVEL(v)		SHIFT_AND_MASK_BITS(v, 10, 8)
634#define VE_VP8_PPS_LAST_LOOP_FILTER_SIMPLE	BIT(7)
635#define VE_VP8_PPS_SEGMENTATION_ENABLE		BIT(6)
636#define VE_VP8_PPS_MB_SEGMENT_ABS_DELTA		BIT(5)
637#define VE_VP8_PPS_UPDATE_MB_SEGMENTATION_MAP	BIT(4)
638#define VE_VP8_PPS_FULL_PIXEL			BIT(3)
639#define VE_VP8_PPS_BILINEAR_MC_FILTER		BIT(2)
640#define VE_VP8_PPS_FILTER_TYPE_SIMPLE		BIT(1)
641#define VE_VP8_PPS_LPF_DISABLE			BIT(0)
642
643#define VE_VP8_QP_INDEX_DELTA		0x218
644#define VE_VP8_QP_INDEX_DELTA_UVAC(v)		SHIFT_AND_MASK_BITS(v, 31, 27)
645#define VE_VP8_QP_INDEX_DELTA_UVDC(v)		SHIFT_AND_MASK_BITS(v, 26, 22)
646#define VE_VP8_QP_INDEX_DELTA_Y2AC(v)		SHIFT_AND_MASK_BITS(v, 21, 17)
647#define VE_VP8_QP_INDEX_DELTA_Y2DC(v)		SHIFT_AND_MASK_BITS(v, 16, 12)
648#define VE_VP8_QP_INDEX_DELTA_Y1DC(v)		SHIFT_AND_MASK_BITS(v, 11, 7)
649#define VE_VP8_QP_INDEX_DELTA_BASE_QINDEX(v)	SHIFT_AND_MASK_BITS(v, 6, 0)
650
651#define VE_VP8_PART_SIZE_OFFSET		0x21c
652#define VE_VP8_ENTROPY_PROBS_ADDR	0x250
653#define VE_VP8_FIRST_DATA_PART_LEN	0x254
654
655#define VE_VP8_FSIZE			0x258
656#define VE_VP8_FSIZE_WIDTH(w) \
657	SHIFT_AND_MASK_BITS(DIV_ROUND_UP(w, 16), 15, 8)
658#define VE_VP8_FSIZE_HEIGHT(h) \
659	SHIFT_AND_MASK_BITS(DIV_ROUND_UP(h, 16), 7, 0)
660
661#define VE_VP8_PICSIZE			0x25c
662#define VE_VP8_PICSIZE_WIDTH(w)			SHIFT_AND_MASK_BITS(w, 27, 16)
663#define VE_VP8_PICSIZE_HEIGHT(h)		SHIFT_AND_MASK_BITS(h, 11, 0)
664
665#define VE_VP8_REC_LUMA			0x2ac
666#define VE_VP8_FWD_LUMA			0x2b0
667#define VE_VP8_BWD_LUMA			0x2b4
668#define VE_VP8_REC_CHROMA		0x2d0
669#define VE_VP8_FWD_CHROMA		0x2d4
670#define VE_VP8_BWD_CHROMA		0x2d8
671#define VE_VP8_ALT_LUMA			0x2e8
672#define VE_VP8_ALT_CHROMA		0x2ec
673
674#define VE_VP8_SEGMENT_FEAT_MB_LV0	0x2f0
675#define VE_VP8_SEGMENT_FEAT_MB_LV1	0x2f4
676
677#define VE_VP8_SEGMENT3(v)			SHIFT_AND_MASK_BITS(v, 31, 24)
678#define VE_VP8_SEGMENT2(v)			SHIFT_AND_MASK_BITS(v, 23, 16)
679#define VE_VP8_SEGMENT1(v)			SHIFT_AND_MASK_BITS(v, 15, 8)
680#define VE_VP8_SEGMENT0(v)			SHIFT_AND_MASK_BITS(v, 7, 0)
681
682#define VE_VP8_REF_LF_DELTA		0x2f8
683#define VE_VP8_MODE_LF_DELTA		0x2fc
684
685#define VE_VP8_LF_DELTA3(v)			SHIFT_AND_MASK_BITS(v, 30, 24)
686#define VE_VP8_LF_DELTA2(v)			SHIFT_AND_MASK_BITS(v, 22, 16)
687#define VE_VP8_LF_DELTA1(v)			SHIFT_AND_MASK_BITS(v, 14, 8)
688#define VE_VP8_LF_DELTA0(v)			SHIFT_AND_MASK_BITS(v, 6, 0)
689
690#define VE_ISP_INPUT_SIZE		0xa00
691#define VE_ISP_INPUT_STRIDE		0xa04
692#define VE_ISP_CTRL			0xa08
693#define VE_ISP_INPUT_LUMA		0xa78
694#define VE_ISP_INPUT_CHROMA		0xa7c
695
696#define VE_AVC_PARAM			0xb04
697#define VE_AVC_QP			0xb08
698#define VE_AVC_MOTION_EST		0xb10
699#define VE_AVC_CTRL			0xb14
700#define VE_AVC_TRIGGER			0xb18
701#define VE_AVC_STATUS			0xb1c
702#define VE_AVC_BASIC_BITS		0xb20
703#define VE_AVC_UNK_BUF			0xb60
704#define VE_AVC_VLE_ADDR			0xb80
705#define VE_AVC_VLE_END			0xb84
706#define VE_AVC_VLE_OFFSET		0xb88
707#define VE_AVC_VLE_MAX			0xb8c
708#define VE_AVC_VLE_LENGTH		0xb90
709#define VE_AVC_REF_LUMA			0xba0
710#define VE_AVC_REF_CHROMA		0xba4
711#define VE_AVC_REC_LUMA			0xbb0
712#define VE_AVC_REC_CHROMA		0xbb4
713#define VE_AVC_REF_SLUMA		0xbb8
714#define VE_AVC_REC_SLUMA		0xbbc
715#define VE_AVC_MB_INFO			0xbc0
716
717#endif