vdec_1.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (C) 2018 BayLibre, SAS
  4 * Author: Maxime Jourdan <mjourdan@baylibre.com>
  5 *
  6 * VDEC_1 is a video decoding block that allows decoding of
  7 * MPEG 1/2/4, H.263, H.264, MJPEG, VC1
  8 */
  9
 10#include <linux/firmware.h>
 11#include <linux/clk.h>
 12
 13#include "vdec_1.h"
 14#include "vdec_helpers.h"
 15#include "dos_regs.h"
 16
 17/* AO Registers */
 18#define AO_RTI_GEN_PWR_SLEEP0	0xe8
 19#define AO_RTI_GEN_PWR_ISO0	0xec
 20	#define GEN_PWR_VDEC_1 (BIT(3) | BIT(2))
 21	#define GEN_PWR_VDEC_1_SM1 (BIT(1))
 22
 23#define MC_SIZE			(4096 * 4)
 24
 25static int
 26vdec_1_load_firmware(struct amvdec_session *sess, const char *fwname)
 27{
 28	const struct firmware *fw;
 29	struct amvdec_core *core = sess->core;
 30	struct device *dev = core->dev_dec;
 31	struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
 32	static void *mc_addr;
 33	static dma_addr_t mc_addr_map;
 34	int ret;
 35	u32 i = 1000;
 36
 37	ret = request_firmware(&fw, fwname, dev);
 38	if (ret < 0)
 39		return -EINVAL;
 40
 41	if (fw->size < MC_SIZE) {
 42		dev_err(dev, "Firmware size %zu is too small. Expected %u.\n",
 43			fw->size, MC_SIZE);
 44		ret = -EINVAL;
 45		goto release_firmware;
 46	}
 47
 48	mc_addr = dma_alloc_coherent(core->dev, MC_SIZE,
 49				     &mc_addr_map, GFP_KERNEL);
 50	if (!mc_addr) {
 51		ret = -ENOMEM;
 52		goto release_firmware;
 53	}
 54
 55	memcpy(mc_addr, fw->data, MC_SIZE);
 56
 57	amvdec_write_dos(core, MPSR, 0);
 58	amvdec_write_dos(core, CPSR, 0);
 59
 60	amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31));
 61
 62	amvdec_write_dos(core, IMEM_DMA_ADR, mc_addr_map);
 63	amvdec_write_dos(core, IMEM_DMA_COUNT, MC_SIZE / 4);
 64	amvdec_write_dos(core, IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
 65
 66	while (--i && amvdec_read_dos(core, IMEM_DMA_CTRL) & 0x8000);
 67
 68	if (i == 0) {
 69		dev_err(dev, "Firmware load fail (DMA hang?)\n");
 70		ret = -EINVAL;
 71		goto free_mc;
 72	}
 73
 74	if (codec_ops->load_extended_firmware)
 75		ret = codec_ops->load_extended_firmware(sess,
 76							fw->data + MC_SIZE,
 77							fw->size - MC_SIZE);
 78
 79free_mc:
 80	dma_free_coherent(core->dev, MC_SIZE, mc_addr, mc_addr_map);
 81release_firmware:
 82	release_firmware(fw);
 83	return ret;
 84}
 85
 86static int vdec_1_stbuf_power_up(struct amvdec_session *sess)
 87{
 88	struct amvdec_core *core = sess->core;
 89
 90	amvdec_write_dos(core, VLD_MEM_VIFIFO_CONTROL, 0);
 91	amvdec_write_dos(core, VLD_MEM_VIFIFO_WRAP_COUNT, 0);
 92	amvdec_write_dos(core, POWER_CTL_VLD, BIT(4));
 93
 94	amvdec_write_dos(core, VLD_MEM_VIFIFO_START_PTR, sess->vififo_paddr);
 95	amvdec_write_dos(core, VLD_MEM_VIFIFO_CURR_PTR, sess->vififo_paddr);
 96	amvdec_write_dos(core, VLD_MEM_VIFIFO_END_PTR,
 97			 sess->vififo_paddr + sess->vififo_size - 8);
 98
 99	amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);
100	amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);
101
102	amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_MANUAL);
103	amvdec_write_dos(core, VLD_MEM_VIFIFO_WP, sess->vififo_paddr);
104
105	amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
106	amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
107
108	amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL,
109			      (0x11 << MEM_FIFO_CNT_BIT) | MEM_FILL_ON_LEVEL |
110			      MEM_CTRL_FILL_EN | MEM_CTRL_EMPTY_EN);
111
112	return 0;
113}
114
115static void vdec_1_conf_esparser(struct amvdec_session *sess)
116{
117	struct amvdec_core *core = sess->core;
118
119	/* VDEC_1 specific ESPARSER stuff */
120	amvdec_write_dos(core, DOS_GEN_CTRL0, 0);
121	amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
122	amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
123}
124
125static u32 vdec_1_vififo_level(struct amvdec_session *sess)
126{
127	struct amvdec_core *core = sess->core;
128
129	return amvdec_read_dos(core, VLD_MEM_VIFIFO_LEVEL);
130}
131
132static void __vdec_1_stop(struct amvdec_session *sess)
133{
134	struct amvdec_core *core = sess->core;
135	struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
136
137	amvdec_write_dos(core, MPSR, 0);
138	amvdec_write_dos(core, CPSR, 0);
139	amvdec_write_dos(core, ASSIST_MBOX1_MASK, 0);
140
141	amvdec_write_dos(core, DOS_SW_RESET0, BIT(12) | BIT(11));
142	amvdec_write_dos(core, DOS_SW_RESET0, 0);
143	amvdec_read_dos(core, DOS_SW_RESET0);
144
145	/* enable vdec1 isolation */
146	if (core->platform->revision == VDEC_REVISION_SM1)
147		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
148				   GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);
149	else
150		regmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0xc0);
151	/* power off vdec1 memories */
152	amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0xffffffff);
153	/* power off vdec1 */
154	if (core->platform->revision == VDEC_REVISION_SM1)
155		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
156				   GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);
157	else
158		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
159				   GEN_PWR_VDEC_1, GEN_PWR_VDEC_1);
160
161	if (sess->priv)
162		codec_ops->stop(sess);
163}
164
165static int vdec_1_stop(struct amvdec_session *sess)
166{
167	struct amvdec_core *core = sess->core;
168
169	__vdec_1_stop(sess);
170
171	clk_disable_unprepare(core->vdec_1_clk);
172
173	return 0;
174}
175
176static int vdec_1_start(struct amvdec_session *sess)
177{
178	int ret;
179	struct amvdec_core *core = sess->core;
180	struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
181
182	/* Configure the vdec clk to the maximum available */
183	clk_set_rate(core->vdec_1_clk, 666666666);
184	ret = clk_prepare_enable(core->vdec_1_clk);
185	if (ret)
186		return ret;
187
188	/* Enable power for VDEC_1 */
189	if (core->platform->revision == VDEC_REVISION_SM1)
190		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
191				   GEN_PWR_VDEC_1_SM1, 0);
192	else
193		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
194				   GEN_PWR_VDEC_1, 0);
195	usleep_range(10, 20);
196
197	/* Reset VDEC1 */
198	amvdec_write_dos(core, DOS_SW_RESET0, 0xfffffffc);
199	amvdec_write_dos(core, DOS_SW_RESET0, 0x00000000);
200
201	amvdec_write_dos(core, DOS_GCLK_EN0, 0x3ff);
202
203	/* enable VDEC Memories */
204	amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0);
205	/* Remove VDEC1 Isolation */
206	if (core->platform->revision == VDEC_REVISION_SM1)
207		regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
208				   GEN_PWR_VDEC_1_SM1, 0);
209	else
210		regmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0);
211	/* Reset DOS top registers */
212	amvdec_write_dos(core, DOS_VDEC_MCRCC_STALL_CTRL, 0);
213
214	amvdec_write_dos(core, GCLK_EN, 0x3ff);
215	amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31));
216
217	vdec_1_stbuf_power_up(sess);
218
219	ret = vdec_1_load_firmware(sess, sess->fmt_out->firmware_path);
220	if (ret)
221		goto stop;
222
223	ret = codec_ops->start(sess);
224	if (ret)
225		goto stop;
226
227	/* Enable IRQ */
228	amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
229	amvdec_write_dos(core, ASSIST_MBOX1_MASK, 1);
230
231	/* Enable 2-plane output */
232	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
233		amvdec_write_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17));
234	else
235		amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17));
236
237	/* Enable firmware processor */
238	amvdec_write_dos(core, MPSR, 1);
239	/* Let the firmware settle */
240	usleep_range(10, 20);
241
242	return 0;
243
244stop:
245	__vdec_1_stop(sess);
246	clk_disable_unprepare(core->vdec_1_clk);
247	return ret;
248}
249
250struct amvdec_ops vdec_1_ops = {
251	.start = vdec_1_start,
252	.stop = vdec_1_stop,
253	.conf_esparser = vdec_1_conf_esparser,
254	.vififo_level = vdec_1_vififo_level,
255};