ipu7.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2013 - 2025 Intel Corporation
  4 */
  5
  6#ifndef IPU7_H
  7#define IPU7_H
  8
  9#include <linux/list.h>
 10#include <linux/pci.h>
 11#include <linux/types.h>
 12
 13#include "ipu7-buttress.h"
 14
 15struct ipu7_bus_device;
 16struct pci_dev;
 17struct firmware;
 18
 19#define IPU_NAME			"intel-ipu7"
 20#define IPU_MEDIA_DEV_MODEL_NAME	"ipu7"
 21
 22#define IPU7_FIRMWARE_NAME		"intel/ipu/ipu7_fw.bin"
 23#define IPU7P5_FIRMWARE_NAME		"intel/ipu/ipu7ptl_fw.bin"
 24#define IPU8_FIRMWARE_NAME		"intel/ipu/ipu8_fw.bin"
 25
 26#define IPU7_ISYS_NUM_STREAMS		12
 27
 28#define IPU7_PCI_ID			0x645d
 29#define IPU7P5_PCI_ID			0xb05d
 30#define IPU8_PCI_ID			0xd719
 31
 32#define FW_LOG_BUF_SIZE			(2 * 1024 * 1024)
 33
 34enum ipu_version {
 35	IPU_VER_INVALID = 0,
 36	IPU_VER_7 = 1,
 37	IPU_VER_7P5 = 2,
 38	IPU_VER_8 = 3,
 39};
 40
 41static inline bool is_ipu7p5(u8 hw_ver)
 42{
 43	return hw_ver == IPU_VER_7P5;
 44}
 45
 46static inline bool is_ipu7(u8 hw_ver)
 47{
 48	return hw_ver == IPU_VER_7;
 49}
 50
 51static inline bool is_ipu8(u8 hw_ver)
 52{
 53	return hw_ver == IPU_VER_8;
 54}
 55
 56#define IPU_UNIFIED_OFFSET		0
 57
 58/*
 59 * ISYS DMA can overshoot. For higher resolutions over allocation is one line
 60 * but it must be at minimum 1024 bytes. Value could be different in
 61 * different versions / generations thus provide it via platform data.
 62 */
 63#define IPU_ISYS_OVERALLOC_MIN		1024
 64
 65#define IPU_FW_CODE_REGION_SIZE		0x1000000 /* 16MB */
 66#define IPU_FW_CODE_REGION_START	0x4000000 /* 64MB */
 67#define IPU_FW_CODE_REGION_END		(IPU_FW_CODE_REGION_START +	\
 68					 IPU_FW_CODE_REGION_SIZE) /* 80MB */
 69
 70struct ipu7_device {
 71	struct pci_dev *pdev;
 72	struct list_head devices;
 73	struct ipu7_bus_device *isys;
 74	struct ipu7_bus_device *psys;
 75	struct ipu_buttress buttress;
 76
 77	const struct firmware *cpd_fw;
 78	const char *cpd_fw_name;
 79	/* Only for non-secure mode. */
 80	void *fw_code_region;
 81
 82	void __iomem *base;
 83	void __iomem *pb_base;
 84	u8 hw_ver;
 85	bool ipc_reinit;
 86	bool secure_mode;
 87	bool ipu7_bus_ready_to_probe;
 88};
 89
 90#define IPU_DMA_MASK			39
 91#define IPU_LIB_CALL_TIMEOUT_MS		2000
 92#define IPU_PSYS_CMD_TIMEOUT_MS		2000
 93#define IPU_PSYS_OPEN_CLOSE_TIMEOUT_US	50
 94#define IPU_PSYS_OPEN_CLOSE_RETRY	(10000 / IPU_PSYS_OPEN_CLOSE_TIMEOUT_US)
 95
 96#define IPU_ISYS_NAME "isys"
 97#define IPU_PSYS_NAME "psys"
 98
 99#define IPU_MMU_ADDR_BITS		32
100/* FW is accessible within the first 2 GiB only in non-secure mode. */
101#define IPU_MMU_ADDR_BITS_NON_SECURE	31
102
103#define IPU7_IS_MMU_NUM			4U
104#define IPU7_PS_MMU_NUM			4U
105#define IPU7P5_IS_MMU_NUM		4U
106#define IPU7P5_PS_MMU_NUM		4U
107#define IPU8_IS_MMU_NUM			5U
108#define IPU8_PS_MMU_NUM			4U
109#define IPU_MMU_MAX_NUM			5U /* max(IS, PS) */
110#define IPU_MMU_MAX_TLB_L1_STREAMS	40U
111#define IPU_MMU_MAX_TLB_L2_STREAMS	40U
112#define IPU_ZLX_MAX_NUM			32U
113#define IPU_ZLX_POOL_NUM		8U
114#define IPU_UAO_PLANE_MAX_NUM		64U
115
116/*
117 * To maximize the IOSF utlization, IPU need to send requests in bursts.
118 * At the DMA interface with the buttress, there are CDC FIFOs with burst
119 * collection capability. CDC FIFO burst collectors have a configurable
120 * threshold and is configured based on the outcome of performance measurements.
121 *
122 * isys has 3 ports with IOSF interface for VC0, VC1 and VC2
123 * psys has 4 ports with IOSF interface for VC0, VC1w, VC1r and VC2
124 *
125 * Threshold values are pre-defined and are arrived at after performance
126 * evaluations on a type of IPU
127 */
128#define IPU_MAX_VC_IOSF_PORTS		4
129
130/*
131 * IPU must configure correct arbitration mechanism related to the IOSF VC
132 * requests. There are two options per VC0 and VC1 - > 0 means rearbitrate on
133 * stall and 1 means stall until the request is completed.
134 */
135#define IPU_BTRS_ARB_MODE_TYPE_REARB	0
136#define IPU_BTRS_ARB_MODE_TYPE_STALL	1
137
138/* Currently chosen arbitration mechanism for VC0 */
139#define IPU_BTRS_ARB_STALL_MODE_VC0	IPU_BTRS_ARB_MODE_TYPE_REARB
140
141/* Currently chosen arbitration mechanism for VC1 */
142#define IPU_BTRS_ARB_STALL_MODE_VC1	IPU_BTRS_ARB_MODE_TYPE_REARB
143
144/* One L2 entry maps 1024 L1 entries and one L1 entry per page */
145#define IPU_MMUV2_L2_RANGE		(1024 * PAGE_SIZE)
146/* Max L2 blocks per stream */
147#define IPU_MMUV2_MAX_L2_BLOCKS		2
148/* Max L1 blocks per stream */
149#define IPU_MMUV2_MAX_L1_BLOCKS		16
150#define IPU_MMUV2_TRASH_RANGE		(IPU_MMUV2_L2_RANGE *	\
151					 IPU_MMUV2_MAX_L2_BLOCKS)
152/* Entries per L1 block */
153#define MMUV2_ENTRIES_PER_L1_BLOCK	16
154#define MMUV2_TRASH_L1_BLOCK_OFFSET	(MMUV2_ENTRIES_PER_L1_BLOCK * PAGE_SIZE)
155#define MMUV2_TRASH_L2_BLOCK_OFFSET	IPU_MMUV2_L2_RANGE
156
157struct ipu7_mmu_hw {
158	char name[32];
159
160	void __iomem *base;
161	void __iomem *zlx_base;
162	void __iomem *uao_base;
163
164	u32 offset;
165	u32 zlx_offset;
166	u32 uao_offset;
167
168	u32 info_bits;
169	u32 refill;
170	u32 collapse_en_bitmap;
171	u32 at_sp_arb_cfg;
172
173	u32 l1_block;
174	u32 l2_block;
175
176	u8 nr_l1streams;
177	u8 nr_l2streams;
178	u32 l1_block_sz[IPU_MMU_MAX_TLB_L1_STREAMS];
179	u32 l2_block_sz[IPU_MMU_MAX_TLB_L2_STREAMS];
180
181	u8 zlx_nr;
182	u32 zlx_axi_pool[IPU_ZLX_POOL_NUM];
183	u32 zlx_en[IPU_ZLX_MAX_NUM];
184	u32 zlx_conf[IPU_ZLX_MAX_NUM];
185
186	u32 uao_p_num;
187	u32 uao_p2tlb[IPU_UAO_PLANE_MAX_NUM];
188};
189
190struct ipu7_mmu_pdata {
191	u32 nr_mmus;
192	struct ipu7_mmu_hw mmu_hw[IPU_MMU_MAX_NUM];
193	int mmid;
194};
195
196struct ipu7_isys_csi2_pdata {
197	void __iomem *base;
198};
199
200struct ipu7_isys_internal_csi2_pdata {
201	u32 nports;
202	u32 const *offsets;
203	u32 gpreg;
204};
205
206struct ipu7_hw_variants {
207	unsigned long offset;
208	u32 nr_mmus;
209	struct ipu7_mmu_hw mmu_hw[IPU_MMU_MAX_NUM];
210	u8 cdc_fifos;
211	u8 cdc_fifo_threshold[IPU_MAX_VC_IOSF_PORTS];
212	u32 dmem_offset;
213	u32 spc_offset;	/* SPC offset from psys base */
214};
215
216struct ipu_isys_internal_pdata {
217	struct ipu7_isys_internal_csi2_pdata csi2;
218	struct ipu7_hw_variants hw_variant;
219	u32 num_parallel_streams;
220	u32 isys_dma_overshoot;
221};
222
223struct ipu7_isys_pdata {
224	void __iomem *base;
225	const struct ipu_isys_internal_pdata *ipdata;
226};
227
228struct ipu_psys_internal_pdata {
229	struct ipu7_hw_variants hw_variant;
230};
231
232struct ipu7_psys_pdata {
233	void __iomem *base;
234	const struct ipu_psys_internal_pdata *ipdata;
235};
236
237int request_cpd_fw(const struct firmware **firmware_p, const char *name,
238		   struct device *device);
239void ipu_internal_pdata_init(struct ipu_isys_internal_pdata *isys_ipdata,
240			     struct ipu_psys_internal_pdata *psys_ipdata);
241void ipu7_dump_fw_error_log(const struct ipu7_bus_device *adev);
242#endif /* IPU7_H */