ipu7-platform-regs.h

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (C) 2018 - 2025 Intel Corporation
 4 */
 5
 6#ifndef IPU7_PLATFORM_REGS_H
 7#define IPU7_PLATFORM_REGS_H
 8
 9#define IS_BASE					0x230000
10#define IS_UC_CTRL_BASE				(IS_BASE + 0x0)
11
12#define PS_BASE					0x130000
13#define PS_UC_CTRL_BASE				(PS_BASE + 0x0)
14
15/*
16 * bit 0: IRQ from FW,
17 * bit 1, 2 and 3: IRQ from HW
18 */
19#define TO_SW_IRQ_MASK				0xf
20#define TO_SW_IRQ_FW				BIT(0)
21
22#define FW_CODE_BASE				0x0
23#define FW_DATA_BASE				0x4
24#define PRINTF_EN_THROUGH_TRACE			0x3004
25#define PRINTF_EN_DIRECTLY_TO_DDR		0x3008
26#define PRINTF_DDR_BASE_ADDR			0x300c
27#define PRINTF_DDR_SIZE				0x3010
28#define PRINTF_DDR_NEXT_ADDR			0x3014
29#define PRINTF_STATUS				0x3018
30#define PRINTF_AXI_CNTL				0x301c
31#define PRINTF_MSG_LENGTH			0x3020
32#define TO_SW_IRQ_CNTL_EDGE			0x4000
33#define TO_SW_IRQ_CNTL_MASK_N			0x4004
34#define TO_SW_IRQ_CNTL_STATUS			0x4008
35#define TO_SW_IRQ_CNTL_CLEAR			0x400c
36#define TO_SW_IRQ_CNTL_ENABLE			0x4010
37#define TO_SW_IRQ_CNTL_LEVEL_NOT_PULSE		0x4014
38#define ERR_IRQ_CNTL_EDGE			0x4018
39#define ERR_IRQ_CNTL_MASK_N			0x401c
40#define ERR_IRQ_CNTL_STATUS			0x4020
41#define ERR_IRQ_CNTL_CLEAR			0x4024
42#define ERR_IRQ_CNTL_ENABLE			0x4028
43#define ERR_IRQ_CNTL_LEVEL_NOT_PULSE		0x402c
44#define LOCAL_DMEM_BASE_ADDR			0x1300000
45
46/*
47 * IS_UC_TO_SW irqs
48 * bit 0: IRQ from local FW
49 * bit 1~3: IRQ from HW
50 */
51#define IS_UC_TO_SW_IRQ_MASK			0xf
52
53#define IPU_ISYS_SPC_OFFSET			0x210000
54#define IPU7_PSYS_SPC_OFFSET			0x118000
55#define IPU_ISYS_DMEM_OFFSET			0x200000
56#define IPU_PSYS_DMEM_OFFSET			0x100000
57
58#define IPU7_ISYS_CSI_PORT_NUM			4
59
60/* IRQ-related registers in PSYS */
61#define IPU_REG_PSYS_TO_SW_IRQ_CNTL_EDGE		0x134000
62#define IPU_REG_PSYS_TO_SW_IRQ_CNTL_MASK		0x134004
63#define IPU_REG_PSYS_TO_SW_IRQ_CNTL_STATUS		0x134008
64#define IPU_REG_PSYS_TO_SW_IRQ_CNTL_CLEAR		0x13400c
65#define IPU_REG_PSYS_TO_SW_IRQ_CNTL_ENABLE		0x134010
66#define IPU_REG_PSYS_TO_SW_IRQ_CNTL_LEVEL_NOT_PULSE	0x134014
67#define IRQ_FROM_LOCAL_FW				BIT(0)
68
69/*
70 * psys subdomains power request regs
71 */
72enum ipu7_device_buttress_psys_domain_pos {
73	IPU_PSYS_SUBDOMAIN_LB		= 0,
74	IPU_PSYS_SUBDOMAIN_BB		= 1,
75};
76
77#define IPU7_PSYS_DOMAIN_POWER_MASK		(BIT(IPU_PSYS_SUBDOMAIN_LB) | \
78						 BIT(IPU_PSYS_SUBDOMAIN_BB))
79#define IPU8_PSYS_DOMAIN_POWER_MASK		BIT(IPU_PSYS_SUBDOMAIN_LB)
80#define IPU_PSYS_DOMAIN_POWER_IN_PROGRESS	BIT(31)
81
82#endif /* IPU7_PLATFORM_REGS_H */