ipu7-mmu.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (C) 2013 - 2025 Intel Corporation
  4 */
  5
  6#ifndef IPU7_MMU_H
  7#define IPU7_MMU_H
  8
  9#include <linux/dma-mapping.h>
 10#include <linux/list.h>
 11#include <linux/spinlock_types.h>
 12#include <linux/types.h>
 13
 14struct device;
 15struct page;
 16struct ipu7_hw_variants;
 17struct ipu7_mmu;
 18struct ipu7_mmu_info;
 19
 20#define ISYS_MMID 0x1
 21#define PSYS_MMID 0x0
 22
 23/* IPU7 for LNL */
 24/* IS MMU Cmd RD */
 25#define IPU7_IS_MMU_FW_RD_OFFSET		0x274000
 26#define IPU7_IS_MMU_FW_RD_STREAM_NUM		3
 27#define IPU7_IS_MMU_FW_RD_L1_BLOCKNR_REG	0x54
 28#define IPU7_IS_MMU_FW_RD_L2_BLOCKNR_REG	0x60
 29
 30/* IS MMU Cmd WR */
 31#define IPU7_IS_MMU_FW_WR_OFFSET		0x275000
 32#define IPU7_IS_MMU_FW_WR_STREAM_NUM		3
 33#define IPU7_IS_MMU_FW_WR_L1_BLOCKNR_REG	0x54
 34#define IPU7_IS_MMU_FW_WR_L2_BLOCKNR_REG	0x60
 35
 36/* IS MMU Data WR Snoop */
 37#define IPU7_IS_MMU_M0_OFFSET			0x276000
 38#define IPU7_IS_MMU_M0_STREAM_NUM		8
 39#define IPU7_IS_MMU_M0_L1_BLOCKNR_REG		0x54
 40#define IPU7_IS_MMU_M0_L2_BLOCKNR_REG		0x74
 41
 42/* IS MMU Data WR ISOC */
 43#define IPU7_IS_MMU_M1_OFFSET			0x277000
 44#define IPU7_IS_MMU_M1_STREAM_NUM		16
 45#define IPU7_IS_MMU_M1_L1_BLOCKNR_REG		0x54
 46#define IPU7_IS_MMU_M1_L2_BLOCKNR_REG		0x94
 47
 48/* PS MMU FW RD */
 49#define IPU7_PS_MMU_FW_RD_OFFSET		0x148000
 50#define IPU7_PS_MMU_FW_RD_STREAM_NUM		20
 51#define IPU7_PS_MMU_FW_RD_L1_BLOCKNR_REG	0x54
 52#define IPU7_PS_MMU_FW_RD_L2_BLOCKNR_REG	0xa4
 53
 54/* PS MMU FW WR */
 55#define IPU7_PS_MMU_FW_WR_OFFSET		0x149000
 56#define IPU7_PS_MMU_FW_WR_STREAM_NUM		10
 57#define IPU7_PS_MMU_FW_WR_L1_BLOCKNR_REG	0x54
 58#define IPU7_PS_MMU_FW_WR_L2_BLOCKNR_REG	0x7c
 59
 60/* PS MMU FW Data RD VC0 */
 61#define IPU7_PS_MMU_SRT_RD_OFFSET		0x14a000
 62#define IPU7_PS_MMU_SRT_RD_STREAM_NUM		40
 63#define IPU7_PS_MMU_SRT_RD_L1_BLOCKNR_REG	0x54
 64#define IPU7_PS_MMU_SRT_RD_L2_BLOCKNR_REG	0xf4
 65
 66/* PS MMU FW Data WR VC0 */
 67#define IPU7_PS_MMU_SRT_WR_OFFSET		0x14b000
 68#define IPU7_PS_MMU_SRT_WR_STREAM_NUM		40
 69#define IPU7_PS_MMU_SRT_WR_L1_BLOCKNR_REG	0x54
 70#define IPU7_PS_MMU_SRT_WR_L2_BLOCKNR_REG	0xf4
 71
 72/* IS UAO UC RD */
 73#define IPU7_IS_UAO_UC_RD_OFFSET		0x27c000
 74#define IPU7_IS_UAO_UC_RD_PLANENUM		4
 75
 76/* IS UAO UC WR */
 77#define IPU7_IS_UAO_UC_WR_OFFSET		0x27d000
 78#define IPU7_IS_UAO_UC_WR_PLANENUM		4
 79
 80/* IS UAO M0 WR */
 81#define IPU7_IS_UAO_M0_WR_OFFSET		0x27e000
 82#define IPU7_IS_UAO_M0_WR_PLANENUM		8
 83
 84/* IS UAO M1 WR */
 85#define IPU7_IS_UAO_M1_WR_OFFSET		0x27f000
 86#define IPU7_IS_UAO_M1_WR_PLANENUM		16
 87
 88/* PS UAO FW RD */
 89#define IPU7_PS_UAO_FW_RD_OFFSET		0x156000
 90#define IPU7_PS_UAO_FW_RD_PLANENUM		20
 91
 92/* PS UAO FW WR */
 93#define IPU7_PS_UAO_FW_WR_OFFSET		0x157000
 94#define IPU7_PS_UAO_FW_WR_PLANENUM		16
 95
 96/* PS UAO SRT RD */
 97#define IPU7_PS_UAO_SRT_RD_OFFSET		0x154000
 98#define IPU7_PS_UAO_SRT_RD_PLANENUM		40
 99
100/* PS UAO SRT WR */
101#define IPU7_PS_UAO_SRT_WR_OFFSET		0x155000
102#define IPU7_PS_UAO_SRT_WR_PLANENUM		40
103
104#define IPU7_IS_ZLX_UC_RD_OFFSET		0x278000
105#define IPU7_IS_ZLX_UC_WR_OFFSET		0x279000
106#define IPU7_IS_ZLX_M0_OFFSET			0x27a000
107#define IPU7_IS_ZLX_M1_OFFSET			0x27b000
108#define IPU7_IS_ZLX_UC_RD_NUM			4
109#define IPU7_IS_ZLX_UC_WR_NUM			4
110#define IPU7_IS_ZLX_M0_NUM			8
111#define IPU7_IS_ZLX_M1_NUM			16
112
113#define IPU7_PS_ZLX_DATA_RD_OFFSET		0x14e000
114#define IPU7_PS_ZLX_DATA_WR_OFFSET		0x14f000
115#define IPU7_PS_ZLX_FW_RD_OFFSET		0x150000
116#define IPU7_PS_ZLX_FW_WR_OFFSET		0x151000
117#define IPU7_PS_ZLX_DATA_RD_NUM			32
118#define IPU7_PS_ZLX_DATA_WR_NUM			32
119#define IPU7_PS_ZLX_FW_RD_NUM			16
120#define IPU7_PS_ZLX_FW_WR_NUM			10
121
122/* IPU7P5 for PTL */
123/* IS MMU Cmd RD */
124#define IPU7P5_IS_MMU_FW_RD_OFFSET		0x274000
125#define IPU7P5_IS_MMU_FW_RD_STREAM_NUM		3
126#define IPU7P5_IS_MMU_FW_RD_L1_BLOCKNR_REG	0x54
127#define IPU7P5_IS_MMU_FW_RD_L2_BLOCKNR_REG	0x60
128
129/* IS MMU Cmd WR */
130#define IPU7P5_IS_MMU_FW_WR_OFFSET		0x275000
131#define IPU7P5_IS_MMU_FW_WR_STREAM_NUM		3
132#define IPU7P5_IS_MMU_FW_WR_L1_BLOCKNR_REG	0x54
133#define IPU7P5_IS_MMU_FW_WR_L2_BLOCKNR_REG	0x60
134
135/* IS MMU Data WR Snoop */
136#define IPU7P5_IS_MMU_M0_OFFSET			0x276000
137#define IPU7P5_IS_MMU_M0_STREAM_NUM		16
138#define IPU7P5_IS_MMU_M0_L1_BLOCKNR_REG		0x54
139#define IPU7P5_IS_MMU_M0_L2_BLOCKNR_REG		0x94
140
141/* IS MMU Data WR ISOC */
142#define IPU7P5_IS_MMU_M1_OFFSET			0x277000
143#define IPU7P5_IS_MMU_M1_STREAM_NUM		16
144#define IPU7P5_IS_MMU_M1_L1_BLOCKNR_REG		0x54
145#define IPU7P5_IS_MMU_M1_L2_BLOCKNR_REG		0x94
146
147/* PS MMU FW RD */
148#define IPU7P5_PS_MMU_FW_RD_OFFSET		0x148000
149#define IPU7P5_PS_MMU_FW_RD_STREAM_NUM		16
150#define IPU7P5_PS_MMU_FW_RD_L1_BLOCKNR_REG	0x54
151#define IPU7P5_PS_MMU_FW_RD_L2_BLOCKNR_REG	0x94
152
153/* PS MMU FW WR */
154#define IPU7P5_PS_MMU_FW_WR_OFFSET		0x149000
155#define IPU7P5_PS_MMU_FW_WR_STREAM_NUM		10
156#define IPU7P5_PS_MMU_FW_WR_L1_BLOCKNR_REG	0x54
157#define IPU7P5_PS_MMU_FW_WR_L2_BLOCKNR_REG	0x7c
158
159/* PS MMU FW Data RD VC0 */
160#define IPU7P5_PS_MMU_SRT_RD_OFFSET		0x14a000
161#define IPU7P5_PS_MMU_SRT_RD_STREAM_NUM		22
162#define IPU7P5_PS_MMU_SRT_RD_L1_BLOCKNR_REG	0x54
163#define IPU7P5_PS_MMU_SRT_RD_L2_BLOCKNR_REG	0xac
164
165/* PS MMU FW Data WR VC0 */
166#define IPU7P5_PS_MMU_SRT_WR_OFFSET		0x14b000
167#define IPU7P5_PS_MMU_SRT_WR_STREAM_NUM		32
168#define IPU7P5_PS_MMU_SRT_WR_L1_BLOCKNR_REG	0x54
169#define IPU7P5_PS_MMU_SRT_WR_L2_BLOCKNR_REG	0xd4
170
171/* IS UAO UC RD */
172#define IPU7P5_IS_UAO_UC_RD_OFFSET		0x27c000
173#define IPU7P5_IS_UAO_UC_RD_PLANENUM		4
174
175/* IS UAO UC WR */
176#define IPU7P5_IS_UAO_UC_WR_OFFSET		0x27d000
177#define IPU7P5_IS_UAO_UC_WR_PLANENUM		4
178
179/* IS UAO M0 WR */
180#define IPU7P5_IS_UAO_M0_WR_OFFSET		0x27e000
181#define IPU7P5_IS_UAO_M0_WR_PLANENUM		16
182
183/* IS UAO M1 WR */
184#define IPU7P5_IS_UAO_M1_WR_OFFSET		0x27f000
185#define IPU7P5_IS_UAO_M1_WR_PLANENUM		16
186
187/* PS UAO FW RD */
188#define IPU7P5_PS_UAO_FW_RD_OFFSET		0x156000
189#define IPU7P5_PS_UAO_FW_RD_PLANENUM		16
190
191/* PS UAO FW WR */
192#define IPU7P5_PS_UAO_FW_WR_OFFSET		0x157000
193#define IPU7P5_PS_UAO_FW_WR_PLANENUM		10
194
195/* PS UAO SRT RD */
196#define IPU7P5_PS_UAO_SRT_RD_OFFSET		0x154000
197#define IPU7P5_PS_UAO_SRT_RD_PLANENUM		22
198
199/* PS UAO SRT WR */
200#define IPU7P5_PS_UAO_SRT_WR_OFFSET		0x155000
201#define IPU7P5_PS_UAO_SRT_WR_PLANENUM		32
202
203#define IPU7P5_IS_ZLX_UC_RD_OFFSET		0x278000
204#define IPU7P5_IS_ZLX_UC_WR_OFFSET		0x279000
205#define IPU7P5_IS_ZLX_M0_OFFSET			0x27a000
206#define IPU7P5_IS_ZLX_M1_OFFSET			0x27b000
207#define IPU7P5_IS_ZLX_UC_RD_NUM			4
208#define IPU7P5_IS_ZLX_UC_WR_NUM			4
209#define IPU7P5_IS_ZLX_M0_NUM			16
210#define IPU7P5_IS_ZLX_M1_NUM			16
211
212#define IPU7P5_PS_ZLX_DATA_RD_OFFSET		0x14e000
213#define IPU7P5_PS_ZLX_DATA_WR_OFFSET		0x14f000
214#define IPU7P5_PS_ZLX_FW_RD_OFFSET		0x150000
215#define IPU7P5_PS_ZLX_FW_WR_OFFSET		0x151000
216#define IPU7P5_PS_ZLX_DATA_RD_NUM		22
217#define IPU7P5_PS_ZLX_DATA_WR_NUM		32
218#define IPU7P5_PS_ZLX_FW_RD_NUM			16
219#define IPU7P5_PS_ZLX_FW_WR_NUM			10
220
221/* IS MMU Cmd RD */
222#define IPU8_IS_MMU_FW_RD_OFFSET		0x270000
223#define IPU8_IS_MMU_FW_RD_STREAM_NUM		3
224#define IPU8_IS_MMU_FW_RD_L1_BLOCKNR_REG	0x54
225#define IPU8_IS_MMU_FW_RD_L2_BLOCKNR_REG	0x60
226
227/* IS MMU Cmd WR */
228#define IPU8_IS_MMU_FW_WR_OFFSET		0x271000
229#define IPU8_IS_MMU_FW_WR_STREAM_NUM		3
230#define IPU8_IS_MMU_FW_WR_L1_BLOCKNR_REG	0x54
231#define IPU8_IS_MMU_FW_WR_L2_BLOCKNR_REG	0x60
232
233/* IS MMU Data WR Snoop */
234#define IPU8_IS_MMU_M0_OFFSET			0x272000
235#define IPU8_IS_MMU_M0_STREAM_NUM		16
236#define IPU8_IS_MMU_M0_L1_BLOCKNR_REG		0x54
237#define IPU8_IS_MMU_M0_L2_BLOCKNR_REG		0x94
238
239/* IS MMU Data WR ISOC */
240#define IPU8_IS_MMU_M1_OFFSET			0x273000
241#define IPU8_IS_MMU_M1_STREAM_NUM		16
242#define IPU8_IS_MMU_M1_L1_BLOCKNR_REG		0x54
243#define IPU8_IS_MMU_M1_L2_BLOCKNR_REG		0x94
244
245/* IS MMU UPIPE ISOC */
246#define IPU8_IS_MMU_UPIPE_OFFSET		0x274000
247#define IPU8_IS_MMU_UPIPE_STREAM_NUM		6
248#define IPU8_IS_MMU_UPIPE_L1_BLOCKNR_REG	0x54
249#define IPU8_IS_MMU_UPIPE_L2_BLOCKNR_REG	0x6c
250
251/* PS MMU FW RD */
252#define IPU8_PS_MMU_FW_RD_OFFSET		0x148000
253#define IPU8_PS_MMU_FW_RD_STREAM_NUM		12
254#define IPU8_PS_MMU_FW_RD_L1_BLOCKNR_REG	0x54
255#define IPU8_PS_MMU_FW_RD_L2_BLOCKNR_REG	0x84
256
257/* PS MMU FW WR */
258#define IPU8_PS_MMU_FW_WR_OFFSET		0x149000
259#define IPU8_PS_MMU_FW_WR_STREAM_NUM		8
260#define IPU8_PS_MMU_FW_WR_L1_BLOCKNR_REG	0x54
261#define IPU8_PS_MMU_FW_WR_L2_BLOCKNR_REG	0x74
262
263/* PS MMU FW Data RD VC0 */
264#define IPU8_PS_MMU_SRT_RD_OFFSET		0x14a000
265#define IPU8_PS_MMU_SRT_RD_STREAM_NUM		26
266#define IPU8_PS_MMU_SRT_RD_L1_BLOCKNR_REG	0x54
267#define IPU8_PS_MMU_SRT_RD_L2_BLOCKNR_REG	0xbc
268
269/* PS MMU FW Data WR VC0 */
270#define IPU8_PS_MMU_SRT_WR_OFFSET		0x14b000
271#define IPU8_PS_MMU_SRT_WR_STREAM_NUM		26
272#define IPU8_PS_MMU_SRT_WR_L1_BLOCKNR_REG	0x54
273#define IPU8_PS_MMU_SRT_WR_L2_BLOCKNR_REG	0xbc
274
275/* IS UAO UC RD */
276#define IPU8_IS_UAO_UC_RD_OFFSET		0x27a000
277#define IPU8_IS_UAO_UC_RD_PLANENUM		4
278
279/* IS UAO UC WR */
280#define IPU8_IS_UAO_UC_WR_OFFSET		0x27b000
281#define IPU8_IS_UAO_UC_WR_PLANENUM		4
282
283/* IS UAO M0 WR */
284#define IPU8_IS_UAO_M0_WR_OFFSET		0x27c000
285#define IPU8_IS_UAO_M0_WR_PLANENUM		16
286
287/* IS UAO M1 WR */
288#define IPU8_IS_UAO_M1_WR_OFFSET		0x27d000
289#define IPU8_IS_UAO_M1_WR_PLANENUM		16
290
291/* IS UAO UPIPE */
292#define IPU8_IS_UAO_UPIPE_OFFSET		0x27e000
293#define IPU8_IS_UAO_UPIPE_PLANENUM		6
294
295/* PS UAO FW RD */
296#define IPU8_PS_UAO_FW_RD_OFFSET		0x156000
297#define IPU8_PS_UAO_FW_RD_PLANENUM		12
298
299/* PS UAO FW WR */
300#define IPU8_PS_UAO_FW_WR_OFFSET		0x157000
301#define IPU8_PS_UAO_FW_WR_PLANENUM		8
302
303/* PS UAO SRT RD */
304#define IPU8_PS_UAO_SRT_RD_OFFSET		0x154000
305#define IPU8_PS_UAO_SRT_RD_PLANENUM		26
306
307/* PS UAO SRT WR */
308#define IPU8_PS_UAO_SRT_WR_OFFSET		0x155000
309#define IPU8_PS_UAO_SRT_WR_PLANENUM		26
310
311#define IPU8_IS_ZLX_UC_RD_OFFSET		0x275000
312#define IPU8_IS_ZLX_UC_WR_OFFSET		0x276000
313#define IPU8_IS_ZLX_M0_OFFSET			0x277000
314#define IPU8_IS_ZLX_M1_OFFSET			0x278000
315#define IPU8_IS_ZLX_UPIPE_OFFSET		0x279000
316#define IPU8_IS_ZLX_UC_RD_NUM			4
317#define IPU8_IS_ZLX_UC_WR_NUM			4
318#define IPU8_IS_ZLX_M0_NUM			16
319#define IPU8_IS_ZLX_M1_NUM			16
320#define IPU8_IS_ZLX_UPIPE_NUM			6
321
322#define IPU8_PS_ZLX_DATA_RD_OFFSET		0x14e000
323#define IPU8_PS_ZLX_DATA_WR_OFFSET		0x14f000
324#define IPU8_PS_ZLX_FW_RD_OFFSET		0x150000
325#define IPU8_PS_ZLX_FW_WR_OFFSET		0x151000
326#define IPU8_PS_ZLX_DATA_RD_NUM			26
327#define IPU8_PS_ZLX_DATA_WR_NUM			26
328#define IPU8_PS_ZLX_FW_RD_NUM			12
329#define IPU8_PS_ZLX_FW_WR_NUM			8
330
331#define MMU_REG_INVALIDATE_0			0x00
332#define MMU_REG_INVALIDATE_1			0x04
333#define MMU_REG_PAGE_TABLE_BASE_ADDR		0x08
334#define MMU_REG_USER_INFO_BITS			0x0c
335#define MMU_REG_AXI_REFILL_IF_ID		0x10
336#define MMU_REG_PW_EN_BITMAP			0x14
337#define MMU_REG_COLLAPSE_ENABLE_BITMAP		0x18
338#define MMU_REG_GENERAL_REG			0x1c
339#define MMU_REG_AT_SP_ARB_CFG			0x20
340#define MMU_REG_INVALIDATION_STATUS		0x24
341#define MMU_REG_IRQ_LEVEL_NO_PULSE		0x28
342#define MMU_REG_IRQ_MASK			0x2c
343#define MMU_REG_IRQ_ENABLE			0x30
344#define MMU_REG_IRQ_EDGE			0x34
345#define MMU_REG_IRQ_CLEAR			0x38
346#define MMU_REG_IRQ_CAUSE			0x3c
347#define MMU_REG_CG_CTRL_BITS			0x40
348#define MMU_REG_RD_FIFOS_STATUS			0x44
349#define MMU_REG_WR_FIFOS_STATUS			0x48
350#define MMU_REG_COMMON_FIFOS_STATUS		0x4c
351#define MMU_REG_FSM_STATUS			0x50
352
353#define ZLX_REG_AXI_POOL			0x0
354#define ZLX_REG_EN				0x20
355#define ZLX_REG_CONF				0x24
356#define ZLX_REG_CG_CTRL				0x900
357#define ZLX_REG_FORCE_BYPASS			0x904
358
359struct ipu7_mmu_info {
360	struct device *dev;
361
362	u32 *l1_pt;
363	u32 l1_pt_dma;
364	u32 **l2_pts;
365
366	u32 *dummy_l2_pt;
367	u32 dummy_l2_pteval;
368	void *dummy_page;
369	u32 dummy_page_pteval;
370
371	dma_addr_t aperture_start;
372	dma_addr_t aperture_end;
373	unsigned long pgsize_bitmap;
374
375	spinlock_t lock;	/* Serialize access to users */
376	struct ipu7_dma_mapping *dmap;
377};
378
379struct ipu7_mmu {
380	struct list_head node;
381
382	struct ipu7_mmu_hw *mmu_hw;
383	unsigned int nr_mmus;
384	unsigned int mmid;
385
386	phys_addr_t pgtbl;
387	struct device *dev;
388
389	struct ipu7_dma_mapping *dmap;
390	struct list_head vma_list;
391
392	struct page *trash_page;
393	dma_addr_t pci_trash_page; /* IOVA from PCI DMA services (parent) */
394	dma_addr_t iova_trash_page; /* IOVA for IPU child nodes to use */
395
396	bool ready;
397	spinlock_t ready_lock;	/* Serialize access to bool ready */
398
399	void (*tlb_invalidate)(struct ipu7_mmu *mmu);
400};
401
402struct ipu7_mmu *ipu7_mmu_init(struct device *dev,
403			       void __iomem *base, int mmid,
404			       const struct ipu7_hw_variants *hw);
405void ipu7_mmu_cleanup(struct ipu7_mmu *mmu);
406int ipu7_mmu_hw_init(struct ipu7_mmu *mmu);
407void ipu7_mmu_hw_cleanup(struct ipu7_mmu *mmu);
408int ipu7_mmu_map(struct ipu7_mmu_info *mmu_info, unsigned long iova,
409		 phys_addr_t paddr, size_t size);
410void ipu7_mmu_unmap(struct ipu7_mmu_info *mmu_info, unsigned long iova,
411		    size_t size);
412phys_addr_t ipu7_mmu_iova_to_phys(struct ipu7_mmu_info *mmu_info,
413				  dma_addr_t iova);
414#endif