system_local.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Support for Intel Camera Imaging ISP subsystem.
 4 * Copyright (c) 2015, Intel Corporation.
 5 */
 6
 7#ifndef __SYSTEM_LOCAL_H_INCLUDED__
 8#define __SYSTEM_LOCAL_H_INCLUDED__
 9
10#ifdef HRT_ISP_CSS_CUSTOM_HOST
11#ifndef HRT_USE_VIR_ADDRS
12#define HRT_USE_VIR_ADDRS
13#endif
14#endif
15
16#include "system_global.h"
17
18/* This interface is deprecated */
19#include "hive_types.h"
20
21/*
22 * Cell specific address maps
23 */
24
25#define GP_FIFO_BASE   ((hrt_address)0x0000000000090104)		/* This is NOT a base address */
26
27/* ISP */
28extern const hrt_address ISP_CTRL_BASE[N_ISP_ID];
29extern const hrt_address ISP_DMEM_BASE[N_ISP_ID];
30extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID];
31
32/* SP */
33extern const hrt_address SP_CTRL_BASE[N_SP_ID];
34extern const hrt_address SP_DMEM_BASE[N_SP_ID];
35
36/* MMU */
37
38extern const hrt_address MMU_BASE[N_MMU_ID];
39
40/* DMA */
41extern const hrt_address DMA_BASE[N_DMA_ID];
42extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID];
43
44/* IRQ */
45extern const hrt_address IRQ_BASE[N_IRQ_ID];
46
47/* GDC */
48extern const hrt_address GDC_BASE[N_GDC_ID];
49
50/* FIFO_MONITOR (not a subset of GP_DEVICE) */
51extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID];
52
53/* GP_DEVICE (single base for all separate GP_REG instances) */
54extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID];
55
56/*GP TIMER , all timer registers are inter-twined,
57 * so, having multiple base addresses for
58 * different timers does not help*/
59extern const hrt_address GP_TIMER_BASE;
60
61/* GPIO */
62extern const hrt_address GPIO_BASE[N_GPIO_ID];
63
64/* TIMED_CTRL */
65extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID];
66
67/* INPUT_FORMATTER */
68extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID];
69
70/* INPUT_SYSTEM */
71extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID];
72
73/* RX, the MIPI lane control regs start at offset 0 */
74extern const hrt_address RX_BASE[N_RX_ID];
75
76/* IBUF_CTRL, part of the Input System 2401 */
77extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID];
78
79/* ISYS IRQ Controllers, part of the Input System 2401 */
80extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID];
81
82/* CSI FE, part of the Input System 2401 */
83extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID];
84
85/* CSI BE, part of the Input System 2401 */
86extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID];
87
88/* PIXEL Generator, part of the Input System 2401 */
89extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID];
90
91/* Stream2MMIO, part of the Input System 2401 */
92extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID];
93
94#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */