ad9832.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * AD9832 SPI DDS driver
  4 *
  5 * Copyright 2011 Analog Devices Inc.
  6 */
  7
  8#include <asm/div64.h>
  9
 10#include <linux/bitfield.h>
 11#include <linux/bits.h>
 12#include <linux/clk.h>
 13#include <linux/device.h>
 14#include <linux/err.h>
 15#include <linux/kernel.h>
 16#include <linux/module.h>
 17#include <linux/regulator/consumer.h>
 18#include <linux/slab.h>
 19#include <linux/spi/spi.h>
 20#include <linux/sysfs.h>
 21#include <linux/unaligned.h>
 22
 23#include <linux/iio/iio.h>
 24#include <linux/iio/sysfs.h>
 25
 26#include "ad9832.h"
 27
 28#include "dds.h"
 29
 30/* Registers */
 31
 32#define AD9832_FREQ0LL		0x0
 33#define AD9832_FREQ0HL		0x1
 34#define AD9832_FREQ0LM		0x2
 35#define AD9832_FREQ0HM		0x3
 36#define AD9832_FREQ1LL		0x4
 37#define AD9832_FREQ1HL		0x5
 38#define AD9832_FREQ1LM		0x6
 39#define AD9832_FREQ1HM		0x7
 40#define AD9832_PHASE0L		0x8
 41#define AD9832_PHASE0H		0x9
 42#define AD9832_PHASE1L		0xA
 43#define AD9832_PHASE1H		0xB
 44#define AD9832_PHASE2L		0xC
 45#define AD9832_PHASE2H		0xD
 46#define AD9832_PHASE3L		0xE
 47#define AD9832_PHASE3H		0xF
 48
 49#define AD9832_PHASE_SYM	0x10
 50#define AD9832_FREQ_SYM		0x11
 51#define AD9832_PINCTRL_EN	0x12
 52#define AD9832_OUTPUT_EN	0x13
 53
 54/* Command Control Bits */
 55
 56#define AD9832_CMD_PHA8BITSW	0x1
 57#define AD9832_CMD_PHA16BITSW	0x0
 58#define AD9832_CMD_FRE8BITSW	0x3
 59#define AD9832_CMD_FRE16BITSW	0x2
 60#define AD9832_CMD_FPSELECT	0x6
 61#define AD9832_CMD_SYNCSELSRC	0x8
 62#define AD9832_CMD_SLEEPRESCLR	0xC
 63
 64#define AD9832_FREQ		BIT(11)
 65#define AD9832_PHASE_MASK	GENMASK(10, 9)
 66#define AD9832_SYNC		BIT(13)
 67#define AD9832_SELSRC		BIT(12)
 68#define AD9832_SLEEP		BIT(13)
 69#define AD9832_RESET		BIT(12)
 70#define AD9832_CLR		BIT(11)
 71#define AD9832_FREQ_BITS	32
 72#define AD9832_PHASE_BITS	12
 73#define AD9832_CMD_MSK		GENMASK(15, 12)
 74#define AD9832_ADD_MSK		GENMASK(11, 8)
 75#define AD9832_DAT_MSK		GENMASK(7, 0)
 76
 77/**
 78 * struct ad9832_state - driver instance specific data
 79 * @spi:		spi_device
 80 * @mclk:		external master clock
 81 * @ctrl_fp:		cached frequency/phase control word
 82 * @ctrl_ss:		cached sync/selsrc control word
 83 * @ctrl_src:		cached sleep/reset/clr word
 84 * @xfer:		default spi transfer
 85 * @msg:		default spi message
 86 * @freq_xfer:		tuning word spi transfer
 87 * @freq_msg:		tuning word spi message
 88 * @phase_xfer:		tuning word spi transfer
 89 * @phase_msg:		tuning word spi message
 90 * @lock:		protect sensor state
 91 * @data:		spi transmit buffer
 92 * @phase_data:		tuning word spi transmit buffer
 93 * @freq_data:		tuning word spi transmit buffer
 94 */
 95
 96struct ad9832_state {
 97	struct spi_device		*spi;
 98	struct clk			*mclk;
 99	unsigned short			ctrl_fp;
100	unsigned short			ctrl_ss;
101	unsigned short			ctrl_src;
102	struct spi_transfer		xfer;
103	struct spi_message		msg;
104	struct spi_transfer		freq_xfer[4];
105	struct spi_message		freq_msg;
106	struct spi_transfer		phase_xfer[2];
107	struct spi_message		phase_msg;
108	struct mutex			lock;	/* protect sensor state */
109	/*
110	 * DMA (thus cache coherency maintenance) requires the
111	 * transfer buffers to live in their own cache lines.
112	 */
113	union {
114		__be16			freq_data[4];
115		__be16			phase_data[2];
116		__be16			data;
117	} __aligned(IIO_DMA_MINALIGN);
118};
119
120static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
121{
122	unsigned long long freqreg = (u64)fout *
123				     (u64)((u64)1L << AD9832_FREQ_BITS);
124	do_div(freqreg, mclk);
125	return freqreg;
126}
127
128static int ad9832_write_frequency(struct ad9832_state *st,
129				  unsigned int addr, unsigned long fout)
130{
131	unsigned long clk_freq;
132	unsigned long regval;
133	u8 regval_bytes[4];
134	u16 freq_cmd;
135
136	clk_freq = clk_get_rate(st->mclk);
137
138	if (!clk_freq || fout > (clk_freq / 2))
139		return -EINVAL;
140
141	regval = ad9832_calc_freqreg(clk_freq, fout);
142	put_unaligned_be32(regval, regval_bytes);
143
144	for (int i = 0; i < ARRAY_SIZE(regval_bytes); i++) {
145		freq_cmd = (i % 2 == 0) ? AD9832_CMD_FRE8BITSW : AD9832_CMD_FRE16BITSW;
146
147		st->freq_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, freq_cmd) |
148			FIELD_PREP(AD9832_ADD_MSK, addr - i) |
149			FIELD_PREP(AD9832_DAT_MSK, regval_bytes[i]));
150	}
151
152	return spi_sync(st->spi, &st->freq_msg);
153}
154
155static int ad9832_write_phase(struct ad9832_state *st,
156			      unsigned long addr, unsigned long phase)
157{
158	u8 phase_bytes[2];
159	u16 phase_cmd;
160
161	if (phase >= BIT(AD9832_PHASE_BITS))
162		return -EINVAL;
163
164	put_unaligned_be16(phase, phase_bytes);
165
166	for (int i = 0; i < ARRAY_SIZE(phase_bytes); i++) {
167		phase_cmd = (i % 2 == 0) ? AD9832_CMD_PHA8BITSW : AD9832_CMD_PHA16BITSW;
168
169		st->phase_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, phase_cmd) |
170			FIELD_PREP(AD9832_ADD_MSK, addr - i) |
171			FIELD_PREP(AD9832_DAT_MSK, phase_bytes[i]));
172	}
173
174	return spi_sync(st->spi, &st->phase_msg);
175}
176
177static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
178			    const char *buf, size_t len)
179{
180	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
181	struct ad9832_state *st = iio_priv(indio_dev);
182	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
183	int ret;
184	unsigned long val;
185
186	ret = kstrtoul(buf, 10, &val);
187	if (ret)
188		goto error_ret;
189
190	mutex_lock(&st->lock);
191	switch ((u32)this_attr->address) {
192	case AD9832_FREQ0HM:
193	case AD9832_FREQ1HM:
194		ret = ad9832_write_frequency(st, this_attr->address, val);
195		break;
196	case AD9832_PHASE0H:
197	case AD9832_PHASE1H:
198	case AD9832_PHASE2H:
199	case AD9832_PHASE3H:
200		ret = ad9832_write_phase(st, this_attr->address, val);
201		break;
202	case AD9832_PINCTRL_EN:
203		st->ctrl_ss &= ~AD9832_SELSRC;
204		st->ctrl_ss |= FIELD_PREP(AD9832_SELSRC, val ? 0 : 1);
205
206		st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SYNCSELSRC) |
207						  st->ctrl_ss);
208		ret = spi_sync(st->spi, &st->msg);
209		break;
210	case AD9832_FREQ_SYM:
211		if (val == 1 || val == 0) {
212			st->ctrl_fp &= ~AD9832_FREQ;
213			st->ctrl_fp |= FIELD_PREP(AD9832_FREQ, val ? 1 : 0);
214		} else {
215			ret = -EINVAL;
216			break;
217		}
218		st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT) |
219						  st->ctrl_fp);
220		ret = spi_sync(st->spi, &st->msg);
221		break;
222	case AD9832_PHASE_SYM:
223		if (val > 3) {
224			ret = -EINVAL;
225			break;
226		}
227
228		st->ctrl_fp &= ~AD9832_PHASE_MASK;
229		st->ctrl_fp |= FIELD_PREP(AD9832_PHASE_MASK, val);
230
231		st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT) |
232						  st->ctrl_fp);
233		ret = spi_sync(st->spi, &st->msg);
234		break;
235	case AD9832_OUTPUT_EN:
236		if (val)
237			st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP | AD9832_CLR);
238		else
239			st->ctrl_src |= FIELD_PREP(AD9832_RESET, 1);
240
241		st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESCLR) |
242						  st->ctrl_src);
243		ret = spi_sync(st->spi, &st->msg);
244		break;
245	default:
246		ret = -ENODEV;
247	}
248	mutex_unlock(&st->lock);
249
250error_ret:
251	return ret ? ret : len;
252}
253
254/*
255 * see dds.h for further information
256 */
257
258static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM);
259static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM);
260static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SYM);
261static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
262
263static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H);
264static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H);
265static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H);
266static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H);
267static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL,
268				ad9832_write, AD9832_PHASE_SYM);
269static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
270
271static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
272				ad9832_write, AD9832_PINCTRL_EN);
273static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL,
274				ad9832_write, AD9832_OUTPUT_EN);
275
276static struct attribute *ad9832_attributes[] = {
277	&iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
278	&iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
279	&iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
280	&iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
281	&iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
282	&iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
283	&iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
284	&iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
285	&iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
286	&iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
287	&iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
288	&iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
289	NULL,
290};
291
292static const struct attribute_group ad9832_attribute_group = {
293	.attrs = ad9832_attributes,
294};
295
296static const struct iio_info ad9832_info = {
297	.attrs = &ad9832_attribute_group,
298};
299
300static int ad9832_probe(struct spi_device *spi)
301{
302	struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev);
303	struct iio_dev *indio_dev;
304	struct ad9832_state *st;
305	int ret;
306
307	if (!pdata) {
308		dev_dbg(&spi->dev, "no platform data?\n");
309		return -ENODEV;
310	}
311
312	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
313	if (!indio_dev)
314		return -ENOMEM;
315
316	st = iio_priv(indio_dev);
317
318	ret = devm_regulator_get_enable(&spi->dev, "avdd");
319	if (ret)
320		return dev_err_probe(&spi->dev, ret, "failed to enable specified AVDD voltage\n");
321
322	ret = devm_regulator_get_enable(&spi->dev, "dvdd");
323	if (ret)
324		return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVDD supply\n");
325
326	st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
327	if (IS_ERR(st->mclk))
328		return PTR_ERR(st->mclk);
329
330	st->spi = spi;
331	mutex_init(&st->lock);
332
333	indio_dev->name = spi_get_device_id(spi)->name;
334	indio_dev->info = &ad9832_info;
335	indio_dev->modes = INDIO_DIRECT_MODE;
336
337	/* Setup default messages */
338
339	st->xfer.tx_buf = &st->data;
340	st->xfer.len = 2;
341
342	spi_message_init(&st->msg);
343	spi_message_add_tail(&st->xfer, &st->msg);
344
345	st->freq_xfer[0].tx_buf = &st->freq_data[0];
346	st->freq_xfer[0].len = 2;
347	st->freq_xfer[0].cs_change = 1;
348	st->freq_xfer[1].tx_buf = &st->freq_data[1];
349	st->freq_xfer[1].len = 2;
350	st->freq_xfer[1].cs_change = 1;
351	st->freq_xfer[2].tx_buf = &st->freq_data[2];
352	st->freq_xfer[2].len = 2;
353	st->freq_xfer[2].cs_change = 1;
354	st->freq_xfer[3].tx_buf = &st->freq_data[3];
355	st->freq_xfer[3].len = 2;
356
357	spi_message_init(&st->freq_msg);
358	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
359	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
360	spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
361	spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
362
363	st->phase_xfer[0].tx_buf = &st->phase_data[0];
364	st->phase_xfer[0].len = 2;
365	st->phase_xfer[0].cs_change = 1;
366	st->phase_xfer[1].tx_buf = &st->phase_data[1];
367	st->phase_xfer[1].len = 2;
368
369	spi_message_init(&st->phase_msg);
370	spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
371	spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
372
373	st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
374	st->data = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESCLR) |
375					  st->ctrl_src);
376	ret = spi_sync(st->spi, &st->msg);
377	if (ret) {
378		dev_err(&spi->dev, "device init failed\n");
379		return ret;
380	}
381
382	ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
383	if (ret)
384		return ret;
385
386	ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
387	if (ret)
388		return ret;
389
390	ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
391	if (ret)
392		return ret;
393
394	ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
395	if (ret)
396		return ret;
397
398	ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
399	if (ret)
400		return ret;
401
402	ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
403	if (ret)
404		return ret;
405
406	return devm_iio_device_register(&spi->dev, indio_dev);
407}
408
409static const struct of_device_id ad9832_of_match[] = {
410	{ .compatible = "adi,ad9832" },
411	{ .compatible = "adi,ad9835" },
412	{ }
413};
414MODULE_DEVICE_TABLE(of, ad9832_of_match);
415
416static const struct spi_device_id ad9832_id[] = {
417	{"ad9832", 0},
418	{"ad9835", 0},
419	{ }
420};
421MODULE_DEVICE_TABLE(spi, ad9832_id);
422
423static struct spi_driver ad9832_driver = {
424	.driver = {
425		.name	= "ad9832",
426		.of_match_table = ad9832_of_match,
427	},
428	.probe		= ad9832_probe,
429	.id_table	= ad9832_id,
430};
431module_spi_driver(ad9832_driver);
432
433MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
434MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
435MODULE_LICENSE("GPL v2");