fb_seps525.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * FB driver for the NHD-1.69-160128UGC3 (Newhaven Display International, Inc.)
  4 * using the SEPS525 (Syncoam) LCD Controller
  5 *
  6 * Copyright (C) 2016 Analog Devices Inc.
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License as published by
 10 * the Free Software Foundation; either version 2 of the License, or
 11 * (at your option) any later version.
 12 *
 13 * This program is distributed in the hope that it will be useful,
 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 * GNU General Public License for more details.
 17 */
 18
 19#include <linux/bits.h>
 20#include <linux/delay.h>
 21#include <linux/init.h>
 22#include <linux/module.h>
 23
 24#include "fbtft.h"
 25
 26#define DRVNAME		"fb_seps525"
 27#define WIDTH		160
 28#define HEIGHT		128
 29
 30#define SEPS525_INDEX 0x00
 31#define SEPS525_STATUS_RD 0x01
 32#define SEPS525_OSC_CTL 0x02
 33#define SEPS525_IREF 0x80
 34#define SEPS525_CLOCK_DIV 0x03
 35#define SEPS525_REDUCE_CURRENT 0x04
 36#define SEPS525_SOFT_RST 0x05
 37#define SEPS525_DISP_ONOFF 0x06
 38#define SEPS525_PRECHARGE_TIME_R 0x08
 39#define SEPS525_PRECHARGE_TIME_G 0x09
 40#define SEPS525_PRECHARGE_TIME_B 0x0A
 41#define SEPS525_PRECHARGE_CURRENT_R 0x0B
 42#define SEPS525_PRECHARGE_CURRENT_G 0x0C
 43#define SEPS525_PRECHARGE_CURRENT_B 0x0D
 44#define SEPS525_DRIVING_CURRENT_R 0x10
 45#define SEPS525_DRIVING_CURRENT_G 0x11
 46#define SEPS525_DRIVING_CURRENT_B 0x12
 47#define SEPS525_DISPLAYMODE_SET 0x13
 48#define SEPS525_RGBIF 0x14
 49#define SEPS525_RGB_POL 0x15
 50#define SEPS525_MEMORY_WRITEMODE 0x16
 51#define SEPS525_MX1_ADDR 0x17
 52#define SEPS525_MX2_ADDR 0x18
 53#define SEPS525_MY1_ADDR 0x19
 54#define SEPS525_MY2_ADDR 0x1A
 55#define SEPS525_MEMORY_ACCESS_POINTER_X 0x20
 56#define SEPS525_MEMORY_ACCESS_POINTER_Y 0x21
 57#define SEPS525_DDRAM_DATA_ACCESS_PORT 0x22
 58#define SEPS525_GRAY_SCALE_TABLE_INDEX 0x50
 59#define SEPS525_GRAY_SCALE_TABLE_DATA 0x51
 60#define SEPS525_DUTY 0x28
 61#define SEPS525_DSL 0x29
 62#define SEPS525_D1_DDRAM_FAC 0x2E
 63#define SEPS525_D1_DDRAM_FAR 0x2F
 64#define SEPS525_D2_DDRAM_SAC 0x31
 65#define SEPS525_D2_DDRAM_SAR 0x32
 66#define SEPS525_SCR1_FX1 0x33
 67#define SEPS525_SCR1_FX2 0x34
 68#define SEPS525_SCR1_FY1 0x35
 69#define SEPS525_SCR1_FY2 0x36
 70#define SEPS525_SCR2_SX1 0x37
 71#define SEPS525_SCR2_SX2 0x38
 72#define SEPS525_SCR2_SY1 0x39
 73#define SEPS525_SCR2_SY2 0x3A
 74#define SEPS525_SCREEN_SAVER_CONTEROL 0x3B
 75#define SEPS525_SS_SLEEP_TIMER 0x3C
 76#define SEPS525_SCREEN_SAVER_MODE 0x3D
 77#define SEPS525_SS_SCR1_FU 0x3E
 78#define SEPS525_SS_SCR1_MXY 0x3F
 79#define SEPS525_SS_SCR2_FU 0x40
 80#define SEPS525_SS_SCR2_MXY 0x41
 81#define SEPS525_MOVING_DIRECTION 0x42
 82#define SEPS525_SS_SCR2_SX1 0x47
 83#define SEPS525_SS_SCR2_SX2 0x48
 84#define SEPS525_SS_SCR2_SY1 0x49
 85#define SEPS525_SS_SCR2_SY2 0x4A
 86
 87/* SEPS525_DISPLAYMODE_SET */
 88#define MODE_SWAP_BGR	BIT(7)
 89#define MODE_SM		BIT(6)
 90#define MODE_RD		BIT(5)
 91#define MODE_CD		BIT(4)
 92
 93#define seps525_use_window	0 /* FBTFT doesn't really use it today */
 94
 95/* Init sequence taken from: Arduino Library for the Adafruit 2.2" display */
 96static int init_display(struct fbtft_par *par)
 97{
 98	par->fbtftops.reset(par);
 99
100	usleep_range(1000, 5000);
101
102	/* Disable Oscillator Power Down */
103	write_reg(par, SEPS525_REDUCE_CURRENT, 0x03);
104	usleep_range(1000, 5000);
105	/* Set Normal Driving Current */
106	write_reg(par, SEPS525_REDUCE_CURRENT, 0x00);
107	usleep_range(1000, 5000);
108
109	write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00);
110	/* Set EXPORT1 Pin at Internal Clock */
111	write_reg(par, SEPS525_OSC_CTL, 0x01);
112	/* Set Clock as 120 Frames/Sec */
113	write_reg(par, SEPS525_CLOCK_DIV, 0x90);
114	/* Set Reference Voltage Controlled by External Resister */
115	write_reg(par, SEPS525_IREF, 0x01);
116
117	/* precharge time R G B */
118	write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04);
119	write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05);
120	write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05);
121
122	/* precharge current R G B (uA) */
123	write_reg(par, SEPS525_PRECHARGE_CURRENT_R, 0x9D);
124	write_reg(par, SEPS525_PRECHARGE_CURRENT_G, 0x8C);
125	write_reg(par, SEPS525_PRECHARGE_CURRENT_B, 0x57);
126
127	/* driving current R G B (uA) */
128	write_reg(par, SEPS525_DRIVING_CURRENT_R, 0x56);
129	write_reg(par, SEPS525_DRIVING_CURRENT_G, 0x4D);
130	write_reg(par, SEPS525_DRIVING_CURRENT_B, 0x46);
131	/* Set Color Sequence */
132	write_reg(par, SEPS525_DISPLAYMODE_SET, 0xA0);
133	write_reg(par, SEPS525_RGBIF, 0x01); /* Set MCU Interface Mode */
134	/* Set Memory Write Mode */
135	write_reg(par, SEPS525_MEMORY_WRITEMODE, 0x66);
136	write_reg(par, SEPS525_DUTY, 0x7F); /* 1/128 Duty (0x0F~0x7F) */
137	/* Set Mapping RAM Display Start Line (0x00~0x7F) */
138	write_reg(par, SEPS525_DSL, 0x00);
139	write_reg(par, SEPS525_DISP_ONOFF, 0x01); /* Display On (0x00/0x01) */
140	/* Set All Internal Register Value as Normal Mode */
141	write_reg(par, SEPS525_SOFT_RST, 0x00);
142	/* Set RGB Interface Polarity as Active Low */
143	write_reg(par, SEPS525_RGB_POL, 0x00);
144
145	write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT);
146
147	return 0;
148}
149
150static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
151{
152	if (seps525_use_window) {
153		/* Set Window Xs,Ys Xe,Ye*/
154		write_reg(par, SEPS525_MX1_ADDR, xs);
155		write_reg(par, SEPS525_MX2_ADDR, xe);
156		write_reg(par, SEPS525_MY1_ADDR, ys);
157		write_reg(par, SEPS525_MY2_ADDR, ye);
158	}
159	/* start position X,Y */
160	write_reg(par, SEPS525_MEMORY_ACCESS_POINTER_X, xs);
161	write_reg(par, SEPS525_MEMORY_ACCESS_POINTER_Y, ys);
162
163	write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT);
164}
165
166static int set_var(struct fbtft_par *par)
167{
168	u8 val;
169
170	switch (par->info->var.rotate) {
171	case 0:
172		val = 0;
173		break;
174	case 180:
175		val = MODE_RD | MODE_CD;
176		break;
177	case 90:
178	case 270:
179
180	default:
181		return -EINVAL;
182	}
183	/* Memory Access Control  */
184	write_reg(par, SEPS525_DISPLAYMODE_SET, val |
185		       (par->bgr ? MODE_SWAP_BGR : 0));
186
187	write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT);
188
189	return 0;
190}
191
192static struct fbtft_display display = {
193	.regwidth = 8,
194	.width = WIDTH,
195	.height = HEIGHT,
196	.fbtftops = {
197		.init_display = init_display,
198		.set_addr_win = set_addr_win,
199		.set_var = set_var,
200	},
201};
202
203FBTFT_REGISTER_DRIVER(DRVNAME, "syncoam,seps525", &display);
204
205MODULE_ALIAS("spi:" DRVNAME);
206MODULE_ALIAS("platform:" DRVNAME);
207MODULE_ALIAS("spi:seps525");
208MODULE_ALIAS("platform:seps525");
209
210MODULE_DESCRIPTION("FB driver for the SEPS525 LCD Controller");
211MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
212MODULE_LICENSE("GPL");