fb_ra8875.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * FBTFT driver for the RA8875 LCD Controller
  4 * Copyright by Pf@nne & NOTRO
  5 */
  6
  7#include <linux/module.h>
  8#include <linux/kernel.h>
  9#include <linux/init.h>
 10#include <linux/delay.h>
 11
 12#include <linux/gpio/consumer.h>
 13#include "fbtft.h"
 14
 15#define DRVNAME "fb_ra8875"
 16
 17static int write_spi(struct fbtft_par *par, void *buf, size_t len)
 18{
 19	struct spi_transfer t = {
 20		.tx_buf = buf,
 21		.len = len,
 22		.speed_hz = 1000000,
 23	};
 24	struct spi_message m;
 25
 26	fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
 27			  "%s(len=%zu): ", __func__, len);
 28
 29	if (!par->spi) {
 30		dev_err(par->info->device,
 31			"%s: par->spi is unexpectedly NULL\n", __func__);
 32		return -1;
 33	}
 34
 35	spi_message_init(&m);
 36	spi_message_add_tail(&t, &m);
 37	return spi_sync(par->spi, &m);
 38}
 39
 40static int init_display(struct fbtft_par *par)
 41{
 42	gpiod_set_value(par->gpio.dc, 1);
 43
 44	par->fbtftops.reset(par);
 45
 46	if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) {
 47		/* PLL clock frequency */
 48		write_reg(par, 0x88, 0x0A);
 49		write_reg(par, 0x89, 0x02);
 50		mdelay(10);
 51		/* color deep / MCU Interface */
 52		write_reg(par, 0x10, 0x0C);
 53		/* pixel clock period  */
 54		write_reg(par, 0x04, 0x03);
 55		mdelay(1);
 56		/* horizontal settings */
 57		write_reg(par, 0x14, 0x27);
 58		write_reg(par, 0x15, 0x00);
 59		write_reg(par, 0x16, 0x05);
 60		write_reg(par, 0x17, 0x04);
 61		write_reg(par, 0x18, 0x03);
 62		/* vertical settings */
 63		write_reg(par, 0x19, 0xEF);
 64		write_reg(par, 0x1A, 0x00);
 65		write_reg(par, 0x1B, 0x05);
 66		write_reg(par, 0x1C, 0x00);
 67		write_reg(par, 0x1D, 0x0E);
 68		write_reg(par, 0x1E, 0x00);
 69		write_reg(par, 0x1F, 0x02);
 70	} else if ((par->info->var.xres == 480) &&
 71		   (par->info->var.yres == 272)) {
 72		/* PLL clock frequency  */
 73		write_reg(par, 0x88, 0x0A);
 74		write_reg(par, 0x89, 0x02);
 75		mdelay(10);
 76		/* color deep / MCU Interface */
 77		write_reg(par, 0x10, 0x0C);
 78		/* pixel clock period  */
 79		write_reg(par, 0x04, 0x82);
 80		mdelay(1);
 81		/* horizontal settings */
 82		write_reg(par, 0x14, 0x3B);
 83		write_reg(par, 0x15, 0x00);
 84		write_reg(par, 0x16, 0x01);
 85		write_reg(par, 0x17, 0x00);
 86		write_reg(par, 0x18, 0x05);
 87		/* vertical settings */
 88		write_reg(par, 0x19, 0x0F);
 89		write_reg(par, 0x1A, 0x01);
 90		write_reg(par, 0x1B, 0x02);
 91		write_reg(par, 0x1C, 0x00);
 92		write_reg(par, 0x1D, 0x07);
 93		write_reg(par, 0x1E, 0x00);
 94		write_reg(par, 0x1F, 0x09);
 95	} else if ((par->info->var.xres == 640) &&
 96		   (par->info->var.yres == 480)) {
 97		/* PLL clock frequency */
 98		write_reg(par, 0x88, 0x0B);
 99		write_reg(par, 0x89, 0x02);
100		mdelay(10);
101		/* color deep / MCU Interface */
102		write_reg(par, 0x10, 0x0C);
103		/* pixel clock period */
104		write_reg(par, 0x04, 0x01);
105		mdelay(1);
106		/* horizontal settings */
107		write_reg(par, 0x14, 0x4F);
108		write_reg(par, 0x15, 0x05);
109		write_reg(par, 0x16, 0x0F);
110		write_reg(par, 0x17, 0x01);
111		write_reg(par, 0x18, 0x00);
112		/* vertical settings */
113		write_reg(par, 0x19, 0xDF);
114		write_reg(par, 0x1A, 0x01);
115		write_reg(par, 0x1B, 0x0A);
116		write_reg(par, 0x1C, 0x00);
117		write_reg(par, 0x1D, 0x0E);
118		write_reg(par, 0x1E, 0x00);
119		write_reg(par, 0x1F, 0x01);
120	} else if ((par->info->var.xres == 800) &&
121		   (par->info->var.yres == 480)) {
122		/* PLL clock frequency */
123		write_reg(par, 0x88, 0x0B);
124		write_reg(par, 0x89, 0x02);
125		mdelay(10);
126		/* color deep / MCU Interface */
127		write_reg(par, 0x10, 0x0C);
128		/* pixel clock period */
129		write_reg(par, 0x04, 0x81);
130		mdelay(1);
131		/* horizontal settings */
132		write_reg(par, 0x14, 0x63);
133		write_reg(par, 0x15, 0x03);
134		write_reg(par, 0x16, 0x03);
135		write_reg(par, 0x17, 0x02);
136		write_reg(par, 0x18, 0x00);
137		/* vertical settings */
138		write_reg(par, 0x19, 0xDF);
139		write_reg(par, 0x1A, 0x01);
140		write_reg(par, 0x1B, 0x14);
141		write_reg(par, 0x1C, 0x00);
142		write_reg(par, 0x1D, 0x06);
143		write_reg(par, 0x1E, 0x00);
144		write_reg(par, 0x1F, 0x01);
145	} else {
146		dev_err(par->info->device, "display size is not supported!!");
147		return -1;
148	}
149
150	/* PWM clock */
151	write_reg(par, 0x8a, 0x81);
152	write_reg(par, 0x8b, 0xFF);
153	mdelay(10);
154
155	/* Display ON */
156	write_reg(par, 0x01, 0x80);
157	mdelay(10);
158
159	return 0;
160}
161
162static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
163{
164	/* Set_Active_Window */
165	write_reg(par, 0x30, xs & 0x00FF);
166	write_reg(par, 0x31, (xs & 0xFF00) >> 8);
167	write_reg(par, 0x32, ys & 0x00FF);
168	write_reg(par, 0x33, (ys & 0xFF00) >> 8);
169	write_reg(par, 0x34, (xs + xe) & 0x00FF);
170	write_reg(par, 0x35, ((xs + xe) & 0xFF00) >> 8);
171	write_reg(par, 0x36, (ys + ye) & 0x00FF);
172	write_reg(par, 0x37, ((ys + ye) & 0xFF00) >> 8);
173
174	/* Set_Memory_Write_Cursor */
175	write_reg(par, 0x46,  xs & 0xff);
176	write_reg(par, 0x47, (xs >> 8) & 0x03);
177	write_reg(par, 0x48,  ys & 0xff);
178	write_reg(par, 0x49, (ys >> 8) & 0x01);
179
180	write_reg(par, 0x02);
181}
182
183static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
184{
185	va_list args;
186	int i, ret;
187	u8 *buf = par->buf;
188
189	/* slow down spi-speed for writing registers */
190	par->fbtftops.write = write_spi;
191
192	if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
193		va_start(args, len);
194		for (i = 0; i < len; i++)
195			buf[i] = (u8)va_arg(args, unsigned int);
196		va_end(args);
197		fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device,
198				  u8, buf, len, "%s: ", __func__);
199	}
200
201	va_start(args, len);
202	*buf++ = 0x80;
203	*buf = (u8)va_arg(args, unsigned int);
204	ret = par->fbtftops.write(par, par->buf, 2);
205	if (ret < 0) {
206		va_end(args);
207		dev_err(par->info->device, "write() failed and returned %dn",
208			ret);
209		return;
210	}
211	len--;
212
213	udelay(100);
214
215	if (len) {
216		buf = (u8 *)par->buf;
217		*buf++ = 0x00;
218		i = len;
219		while (i--)
220			*buf++ = (u8)va_arg(args, unsigned int);
221
222		ret = par->fbtftops.write(par, par->buf, len + 1);
223		if (ret < 0) {
224			va_end(args);
225			dev_err(par->info->device,
226				"write() failed and returned %dn", ret);
227			return;
228		}
229	}
230	va_end(args);
231
232	/* restore user spi-speed */
233	par->fbtftops.write = fbtft_write_spi;
234	udelay(100);
235}
236
237static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len)
238{
239	u16 *vmem16;
240	__be16 *txbuf16;
241	size_t remain;
242	size_t to_copy;
243	size_t tx_array_size;
244	int i;
245	int ret = 0;
246	size_t startbyte_size = 0;
247
248	fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
249		      __func__, offset, len);
250
251	remain = len / 2;
252	vmem16 = (u16 *)(par->info->screen_buffer + offset);
253	tx_array_size = par->txbuf.len / 2;
254	txbuf16 = par->txbuf.buf + 1;
255	tx_array_size -= 2;
256	*(u8 *)(par->txbuf.buf) = 0x00;
257	startbyte_size = 1;
258
259	while (remain) {
260		to_copy = min(tx_array_size, remain);
261		dev_dbg(par->info->device, "    to_copy=%zu, remain=%zu\n",
262			to_copy, remain - to_copy);
263
264		for (i = 0; i < to_copy; i++)
265			txbuf16[i] = cpu_to_be16(vmem16[i]);
266
267		vmem16 = vmem16 + to_copy;
268		ret = par->fbtftops.write(par, par->txbuf.buf,
269			startbyte_size + to_copy * 2);
270		if (ret < 0)
271			return ret;
272		remain -= to_copy;
273	}
274
275	return ret;
276}
277
278static struct fbtft_display display = {
279	.regwidth = 8,
280	.fbtftops = {
281		.init_display = init_display,
282		.set_addr_win = set_addr_win,
283		.write_register = write_reg8_bus8,
284		.write_vmem = write_vmem16_bus8,
285		.write = write_spi,
286	},
287};
288
289FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display);
290
291MODULE_ALIAS("spi:" DRVNAME);
292MODULE_ALIAS("platform:" DRVNAME);
293MODULE_ALIAS("spi:ra8875");
294MODULE_ALIAS("platform:ra8875");
295
296MODULE_DESCRIPTION("FB driver for the RA8875 LCD Controller");
297MODULE_AUTHOR("Pf@nne");
298MODULE_LICENSE("GPL");