spi-zynqmp-gqspi.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
   4 * (host mode only)
   5 *
   6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
   7 */
   8
   9#include <linux/clk.h>
  10#include <linux/delay.h>
  11#include <linux/dma-mapping.h>
  12#include <linux/dmaengine.h>
  13#include <linux/firmware/xlnx-zynqmp.h>
  14#include <linux/interrupt.h>
  15#include <linux/io.h>
  16#include <linux/module.h>
  17#include <linux/of.h>
  18#include <linux/platform_device.h>
  19#include <linux/pm_runtime.h>
  20#include <linux/spi/spi.h>
  21#include <linux/spinlock.h>
  22#include <linux/workqueue.h>
  23#include <linux/spi/spi-mem.h>
  24
  25/* Generic QSPI register offsets */
  26#define GQSPI_CONFIG_OFST		0x00000100
  27#define GQSPI_ISR_OFST			0x00000104
  28#define GQSPI_IDR_OFST			0x0000010C
  29#define GQSPI_IER_OFST			0x00000108
  30#define GQSPI_IMASK_OFST		0x00000110
  31#define GQSPI_EN_OFST			0x00000114
  32#define GQSPI_TXD_OFST			0x0000011C
  33#define GQSPI_RXD_OFST			0x00000120
  34#define GQSPI_TX_THRESHOLD_OFST		0x00000128
  35#define GQSPI_RX_THRESHOLD_OFST		0x0000012C
  36#define IOU_TAPDLY_BYPASS_OFST		0x0000003C
  37#define GQSPI_LPBK_DLY_ADJ_OFST		0x00000138
  38#define GQSPI_GEN_FIFO_OFST		0x00000140
  39#define GQSPI_SEL_OFST			0x00000144
  40#define GQSPI_GF_THRESHOLD_OFST		0x00000150
  41#define GQSPI_FIFO_CTRL_OFST		0x0000014C
  42#define GQSPI_QSPIDMA_DST_CTRL_OFST	0x0000080C
  43#define GQSPI_QSPIDMA_DST_SIZE_OFST	0x00000804
  44#define GQSPI_QSPIDMA_DST_STS_OFST	0x00000808
  45#define GQSPI_QSPIDMA_DST_I_STS_OFST	0x00000814
  46#define GQSPI_QSPIDMA_DST_I_EN_OFST	0x00000818
  47#define GQSPI_QSPIDMA_DST_I_DIS_OFST	0x0000081C
  48#define GQSPI_QSPIDMA_DST_I_MASK_OFST	0x00000820
  49#define GQSPI_QSPIDMA_DST_ADDR_OFST	0x00000800
  50#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
  51#define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
  52
  53/* GQSPI register bit masks */
  54#define GQSPI_SEL_MASK				0x00000001
  55#define GQSPI_EN_MASK				0x00000001
  56#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK	0x00000020
  57#define GQSPI_ISR_WR_TO_CLR_MASK		0x00000002
  58#define GQSPI_IDR_ALL_MASK			0x00000FBE
  59#define GQSPI_CFG_MODE_EN_MASK			0xC0000000
  60#define GQSPI_CFG_GEN_FIFO_START_MODE_MASK	0x20000000
  61#define GQSPI_CFG_ENDIAN_MASK			0x04000000
  62#define GQSPI_CFG_EN_POLL_TO_MASK		0x00100000
  63#define GQSPI_CFG_WP_HOLD_MASK			0x00080000
  64#define GQSPI_CFG_BAUD_RATE_DIV_MASK		0x00000038
  65#define GQSPI_CFG_CLK_PHA_MASK			0x00000004
  66#define GQSPI_CFG_CLK_POL_MASK			0x00000002
  67#define GQSPI_CFG_START_GEN_FIFO_MASK		0x10000000
  68#define GQSPI_GENFIFO_IMM_DATA_MASK		0x000000FF
  69#define GQSPI_GENFIFO_DATA_XFER			0x00000100
  70#define GQSPI_GENFIFO_EXP			0x00000200
  71#define GQSPI_GENFIFO_MODE_SPI			0x00000400
  72#define GQSPI_GENFIFO_MODE_DUALSPI		0x00000800
  73#define GQSPI_GENFIFO_MODE_QUADSPI		0x00000C00
  74#define GQSPI_GENFIFO_MODE_MASK			0x00000C00
  75#define GQSPI_GENFIFO_CS_LOWER			0x00001000
  76#define GQSPI_GENFIFO_CS_UPPER			0x00002000
  77#define GQSPI_GENFIFO_BUS_LOWER			0x00004000
  78#define GQSPI_GENFIFO_BUS_UPPER			0x00008000
  79#define GQSPI_GENFIFO_BUS_BOTH			0x0000C000
  80#define GQSPI_GENFIFO_BUS_MASK			0x0000C000
  81#define GQSPI_GENFIFO_TX			0x00010000
  82#define GQSPI_GENFIFO_RX			0x00020000
  83#define GQSPI_GENFIFO_STRIPE			0x00040000
  84#define GQSPI_GENFIFO_POLL			0x00080000
  85#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK	0x00000004
  86#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK	0x00000002
  87#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK	0x00000001
  88#define GQSPI_ISR_RXEMPTY_MASK			0x00000800
  89#define GQSPI_ISR_GENFIFOFULL_MASK		0x00000400
  90#define GQSPI_ISR_GENFIFONOT_FULL_MASK		0x00000200
  91#define GQSPI_ISR_TXEMPTY_MASK			0x00000100
  92#define GQSPI_ISR_GENFIFOEMPTY_MASK		0x00000080
  93#define GQSPI_ISR_RXFULL_MASK			0x00000020
  94#define GQSPI_ISR_RXNEMPTY_MASK			0x00000010
  95#define GQSPI_ISR_TXFULL_MASK			0x00000008
  96#define GQSPI_ISR_TXNOT_FULL_MASK		0x00000004
  97#define GQSPI_ISR_POLL_TIME_EXPIRE_MASK		0x00000002
  98#define GQSPI_IER_TXNOT_FULL_MASK		0x00000004
  99#define GQSPI_IER_RXEMPTY_MASK			0x00000800
 100#define GQSPI_IER_POLL_TIME_EXPIRE_MASK		0x00000002
 101#define GQSPI_IER_RXNEMPTY_MASK			0x00000010
 102#define GQSPI_IER_GENFIFOEMPTY_MASK		0x00000080
 103#define GQSPI_IER_TXEMPTY_MASK			0x00000100
 104#define GQSPI_QSPIDMA_DST_INTR_ALL_MASK		0x000000FE
 105#define GQSPI_QSPIDMA_DST_STS_WTC		0x0000E000
 106#define GQSPI_CFG_MODE_EN_DMA_MASK		0x80000000
 107#define GQSPI_ISR_IDR_MASK			0x00000994
 108#define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK	0x00000002
 109#define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK	0x00000002
 110#define GQSPI_IRQ_MASK				0x00000980
 111
 112#define GQSPI_CFG_BAUD_RATE_DIV_SHIFT		3
 113#define GQSPI_GENFIFO_CS_SETUP			0x4
 114#define GQSPI_GENFIFO_CS_HOLD			0x3
 115#define GQSPI_TXD_DEPTH				64
 116#define GQSPI_RX_FIFO_THRESHOLD			32
 117#define GQSPI_RX_FIFO_FILL	(GQSPI_RX_FIFO_THRESHOLD * 4)
 118#define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL	32
 119#define GQSPI_TX_FIFO_FILL	(GQSPI_TXD_DEPTH -\
 120				GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
 121#define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL	0X10
 122#define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL	0x803FFA00
 123#define GQSPI_SELECT_FLASH_CS_LOWER		0x1
 124#define GQSPI_SELECT_FLASH_CS_UPPER		0x2
 125#define GQSPI_SELECT_FLASH_CS_BOTH		0x3
 126#define GQSPI_SELECT_FLASH_BUS_LOWER		0x1
 127#define GQSPI_SELECT_FLASH_BUS_UPPER		0x2
 128#define GQSPI_SELECT_FLASH_BUS_BOTH		0x3
 129#define GQSPI_BAUD_DIV_MAX	7	/* Baud rate divisor maximum */
 130#define GQSPI_BAUD_DIV_SHIFT	2	/* Baud rate divisor shift */
 131#define GQSPI_SELECT_MODE_SPI		0x1
 132#define GQSPI_SELECT_MODE_DUALSPI	0x2
 133#define GQSPI_SELECT_MODE_QUADSPI	0x4
 134#define GQSPI_DMA_UNALIGN		0x3
 135#define GQSPI_DEFAULT_NUM_CS	1	/* Default number of chip selects */
 136
 137#define GQSPI_MAX_NUM_CS	2	/* Maximum number of chip selects */
 138
 139#define GQSPI_USE_DATA_DLY		0x1
 140#define GQSPI_USE_DATA_DLY_SHIFT	31
 141#define GQSPI_DATA_DLY_ADJ_VALUE	0x2
 142#define GQSPI_DATA_DLY_ADJ_SHIFT	28
 143#define GQSPI_LPBK_DLY_ADJ_DLY_1	0x1
 144#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT	0x3
 145#define TAP_DLY_BYPASS_LQSPI_RX_VALUE	0x1
 146#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT	0x2
 147
 148/* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
 149#define QSPI_QUIRK_HAS_TAPDELAY		BIT(0)
 150
 151#define GQSPI_FREQ_37_5MHZ	37500000
 152#define GQSPI_FREQ_40MHZ	40000000
 153#define GQSPI_FREQ_100MHZ	100000000
 154#define GQSPI_FREQ_150MHZ	150000000
 155
 156#define SPI_AUTOSUSPEND_TIMEOUT		3000
 157enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
 158
 159/**
 160 * struct qspi_platform_data - zynqmp qspi platform data structure
 161 * @quirks:    Flags is used to identify the platform
 162 */
 163struct qspi_platform_data {
 164	u32 quirks;
 165};
 166
 167/**
 168 * struct zynqmp_qspi - Defines qspi driver instance
 169 * @ctlr:		Pointer to the spi controller information
 170 * @regs:		Virtual address of the QSPI controller registers
 171 * @refclk:		Pointer to the peripheral clock
 172 * @pclk:		Pointer to the APB clock
 173 * @irq:		IRQ number
 174 * @dev:		Pointer to struct device
 175 * @txbuf:		Pointer to the TX buffer
 176 * @rxbuf:		Pointer to the RX buffer
 177 * @bytes_to_transfer:	Number of bytes left to transfer
 178 * @bytes_to_receive:	Number of bytes left to receive
 179 * @genfifocs:		Used for chip select
 180 * @genfifobus:		Used to select the upper or lower bus
 181 * @dma_rx_bytes:	Remaining bytes to receive by DMA mode
 182 * @dma_addr:		DMA address after mapping the kernel buffer
 183 * @genfifoentry:	Used for storing the genfifoentry instruction.
 184 * @mode:		Defines the mode in which QSPI is operating
 185 * @data_completion:	completion structure
 186 * @op_lock:		Operational lock
 187 * @speed_hz:          Current SPI bus clock speed in hz
 188 * @has_tapdelay:	Used for tapdelay register available in qspi
 189 */
 190struct zynqmp_qspi {
 191	struct spi_controller *ctlr;
 192	void __iomem *regs;
 193	struct clk *refclk;
 194	struct clk *pclk;
 195	int irq;
 196	struct device *dev;
 197	const void *txbuf;
 198	void *rxbuf;
 199	int bytes_to_transfer;
 200	int bytes_to_receive;
 201	u32 genfifocs;
 202	u32 genfifobus;
 203	u32 dma_rx_bytes;
 204	dma_addr_t dma_addr;
 205	u32 genfifoentry;
 206	enum mode_type mode;
 207	struct completion data_completion;
 208	struct mutex op_lock;
 209	u32 speed_hz;
 210	bool has_tapdelay;
 211};
 212
 213/**
 214 * zynqmp_gqspi_read - For GQSPI controller read operation
 215 * @xqspi:	Pointer to the zynqmp_qspi structure
 216 * @offset:	Offset from where to read
 217 * Return:      Value at the offset
 218 */
 219static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
 220{
 221	return readl_relaxed(xqspi->regs + offset);
 222}
 223
 224/**
 225 * zynqmp_gqspi_write - For GQSPI controller write operation
 226 * @xqspi:	Pointer to the zynqmp_qspi structure
 227 * @offset:	Offset where to write
 228 * @val:	Value to be written
 229 */
 230static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
 231				      u32 val)
 232{
 233	writel_relaxed(val, (xqspi->regs + offset));
 234}
 235
 236/**
 237 * zynqmp_gqspi_selecttarget - For selection of target device
 238 * @instanceptr:	Pointer to the zynqmp_qspi structure
 239 * @targetcs:	For chip select
 240 * @targetbus:	To check which bus is selected- upper or lower
 241 */
 242static void zynqmp_gqspi_selecttarget(struct zynqmp_qspi *instanceptr,
 243				      u8 targetcs, u8 targetbus)
 244{
 245	/*
 246	 * Bus and CS lines selected here will be updated in the instance and
 247	 * used for subsequent GENFIFO entries during transfer.
 248	 */
 249
 250	/* Choose target select line */
 251	switch (targetcs) {
 252	case GQSPI_SELECT_FLASH_CS_BOTH:
 253		instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
 254			GQSPI_GENFIFO_CS_UPPER;
 255		break;
 256	case GQSPI_SELECT_FLASH_CS_UPPER:
 257		instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
 258		break;
 259	case GQSPI_SELECT_FLASH_CS_LOWER:
 260		instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 261		break;
 262	default:
 263		dev_warn(instanceptr->dev, "Invalid target select\n");
 264	}
 265
 266	/* Choose the bus */
 267	switch (targetbus) {
 268	case GQSPI_SELECT_FLASH_BUS_BOTH:
 269		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
 270			GQSPI_GENFIFO_BUS_UPPER;
 271		break;
 272	case GQSPI_SELECT_FLASH_BUS_UPPER:
 273		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
 274		break;
 275	case GQSPI_SELECT_FLASH_BUS_LOWER:
 276		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 277		break;
 278	default:
 279		dev_warn(instanceptr->dev, "Invalid target bus\n");
 280	}
 281}
 282
 283/**
 284 * zynqmp_qspi_set_tapdelay:   To configure qspi tap delays
 285 * @xqspi:             Pointer to the zynqmp_qspi structure
 286 * @baudrateval:       Buadrate to configure
 287 */
 288static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
 289{
 290	u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 291	u32 reqhz = 0;
 292
 293	clk_rate = clk_get_rate(xqspi->refclk);
 294	reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 295
 296	if (!xqspi->has_tapdelay) {
 297		if (reqhz <= GQSPI_FREQ_40MHZ) {
 298			zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
 299						      PM_TAPDELAY_BYPASS_ENABLE);
 300		} else if (reqhz <= GQSPI_FREQ_100MHZ) {
 301			zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
 302						      PM_TAPDELAY_BYPASS_ENABLE);
 303			lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 304			datadlyadj |= ((GQSPI_USE_DATA_DLY <<
 305					GQSPI_USE_DATA_DLY_SHIFT)
 306					| (GQSPI_DATA_DLY_ADJ_VALUE <<
 307						GQSPI_DATA_DLY_ADJ_SHIFT));
 308		} else if (reqhz <= GQSPI_FREQ_150MHZ) {
 309			lpbkdlyadj |= GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK;
 310		}
 311	} else {
 312		if (reqhz <= GQSPI_FREQ_37_5MHZ) {
 313			tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 314					TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 315		} else if (reqhz <= GQSPI_FREQ_100MHZ) {
 316			tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 317					TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 318			lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
 319			datadlyadj |= (GQSPI_USE_DATA_DLY <<
 320					GQSPI_USE_DATA_DLY_SHIFT);
 321		} else if (reqhz <= GQSPI_FREQ_150MHZ) {
 322			lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK
 323				       | (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
 324					       GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT));
 325		}
 326		zynqmp_gqspi_write(xqspi,
 327				   IOU_TAPDLY_BYPASS_OFST, tapdlybypass);
 328	}
 329	zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);
 330	zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);
 331}
 332
 333/**
 334 * zynqmp_qspi_init_hw - Initialize the hardware
 335 * @xqspi:	Pointer to the zynqmp_qspi structure
 336 *
 337 * The default settings of the QSPI controller's configurable parameters on
 338 * reset are
 339 *	- Host mode
 340 *	- TX threshold set to 1
 341 *	- RX threshold set to 1
 342 *	- Flash memory interface mode enabled
 343 * This function performs the following actions
 344 *	- Disable and clear all the interrupts
 345 *	- Enable manual target select
 346 *	- Enable manual start
 347 *	- Deselect all the chip select lines
 348 *	- Set the little endian mode of TX FIFO
 349 *	- Set clock phase
 350 *	- Set clock polarity and
 351 *	- Enable the QSPI controller
 352 */
 353static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
 354{
 355	u32 config_reg, baud_rate_val = 0;
 356	ulong clk_rate;
 357
 358	/* Select the GQSPI mode */
 359	zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
 360	/* Clear and disable interrupts */
 361	zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
 362			   zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
 363			   GQSPI_ISR_WR_TO_CLR_MASK);
 364	/* Clear the DMA STS */
 365	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 366			   zynqmp_gqspi_read(xqspi,
 367					     GQSPI_QSPIDMA_DST_I_STS_OFST));
 368	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
 369			   zynqmp_gqspi_read(xqspi,
 370					     GQSPI_QSPIDMA_DST_STS_OFST) |
 371					     GQSPI_QSPIDMA_DST_STS_WTC);
 372	zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
 373	zynqmp_gqspi_write(xqspi,
 374			   GQSPI_QSPIDMA_DST_I_DIS_OFST,
 375			   GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
 376	/* Disable the GQSPI */
 377	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 378	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 379	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 380	/* Manual start */
 381	config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
 382	/* Little endian by default */
 383	config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
 384	/* Disable poll time out */
 385	config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
 386	/* Set hold bit */
 387	config_reg |= GQSPI_CFG_WP_HOLD_MASK;
 388	/* Clear pre-scalar by default */
 389	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 390	/* Set CPHA */
 391	if (xqspi->ctlr->mode_bits & SPI_CPHA)
 392		config_reg |= GQSPI_CFG_CLK_PHA_MASK;
 393	else
 394		config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
 395	/* Set CPOL */
 396	if (xqspi->ctlr->mode_bits & SPI_CPOL)
 397		config_reg |= GQSPI_CFG_CLK_POL_MASK;
 398	else
 399		config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
 400
 401	/* Set the clock frequency */
 402	clk_rate = clk_get_rate(xqspi->refclk);
 403	while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
 404	       (clk_rate /
 405		(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz)
 406		baud_rate_val++;
 407
 408	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 409	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
 410
 411	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 412
 413	/* Set the tapdelay for clock frequency */
 414	zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
 415
 416	/* Clear the TX and RX FIFO */
 417	zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
 418			   GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
 419			   GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
 420			   GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
 421	/* Reset thresholds */
 422	zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
 423			   GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
 424	zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
 425			   GQSPI_RX_FIFO_THRESHOLD);
 426	zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
 427			   GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
 428	zynqmp_gqspi_selecttarget(xqspi,
 429				  GQSPI_SELECT_FLASH_CS_LOWER,
 430				  GQSPI_SELECT_FLASH_BUS_LOWER);
 431	/* Initialize DMA */
 432	zynqmp_gqspi_write(xqspi,
 433			   GQSPI_QSPIDMA_DST_CTRL_OFST,
 434			   GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
 435
 436	/* Enable the GQSPI */
 437	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 438}
 439
 440/**
 441 * zynqmp_qspi_copy_read_data - Copy data to RX buffer
 442 * @xqspi:	Pointer to the zynqmp_qspi structure
 443 * @data:	The variable where data is stored
 444 * @size:	Number of bytes to be copied from data to RX buffer
 445 */
 446static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
 447				       ulong data, u8 size)
 448{
 449	memcpy(xqspi->rxbuf, &data, size);
 450	xqspi->rxbuf += size;
 451	xqspi->bytes_to_receive -= size;
 452}
 453
 454/**
 455 * zynqmp_qspi_chipselect - Select or deselect the chip select line
 456 * @qspi:	Pointer to the spi_device structure
 457 * @is_high:	Select(0) or deselect (1) the chip select line
 458 */
 459static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
 460{
 461	struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller);
 462	ulong timeout;
 463	u32 genfifoentry = 0, statusreg;
 464
 465	genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
 466
 467	if (!is_high) {
 468		if (!spi_get_chipselect(qspi, 0)) {
 469			xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
 470			xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
 471		} else {
 472			xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
 473			xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
 474		}
 475		genfifoentry |= xqspi->genfifobus;
 476		genfifoentry |= xqspi->genfifocs;
 477		genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
 478	} else {
 479		genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
 480	}
 481
 482	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 483
 484	/* Manually start the generic FIFO command */
 485	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 486			   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
 487			   GQSPI_CFG_START_GEN_FIFO_MASK);
 488
 489	timeout = jiffies + msecs_to_jiffies(1000);
 490
 491	/* Wait until the generic FIFO command is empty */
 492	do {
 493		statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 494
 495		if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
 496		    (statusreg & GQSPI_ISR_TXEMPTY_MASK))
 497			break;
 498		cpu_relax();
 499	} while (!time_after_eq(jiffies, timeout));
 500
 501	if (time_after_eq(jiffies, timeout))
 502		dev_err(xqspi->dev, "Chip select timed out\n");
 503}
 504
 505/**
 506 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
 507 * @xqspi:	xqspi is a pointer to the GQSPI instance
 508 * @spimode:	spimode - SPI or DUAL or QUAD.
 509 * Return:	Mask to set desired SPI mode in GENFIFO entry.
 510 */
 511static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
 512					    u8 spimode)
 513{
 514	u32 mask = 0;
 515
 516	switch (spimode) {
 517	case GQSPI_SELECT_MODE_DUALSPI:
 518		mask = GQSPI_GENFIFO_MODE_DUALSPI;
 519		break;
 520	case GQSPI_SELECT_MODE_QUADSPI:
 521		mask = GQSPI_GENFIFO_MODE_QUADSPI;
 522		break;
 523	case GQSPI_SELECT_MODE_SPI:
 524		mask = GQSPI_GENFIFO_MODE_SPI;
 525		break;
 526	default:
 527		dev_warn(xqspi->dev, "Invalid SPI mode\n");
 528	}
 529
 530	return mask;
 531}
 532
 533/**
 534 * zynqmp_qspi_config_op - Configure QSPI controller for specified
 535 *				transfer
 536 * @xqspi:	Pointer to the zynqmp_qspi structure
 537 * @op:		The memory operation to execute
 538 *
 539 * Sets the operational mode of QSPI controller for the next QSPI transfer and
 540 * sets the requested clock frequency.
 541 *
 542 * Return:	Always 0
 543 *
 544 * Note:
 545 *	If the requested frequency is not an exact match with what can be
 546 *	obtained using the pre-scalar value, the driver sets the clock
 547 *	frequency which is lower than the requested frequency (maximum lower)
 548 *	for the transfer.
 549 *
 550 *	If the requested frequency is higher or lower than that is supported
 551 *	by the QSPI controller the driver will set the highest or lowest
 552 *	frequency supported by controller.
 553 */
 554static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
 555				 const struct spi_mem_op *op)
 556{
 557	ulong clk_rate;
 558	u32 config_reg, req_speed_hz, baud_rate_val = 0;
 559
 560	req_speed_hz = op->max_freq;
 561
 562	if (xqspi->speed_hz != req_speed_hz) {
 563		xqspi->speed_hz = req_speed_hz;
 564
 565		/* Set the clock frequency */
 566		/* If req_speed_hz == 0, default to lowest speed */
 567		clk_rate = clk_get_rate(xqspi->refclk);
 568
 569		while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
 570		       (clk_rate /
 571			(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) >
 572		       req_speed_hz)
 573			baud_rate_val++;
 574
 575		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 576
 577		config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
 578		config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
 579		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 580		zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
 581	}
 582
 583	dev_dbg(xqspi->dev, "config speed %u\n", req_speed_hz);
 584	return 0;
 585}
 586
 587/**
 588 * zynqmp_qspi_setup_op - Configure the QSPI controller
 589 * @qspi:	Pointer to the spi_device structure
 590 *
 591 * Sets the operational mode of QSPI controller for the next QSPI transfer,
 592 * baud rate and divisor value to setup the requested qspi clock.
 593 *
 594 * Return:	0 on success; error value otherwise.
 595 */
 596static int zynqmp_qspi_setup_op(struct spi_device *qspi)
 597{
 598	struct spi_controller *ctlr = qspi->controller;
 599	struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
 600
 601	if (ctlr->busy)
 602		return -EBUSY;
 603
 604	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 605
 606	return 0;
 607}
 608
 609/**
 610 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
 611 *				the FIFO or the bytes required to be
 612 *				transmitted.
 613 * @xqspi:	Pointer to the zynqmp_qspi structure
 614 * @size:	Number of bytes to be copied from TX buffer to TX FIFO
 615 */
 616static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
 617{
 618	u32 count = 0, intermediate;
 619
 620	while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
 621		if (xqspi->bytes_to_transfer >= 4) {
 622			memcpy(&intermediate, xqspi->txbuf, 4);
 623			xqspi->txbuf += 4;
 624			xqspi->bytes_to_transfer -= 4;
 625			count += 4;
 626		} else {
 627			memcpy(&intermediate, xqspi->txbuf,
 628			       xqspi->bytes_to_transfer);
 629			xqspi->txbuf += xqspi->bytes_to_transfer;
 630			xqspi->bytes_to_transfer = 0;
 631			count += xqspi->bytes_to_transfer;
 632		}
 633		zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
 634	}
 635}
 636
 637/**
 638 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
 639 *				the FIFO.
 640 * @xqspi:	Pointer to the zynqmp_qspi structure
 641 * @size:	Number of bytes to be copied from RX buffer to RX FIFO
 642 */
 643static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
 644{
 645	ulong data;
 646	int count = 0;
 647
 648	while ((count < size) && (xqspi->bytes_to_receive > 0)) {
 649		if (xqspi->bytes_to_receive >= 4) {
 650			(*(u32 *)xqspi->rxbuf) =
 651			zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 652			xqspi->rxbuf += 4;
 653			xqspi->bytes_to_receive -= 4;
 654			count += 4;
 655		} else {
 656			data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
 657			count += xqspi->bytes_to_receive;
 658			zynqmp_qspi_copy_read_data(xqspi, data,
 659						   xqspi->bytes_to_receive);
 660			xqspi->bytes_to_receive = 0;
 661		}
 662	}
 663}
 664
 665/**
 666 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
 667 * @xqspi:	Pointer to the zynqmp_qspi structure
 668 * @nbits:	Transfer/Receive buswidth.
 669 * @genfifoentry:       Variable in which GENFIFO mask is saved
 670 */
 671static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
 672				    u32 genfifoentry)
 673{
 674	u32 transfer_len, tempcount, exponent;
 675	u8 imm_data;
 676
 677	genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
 678	if (xqspi->rxbuf) {
 679		genfifoentry |= GQSPI_GENFIFO_RX;
 680		if (xqspi->mode == GQSPI_MODE_DMA)
 681			transfer_len = xqspi->dma_rx_bytes;
 682		else
 683			transfer_len = xqspi->bytes_to_receive;
 684	} else {
 685		transfer_len = xqspi->bytes_to_transfer;
 686	}
 687
 688	if (xqspi->txbuf)
 689		genfifoentry |= GQSPI_GENFIFO_TX;
 690
 691	genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
 692	xqspi->genfifoentry = genfifoentry;
 693	dev_dbg(xqspi->dev, "genfifo %05x transfer_len %u\n",
 694		genfifoentry, transfer_len);
 695
 696	/* Exponent entries */
 697	imm_data = transfer_len;
 698	tempcount = transfer_len >> 8;
 699	exponent = 8;
 700	genfifoentry |= GQSPI_GENFIFO_EXP;
 701	while (tempcount) {
 702		if (tempcount & 1)
 703			zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
 704					   genfifoentry | exponent);
 705		tempcount >>= 1;
 706		exponent++;
 707	}
 708
 709	/* Immediate entry */
 710	genfifoentry &= ~GQSPI_GENFIFO_EXP;
 711	if (imm_data)
 712		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
 713				   genfifoentry | imm_data);
 714
 715	/* Dummy generic FIFO entry */
 716	if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf)
 717		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0);
 718}
 719
 720/**
 721 * zynqmp_qspi_disable_dma() - Disable DMA mode
 722 * @xqspi: GQSPI instance
 723 */
 724static void zynqmp_qspi_disable_dma(struct zynqmp_qspi *xqspi)
 725{
 726	u32 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 727
 728	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 729	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 730	xqspi->mode = GQSPI_MODE_IO;
 731}
 732
 733/**
 734 * zynqmp_qspi_enable_dma() - Enable DMA mode
 735 * @xqspi: GQSPI instance
 736 */
 737static void zynqmp_qspi_enable_dma(struct zynqmp_qspi *xqspi)
 738{
 739	u32 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
 740
 741	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
 742	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
 743	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
 744	xqspi->mode = GQSPI_MODE_DMA;
 745}
 746
 747/**
 748 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
 749 *				controller
 750 * @xqspi:	zynqmp_qspi instance pointer
 751 *
 752 * This function handles DMA interrupt only.
 753 */
 754static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
 755{
 756	u32 genfifoentry;
 757
 758	dma_unmap_single(xqspi->dev, xqspi->dma_addr,
 759			 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
 760	xqspi->rxbuf += xqspi->dma_rx_bytes;
 761	xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
 762	xqspi->dma_rx_bytes = 0;
 763
 764	/* Disabling the DMA interrupts */
 765	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
 766			   GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
 767
 768	if (xqspi->bytes_to_receive > 0) {
 769		/* Switch to IO mode,for remaining bytes to receive */
 770		zynqmp_qspi_disable_dma(xqspi);
 771
 772		/* Initiate the transfer of remaining bytes */
 773		genfifoentry = xqspi->genfifoentry;
 774		genfifoentry |= xqspi->bytes_to_receive;
 775		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
 776
 777		/* Dummy generic FIFO entry */
 778		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
 779
 780		/* Manual start */
 781		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
 782				   (zynqmp_gqspi_read(xqspi,
 783						      GQSPI_CONFIG_OFST) |
 784				   GQSPI_CFG_START_GEN_FIFO_MASK));
 785
 786		/* Enable the RX interrupts for IO mode */
 787		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
 788				   GQSPI_IER_GENFIFOEMPTY_MASK |
 789				   GQSPI_IER_RXNEMPTY_MASK |
 790				   GQSPI_IER_RXEMPTY_MASK);
 791	}
 792}
 793
 794/**
 795 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
 796 * @irq:	IRQ number
 797 * @dev_id:	Pointer to the xqspi structure
 798 *
 799 * This function handles TX empty only.
 800 * On TX empty interrupt this function reads the received data from RX FIFO
 801 * and fills the TX FIFO if there is any data remaining to be transferred.
 802 *
 803 * Return:	IRQ_HANDLED when interrupt is handled
 804 *		IRQ_NONE otherwise.
 805 */
 806static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
 807{
 808	struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
 809	u32 status, mask, dma_status = 0;
 810
 811	status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
 812	zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
 813	mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
 814
 815	/* Read and clear DMA status */
 816	if (xqspi->mode == GQSPI_MODE_DMA) {
 817		dma_status =
 818			zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
 819		zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
 820				   dma_status);
 821	}
 822
 823	if (!mask && !dma_status)
 824		return IRQ_NONE;
 825
 826	if (mask & GQSPI_ISR_TXNOT_FULL_MASK)
 827		zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
 828
 829	if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK)
 830		zynqmp_process_dma_irq(xqspi);
 831	else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
 832			(mask & GQSPI_IER_GENFIFOEMPTY_MASK))
 833		zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
 834
 835	if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
 836	    ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
 837		zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
 838		complete(&xqspi->data_completion);
 839	}
 840	return IRQ_HANDLED;
 841}
 842
 843/**
 844 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
 845 * @xqspi:	xqspi is a pointer to the GQSPI instance.
 846 *
 847 * Return:	0 on success; error value otherwise.
 848 */
 849static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
 850{
 851	u32 rx_bytes, rx_rem;
 852	dma_addr_t addr;
 853	u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
 854
 855	if (xqspi->bytes_to_receive < 8 ||
 856	    ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
 857		/* Setting to IO mode */
 858		zynqmp_qspi_disable_dma(xqspi);
 859		xqspi->dma_rx_bytes = 0;
 860		return 0;
 861	}
 862
 863	rx_rem = xqspi->bytes_to_receive % 4;
 864	rx_bytes = (xqspi->bytes_to_receive - rx_rem);
 865
 866	addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
 867			      rx_bytes, DMA_FROM_DEVICE);
 868	if (dma_mapping_error(xqspi->dev, addr)) {
 869		dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
 870		return -ENOMEM;
 871	}
 872
 873	xqspi->dma_rx_bytes = rx_bytes;
 874	xqspi->dma_addr = addr;
 875	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
 876			   (u32)(addr & 0xffffffff));
 877	addr = ((addr >> 16) >> 16);
 878	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
 879			   ((u32)addr) & 0xfff);
 880
 881	zynqmp_qspi_enable_dma(xqspi);
 882
 883	/* Write the number of bytes to transfer */
 884	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
 885
 886	return 0;
 887}
 888
 889/**
 890 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
 891 *			TX FIFO, and fills the TX FIFO with as many
 892 *			bytes as possible.
 893 * @xqspi:	Pointer to the GQSPI instance.
 894 * @tx_nbits:	Transfer buswidth.
 895 * @genfifoentry:	Variable in which GENFIFO mask is returned
 896 *			to calling function
 897 */
 898static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
 899				 u32 genfifoentry)
 900{
 901	zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
 902	zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
 903	if (xqspi->mode == GQSPI_MODE_DMA)
 904		zynqmp_qspi_disable_dma(xqspi);
 905}
 906
 907/**
 908 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
 909 *				RX DMA operation.
 910 * @xqspi:	xqspi is a pointer to the GQSPI instance.
 911 * @rx_nbits:	Receive buswidth.
 912 * @genfifoentry:	genfifoentry is pointer to the variable in which
 913 *			GENFIFO	mask is returned to calling function
 914 *
 915 * Return:	0 on success; error value otherwise.
 916 */
 917static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
 918				u32 genfifoentry)
 919{
 920	int ret;
 921
 922	ret = zynqmp_qspi_setuprxdma(xqspi);
 923	if (ret)
 924		return ret;
 925	zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
 926
 927	return 0;
 928}
 929
 930/**
 931 * zynqmp_qspi_suspend - Suspend method for the QSPI driver
 932 * @dev:	Address of the platform_device structure
 933 *
 934 * This function stops the QSPI driver queue and disables the QSPI controller
 935 *
 936 * Return:	Always 0
 937 */
 938static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
 939{
 940	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
 941	struct spi_controller *ctlr = xqspi->ctlr;
 942	int ret;
 943
 944	ret = spi_controller_suspend(ctlr);
 945	if (ret)
 946		return ret;
 947
 948	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
 949
 950	return 0;
 951}
 952
 953/**
 954 * zynqmp_qspi_resume - Resume method for the QSPI driver
 955 * @dev:	Address of the platform_device structure
 956 *
 957 * The function starts the QSPI driver queue and initializes the QSPI
 958 * controller
 959 *
 960 * Return:	0 on success; error value otherwise
 961 */
 962static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
 963{
 964	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
 965	struct spi_controller *ctlr = xqspi->ctlr;
 966
 967	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
 968
 969	spi_controller_resume(ctlr);
 970
 971	return 0;
 972}
 973
 974/**
 975 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
 976 * @dev:	Address of the platform_device structure
 977 *
 978 * This function disables the clocks
 979 *
 980 * Return:	Always 0
 981 */
 982static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
 983{
 984	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
 985
 986	clk_disable_unprepare(xqspi->refclk);
 987	clk_disable_unprepare(xqspi->pclk);
 988
 989	return 0;
 990}
 991
 992/**
 993 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
 994 * @dev:	Address of the platform_device structure
 995 *
 996 * This function enables the clocks
 997 *
 998 * Return:	0 on success and error value on error
 999 */
1000static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
1001{
1002	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
1003	int ret;
1004
1005	ret = clk_prepare_enable(xqspi->pclk);
1006	if (ret) {
1007		dev_err(dev, "Cannot enable APB clock.\n");
1008		return ret;
1009	}
1010
1011	ret = clk_prepare_enable(xqspi->refclk);
1012	if (ret) {
1013		dev_err(dev, "Cannot enable device clock.\n");
1014		clk_disable_unprepare(xqspi->pclk);
1015		return ret;
1016	}
1017
1018	return 0;
1019}
1020
1021static unsigned long zynqmp_qspi_timeout(struct zynqmp_qspi *xqspi, u8 bits,
1022					 unsigned long bytes)
1023{
1024	unsigned long timeout;
1025
1026	/* Assume we are at most 2x slower than the nominal bus speed */
1027	timeout = mult_frac(bytes, 2 * 8 * MSEC_PER_SEC,
1028			    bits * xqspi->speed_hz);
1029	/* And add 100 ms for scheduling delays */
1030	return msecs_to_jiffies(timeout + 100);
1031}
1032
1033/**
1034 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
1035 * @mem: The SPI memory
1036 * @op: The memory operation to execute
1037 *
1038 * Executes a memory operation.
1039 *
1040 * This function first selects the chip and starts the memory operation.
1041 *
1042 * Return: 0 in case of success, a negative error code otherwise.
1043 */
1044static int zynqmp_qspi_exec_op(struct spi_mem *mem,
1045			       const struct spi_mem_op *op)
1046{
1047	struct zynqmp_qspi *xqspi =
1048		spi_controller_get_devdata(mem->spi->controller);
1049	unsigned long timeout;
1050	int err = 0, i;
1051	u32 genfifoentry = 0;
1052	u16 opcode = op->cmd.opcode;
1053	u64 opaddr;
1054
1055	mutex_lock(&xqspi->op_lock);
1056	zynqmp_qspi_config_op(xqspi, op);
1057	zynqmp_qspi_chipselect(mem->spi, false);
1058	genfifoentry |= xqspi->genfifocs;
1059	genfifoentry |= xqspi->genfifobus;
1060
1061	if (op->cmd.opcode) {
1062		reinit_completion(&xqspi->data_completion);
1063		xqspi->txbuf = &opcode;
1064		xqspi->rxbuf = NULL;
1065		xqspi->bytes_to_transfer = op->cmd.nbytes;
1066		xqspi->bytes_to_receive = 0;
1067		zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
1068		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1069				   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1070				   GQSPI_CFG_START_GEN_FIFO_MASK);
1071		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1072				   GQSPI_IER_GENFIFOEMPTY_MASK |
1073				   GQSPI_IER_TXNOT_FULL_MASK);
1074		timeout = zynqmp_qspi_timeout(xqspi, op->cmd.buswidth,
1075					      op->cmd.nbytes);
1076		if (!wait_for_completion_timeout(&xqspi->data_completion,
1077						 timeout)) {
1078			err = -ETIMEDOUT;
1079			goto return_err;
1080		}
1081	}
1082
1083	if (op->addr.nbytes) {
1084		xqspi->txbuf = &opaddr;
1085		for (i = 0; i < op->addr.nbytes; i++) {
1086			*(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
1087					(8 * (op->addr.nbytes - i - 1));
1088		}
1089
1090		reinit_completion(&xqspi->data_completion);
1091		xqspi->rxbuf = NULL;
1092		xqspi->bytes_to_transfer = op->addr.nbytes;
1093		xqspi->bytes_to_receive = 0;
1094		zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
1095		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1096				   zynqmp_gqspi_read(xqspi,
1097						     GQSPI_CONFIG_OFST) |
1098				   GQSPI_CFG_START_GEN_FIFO_MASK);
1099		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1100				   GQSPI_IER_TXEMPTY_MASK |
1101				   GQSPI_IER_GENFIFOEMPTY_MASK |
1102				   GQSPI_IER_TXNOT_FULL_MASK);
1103		timeout = zynqmp_qspi_timeout(xqspi, op->addr.buswidth,
1104					      op->addr.nbytes);
1105		if (!wait_for_completion_timeout(&xqspi->data_completion,
1106						 timeout)) {
1107			err = -ETIMEDOUT;
1108			goto return_err;
1109		}
1110	}
1111
1112	if (op->dummy.nbytes) {
1113		xqspi->txbuf = NULL;
1114		xqspi->rxbuf = NULL;
1115		/*
1116		 * xqspi->bytes_to_transfer here represents the dummy circles
1117		 * which need to be sent.
1118		 */
1119		xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1120		xqspi->bytes_to_receive = 0;
1121		/*
1122		 * Using op->data.buswidth instead of op->dummy.buswidth here because
1123		 * we need to use it to configure the correct SPI mode.
1124		 */
1125		zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1126				     genfifoentry);
1127		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1128				   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1129				   GQSPI_CFG_START_GEN_FIFO_MASK);
1130	}
1131
1132	if (op->data.nbytes) {
1133		reinit_completion(&xqspi->data_completion);
1134		if (op->data.dir == SPI_MEM_DATA_OUT) {
1135			xqspi->txbuf = (u8 *)op->data.buf.out;
1136			xqspi->rxbuf = NULL;
1137			xqspi->bytes_to_transfer = op->data.nbytes;
1138			xqspi->bytes_to_receive = 0;
1139			zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1140					     genfifoentry);
1141			zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1142					   zynqmp_gqspi_read
1143					   (xqspi, GQSPI_CONFIG_OFST) |
1144					   GQSPI_CFG_START_GEN_FIFO_MASK);
1145			zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1146					   GQSPI_IER_TXEMPTY_MASK |
1147					   GQSPI_IER_GENFIFOEMPTY_MASK |
1148					   GQSPI_IER_TXNOT_FULL_MASK);
1149		} else {
1150			xqspi->txbuf = NULL;
1151			xqspi->rxbuf = (u8 *)op->data.buf.in;
1152			xqspi->bytes_to_receive = op->data.nbytes;
1153			xqspi->bytes_to_transfer = 0;
1154			err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1155					    genfifoentry);
1156			if (err)
1157				goto return_err;
1158
1159			zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1160					   zynqmp_gqspi_read
1161					   (xqspi, GQSPI_CONFIG_OFST) |
1162					   GQSPI_CFG_START_GEN_FIFO_MASK);
1163			if (xqspi->mode == GQSPI_MODE_DMA) {
1164				zynqmp_gqspi_write
1165					(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1166					 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1167			} else {
1168				zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1169						   GQSPI_IER_GENFIFOEMPTY_MASK |
1170						   GQSPI_IER_RXNEMPTY_MASK |
1171						   GQSPI_IER_RXEMPTY_MASK);
1172			}
1173		}
1174		timeout = zynqmp_qspi_timeout(xqspi, op->data.buswidth,
1175					      op->data.nbytes);
1176		if (!wait_for_completion_timeout(&xqspi->data_completion, timeout))
1177			err = -ETIMEDOUT;
1178	}
1179
1180return_err:
1181
1182	zynqmp_qspi_chipselect(mem->spi, true);
1183	mutex_unlock(&xqspi->op_lock);
1184
1185	return err;
1186}
1187
1188static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1189	SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1190			   zynqmp_runtime_resume, NULL)
1191	SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1192};
1193
1194static const struct qspi_platform_data versal_qspi_def = {
1195	.quirks = QSPI_QUIRK_HAS_TAPDELAY,
1196};
1197
1198static const struct of_device_id zynqmp_qspi_of_match[] = {
1199	{ .compatible = "xlnx,zynqmp-qspi-1.0"},
1200	{ .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },
1201	{ /* End of table */ }
1202};
1203
1204static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1205	.exec_op = zynqmp_qspi_exec_op,
1206};
1207
1208static const struct spi_controller_mem_caps zynqmp_qspi_mem_caps = {
1209	.per_op_freq = true,
1210};
1211
1212/**
1213 * zynqmp_qspi_probe - Probe method for the QSPI driver
1214 * @pdev:	Pointer to the platform_device structure
1215 *
1216 * This function initializes the driver data structures and the hardware.
1217 *
1218 * Return:	0 on success; error value otherwise
1219 */
1220static int zynqmp_qspi_probe(struct platform_device *pdev)
1221{
1222	int ret = 0;
1223	struct spi_controller *ctlr;
1224	struct zynqmp_qspi *xqspi;
1225	struct device *dev = &pdev->dev;
1226	struct device_node *np = dev->of_node;
1227	u32 num_cs;
1228	const struct qspi_platform_data *p_data;
1229
1230	ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*xqspi));
1231	if (!ctlr)
1232		return -ENOMEM;
1233
1234	xqspi = spi_controller_get_devdata(ctlr);
1235	xqspi->dev = dev;
1236	xqspi->ctlr = ctlr;
1237	platform_set_drvdata(pdev, xqspi);
1238
1239	p_data = of_device_get_match_data(&pdev->dev);
1240	if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY))
1241		xqspi->has_tapdelay = true;
1242
1243	xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1244	if (IS_ERR(xqspi->regs))
1245		return PTR_ERR(xqspi->regs);
1246
1247	xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1248	if (IS_ERR(xqspi->pclk))
1249		return dev_err_probe(dev, PTR_ERR(xqspi->pclk),
1250				     "pclk clock not found.\n");
1251
1252	xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1253	if (IS_ERR(xqspi->refclk))
1254		return dev_err_probe(dev, PTR_ERR(xqspi->refclk),
1255				     "ref_clk clock not found.\n");
1256
1257	ret = clk_prepare_enable(xqspi->pclk);
1258	if (ret)
1259		return dev_err_probe(dev, ret, "Unable to enable APB clock.\n");
1260
1261	ret = clk_prepare_enable(xqspi->refclk);
1262	if (ret) {
1263		dev_err(dev, "Unable to enable device clock.\n");
1264		goto clk_dis_pclk;
1265	}
1266
1267	init_completion(&xqspi->data_completion);
1268
1269	mutex_init(&xqspi->op_lock);
1270
1271	pm_runtime_use_autosuspend(&pdev->dev);
1272	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1273	pm_runtime_set_active(&pdev->dev);
1274	pm_runtime_enable(&pdev->dev);
1275
1276	ret = pm_runtime_get_sync(&pdev->dev);
1277	if (ret < 0) {
1278		dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
1279		goto clk_dis_all;
1280	}
1281
1282	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1283		SPI_TX_DUAL | SPI_TX_QUAD;
1284	ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1285	xqspi->speed_hz = ctlr->max_speed_hz;
1286
1287	/* QSPI controller initializations */
1288	zynqmp_qspi_init_hw(xqspi);
1289
1290	xqspi->irq = platform_get_irq(pdev, 0);
1291	if (xqspi->irq < 0) {
1292		ret = xqspi->irq;
1293		goto clk_dis_all;
1294	}
1295	ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1296			       0, pdev->name, xqspi);
1297	if (ret != 0) {
1298		ret = -ENXIO;
1299		dev_err(dev, "request_irq failed\n");
1300		goto clk_dis_all;
1301	}
1302
1303	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1304	if (ret)
1305		goto clk_dis_all;
1306
1307	ret = of_property_read_u32(np, "num-cs", &num_cs);
1308	if (ret < 0) {
1309		ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1310	} else if (num_cs > GQSPI_MAX_NUM_CS) {
1311		ret = -EINVAL;
1312		dev_err(&pdev->dev, "only %d chip selects are available\n",
1313			GQSPI_MAX_NUM_CS);
1314		goto clk_dis_all;
1315	} else {
1316		ctlr->num_chipselect = num_cs;
1317	}
1318
1319	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1320	ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1321	ctlr->mem_caps = &zynqmp_qspi_mem_caps;
1322	ctlr->setup = zynqmp_qspi_setup_op;
1323	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1324	ctlr->dev.of_node = np;
1325	ctlr->auto_runtime_pm = true;
1326
1327	ret = devm_spi_register_controller(&pdev->dev, ctlr);
1328	if (ret) {
1329		dev_err(&pdev->dev, "spi_register_controller failed\n");
1330		goto clk_dis_all;
1331	}
1332
1333	pm_runtime_put_autosuspend(&pdev->dev);
1334
1335	return 0;
1336
1337clk_dis_all:
1338	pm_runtime_disable(&pdev->dev);
1339	pm_runtime_dont_use_autosuspend(&pdev->dev);
1340	pm_runtime_put_noidle(&pdev->dev);
1341	pm_runtime_set_suspended(&pdev->dev);
1342	clk_disable_unprepare(xqspi->refclk);
1343clk_dis_pclk:
1344	clk_disable_unprepare(xqspi->pclk);
1345
1346	return ret;
1347}
1348
1349/**
1350 * zynqmp_qspi_remove - Remove method for the QSPI driver
1351 * @pdev:	Pointer to the platform_device structure
1352 *
1353 * This function is called if a device is physically removed from the system or
1354 * if the driver module is being unloaded. It frees all resources allocated to
1355 * the device.
1356 *
1357 * Return:	0 Always
1358 */
1359static void zynqmp_qspi_remove(struct platform_device *pdev)
1360{
1361	struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
1362
1363	pm_runtime_get_sync(&pdev->dev);
1364
1365	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1366
1367	pm_runtime_disable(&pdev->dev);
1368	pm_runtime_dont_use_autosuspend(&pdev->dev);
1369	pm_runtime_put_noidle(&pdev->dev);
1370	pm_runtime_set_suspended(&pdev->dev);
1371	clk_disable_unprepare(xqspi->refclk);
1372	clk_disable_unprepare(xqspi->pclk);
1373}
1374
1375MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1376
1377static struct platform_driver zynqmp_qspi_driver = {
1378	.probe = zynqmp_qspi_probe,
1379	.remove = zynqmp_qspi_remove,
1380	.driver = {
1381		.name = "zynqmp-qspi",
1382		.of_match_table = zynqmp_qspi_of_match,
1383		.pm = &zynqmp_qspi_dev_pm_ops,
1384	},
1385};
1386
1387module_platform_driver(zynqmp_qspi_driver);
1388
1389MODULE_AUTHOR("Xilinx, Inc.");
1390MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1391MODULE_LICENSE("GPL");