spi-zynq-qspi.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (C) 2019 Xilinx, Inc.
  4 *
  5 * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>
  6 */
  7
  8#include <linux/clk.h>
  9#include <linux/delay.h>
 10#include <linux/interrupt.h>
 11#include <linux/io.h>
 12#include <linux/module.h>
 13#include <linux/of_irq.h>
 14#include <linux/of_address.h>
 15#include <linux/platform_device.h>
 16#include <linux/spi/spi.h>
 17#include <linux/workqueue.h>
 18#include <linux/spi/spi-mem.h>
 19
 20/* Register offset definitions */
 21#define ZYNQ_QSPI_CONFIG_OFFSET		0x00 /* Configuration  Register, RW */
 22#define ZYNQ_QSPI_STATUS_OFFSET		0x04 /* Interrupt Status Register, RO */
 23#define ZYNQ_QSPI_IEN_OFFSET		0x08 /* Interrupt Enable Register, WO */
 24#define ZYNQ_QSPI_IDIS_OFFSET		0x0C /* Interrupt Disable Reg, WO */
 25#define ZYNQ_QSPI_IMASK_OFFSET		0x10 /* Interrupt Enabled Mask Reg,RO */
 26#define ZYNQ_QSPI_ENABLE_OFFSET		0x14 /* Enable/Disable Register, RW */
 27#define ZYNQ_QSPI_DELAY_OFFSET		0x18 /* Delay Register, RW */
 28#define ZYNQ_QSPI_TXD_00_00_OFFSET	0x1C /* Transmit 4-byte inst, WO */
 29#define ZYNQ_QSPI_TXD_00_01_OFFSET	0x80 /* Transmit 1-byte inst, WO */
 30#define ZYNQ_QSPI_TXD_00_10_OFFSET	0x84 /* Transmit 2-byte inst, WO */
 31#define ZYNQ_QSPI_TXD_00_11_OFFSET	0x88 /* Transmit 3-byte inst, WO */
 32#define ZYNQ_QSPI_RXD_OFFSET		0x20 /* Data Receive Register, RO */
 33#define ZYNQ_QSPI_SIC_OFFSET		0x24 /* Slave Idle Count Register, RW */
 34#define ZYNQ_QSPI_TX_THRESH_OFFSET	0x28 /* TX FIFO Watermark Reg, RW */
 35#define ZYNQ_QSPI_RX_THRESH_OFFSET	0x2C /* RX FIFO Watermark Reg, RW */
 36#define ZYNQ_QSPI_GPIO_OFFSET		0x30 /* GPIO Register, RW */
 37#define ZYNQ_QSPI_LINEAR_CFG_OFFSET	0xA0 /* Linear Adapter Config Ref, RW */
 38#define ZYNQ_QSPI_MOD_ID_OFFSET		0xFC /* Module ID Register, RO */
 39
 40/*
 41 * QSPI Configuration Register bit Masks
 42 *
 43 * This register contains various control bits that effect the operation
 44 * of the QSPI controller
 45 */
 46#define ZYNQ_QSPI_CONFIG_IFMODE_MASK	BIT(31) /* Flash Memory Interface */
 47#define ZYNQ_QSPI_CONFIG_MANSRT_MASK	BIT(16) /* Manual TX Start */
 48#define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK	BIT(15) /* Enable Manual TX Mode */
 49#define ZYNQ_QSPI_CONFIG_SSFORCE_MASK	BIT(14) /* Manual Chip Select */
 50#define ZYNQ_QSPI_CONFIG_BDRATE_MASK	GENMASK(5, 3) /* Baud Rate Mask */
 51#define ZYNQ_QSPI_CONFIG_CPHA_MASK	BIT(2) /* Clock Phase Control */
 52#define ZYNQ_QSPI_CONFIG_CPOL_MASK	BIT(1) /* Clock Polarity Control */
 53#define ZYNQ_QSPI_CONFIG_FWIDTH_MASK	GENMASK(7, 6) /* FIFO width */
 54#define ZYNQ_QSPI_CONFIG_MSTREN_MASK	BIT(0) /* Master Mode */
 55
 56/*
 57 * QSPI Configuration Register - Baud rate and target select
 58 *
 59 * These are the values used in the calculation of baud rate divisor and
 60 * setting the target select.
 61 */
 62#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX	GENMASK(2, 0) /* Baud rate maximum */
 63#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT	3 /* Baud rate divisor shift */
 64#define ZYNQ_QSPI_CONFIG_PCS		BIT(10) /* Peripheral Chip Select */
 65
 66/*
 67 * QSPI Interrupt Registers bit Masks
 68 *
 69 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
 70 * bit definitions.
 71 */
 72#define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK	BIT(0) /* QSPI RX FIFO Overflow */
 73#define ZYNQ_QSPI_IXR_TXNFULL_MASK	BIT(2) /* QSPI TX FIFO Overflow */
 74#define ZYNQ_QSPI_IXR_TXFULL_MASK	BIT(3) /* QSPI TX FIFO is full */
 75#define ZYNQ_QSPI_IXR_RXNEMTY_MASK	BIT(4) /* QSPI RX FIFO Not Empty */
 76#define ZYNQ_QSPI_IXR_RXF_FULL_MASK	BIT(5) /* QSPI RX FIFO is full */
 77#define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK	BIT(6) /* QSPI TX FIFO Underflow */
 78#define ZYNQ_QSPI_IXR_ALL_MASK		(ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \
 79					ZYNQ_QSPI_IXR_TXNFULL_MASK | \
 80					ZYNQ_QSPI_IXR_TXFULL_MASK | \
 81					ZYNQ_QSPI_IXR_RXNEMTY_MASK | \
 82					ZYNQ_QSPI_IXR_RXF_FULL_MASK | \
 83					ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK)
 84#define ZYNQ_QSPI_IXR_RXTX_MASK		(ZYNQ_QSPI_IXR_TXNFULL_MASK | \
 85					ZYNQ_QSPI_IXR_RXNEMTY_MASK)
 86
 87/*
 88 * QSPI Enable Register bit Masks
 89 *
 90 * This register is used to enable or disable the QSPI controller
 91 */
 92#define ZYNQ_QSPI_ENABLE_ENABLE_MASK	BIT(0) /* QSPI Enable Bit Mask */
 93
 94/*
 95 * QSPI Linear Configuration Register
 96 *
 97 * It is named Linear Configuration but it controls other modes when not in
 98 * linear mode also.
 99 */
100#define ZYNQ_QSPI_LCFG_TWO_MEM		BIT(30) /* LQSPI Two memories */
101#define ZYNQ_QSPI_LCFG_SEP_BUS		BIT(29) /* LQSPI Separate bus */
102#define ZYNQ_QSPI_LCFG_U_PAGE		BIT(28) /* LQSPI Upper Page */
103
104#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT	8
105
106#define ZYNQ_QSPI_FAST_READ_QOUT_CODE	0x6B /* read instruction code */
107#define ZYNQ_QSPI_FIFO_DEPTH		63 /* FIFO depth in words */
108#define ZYNQ_QSPI_RX_THRESHOLD		32 /* Rx FIFO threshold level */
109#define ZYNQ_QSPI_TX_THRESHOLD		1 /* Tx FIFO threshold level */
110
111/*
112 * The modebits configurable by the driver to make the SPI support different
113 * data formats
114 */
115#define ZYNQ_QSPI_MODEBITS			(SPI_CPOL | SPI_CPHA)
116
117/* Maximum number of chip selects */
118#define ZYNQ_QSPI_MAX_NUM_CS		2
119
120/**
121 * struct zynq_qspi - Defines qspi driver instance
122 * @dev:		Pointer to the this device's information
123 * @regs:		Virtual address of the QSPI controller registers
124 * @refclk:		Pointer to the peripheral clock
125 * @pclk:		Pointer to the APB clock
126 * @irq:		IRQ number
127 * @txbuf:		Pointer to the TX buffer
128 * @rxbuf:		Pointer to the RX buffer
129 * @tx_bytes:		Number of bytes left to transfer
130 * @rx_bytes:		Number of bytes left to receive
131 * @data_completion:	completion structure
132 */
133struct zynq_qspi {
134	struct device *dev;
135	void __iomem *regs;
136	struct clk *refclk;
137	struct clk *pclk;
138	int irq;
139	u8 *txbuf;
140	u8 *rxbuf;
141	int tx_bytes;
142	int rx_bytes;
143	struct completion data_completion;
144};
145
146/*
147 * Inline functions for the QSPI controller read/write
148 */
149static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset)
150{
151	return readl_relaxed(xqspi->regs + offset);
152}
153
154static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,
155				   u32 val)
156{
157	writel_relaxed(val, xqspi->regs + offset);
158}
159
160/**
161 * zynq_qspi_init_hw - Initialize the hardware
162 * @xqspi:	Pointer to the zynq_qspi structure
163 * @num_cs:	Number of connected CS (to enable dual memories if needed)
164 *
165 * The default settings of the QSPI controller's configurable parameters on
166 * reset are
167 *	- Host mode
168 *	- Baud rate divisor is set to 2
169 *	- Tx threshold set to 1l Rx threshold set to 32
170 *	- Flash memory interface mode enabled
171 *	- Size of the word to be transferred as 8 bit
172 * This function performs the following actions
173 *	- Disable and clear all the interrupts
174 *	- Enable manual target select
175 *	- Enable manual start
176 *	- Deselect all the chip select lines
177 *	- Set the size of the word to be transferred as 32 bit
178 *	- Set the little endian mode of TX FIFO and
179 *	- Enable the QSPI controller
180 */
181static void zynq_qspi_init_hw(struct zynq_qspi *xqspi, unsigned int num_cs)
182{
183	u32 config_reg;
184
185	zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
186	zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
187
188	/* Disable linear mode as the boot loader may have used it */
189	config_reg = 0;
190	/* At the same time, enable dual mode if more than 1 CS is available */
191	if (num_cs > 1)
192		config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM;
193
194	zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
195
196	/* Clear the RX FIFO */
197	while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) &
198			      ZYNQ_QSPI_IXR_RXNEMTY_MASK)
199		zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
200
201	zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);
202	config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
203	config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |
204			ZYNQ_QSPI_CONFIG_CPOL_MASK |
205			ZYNQ_QSPI_CONFIG_CPHA_MASK |
206			ZYNQ_QSPI_CONFIG_BDRATE_MASK |
207			ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
208			ZYNQ_QSPI_CONFIG_MANSRTEN_MASK |
209			ZYNQ_QSPI_CONFIG_MANSRT_MASK);
210	config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |
211		       ZYNQ_QSPI_CONFIG_SSFORCE_MASK |
212		       ZYNQ_QSPI_CONFIG_FWIDTH_MASK |
213		       ZYNQ_QSPI_CONFIG_IFMODE_MASK);
214	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
215
216	zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,
217			ZYNQ_QSPI_RX_THRESHOLD);
218	zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,
219			ZYNQ_QSPI_TX_THRESHOLD);
220
221	zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,
222			ZYNQ_QSPI_ENABLE_ENABLE_MASK);
223}
224
225static bool zynq_qspi_supports_op(struct spi_mem *mem,
226				  const struct spi_mem_op *op)
227{
228	if (!spi_mem_default_supports_op(mem, op))
229		return false;
230
231	/*
232	 * The number of address bytes should be equal to or less than 3 bytes.
233	 */
234	if (op->addr.nbytes > 3)
235		return false;
236
237	return true;
238}
239
240/**
241 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
242 * @xqspi:	Pointer to the zynq_qspi structure
243 * @size:	Number of bytes to be read (1..4)
244 */
245static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size)
246{
247	u32 data;
248
249	data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);
250
251	if (xqspi->rxbuf) {
252		memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size);
253		xqspi->rxbuf += size;
254	}
255
256	xqspi->rx_bytes -= size;
257	if (xqspi->rx_bytes < 0)
258		xqspi->rx_bytes = 0;
259}
260
261/**
262 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
263 * @xqspi:	Pointer to the zynq_qspi structure
264 * @size:	Number of bytes to be written (1..4)
265 */
266static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)
267{
268	static const unsigned int offset[4] = {
269		ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,
270		ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };
271	u32 data;
272
273	if (xqspi->txbuf) {
274		data = 0xffffffff;
275		memcpy(&data, xqspi->txbuf, size);
276		xqspi->txbuf += size;
277	} else {
278		data = 0;
279	}
280
281	xqspi->tx_bytes -= size;
282	zynq_qspi_write(xqspi, offset[size - 1], data);
283}
284
285/**
286 * zynq_qspi_chipselect - Select or deselect the chip select line
287 * @spi:	Pointer to the spi_device structure
288 * @assert:	1 for select or 0 for deselect the chip select line
289 */
290static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
291{
292	struct spi_controller *ctlr = spi->controller;
293	struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);
294	u32 config_reg;
295
296	/* Select the lower (CS0) or upper (CS1) memory */
297	if (ctlr->num_chipselect > 1) {
298		config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET);
299		if (!spi_get_chipselect(spi, 0))
300			config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE;
301		else
302			config_reg |= ZYNQ_QSPI_LCFG_U_PAGE;
303
304		zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);
305	}
306
307	/* Ground the line to assert the CS */
308	config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
309	if (assert)
310		config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;
311	else
312		config_reg |= ZYNQ_QSPI_CONFIG_PCS;
313
314	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
315}
316
317/**
318 * zynq_qspi_config_op - Configure QSPI controller for specified transfer
319 * @xqspi:	Pointer to the zynq_qspi structure
320 * @spi:	Pointer to the spi_device structure
321 * @op:		The memory operation to execute
322 *
323 * Sets the operational mode of QSPI controller for the next QSPI transfer and
324 * sets the requested clock frequency.
325 *
326 * Return:	0 on success and -EINVAL on invalid input parameter
327 *
328 * Note: If the requested frequency is not an exact match with what can be
329 * obtained using the prescalar value, the driver sets the clock frequency which
330 * is lower than the requested frequency (maximum lower) for the transfer. If
331 * the requested frequency is higher or lower than that is supported by the QSPI
332 * controller the driver will set the highest or lowest frequency supported by
333 * controller.
334 */
335static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi,
336			       const struct spi_mem_op *op)
337{
338	u32 config_reg, baud_rate_val = 0;
339
340	/*
341	 * Set the clock frequency
342	 * The baud rate divisor is not a direct mapping to the value written
343	 * into the configuration register (config_reg[5:3])
344	 * i.e. 000 - divide by 2
345	 *      001 - divide by 4
346	 *      ----------------
347	 *      111 - divide by 256
348	 */
349	while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX)  &&
350	       (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
351		op->max_freq)
352		baud_rate_val++;
353
354	config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);
355
356	/* Set the QSPI clock phase and clock polarity */
357	config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &
358		      (~ZYNQ_QSPI_CONFIG_CPOL_MASK);
359	if (spi->mode & SPI_CPHA)
360		config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;
361	if (spi->mode & SPI_CPOL)
362		config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
363
364	config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
365	config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);
366	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
367
368	return 0;
369}
370
371/**
372 * zynq_qspi_setup_op - Configure the QSPI controller
373 * @spi:	Pointer to the spi_device structure
374 *
375 * Sets the operational mode of QSPI controller for the next QSPI transfer, baud
376 * rate and divisor value to setup the requested qspi clock.
377 *
378 * Return:	0 on success and error value on failure
379 */
380static int zynq_qspi_setup_op(struct spi_device *spi)
381{
382	struct spi_controller *ctlr = spi->controller;
383	struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);
384	int ret;
385
386	if (ctlr->busy)
387		return -EBUSY;
388
389	ret = clk_enable(qspi->refclk);
390	if (ret)
391		return ret;
392
393	ret = clk_enable(qspi->pclk);
394	if (ret) {
395		clk_disable(qspi->refclk);
396		return ret;
397	}
398
399	zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,
400			ZYNQ_QSPI_ENABLE_ENABLE_MASK);
401
402	return 0;
403}
404
405/**
406 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
407 * @xqspi:	Pointer to the zynq_qspi structure
408 * @txcount:	Maximum number of words to write
409 * @txempty:	Indicates that TxFIFO is empty
410 */
411static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount,
412			       bool txempty)
413{
414	int count, len, k;
415
416	len = xqspi->tx_bytes;
417	if (len && len < 4) {
418		/*
419		 * We must empty the TxFIFO between accesses to TXD0,
420		 * TXD1, TXD2, TXD3.
421		 */
422		if (txempty)
423			zynq_qspi_txfifo_op(xqspi, len);
424
425		return;
426	}
427
428	count = len / 4;
429	if (count > txcount)
430		count = txcount;
431
432	if (xqspi->txbuf) {
433		iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET,
434			      xqspi->txbuf, count);
435		xqspi->txbuf += count * 4;
436	} else {
437		for (k = 0; k < count; k++)
438			writel_relaxed(0, xqspi->regs +
439					  ZYNQ_QSPI_TXD_00_00_OFFSET);
440	}
441
442	xqspi->tx_bytes -= count * 4;
443}
444
445/**
446 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
447 * @xqspi:	Pointer to the zynq_qspi structure
448 * @rxcount:	Maximum number of words to read
449 */
450static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount)
451{
452	int count, len, k;
453
454	len = xqspi->rx_bytes - xqspi->tx_bytes;
455	count = len / 4;
456	if (count > rxcount)
457		count = rxcount;
458	if (xqspi->rxbuf) {
459		ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET,
460			     xqspi->rxbuf, count);
461		xqspi->rxbuf += count * 4;
462	} else {
463		for (k = 0; k < count; k++)
464			readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET);
465	}
466	xqspi->rx_bytes -= count * 4;
467	len -= count * 4;
468
469	if (len && len < 4 && count < rxcount)
470		zynq_qspi_rxfifo_op(xqspi, len);
471}
472
473/**
474 * zynq_qspi_irq - Interrupt service routine of the QSPI controller
475 * @irq:	IRQ number
476 * @dev_id:	Pointer to the xqspi structure
477 *
478 * This function handles TX empty only.
479 * On TX empty interrupt this function reads the received data from RX FIFO and
480 * fills the TX FIFO if there is any data remaining to be transferred.
481 *
482 * Return:	IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise.
483 */
484static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)
485{
486	u32 intr_status;
487	bool txempty;
488	struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id;
489
490	intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET);
491	zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);
492
493	if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) ||
494	    (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {
495		/*
496		 * This bit is set when Tx FIFO has < THRESHOLD entries.
497		 * We have the THRESHOLD value set to 1,
498		 * so this bit indicates Tx FIFO is empty.
499		 */
500		txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK);
501		/* Read out the data from the RX FIFO */
502		zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD);
503		if (xqspi->tx_bytes) {
504			/* There is more data to send */
505			zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD,
506					   txempty);
507		} else {
508			/*
509			 * If transfer and receive is completed then only send
510			 * complete signal.
511			 */
512			if (!xqspi->rx_bytes) {
513				zynq_qspi_write(xqspi,
514						ZYNQ_QSPI_IDIS_OFFSET,
515						ZYNQ_QSPI_IXR_RXTX_MASK);
516				complete(&xqspi->data_completion);
517			}
518		}
519		return IRQ_HANDLED;
520	}
521
522	return IRQ_NONE;
523}
524
525/**
526 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
527 * @mem: the SPI memory
528 * @op: the memory operation to execute
529 *
530 * Executes a memory operation.
531 *
532 * This function first selects the chip and starts the memory operation.
533 *
534 * Return: 0 in case of success, a negative error code otherwise.
535 */
536static int zynq_qspi_exec_mem_op(struct spi_mem *mem,
537				 const struct spi_mem_op *op)
538{
539	struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->controller);
540	int err = 0, i;
541	u8 *tmpbuf;
542
543	zynq_qspi_chipselect(mem->spi, true);
544	zynq_qspi_config_op(xqspi, mem->spi, op);
545
546	if (op->cmd.opcode) {
547		reinit_completion(&xqspi->data_completion);
548		xqspi->txbuf = (u8 *)&op->cmd.opcode;
549		xqspi->rxbuf = NULL;
550		xqspi->tx_bytes = op->cmd.nbytes;
551		xqspi->rx_bytes = op->cmd.nbytes;
552		zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
553		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
554				ZYNQ_QSPI_IXR_RXTX_MASK);
555		if (!wait_for_completion_timeout(&xqspi->data_completion,
556							       msecs_to_jiffies(1000)))
557			err = -ETIMEDOUT;
558	}
559
560	if (op->addr.nbytes) {
561		for (i = 0; i < op->addr.nbytes; i++) {
562			xqspi->txbuf[i] = op->addr.val >>
563					(8 * (op->addr.nbytes - i - 1));
564		}
565
566		reinit_completion(&xqspi->data_completion);
567		xqspi->rxbuf = NULL;
568		xqspi->tx_bytes = op->addr.nbytes;
569		xqspi->rx_bytes = op->addr.nbytes;
570		zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
571		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
572				ZYNQ_QSPI_IXR_RXTX_MASK);
573		if (!wait_for_completion_timeout(&xqspi->data_completion,
574							       msecs_to_jiffies(1000)))
575			err = -ETIMEDOUT;
576	}
577
578	if (op->dummy.nbytes) {
579		tmpbuf = kmalloc(op->dummy.nbytes, GFP_KERNEL);
580		if (!tmpbuf)
581			return -ENOMEM;
582
583		memset(tmpbuf, 0xff, op->dummy.nbytes);
584		reinit_completion(&xqspi->data_completion);
585		xqspi->txbuf = tmpbuf;
586		xqspi->rxbuf = NULL;
587		xqspi->tx_bytes = op->dummy.nbytes;
588		xqspi->rx_bytes = op->dummy.nbytes;
589		zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
590		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
591				ZYNQ_QSPI_IXR_RXTX_MASK);
592		if (!wait_for_completion_timeout(&xqspi->data_completion,
593							       msecs_to_jiffies(1000)))
594			err = -ETIMEDOUT;
595
596		kfree(tmpbuf);
597	}
598
599	if (op->data.nbytes) {
600		reinit_completion(&xqspi->data_completion);
601		if (op->data.dir == SPI_MEM_DATA_OUT) {
602			xqspi->txbuf = (u8 *)op->data.buf.out;
603			xqspi->tx_bytes = op->data.nbytes;
604			xqspi->rxbuf = NULL;
605			xqspi->rx_bytes = op->data.nbytes;
606		} else {
607			xqspi->txbuf = NULL;
608			xqspi->rxbuf = (u8 *)op->data.buf.in;
609			xqspi->rx_bytes = op->data.nbytes;
610			xqspi->tx_bytes = op->data.nbytes;
611		}
612
613		zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);
614		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,
615				ZYNQ_QSPI_IXR_RXTX_MASK);
616		if (!wait_for_completion_timeout(&xqspi->data_completion,
617							       msecs_to_jiffies(1000)))
618			err = -ETIMEDOUT;
619	}
620	zynq_qspi_chipselect(mem->spi, false);
621
622	return err;
623}
624
625static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
626	.supports_op = zynq_qspi_supports_op,
627	.exec_op = zynq_qspi_exec_mem_op,
628};
629
630static const struct spi_controller_mem_caps zynq_qspi_mem_caps = {
631	.per_op_freq = true,
632};
633
634/**
635 * zynq_qspi_probe - Probe method for the QSPI driver
636 * @pdev:	Pointer to the platform_device structure
637 *
638 * This function initializes the driver data structures and the hardware.
639 *
640 * Return:	0 on success and error value on failure
641 */
642static int zynq_qspi_probe(struct platform_device *pdev)
643{
644	int ret = 0;
645	struct spi_controller *ctlr;
646	struct device *dev = &pdev->dev;
647	struct device_node *np = dev->of_node;
648	struct zynq_qspi *xqspi;
649	u32 num_cs;
650
651	ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi));
652	if (!ctlr)
653		return -ENOMEM;
654
655	xqspi = spi_controller_get_devdata(ctlr);
656	xqspi->dev = dev;
657	platform_set_drvdata(pdev, xqspi);
658	xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
659	if (IS_ERR(xqspi->regs)) {
660		ret = PTR_ERR(xqspi->regs);
661		goto remove_ctlr;
662	}
663
664	xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
665	if (IS_ERR(xqspi->pclk)) {
666		dev_err(&pdev->dev, "pclk clock not found.\n");
667		ret = PTR_ERR(xqspi->pclk);
668		goto remove_ctlr;
669	}
670
671	init_completion(&xqspi->data_completion);
672
673	xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
674	if (IS_ERR(xqspi->refclk)) {
675		dev_err(&pdev->dev, "ref_clk clock not found.\n");
676		ret = PTR_ERR(xqspi->refclk);
677		goto remove_ctlr;
678	}
679
680	ret = clk_prepare_enable(xqspi->pclk);
681	if (ret) {
682		dev_err(&pdev->dev, "Unable to enable APB clock.\n");
683		goto remove_ctlr;
684	}
685
686	ret = clk_prepare_enable(xqspi->refclk);
687	if (ret) {
688		dev_err(&pdev->dev, "Unable to enable device clock.\n");
689		goto clk_dis_pclk;
690	}
691
692	xqspi->irq = platform_get_irq(pdev, 0);
693	if (xqspi->irq < 0) {
694		ret = xqspi->irq;
695		goto clk_dis_all;
696	}
697	ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
698			       0, pdev->name, xqspi);
699	if (ret != 0) {
700		ret = -ENXIO;
701		dev_err(&pdev->dev, "request_irq failed\n");
702		goto clk_dis_all;
703	}
704
705	ret = of_property_read_u32(np, "num-cs",
706				   &num_cs);
707	if (ret < 0) {
708		ctlr->num_chipselect = 1;
709	} else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) {
710		ret = -EINVAL;
711		dev_err(&pdev->dev, "only 2 chip selects are available\n");
712		goto clk_dis_all;
713	} else {
714		ctlr->num_chipselect = num_cs;
715	}
716
717	ctlr->mode_bits =  SPI_RX_DUAL | SPI_RX_QUAD |
718			    SPI_TX_DUAL | SPI_TX_QUAD;
719	ctlr->mem_ops = &zynq_qspi_mem_ops;
720	ctlr->mem_caps = &zynq_qspi_mem_caps;
721	ctlr->setup = zynq_qspi_setup_op;
722	ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
723	ctlr->dev.of_node = np;
724
725	/* QSPI controller initializations */
726	zynq_qspi_init_hw(xqspi, ctlr->num_chipselect);
727
728	ret = devm_spi_register_controller(&pdev->dev, ctlr);
729	if (ret) {
730		dev_err(&pdev->dev, "devm_spi_register_controller failed\n");
731		goto clk_dis_all;
732	}
733
734	return ret;
735
736clk_dis_all:
737	clk_disable_unprepare(xqspi->refclk);
738clk_dis_pclk:
739	clk_disable_unprepare(xqspi->pclk);
740remove_ctlr:
741	spi_controller_put(ctlr);
742
743	return ret;
744}
745
746/**
747 * zynq_qspi_remove - Remove method for the QSPI driver
748 * @pdev:	Pointer to the platform_device structure
749 *
750 * This function is called if a device is physically removed from the system or
751 * if the driver module is being unloaded. It frees all resources allocated to
752 * the device.
753 *
754 * Return:	0 on success and error value on failure
755 */
756static void zynq_qspi_remove(struct platform_device *pdev)
757{
758	struct zynq_qspi *xqspi = platform_get_drvdata(pdev);
759
760	zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);
761
762	clk_disable_unprepare(xqspi->refclk);
763	clk_disable_unprepare(xqspi->pclk);
764}
765
766static const struct of_device_id zynq_qspi_of_match[] = {
767	{ .compatible = "xlnx,zynq-qspi-1.0", },
768	{ /* end of table */ }
769};
770
771MODULE_DEVICE_TABLE(of, zynq_qspi_of_match);
772
773/*
774 * zynq_qspi_driver - This structure defines the QSPI platform driver
775 */
776static struct platform_driver zynq_qspi_driver = {
777	.probe = zynq_qspi_probe,
778	.remove = zynq_qspi_remove,
779	.driver = {
780		.name = "zynq-qspi",
781		.of_match_table = zynq_qspi_of_match,
782	},
783};
784
785module_platform_driver(zynq_qspi_driver);
786
787MODULE_AUTHOR("Xilinx, Inc.");
788MODULE_DESCRIPTION("Xilinx Zynq QSPI driver");
789MODULE_LICENSE("GPL");