spi-sun4i.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2012 - 2014 Allwinner Tech
  4 * Pan Nan <pannan@allwinnertech.com>
  5 *
  6 * Copyright (C) 2014 Maxime Ripard
  7 * Maxime Ripard <maxime.ripard@free-electrons.com>
  8 */
  9
 10#include <linux/clk.h>
 11#include <linux/delay.h>
 12#include <linux/device.h>
 13#include <linux/interrupt.h>
 14#include <linux/io.h>
 15#include <linux/module.h>
 16#include <linux/platform_device.h>
 17#include <linux/pm_runtime.h>
 18
 19#include <linux/spi/spi.h>
 20
 21#define SUN4I_FIFO_DEPTH		64
 22
 23#define SUN4I_RXDATA_REG		0x00
 24
 25#define SUN4I_TXDATA_REG		0x04
 26
 27#define SUN4I_CTL_REG			0x08
 28#define SUN4I_CTL_ENABLE			BIT(0)
 29#define SUN4I_CTL_MASTER			BIT(1)
 30#define SUN4I_CTL_CPHA				BIT(2)
 31#define SUN4I_CTL_CPOL				BIT(3)
 32#define SUN4I_CTL_CS_ACTIVE_LOW			BIT(4)
 33#define SUN4I_CTL_LMTF				BIT(6)
 34#define SUN4I_CTL_TF_RST			BIT(8)
 35#define SUN4I_CTL_RF_RST			BIT(9)
 36#define SUN4I_CTL_XCH				BIT(10)
 37#define SUN4I_CTL_CS_MASK			0x3000
 38#define SUN4I_CTL_CS(cs)			(((cs) << 12) & SUN4I_CTL_CS_MASK)
 39#define SUN4I_CTL_DHB				BIT(15)
 40#define SUN4I_CTL_CS_MANUAL			BIT(16)
 41#define SUN4I_CTL_CS_LEVEL			BIT(17)
 42#define SUN4I_CTL_TP				BIT(18)
 43
 44#define SUN4I_INT_CTL_REG		0x0c
 45#define SUN4I_INT_CTL_RF_F34			BIT(4)
 46#define SUN4I_INT_CTL_TF_E34			BIT(12)
 47#define SUN4I_INT_CTL_TC			BIT(16)
 48
 49#define SUN4I_INT_STA_REG		0x10
 50
 51#define SUN4I_DMA_CTL_REG		0x14
 52
 53#define SUN4I_WAIT_REG			0x18
 54
 55#define SUN4I_CLK_CTL_REG		0x1c
 56#define SUN4I_CLK_CTL_CDR2_MASK			0xff
 57#define SUN4I_CLK_CTL_CDR2(div)			((div) & SUN4I_CLK_CTL_CDR2_MASK)
 58#define SUN4I_CLK_CTL_CDR1_MASK			0xf
 59#define SUN4I_CLK_CTL_CDR1(div)			(((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
 60#define SUN4I_CLK_CTL_DRS			BIT(12)
 61
 62#define SUN4I_MAX_XFER_SIZE			0xffffff
 63
 64#define SUN4I_BURST_CNT_REG		0x20
 65#define SUN4I_BURST_CNT(cnt)			((cnt) & SUN4I_MAX_XFER_SIZE)
 66
 67#define SUN4I_XMIT_CNT_REG		0x24
 68#define SUN4I_XMIT_CNT(cnt)			((cnt) & SUN4I_MAX_XFER_SIZE)
 69
 70
 71#define SUN4I_FIFO_STA_REG		0x28
 72#define SUN4I_FIFO_STA_RF_CNT_MASK		0x7f
 73#define SUN4I_FIFO_STA_RF_CNT_BITS		0
 74#define SUN4I_FIFO_STA_TF_CNT_MASK		0x7f
 75#define SUN4I_FIFO_STA_TF_CNT_BITS		16
 76
 77struct sun4i_spi {
 78	struct spi_controller	*host;
 79	void __iomem		*base_addr;
 80	struct clk		*hclk;
 81	struct clk		*mclk;
 82
 83	struct completion	done;
 84
 85	const u8		*tx_buf;
 86	u8			*rx_buf;
 87	int			len;
 88};
 89
 90static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
 91{
 92	return readl(sspi->base_addr + reg);
 93}
 94
 95static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
 96{
 97	writel(value, sspi->base_addr + reg);
 98}
 99
100static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
101{
102	u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
103
104	reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
105
106	return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
107}
108
109static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
110{
111	u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
112
113	reg |= mask;
114	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
115}
116
117static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
118{
119	u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
120
121	reg &= ~mask;
122	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
123}
124
125static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
126{
127	u32 reg, cnt;
128	u8 byte;
129
130	/* See how much data is available */
131	reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
132	reg &= SUN4I_FIFO_STA_RF_CNT_MASK;
133	cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS;
134
135	if (len > cnt)
136		len = cnt;
137
138	while (len--) {
139		byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
140		if (sspi->rx_buf)
141			*sspi->rx_buf++ = byte;
142	}
143}
144
145static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
146{
147	u32 cnt;
148	u8 byte;
149
150	/* See how much data we can fit */
151	cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
152
153	len = min3(len, (int)cnt, sspi->len);
154
155	while (len--) {
156		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
157		writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
158		sspi->len--;
159	}
160}
161
162static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
163{
164	struct sun4i_spi *sspi = spi_controller_get_devdata(spi->controller);
165	u32 reg;
166
167	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
168
169	reg &= ~SUN4I_CTL_CS_MASK;
170	reg |= SUN4I_CTL_CS(spi_get_chipselect(spi, 0));
171
172	/* We want to control the chip select manually */
173	reg |= SUN4I_CTL_CS_MANUAL;
174
175	if (enable)
176		reg |= SUN4I_CTL_CS_LEVEL;
177	else
178		reg &= ~SUN4I_CTL_CS_LEVEL;
179
180	/*
181	 * Even though this looks irrelevant since we are supposed to
182	 * be controlling the chip select manually, this bit also
183	 * controls the levels of the chip select for inactive
184	 * devices.
185	 *
186	 * If we don't set it, the chip select level will go low by
187	 * default when the device is idle, which is not really
188	 * expected in the common case where the chip select is active
189	 * low.
190	 */
191	if (spi->mode & SPI_CS_HIGH)
192		reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
193	else
194		reg |= SUN4I_CTL_CS_ACTIVE_LOW;
195
196	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
197}
198
199static size_t sun4i_spi_max_transfer_size(struct spi_device *spi)
200{
201	return SUN4I_MAX_XFER_SIZE - 1;
202}
203
204static int sun4i_spi_transfer_one(struct spi_controller *host,
205				  struct spi_device *spi,
206				  struct spi_transfer *tfr)
207{
208	struct sun4i_spi *sspi = spi_controller_get_devdata(host);
209	unsigned int mclk_rate, div;
210	unsigned long time_left;
211	unsigned int start, end, tx_time;
212	unsigned int tx_len = 0;
213	int ret = 0;
214	u32 reg;
215
216	/* We don't support transfer larger than the FIFO */
217	if (tfr->len > SUN4I_MAX_XFER_SIZE)
218		return -EMSGSIZE;
219
220	if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
221		return -EMSGSIZE;
222
223	reinit_completion(&sspi->done);
224	sspi->tx_buf = tfr->tx_buf;
225	sspi->rx_buf = tfr->rx_buf;
226	sspi->len = tfr->len;
227
228	/* Clear pending interrupts */
229	sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
230
231
232	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
233
234	/* Reset FIFOs */
235	sun4i_spi_write(sspi, SUN4I_CTL_REG,
236			reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST);
237
238	/*
239	 * Setup the transfer control register: Chip Select,
240	 * polarities, etc.
241	 */
242	if (spi->mode & SPI_CPOL)
243		reg |= SUN4I_CTL_CPOL;
244	else
245		reg &= ~SUN4I_CTL_CPOL;
246
247	if (spi->mode & SPI_CPHA)
248		reg |= SUN4I_CTL_CPHA;
249	else
250		reg &= ~SUN4I_CTL_CPHA;
251
252	if (spi->mode & SPI_LSB_FIRST)
253		reg |= SUN4I_CTL_LMTF;
254	else
255		reg &= ~SUN4I_CTL_LMTF;
256
257
258	/*
259	 * If it's a TX only transfer, we don't want to fill the RX
260	 * FIFO with bogus data
261	 */
262	if (sspi->rx_buf)
263		reg &= ~SUN4I_CTL_DHB;
264	else
265		reg |= SUN4I_CTL_DHB;
266
267	/* Now that the settings are correct, enable the interface */
268	reg |= SUN4I_CTL_ENABLE;
269
270	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
271
272	/* Ensure that we have a parent clock fast enough */
273	mclk_rate = clk_get_rate(sspi->mclk);
274	if (mclk_rate < (2 * tfr->speed_hz)) {
275		clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
276		mclk_rate = clk_get_rate(sspi->mclk);
277	}
278
279	/*
280	 * Setup clock divider.
281	 *
282	 * We have two choices there. Either we can use the clock
283	 * divide rate 1, which is calculated thanks to this formula:
284	 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
285	 * Or we can use CDR2, which is calculated with the formula:
286	 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
287	 * Whether we use the former or the latter is set through the
288	 * DRS bit.
289	 *
290	 * First try CDR2, and if we can't reach the expected
291	 * frequency, fall back to CDR1.
292	 */
293	div = mclk_rate / (2 * tfr->speed_hz);
294	if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
295		if (div > 0)
296			div--;
297
298		reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
299	} else {
300		div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
301		reg = SUN4I_CLK_CTL_CDR1(div);
302	}
303
304	sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
305
306	/* Setup the transfer now... */
307	if (sspi->tx_buf)
308		tx_len = tfr->len;
309
310	/* Setup the counters */
311	sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
312	sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
313
314	/*
315	 * Fill the TX FIFO
316	 * Filling the FIFO fully causes timeout for some reason
317	 * at least on spi2 on A10s
318	 */
319	sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
320
321	/* Enable the interrupts */
322	sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
323					 SUN4I_INT_CTL_RF_F34);
324	/* Only enable Tx FIFO interrupt if we really need it */
325	if (tx_len > SUN4I_FIFO_DEPTH)
326		sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
327
328	/* Start the transfer */
329	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
330	sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
331
332	tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
333	start = jiffies;
334	time_left = wait_for_completion_timeout(&sspi->done,
335						msecs_to_jiffies(tx_time));
336	end = jiffies;
337	if (!time_left) {
338		dev_warn(&host->dev,
339			 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
340			 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
341			 jiffies_to_msecs(end - start), tx_time);
342		ret = -ETIMEDOUT;
343		goto out;
344	}
345
346
347out:
348	sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
349
350	return ret;
351}
352
353static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
354{
355	struct sun4i_spi *sspi = dev_id;
356	u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
357
358	/* Transfer complete */
359	if (status & SUN4I_INT_CTL_TC) {
360		sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
361		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
362		complete(&sspi->done);
363		return IRQ_HANDLED;
364	}
365
366	/* Receive FIFO 3/4 full */
367	if (status & SUN4I_INT_CTL_RF_F34) {
368		sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
369		/* Only clear the interrupt _after_ draining the FIFO */
370		sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
371		return IRQ_HANDLED;
372	}
373
374	/* Transmit FIFO 3/4 empty */
375	if (status & SUN4I_INT_CTL_TF_E34) {
376		sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
377
378		if (!sspi->len)
379			/* nothing left to transmit */
380			sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
381
382		/* Only clear the interrupt _after_ re-seeding the FIFO */
383		sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
384
385		return IRQ_HANDLED;
386	}
387
388	return IRQ_NONE;
389}
390
391static int sun4i_spi_runtime_resume(struct device *dev)
392{
393	struct spi_controller *host = dev_get_drvdata(dev);
394	struct sun4i_spi *sspi = spi_controller_get_devdata(host);
395	int ret;
396
397	ret = clk_prepare_enable(sspi->hclk);
398	if (ret) {
399		dev_err(dev, "Couldn't enable AHB clock\n");
400		goto out;
401	}
402
403	ret = clk_prepare_enable(sspi->mclk);
404	if (ret) {
405		dev_err(dev, "Couldn't enable module clock\n");
406		goto err;
407	}
408
409	sun4i_spi_write(sspi, SUN4I_CTL_REG,
410			SUN4I_CTL_MASTER | SUN4I_CTL_TP);
411
412	return 0;
413
414err:
415	clk_disable_unprepare(sspi->hclk);
416out:
417	return ret;
418}
419
420static int sun4i_spi_runtime_suspend(struct device *dev)
421{
422	struct spi_controller *host = dev_get_drvdata(dev);
423	struct sun4i_spi *sspi = spi_controller_get_devdata(host);
424
425	clk_disable_unprepare(sspi->mclk);
426	clk_disable_unprepare(sspi->hclk);
427
428	return 0;
429}
430
431static int sun4i_spi_probe(struct platform_device *pdev)
432{
433	struct spi_controller *host;
434	struct sun4i_spi *sspi;
435	int ret = 0, irq;
436
437	host = spi_alloc_host(&pdev->dev, sizeof(struct sun4i_spi));
438	if (!host) {
439		dev_err(&pdev->dev, "Unable to allocate SPI Host\n");
440		return -ENOMEM;
441	}
442
443	platform_set_drvdata(pdev, host);
444	sspi = spi_controller_get_devdata(host);
445
446	sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
447	if (IS_ERR(sspi->base_addr)) {
448		ret = PTR_ERR(sspi->base_addr);
449		goto err_free_host;
450	}
451
452	irq = platform_get_irq(pdev, 0);
453	if (irq < 0) {
454		ret = -ENXIO;
455		goto err_free_host;
456	}
457
458	ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler,
459			       0, "sun4i-spi", sspi);
460	if (ret) {
461		dev_err(&pdev->dev, "Cannot request IRQ\n");
462		goto err_free_host;
463	}
464
465	sspi->host = host;
466	host->max_speed_hz = 100 * 1000 * 1000;
467	host->min_speed_hz = 3 * 1000;
468	host->use_gpio_descriptors = true;
469	host->set_cs = sun4i_spi_set_cs;
470	host->transfer_one = sun4i_spi_transfer_one;
471	host->num_chipselect = 4;
472	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
473	host->bits_per_word_mask = SPI_BPW_MASK(8);
474	host->dev.of_node = pdev->dev.of_node;
475	host->auto_runtime_pm = true;
476	host->max_transfer_size = sun4i_spi_max_transfer_size;
477
478	sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
479	if (IS_ERR(sspi->hclk)) {
480		dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
481		ret = PTR_ERR(sspi->hclk);
482		goto err_free_host;
483	}
484
485	sspi->mclk = devm_clk_get(&pdev->dev, "mod");
486	if (IS_ERR(sspi->mclk)) {
487		dev_err(&pdev->dev, "Unable to acquire module clock\n");
488		ret = PTR_ERR(sspi->mclk);
489		goto err_free_host;
490	}
491
492	init_completion(&sspi->done);
493
494	/*
495	 * This wake-up/shutdown pattern is to be able to have the
496	 * device woken up, even if runtime_pm is disabled
497	 */
498	ret = sun4i_spi_runtime_resume(&pdev->dev);
499	if (ret) {
500		dev_err(&pdev->dev, "Couldn't resume the device\n");
501		goto err_free_host;
502	}
503
504	pm_runtime_set_active(&pdev->dev);
505	pm_runtime_enable(&pdev->dev);
506	pm_runtime_idle(&pdev->dev);
507
508	ret = devm_spi_register_controller(&pdev->dev, host);
509	if (ret) {
510		dev_err(&pdev->dev, "cannot register SPI host\n");
511		goto err_pm_disable;
512	}
513
514	return 0;
515
516err_pm_disable:
517	pm_runtime_disable(&pdev->dev);
518	sun4i_spi_runtime_suspend(&pdev->dev);
519err_free_host:
520	spi_controller_put(host);
521	return ret;
522}
523
524static void sun4i_spi_remove(struct platform_device *pdev)
525{
526	pm_runtime_force_suspend(&pdev->dev);
527}
528
529static const struct of_device_id sun4i_spi_match[] = {
530	{ .compatible = "allwinner,sun4i-a10-spi", },
531	{}
532};
533MODULE_DEVICE_TABLE(of, sun4i_spi_match);
534
535static const struct dev_pm_ops sun4i_spi_pm_ops = {
536	.runtime_resume		= sun4i_spi_runtime_resume,
537	.runtime_suspend	= sun4i_spi_runtime_suspend,
538};
539
540static struct platform_driver sun4i_spi_driver = {
541	.probe	= sun4i_spi_probe,
542	.remove = sun4i_spi_remove,
543	.driver	= {
544		.name		= "sun4i-spi",
545		.of_match_table	= sun4i_spi_match,
546		.pm		= &sun4i_spi_pm_ops,
547	},
548};
549module_platform_driver(sun4i_spi_driver);
550
551MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
552MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
553MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
554MODULE_LICENSE("GPL");