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spi-stm32-qspi.c
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linux-6.19.14/drivers/spi/spi-stm32-qspi.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <linux/bitfield.h> 7#include <linux/clk.h> 8#include <linux/dmaengine.h> 9#include <linux/dma-mapping.h> 10#include <linux/errno.h> 11#include <linux/gpio/consumer.h> 12#include <linux/io.h> 13#include <linux/iopoll.h> 14#include <linux/interrupt.h> 15#include <linux/module.h> 16#include <linux/mutex.h> 17#include <linux/of.h> 18#include <linux/pinctrl/consumer.h> 19#include <linux/pm_runtime.h> 20#include <linux/platform_device.h> 21#include <linux/reset.h> 22#include <linux/sizes.h> 23#include <linux/spi/spi-mem.h> 24 25#define QSPI_CR 0x00 26#define CR_EN BIT(0) 27#define CR_ABORT BIT(1) 28#define CR_DMAEN BIT(2) 29#define CR_TCEN BIT(3) 30#define CR_SSHIFT BIT(4) 31#define CR_DFM BIT(6) 32#define CR_FSEL BIT(7) 33#define CR_FTHRES_SHIFT 8 34#define CR_TEIE BIT(16) 35#define CR_TCIE BIT(17) 36#define CR_FTIE BIT(18) 37#define CR_SMIE BIT(19) 38#define CR_TOIE BIT(20) 39#define CR_APMS BIT(22) 40#define CR_PRESC_MASK GENMASK(31, 24) 41 42#define QSPI_DCR 0x04 43#define DCR_FSIZE_MASK GENMASK(20, 16) 44 45#define QSPI_SR 0x08 46#define SR_TEF BIT(0) 47#define SR_TCF BIT(1) 48#define SR_FTF BIT(2) 49#define SR_SMF BIT(3) 50#define SR_TOF BIT(4) 51#define SR_BUSY BIT(5) 52#define SR_FLEVEL_MASK GENMASK(13, 8) 53 54#define QSPI_FCR 0x0c 55#define FCR_CTEF BIT(0) 56#define FCR_CTCF BIT(1) 57#define FCR_CSMF BIT(3) 58 59#define QSPI_DLR 0x10 60 61#define QSPI_CCR 0x14 62#define CCR_INST_MASK GENMASK(7, 0) 63#define CCR_IMODE_MASK GENMASK(9, 8) 64#define CCR_ADMODE_MASK GENMASK(11, 10) 65#define CCR_ADSIZE_MASK GENMASK(13, 12) 66#define CCR_DCYC_MASK GENMASK(22, 18) 67#define CCR_DMODE_MASK GENMASK(25, 24) 68#define CCR_FMODE_MASK GENMASK(27, 26) 69#define CCR_FMODE_INDW (0U << 26) 70#define CCR_FMODE_INDR (1U << 26) 71#define CCR_FMODE_APM (2U << 26) 72#define CCR_FMODE_MM (3U << 26) 73#define CCR_BUSWIDTH_0 0x0 74#define CCR_BUSWIDTH_1 0x1 75#define CCR_BUSWIDTH_2 0x2 76#define CCR_BUSWIDTH_4 0x3 77 78#define QSPI_AR 0x18 79#define QSPI_ABR 0x1c 80#define QSPI_DR 0x20 81#define QSPI_PSMKR 0x24 82#define QSPI_PSMAR 0x28 83#define QSPI_PIR 0x2c 84#define QSPI_LPTR 0x30 85 86#define STM32_QSPI_MAX_MMAP_SZ SZ_256M 87#define STM32_QSPI_MAX_NORCHIP 2 88 89#define STM32_FIFO_TIMEOUT_US 30000 90#define STM32_BUSY_TIMEOUT_US 100000 91#define STM32_ABT_TIMEOUT_US 100000 92#define STM32_COMP_TIMEOUT_MS 1000 93#define STM32_AUTOSUSPEND_DELAY -1 94 95struct stm32_qspi_flash { 96 u32 cs; 97 u32 presc; 98}; 99 100struct stm32_qspi { 101 struct device *dev; 102 struct spi_controller *ctrl; 103 phys_addr_t phys_base; 104 void __iomem *io_base; 105 void __iomem *mm_base; 106 resource_size_t mm_size; 107 struct clk *clk; 108 u32 clk_rate; 109 struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP]; 110 struct completion data_completion; 111 struct completion match_completion; 112 u32 fmode; 113 114 struct dma_chan *dma_chtx; 115 struct dma_chan *dma_chrx; 116 struct completion dma_completion; 117 118 u32 cr_reg; 119 u32 dcr_reg; 120 unsigned long status_timeout; 121 122 /* 123 * to protect device configuration, could be different between 124 * 2 flash access (bk1, bk2) 125 */ 126 struct mutex lock; 127}; 128 129static irqreturn_t stm32_qspi_irq(int irq, void *dev_id) 130{ 131 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; 132 u32 cr, sr; 133 134 cr = readl_relaxed(qspi->io_base + QSPI_CR); 135 sr = readl_relaxed(qspi->io_base + QSPI_SR); 136 137 if (cr & CR_SMIE && sr & SR_SMF) { 138 /* disable irq */ 139 cr &= ~CR_SMIE; 140 writel_relaxed(cr, qspi->io_base + QSPI_CR); 141 complete(&qspi->match_completion); 142 143 return IRQ_HANDLED; 144 } 145 146 if (sr & (SR_TEF | SR_TCF)) { 147 /* disable irq */ 148 cr &= ~CR_TCIE & ~CR_TEIE; 149 writel_relaxed(cr, qspi->io_base + QSPI_CR); 150 complete(&qspi->data_completion); 151 } 152 153 return IRQ_HANDLED; 154} 155 156static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr) 157{ 158 *val = readb_relaxed(addr); 159} 160 161static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr) 162{ 163 writeb_relaxed(*val, addr); 164} 165 166static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, 167 const struct spi_mem_op *op) 168{ 169 void (*tx_fifo)(u8 *val, void __iomem *addr); 170 u32 len = op->data.nbytes, sr; 171 u8 *buf; 172 int ret; 173 174 if (op->data.dir == SPI_MEM_DATA_IN) { 175 tx_fifo = stm32_qspi_read_fifo; 176 buf = op->data.buf.in; 177 178 } else { 179 tx_fifo = stm32_qspi_write_fifo; 180 buf = (u8 *)op->data.buf.out; 181 } 182 183 while (len--) { 184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, 185 sr, (sr & SR_FTF), 1, 186 STM32_FIFO_TIMEOUT_US); 187 if (ret) { 188 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", 189 len, sr); 190 return ret; 191 } 192 tx_fifo(buf++, qspi->io_base + QSPI_DR); 193 } 194 195 return 0; 196} 197 198static int stm32_qspi_tx_mm(struct stm32_qspi *qspi, 199 const struct spi_mem_op *op) 200{ 201 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val, 202 op->data.nbytes); 203 return 0; 204} 205 206static void stm32_qspi_dma_callback(void *arg) 207{ 208 struct completion *dma_completion = arg; 209 210 complete(dma_completion); 211} 212 213static int stm32_qspi_tx_dma(struct stm32_qspi *qspi, 214 const struct spi_mem_op *op) 215{ 216 struct dma_async_tx_descriptor *desc; 217 enum dma_transfer_direction dma_dir; 218 struct dma_chan *dma_ch; 219 struct sg_table sgt; 220 dma_cookie_t cookie; 221 u32 cr, t_out; 222 int err; 223 224 if (op->data.dir == SPI_MEM_DATA_IN) { 225 dma_dir = DMA_DEV_TO_MEM; 226 dma_ch = qspi->dma_chrx; 227 } else { 228 dma_dir = DMA_MEM_TO_DEV; 229 dma_ch = qspi->dma_chtx; 230 } 231 232 /* 233 * spi_map_buf return -EINVAL if the buffer is not DMA-able 234 * (DMA-able: in vmalloc | kmap | virt_addr_valid) 235 */ 236 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt); 237 if (err) 238 return err; 239 240 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents, 241 dma_dir, DMA_PREP_INTERRUPT); 242 if (!desc) { 243 err = -ENOMEM; 244 goto out_unmap; 245 } 246 247 cr = readl_relaxed(qspi->io_base + QSPI_CR); 248 249 reinit_completion(&qspi->dma_completion); 250 desc->callback = stm32_qspi_dma_callback; 251 desc->callback_param = &qspi->dma_completion; 252 cookie = dmaengine_submit(desc); 253 err = dma_submit_error(cookie); 254 if (err) 255 goto out; 256 257 dma_async_issue_pending(dma_ch); 258 259 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); 260 261 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS; 262 if (!wait_for_completion_timeout(&qspi->dma_completion, 263 msecs_to_jiffies(t_out))) 264 err = -ETIMEDOUT; 265 266 if (err) 267 dmaengine_terminate_all(dma_ch); 268 269out: 270 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); 271out_unmap: 272 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt); 273 274 return err; 275} 276 277static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op) 278{ 279 if (!op->data.nbytes) 280 return 0; 281 282 if (qspi->fmode == CCR_FMODE_MM) 283 return stm32_qspi_tx_mm(qspi, op); 284 else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) || 285 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) && 286 op->data.nbytes > 4) 287 if (!stm32_qspi_tx_dma(qspi, op)) 288 return 0; 289 290 return stm32_qspi_tx_poll(qspi, op); 291} 292 293static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi) 294{ 295 u32 sr; 296 297 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, 298 !(sr & SR_BUSY), 1, 299 STM32_BUSY_TIMEOUT_US); 300} 301 302static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi) 303{ 304 u32 cr, sr; 305 int err = 0; 306 307 if ((readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) || 308 qspi->fmode == CCR_FMODE_APM) 309 goto out; 310 311 reinit_completion(&qspi->data_completion); 312 cr = readl_relaxed(qspi->io_base + QSPI_CR); 313 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR); 314 315 if (!wait_for_completion_timeout(&qspi->data_completion, 316 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) { 317 err = -ETIMEDOUT; 318 } else { 319 sr = readl_relaxed(qspi->io_base + QSPI_SR); 320 if (sr & SR_TEF) 321 err = -EIO; 322 } 323 324out: 325 /* clear flags */ 326 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR); 327 if (!err) 328 err = stm32_qspi_wait_nobusy(qspi); 329 330 return err; 331} 332 333static int stm32_qspi_wait_poll_status(struct stm32_qspi *qspi) 334{ 335 u32 cr; 336 337 reinit_completion(&qspi->match_completion); 338 cr = readl_relaxed(qspi->io_base + QSPI_CR); 339 writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR); 340 341 if (!wait_for_completion_timeout(&qspi->match_completion, 342 msecs_to_jiffies(qspi->status_timeout))) 343 return -ETIMEDOUT; 344 345 writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR); 346 347 return 0; 348} 349 350static int stm32_qspi_get_mode(u8 buswidth) 351{ 352 if (buswidth >= 4) 353 return CCR_BUSWIDTH_4; 354 355 return buswidth; 356} 357 358static int stm32_qspi_send(struct spi_device *spi, const struct spi_mem_op *op) 359{ 360 struct stm32_qspi *qspi = spi_controller_get_devdata(spi->controller); 361 struct stm32_qspi_flash *flash = &qspi->flash[spi_get_chipselect(spi, 0)]; 362 u32 ccr, cr; 363 int timeout, err = 0, err_poll_status = 0; 364 365 cr = readl_relaxed(qspi->io_base + QSPI_CR); 366 cr &= ~CR_PRESC_MASK & ~CR_FSEL; 367 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc); 368 cr |= FIELD_PREP(CR_FSEL, flash->cs); 369 writel_relaxed(cr, qspi->io_base + QSPI_CR); 370 371 if (op->data.nbytes) 372 writel_relaxed(op->data.nbytes - 1, 373 qspi->io_base + QSPI_DLR); 374 375 ccr = qspi->fmode; 376 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode); 377 ccr |= FIELD_PREP(CCR_IMODE_MASK, 378 stm32_qspi_get_mode(op->cmd.buswidth)); 379 380 if (op->addr.nbytes) { 381 ccr |= FIELD_PREP(CCR_ADMODE_MASK, 382 stm32_qspi_get_mode(op->addr.buswidth)); 383 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1); 384 } 385 386 if (op->dummy.nbytes) 387 ccr |= FIELD_PREP(CCR_DCYC_MASK, 388 op->dummy.nbytes * 8 / op->dummy.buswidth); 389 390 if (op->data.nbytes) { 391 ccr |= FIELD_PREP(CCR_DMODE_MASK, 392 stm32_qspi_get_mode(op->data.buswidth)); 393 } 394 395 writel_relaxed(ccr, qspi->io_base + QSPI_CCR); 396 397 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM) 398 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR); 399 400 if (qspi->fmode == CCR_FMODE_APM) 401 err_poll_status = stm32_qspi_wait_poll_status(qspi); 402 403 err = stm32_qspi_tx(qspi, op); 404 405 /* 406 * Abort in: 407 * -error case 408 * -read memory map: prefetching must be stopped if we read the last 409 * byte of device (device size - fifo size). like device size is not 410 * knows, the prefetching is always stop. 411 */ 412 if (err || err_poll_status || qspi->fmode == CCR_FMODE_MM) 413 goto abort; 414 415 /* wait end of tx in indirect mode */ 416 err = stm32_qspi_wait_cmd(qspi); 417 if (err) 418 goto abort; 419 420 return 0; 421 422abort: 423 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT; 424 writel_relaxed(cr, qspi->io_base + QSPI_CR); 425 426 /* wait clear of abort bit by hw */ 427 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR, 428 cr, !(cr & CR_ABORT), 1, 429 STM32_ABT_TIMEOUT_US); 430 431 writel_relaxed(FCR_CTCF | FCR_CSMF, qspi->io_base + QSPI_FCR); 432 433 if (err || err_poll_status || timeout) 434 dev_err(qspi->dev, "%s err:%d err_poll_status:%d abort timeout:%d\n", 435 __func__, err, err_poll_status, timeout); 436 437 return err; 438} 439 440static int stm32_qspi_poll_status(struct spi_mem *mem, const struct spi_mem_op *op, 441 u16 mask, u16 match, 442 unsigned long initial_delay_us, 443 unsigned long polling_rate_us, 444 unsigned long timeout_ms) 445{ 446 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); 447 int ret; 448 449 if (!spi_mem_supports_op(mem, op)) 450 return -EOPNOTSUPP; 451 452 ret = pm_runtime_resume_and_get(qspi->dev); 453 if (ret < 0) 454 return ret; 455 456 mutex_lock(&qspi->lock); 457 458 writel_relaxed(mask, qspi->io_base + QSPI_PSMKR); 459 writel_relaxed(match, qspi->io_base + QSPI_PSMAR); 460 qspi->fmode = CCR_FMODE_APM; 461 qspi->status_timeout = timeout_ms; 462 463 ret = stm32_qspi_send(mem->spi, op); 464 mutex_unlock(&qspi->lock); 465 466 pm_runtime_put_autosuspend(qspi->dev); 467 468 return ret; 469} 470 471static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 472{ 473 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->controller); 474 int ret; 475 476 ret = pm_runtime_resume_and_get(qspi->dev); 477 if (ret < 0) 478 return ret; 479 480 mutex_lock(&qspi->lock); 481 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) 482 qspi->fmode = CCR_FMODE_INDR; 483 else 484 qspi->fmode = CCR_FMODE_INDW; 485 486 ret = stm32_qspi_send(mem->spi, op); 487 mutex_unlock(&qspi->lock); 488 489 pm_runtime_put_autosuspend(qspi->dev); 490 491 return ret; 492} 493 494static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc) 495{ 496 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller); 497 498 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) 499 return -EOPNOTSUPP; 500 501 /* should never happen, as mm_base == null is an error probe exit condition */ 502 if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) 503 return -EOPNOTSUPP; 504 505 if (!qspi->mm_size) 506 return -EOPNOTSUPP; 507 508 return 0; 509} 510 511static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc, 512 u64 offs, size_t len, void *buf) 513{ 514 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller); 515 struct spi_mem_op op; 516 u32 addr_max; 517 int ret; 518 519 ret = pm_runtime_resume_and_get(qspi->dev); 520 if (ret < 0) 521 return ret; 522 523 mutex_lock(&qspi->lock); 524 /* make a local copy of desc op_tmpl and complete dirmap rdesc 525 * spi_mem_op template with offs, len and *buf in order to get 526 * all needed transfer information into struct spi_mem_op 527 */ 528 memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op)); 529 dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf); 530 531 op.data.nbytes = len; 532 op.addr.val = desc->info.offset + offs; 533 op.data.buf.in = buf; 534 535 addr_max = op.addr.val + op.data.nbytes + 1; 536 if (addr_max < qspi->mm_size && op.addr.buswidth) 537 qspi->fmode = CCR_FMODE_MM; 538 else 539 qspi->fmode = CCR_FMODE_INDR; 540 541 ret = stm32_qspi_send(desc->mem->spi, &op); 542 mutex_unlock(&qspi->lock); 543 544 pm_runtime_put_autosuspend(qspi->dev); 545 546 return ret ?: len; 547} 548 549static int stm32_qspi_transfer_one_message(struct spi_controller *ctrl, 550 struct spi_message *msg) 551{ 552 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); 553 struct spi_transfer *transfer; 554 struct spi_device *spi = msg->spi; 555 struct spi_mem_op op; 556 int ret = 0; 557 558 if (!spi_get_csgpiod(spi, 0)) 559 return -EOPNOTSUPP; 560 561 ret = pm_runtime_resume_and_get(qspi->dev); 562 if (ret < 0) 563 return ret; 564 565 mutex_lock(&qspi->lock); 566 567 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true); 568 569 list_for_each_entry(transfer, &msg->transfers, transfer_list) { 570 u8 dummy_bytes = 0; 571 572 memset(&op, 0, sizeof(op)); 573 574 dev_dbg(qspi->dev, "tx_buf:%p tx_nbits:%d rx_buf:%p rx_nbits:%d len:%d dummy_data:%d\n", 575 transfer->tx_buf, transfer->tx_nbits, 576 transfer->rx_buf, transfer->rx_nbits, 577 transfer->len, transfer->dummy_data); 578 579 /* 580 * QSPI hardware supports dummy bytes transfer. 581 * If current transfer is dummy byte, merge it with the next 582 * transfer in order to take into account QSPI block constraint 583 */ 584 if (transfer->dummy_data) { 585 op.dummy.buswidth = transfer->tx_nbits; 586 op.dummy.nbytes = transfer->len; 587 dummy_bytes = transfer->len; 588 589 /* if happens, means that message is not correctly built */ 590 if (list_is_last(&transfer->transfer_list, &msg->transfers)) { 591 ret = -EINVAL; 592 goto end_of_transfer; 593 } 594 595 transfer = list_next_entry(transfer, transfer_list); 596 } 597 598 op.data.nbytes = transfer->len; 599 600 if (transfer->rx_buf) { 601 qspi->fmode = CCR_FMODE_INDR; 602 op.data.buswidth = transfer->rx_nbits; 603 op.data.dir = SPI_MEM_DATA_IN; 604 op.data.buf.in = transfer->rx_buf; 605 } else { 606 qspi->fmode = CCR_FMODE_INDW; 607 op.data.buswidth = transfer->tx_nbits; 608 op.data.dir = SPI_MEM_DATA_OUT; 609 op.data.buf.out = transfer->tx_buf; 610 } 611 612 ret = stm32_qspi_send(spi, &op); 613 if (ret) 614 goto end_of_transfer; 615 616 msg->actual_length += transfer->len + dummy_bytes; 617 } 618 619end_of_transfer: 620 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false); 621 622 mutex_unlock(&qspi->lock); 623 624 msg->status = ret; 625 spi_finalize_current_message(ctrl); 626 627 pm_runtime_put_autosuspend(qspi->dev); 628 629 return ret; 630} 631 632static int stm32_qspi_setup(struct spi_device *spi) 633{ 634 struct spi_controller *ctrl = spi->controller; 635 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); 636 struct stm32_qspi_flash *flash; 637 u32 presc, mode; 638 int ret; 639 640 if (ctrl->busy) 641 return -EBUSY; 642 643 if (!spi->max_speed_hz) 644 return -EINVAL; 645 646 mode = spi->mode & (SPI_TX_OCTAL | SPI_RX_OCTAL); 647 if (mode && gpiod_count(qspi->dev, "cs") == -ENOENT) { 648 dev_err(qspi->dev, "spi-rx-bus-width\\/spi-tx-bus-width\\/cs-gpios\n"); 649 dev_err(qspi->dev, "configuration not supported\n"); 650 651 return -EINVAL; 652 } 653 654 ret = pm_runtime_resume_and_get(qspi->dev); 655 if (ret < 0) 656 return ret; 657 658 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1; 659 660 flash = &qspi->flash[spi_get_chipselect(spi, 0)]; 661 flash->cs = spi_get_chipselect(spi, 0); 662 flash->presc = presc; 663 664 mutex_lock(&qspi->lock); 665 qspi->cr_reg = CR_APMS | 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN; 666 667 /* 668 * Dual flash mode is only enable in case SPI_TX_OCTAL or SPI_RX_OCTAL 669 * is set in spi->mode and "cs-gpios" properties is found in DT 670 */ 671 if (mode) { 672 qspi->cr_reg |= CR_DFM; 673 dev_dbg(qspi->dev, "Dual flash mode enable"); 674 } 675 676 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); 677 678 /* set dcr fsize to max address */ 679 qspi->dcr_reg = DCR_FSIZE_MASK; 680 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); 681 mutex_unlock(&qspi->lock); 682 683 pm_runtime_put_autosuspend(qspi->dev); 684 685 return 0; 686} 687 688static int stm32_qspi_dma_setup(struct stm32_qspi *qspi) 689{ 690 struct dma_slave_config dma_cfg; 691 struct device *dev = qspi->dev; 692 int ret = 0; 693 694 memset(&dma_cfg, 0, sizeof(dma_cfg)); 695 696 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 697 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 698 dma_cfg.src_addr = qspi->phys_base + QSPI_DR; 699 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR; 700 dma_cfg.src_maxburst = 4; 701 dma_cfg.dst_maxburst = 4; 702 703 qspi->dma_chrx = dma_request_chan(dev, "rx"); 704 if (IS_ERR(qspi->dma_chrx)) { 705 ret = PTR_ERR(qspi->dma_chrx); 706 qspi->dma_chrx = NULL; 707 if (ret == -EPROBE_DEFER) 708 goto out; 709 } else { 710 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) { 711 dev_err(dev, "dma rx config failed\n"); 712 dma_release_channel(qspi->dma_chrx); 713 qspi->dma_chrx = NULL; 714 } 715 } 716 717 qspi->dma_chtx = dma_request_chan(dev, "tx"); 718 if (IS_ERR(qspi->dma_chtx)) { 719 ret = PTR_ERR(qspi->dma_chtx); 720 qspi->dma_chtx = NULL; 721 } else { 722 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) { 723 dev_err(dev, "dma tx config failed\n"); 724 dma_release_channel(qspi->dma_chtx); 725 qspi->dma_chtx = NULL; 726 } 727 } 728 729out: 730 init_completion(&qspi->dma_completion); 731 732 if (ret != -EPROBE_DEFER) 733 ret = 0; 734 735 return ret; 736} 737 738static void stm32_qspi_dma_free(struct stm32_qspi *qspi) 739{ 740 if (qspi->dma_chtx) 741 dma_release_channel(qspi->dma_chtx); 742 if (qspi->dma_chrx) 743 dma_release_channel(qspi->dma_chrx); 744} 745 746/* 747 * no special host constraint, so use default spi_mem_default_supports_op 748 * to check supported mode. 749 */ 750static const struct spi_controller_mem_ops stm32_qspi_mem_ops = { 751 .exec_op = stm32_qspi_exec_op, 752 .dirmap_create = stm32_qspi_dirmap_create, 753 .dirmap_read = stm32_qspi_dirmap_read, 754 .poll_status = stm32_qspi_poll_status, 755}; 756 757static int stm32_qspi_probe(struct platform_device *pdev) 758{ 759 struct device *dev = &pdev->dev; 760 struct spi_controller *ctrl; 761 struct reset_control *rstc; 762 struct stm32_qspi *qspi; 763 struct resource *res; 764 int ret, irq; 765 766 ctrl = devm_spi_alloc_host(dev, sizeof(*qspi)); 767 if (!ctrl) 768 return -ENOMEM; 769 770 qspi = spi_controller_get_devdata(ctrl); 771 qspi->ctrl = ctrl; 772 773 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi"); 774 qspi->io_base = devm_ioremap_resource(dev, res); 775 if (IS_ERR(qspi->io_base)) 776 return PTR_ERR(qspi->io_base); 777 778 qspi->phys_base = res->start; 779 780 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm"); 781 qspi->mm_base = devm_ioremap_resource(dev, res); 782 if (IS_ERR(qspi->mm_base)) 783 return PTR_ERR(qspi->mm_base); 784 785 qspi->mm_size = resource_size(res); 786 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) 787 return -EINVAL; 788 789 irq = platform_get_irq(pdev, 0); 790 if (irq < 0) 791 return irq; 792 793 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0, 794 dev_name(dev), qspi); 795 if (ret) { 796 dev_err(dev, "failed to request irq\n"); 797 return ret; 798 } 799 800 init_completion(&qspi->data_completion); 801 init_completion(&qspi->match_completion); 802 803 qspi->clk = devm_clk_get(dev, NULL); 804 if (IS_ERR(qspi->clk)) 805 return PTR_ERR(qspi->clk); 806 807 qspi->clk_rate = clk_get_rate(qspi->clk); 808 if (!qspi->clk_rate) 809 return -EINVAL; 810 811 ret = clk_prepare_enable(qspi->clk); 812 if (ret) { 813 dev_err(dev, "can not enable the clock\n"); 814 return ret; 815 } 816 817 rstc = devm_reset_control_get_exclusive(dev, NULL); 818 if (IS_ERR(rstc)) { 819 ret = PTR_ERR(rstc); 820 if (ret == -EPROBE_DEFER) 821 goto err_clk_disable; 822 } else { 823 reset_control_assert(rstc); 824 udelay(2); 825 reset_control_deassert(rstc); 826 } 827 828 qspi->dev = dev; 829 platform_set_drvdata(pdev, qspi); 830 ret = stm32_qspi_dma_setup(qspi); 831 if (ret) 832 goto err_dma_free; 833 834 mutex_init(&qspi->lock); 835 836 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL 837 | SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_OCTAL; 838 ctrl->setup = stm32_qspi_setup; 839 ctrl->bus_num = -1; 840 ctrl->mem_ops = &stm32_qspi_mem_ops; 841 ctrl->use_gpio_descriptors = true; 842 ctrl->transfer_one_message = stm32_qspi_transfer_one_message; 843 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP; 844 ctrl->dev.of_node = dev->of_node; 845 846 pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY); 847 pm_runtime_use_autosuspend(dev); 848 pm_runtime_set_active(dev); 849 pm_runtime_enable(dev); 850 pm_runtime_get_noresume(dev); 851 852 ret = spi_register_controller(ctrl); 853 if (ret) 854 goto err_pm_runtime_free; 855 856 pm_runtime_put_autosuspend(dev); 857 858 return 0; 859 860err_pm_runtime_free: 861 pm_runtime_get_sync(qspi->dev); 862 /* disable qspi */ 863 writel_relaxed(0, qspi->io_base + QSPI_CR); 864 mutex_destroy(&qspi->lock); 865 pm_runtime_put_noidle(qspi->dev); 866 pm_runtime_disable(qspi->dev); 867 pm_runtime_set_suspended(qspi->dev); 868 pm_runtime_dont_use_autosuspend(qspi->dev); 869err_dma_free: 870 stm32_qspi_dma_free(qspi); 871err_clk_disable: 872 clk_disable_unprepare(qspi->clk); 873 874 return ret; 875} 876 877static void stm32_qspi_remove(struct platform_device *pdev) 878{ 879 struct stm32_qspi *qspi = platform_get_drvdata(pdev); 880 881 pm_runtime_get_sync(qspi->dev); 882 spi_unregister_controller(qspi->ctrl); 883 /* disable qspi */ 884 writel_relaxed(0, qspi->io_base + QSPI_CR); 885 stm32_qspi_dma_free(qspi); 886 mutex_destroy(&qspi->lock); 887 pm_runtime_put_noidle(qspi->dev); 888 pm_runtime_disable(qspi->dev); 889 pm_runtime_set_suspended(qspi->dev); 890 pm_runtime_dont_use_autosuspend(qspi->dev); 891 clk_disable_unprepare(qspi->clk); 892} 893 894static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev) 895{ 896 struct stm32_qspi *qspi = dev_get_drvdata(dev); 897 898 clk_disable_unprepare(qspi->clk); 899 900 return 0; 901} 902 903static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev) 904{ 905 struct stm32_qspi *qspi = dev_get_drvdata(dev); 906 907 return clk_prepare_enable(qspi->clk); 908} 909 910static int __maybe_unused stm32_qspi_suspend(struct device *dev) 911{ 912 pinctrl_pm_select_sleep_state(dev); 913 914 return pm_runtime_force_suspend(dev); 915} 916 917static int __maybe_unused stm32_qspi_resume(struct device *dev) 918{ 919 struct stm32_qspi *qspi = dev_get_drvdata(dev); 920 int ret; 921 922 ret = pm_runtime_force_resume(dev); 923 if (ret < 0) 924 return ret; 925 926 pinctrl_pm_select_default_state(dev); 927 928 ret = pm_runtime_resume_and_get(dev); 929 if (ret < 0) 930 return ret; 931 932 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); 933 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); 934 935 pm_runtime_put_autosuspend(dev); 936 937 return 0; 938} 939 940static const struct dev_pm_ops stm32_qspi_pm_ops = { 941 SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend, 942 stm32_qspi_runtime_resume, NULL) 943 SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume) 944}; 945 946static const struct of_device_id stm32_qspi_match[] = { 947 {.compatible = "st,stm32f469-qspi"}, 948 {} 949}; 950MODULE_DEVICE_TABLE(of, stm32_qspi_match); 951 952static struct platform_driver stm32_qspi_driver = { 953 .probe = stm32_qspi_probe, 954 .remove = stm32_qspi_remove, 955 .driver = { 956 .name = "stm32-qspi", 957 .of_match_table = stm32_qspi_match, 958 .pm = &stm32_qspi_pm_ops, 959 }, 960}; 961module_platform_driver(stm32_qspi_driver); 962 963MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>"); 964MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver"); 965MODULE_LICENSE("GPL v2");
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