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spi-sh-msiof.c
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linux-6.19.14/drivers/spi/spi-sh-msiof.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SuperH MSIOF SPI Controller Interface 4 * 5 * Copyright (c) 2009 Magnus Damm 6 * Copyright (C) 2014 Renesas Electronics Corporation 7 * Copyright (C) 2014-2017 Glider bvba 8 */ 9 10#include <linux/bitmap.h> 11#include <linux/clk.h> 12#include <linux/completion.h> 13#include <linux/delay.h> 14#include <linux/dma-mapping.h> 15#include <linux/dmaengine.h> 16#include <linux/err.h> 17#include <linux/interrupt.h> 18#include <linux/io.h> 19#include <linux/iopoll.h> 20#include <linux/kernel.h> 21#include <linux/module.h> 22#include <linux/of.h> 23#include <linux/of_graph.h> 24#include <linux/platform_device.h> 25#include <linux/pm_runtime.h> 26#include <linux/sh_dma.h> 27 28#include <linux/spi/sh_msiof.h> 29#include <linux/spi/spi.h> 30 31#include <linux/unaligned.h> 32 33#define SH_MSIOF_FLAG_FIXED_DTDL_200 BIT(0) 34 35struct sh_msiof_chipdata { 36 u32 bits_per_word_mask; 37 u16 tx_fifo_size; 38 u16 rx_fifo_size; 39 u16 ctlr_flags; 40 u16 min_div_pow; 41 u32 flags; 42}; 43 44struct sh_msiof_spi_priv { 45 struct spi_controller *ctlr; 46 void __iomem *mapbase; 47 struct clk *clk; 48 struct platform_device *pdev; 49 struct sh_msiof_spi_info *info; 50 struct completion done; 51 struct completion done_txdma; 52 unsigned int tx_fifo_size; 53 unsigned int rx_fifo_size; 54 unsigned int min_div_pow; 55 void *tx_dma_page; 56 void *rx_dma_page; 57 dma_addr_t tx_dma_addr; 58 dma_addr_t rx_dma_addr; 59 bool native_cs_inited; 60 bool native_cs_high; 61 bool target_aborted; 62}; 63 64#define MAX_SS 3 /* Maximum number of native chip selects */ 65 66static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 67{ 68 switch (reg_offs) { 69 case SITSCR: 70 case SIRSCR: 71 return ioread16(p->mapbase + reg_offs); 72 default: 73 return ioread32(p->mapbase + reg_offs); 74 } 75} 76 77static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, 78 u32 value) 79{ 80 switch (reg_offs) { 81 case SITSCR: 82 case SIRSCR: 83 iowrite16(value, p->mapbase + reg_offs); 84 break; 85 default: 86 iowrite32(value, p->mapbase + reg_offs); 87 break; 88 } 89} 90 91static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, 92 u32 clr, u32 set) 93{ 94 u32 mask = clr | set; 95 u32 data; 96 97 data = sh_msiof_read(p, SICTR); 98 data &= ~clr; 99 data |= set; 100 sh_msiof_write(p, SICTR, data); 101 102 return readl_poll_timeout_atomic(p->mapbase + SICTR, data, 103 (data & mask) == set, 1, 100); 104} 105 106static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 107{ 108 struct sh_msiof_spi_priv *p = data; 109 110 /* just disable the interrupt and wake up */ 111 sh_msiof_write(p, SIIER, 0); 112 complete(&p->done); 113 114 return IRQ_HANDLED; 115} 116 117static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p) 118{ 119 u32 mask = SICTR_TXRST | SICTR_RXRST; 120 u32 data; 121 122 data = sh_msiof_read(p, SICTR); 123 data |= mask; 124 sh_msiof_write(p, SICTR, data); 125 126 readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1, 127 100); 128} 129 130static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 131 struct spi_transfer *t) 132{ 133 unsigned long parent_rate = clk_get_rate(p->clk); 134 unsigned int div_pow = p->min_div_pow; 135 u32 spi_hz = t->speed_hz; 136 unsigned long div; 137 u32 brps, scr; 138 139 if (!spi_hz || !parent_rate) { 140 WARN(1, "Invalid clock rate parameters %lu and %u\n", 141 parent_rate, spi_hz); 142 return; 143 } 144 145 div = DIV_ROUND_UP(parent_rate, spi_hz); 146 if (div <= 1024) { 147 /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ 148 if (!div_pow && div <= 32 && div > 2) 149 div_pow = 1; 150 151 if (div_pow) 152 brps = (div + 1) >> div_pow; 153 else 154 brps = div; 155 156 for (; brps > 32; div_pow++) 157 brps = (brps + 1) >> 1; 158 } else { 159 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */ 160 dev_err(&p->pdev->dev, 161 "Requested SPI transfer rate %d is too low\n", spi_hz); 162 div_pow = 5; 163 brps = 32; 164 } 165 166 t->effective_speed_hz = parent_rate / (brps << div_pow); 167 168 /* div_pow == 0 maps to SISCR_BRDV_DIV_1 == all ones */ 169 scr = FIELD_PREP(SISCR_BRDV, div_pow - 1) | 170 FIELD_PREP(SISCR_BRPS, brps - 1); 171 sh_msiof_write(p, SITSCR, scr); 172 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 173 sh_msiof_write(p, SIRSCR, scr); 174} 175 176static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) 177{ 178 /* 179 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl 180 * b'000 : 0 181 * b'001 : 100 182 * b'010 : 200 183 * b'011 (SYNCDL only) : 300 184 * b'101 : 50 185 * b'110 : 150 186 */ 187 if (dtdl_or_syncdl % 100) 188 return dtdl_or_syncdl / 100 + 5; 189 else 190 return dtdl_or_syncdl / 100; 191} 192 193static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) 194{ 195 u32 val; 196 197 if (!p->info) 198 return 0; 199 200 /* check if DTDL and SYNCDL is allowed value */ 201 if (p->info->dtdl > 200 || p->info->syncdl > 300) { 202 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); 203 return 0; 204 } 205 206 /* check if the sum of DTDL and SYNCDL becomes an integer value */ 207 if ((p->info->dtdl + p->info->syncdl) % 100) { 208 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); 209 return 0; 210 } 211 212 val = FIELD_PREP(SIMDR1_DTDL, sh_msiof_get_delay_bit(p->info->dtdl)) | 213 FIELD_PREP(SIMDR1_SYNCDL, 214 sh_msiof_get_delay_bit(p->info->syncdl)); 215 216 return val; 217} 218 219static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, 220 bool cpol, bool cpha, bool tx_hi_z, 221 bool lsb_first, bool cs_high) 222{ 223 bool edge; 224 u32 tmp; 225 226 /* 227 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG 228 * 0 0 10 10 1 1 229 * 0 1 10 10 0 0 230 * 1 0 11 11 0 0 231 * 1 1 11 11 1 1 232 */ 233 tmp = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_SPI) | 234 FIELD_PREP(SIMDR1_FLD, 1) | SIMDR1_XXSTP | 235 FIELD_PREP(SIMDR1_SYNCAC, !cs_high) | 236 FIELD_PREP(SIMDR1_BITLSB, lsb_first); 237 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); 238 if (spi_controller_is_target(p->ctlr)) { 239 sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON); 240 } else { 241 sh_msiof_write(p, SITMDR1, 242 tmp | SIMDR1_TRMD | SITMDR1_PCON | 243 FIELD_PREP(SITMDR1_SYNCCH, 244 ss < MAX_SS ? ss : 0)); 245 } 246 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) { 247 /* These bits are reserved if RX needs TX */ 248 tmp &= ~0x0000ffff; 249 } 250 sh_msiof_write(p, SIRMDR1, tmp); 251 252 tmp = 0; 253 tmp |= SICTR_TSCKIZ_SCK | FIELD_PREP(SICTR_TSCKIZ_POL, cpol); 254 tmp |= SICTR_RSCKIZ_SCK | FIELD_PREP(SICTR_RSCKIZ_POL, cpol); 255 256 edge = cpol ^ !cpha; 257 258 tmp |= FIELD_PREP(SICTR_TEDG, edge); 259 tmp |= FIELD_PREP(SICTR_REDG, edge); 260 tmp |= FIELD_PREP(SICTR_TXDIZ, 261 tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW); 262 sh_msiof_write(p, SICTR, tmp); 263} 264 265static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 266 const void *tx_buf, void *rx_buf, 267 u32 bits, u32 words1, u32 words2) 268{ 269 u32 dr2 = FIELD_PREP(SIMDR2_GRP, words2 ? 1 : 0) | 270 FIELD_PREP(SIMDR2_BITLEN1, bits - 1) | 271 FIELD_PREP(SIMDR2_WDLEN1, words1 - 1); 272 273 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 274 sh_msiof_write(p, SITMDR2, dr2); 275 else 276 sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK); 277 278 if (rx_buf) 279 sh_msiof_write(p, SIRMDR2, dr2); 280 281 if (words2) { 282 u32 dr3 = FIELD_PREP(SIMDR3_BITLEN2, bits - 1) | 283 FIELD_PREP(SIMDR3_WDLEN2, words2 - 1); 284 285 sh_msiof_write(p, SITMDR3, dr3); 286 if (rx_buf) 287 sh_msiof_write(p, SIRMDR3, dr3); 288 } 289} 290 291static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 292{ 293 sh_msiof_write(p, SISTR, 294 sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ)); 295} 296 297static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, 298 const void *tx_buf, unsigned int words, 299 unsigned int fs) 300{ 301 const u8 *buf_8 = tx_buf; 302 unsigned int k; 303 304 for (k = 0; k < words; k++) 305 sh_msiof_write(p, SITFDR, buf_8[k] << fs); 306} 307 308static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, 309 const void *tx_buf, unsigned int words, 310 unsigned int fs) 311{ 312 const u16 *buf_16 = tx_buf; 313 unsigned int k; 314 315 for (k = 0; k < words; k++) 316 sh_msiof_write(p, SITFDR, buf_16[k] << fs); 317} 318 319static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, 320 const void *tx_buf, unsigned int words, 321 unsigned int fs) 322{ 323 const u16 *buf_16 = tx_buf; 324 unsigned int k; 325 326 for (k = 0; k < words; k++) 327 sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs); 328} 329 330static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, 331 const void *tx_buf, unsigned int words, 332 unsigned int fs) 333{ 334 const u32 *buf_32 = tx_buf; 335 unsigned int k; 336 337 for (k = 0; k < words; k++) 338 sh_msiof_write(p, SITFDR, buf_32[k] << fs); 339} 340 341static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, 342 const void *tx_buf, unsigned int words, 343 unsigned int fs) 344{ 345 const u32 *buf_32 = tx_buf; 346 unsigned int k; 347 348 for (k = 0; k < words; k++) 349 sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs); 350} 351 352static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, 353 const void *tx_buf, unsigned int words, 354 unsigned int fs) 355{ 356 const u32 *buf_32 = tx_buf; 357 unsigned int k; 358 359 for (k = 0; k < words; k++) 360 sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs)); 361} 362 363static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, 364 const void *tx_buf, 365 unsigned int words, unsigned int fs) 366{ 367 const u32 *buf_32 = tx_buf; 368 unsigned int k; 369 370 for (k = 0; k < words; k++) 371 sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs)); 372} 373 374static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, 375 void *rx_buf, unsigned int words, 376 unsigned int fs) 377{ 378 u8 *buf_8 = rx_buf; 379 unsigned int k; 380 381 for (k = 0; k < words; k++) 382 buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs; 383} 384 385static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, 386 void *rx_buf, unsigned int words, 387 unsigned int fs) 388{ 389 u16 *buf_16 = rx_buf; 390 unsigned int k; 391 392 for (k = 0; k < words; k++) 393 buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs; 394} 395 396static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, 397 void *rx_buf, unsigned int words, 398 unsigned int fs) 399{ 400 u16 *buf_16 = rx_buf; 401 unsigned int k; 402 403 for (k = 0; k < words; k++) 404 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]); 405} 406 407static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, 408 void *rx_buf, unsigned int words, 409 unsigned int fs) 410{ 411 u32 *buf_32 = rx_buf; 412 unsigned int k; 413 414 for (k = 0; k < words; k++) 415 buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs; 416} 417 418static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, 419 void *rx_buf, unsigned int words, 420 unsigned int fs) 421{ 422 u32 *buf_32 = rx_buf; 423 unsigned int k; 424 425 for (k = 0; k < words; k++) 426 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]); 427} 428 429static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, 430 void *rx_buf, unsigned int words, 431 unsigned int fs) 432{ 433 u32 *buf_32 = rx_buf; 434 unsigned int k; 435 436 for (k = 0; k < words; k++) 437 buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs); 438} 439 440static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, 441 void *rx_buf, unsigned int words, 442 unsigned int fs) 443{ 444 u32 *buf_32 = rx_buf; 445 unsigned int k; 446 447 for (k = 0; k < words; k++) 448 put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]); 449} 450 451static int sh_msiof_spi_setup(struct spi_device *spi) 452{ 453 struct sh_msiof_spi_priv *p = 454 spi_controller_get_devdata(spi->controller); 455 u32 clr, set, tmp; 456 457 if (spi_get_csgpiod(spi, 0) || spi_controller_is_target(p->ctlr)) 458 return 0; 459 460 if (p->native_cs_inited && 461 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH))) 462 return 0; 463 464 /* Configure native chip select mode/polarity early */ 465 clr = SIMDR1_SYNCMD; 466 set = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_SPI); 467 if (spi->mode & SPI_CS_HIGH) 468 clr |= SIMDR1_SYNCAC; 469 else 470 set |= SIMDR1_SYNCAC; 471 pm_runtime_get_sync(&p->pdev->dev); 472 tmp = sh_msiof_read(p, SITMDR1) & ~clr; 473 sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON); 474 tmp = sh_msiof_read(p, SIRMDR1) & ~clr; 475 sh_msiof_write(p, SIRMDR1, tmp | set); 476 pm_runtime_put(&p->pdev->dev); 477 p->native_cs_high = spi->mode & SPI_CS_HIGH; 478 p->native_cs_inited = true; 479 return 0; 480} 481 482static int sh_msiof_prepare_message(struct spi_controller *ctlr, 483 struct spi_message *msg) 484{ 485 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 486 const struct spi_device *spi = msg->spi; 487 bool cs_high; 488 u32 ss; 489 490 /* Configure pins before asserting CS */ 491 if (spi_get_csgpiod(spi, 0)) { 492 ss = ctlr->unused_native_cs; 493 cs_high = p->native_cs_high; 494 } else { 495 ss = spi_get_chipselect(spi, 0); 496 cs_high = spi->mode & SPI_CS_HIGH; 497 } 498 sh_msiof_spi_set_pin_regs(p, ss, spi->mode & SPI_CPOL, 499 spi->mode & SPI_CPHA, spi->mode & SPI_3WIRE, 500 spi->mode & SPI_LSB_FIRST, cs_high); 501 return 0; 502} 503 504static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 505{ 506 bool target = spi_controller_is_target(p->ctlr); 507 int ret = 0; 508 509 /* setup clock and rx/tx signals */ 510 if (!target) 511 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE); 512 if (rx_buf && !ret) 513 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE); 514 if (!ret) 515 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE); 516 517 /* start by setting frame bit */ 518 if (!ret && !target) 519 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE); 520 521 return ret; 522} 523 524static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 525{ 526 bool target = spi_controller_is_target(p->ctlr); 527 int ret = 0; 528 529 /* shut down frame, rx/tx and clock signals */ 530 if (!target) 531 ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0); 532 if (!ret) 533 ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0); 534 if (rx_buf && !ret) 535 ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0); 536 if (!ret && !target) 537 ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0); 538 539 return ret; 540} 541 542static int sh_msiof_target_abort(struct spi_controller *ctlr) 543{ 544 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 545 546 p->target_aborted = true; 547 complete(&p->done); 548 complete(&p->done_txdma); 549 return 0; 550} 551 552static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p, 553 struct completion *x) 554{ 555 if (spi_controller_is_target(p->ctlr)) { 556 if (wait_for_completion_interruptible(x) || 557 p->target_aborted) { 558 dev_dbg(&p->pdev->dev, "interrupted\n"); 559 return -EINTR; 560 } 561 } else { 562 if (!wait_for_completion_timeout(x, HZ)) { 563 dev_err(&p->pdev->dev, "timeout\n"); 564 return -ETIMEDOUT; 565 } 566 } 567 568 return 0; 569} 570 571static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 572 void (*tx_fifo)(struct sh_msiof_spi_priv *, 573 const void *, unsigned int, 574 unsigned int), 575 void (*rx_fifo)(struct sh_msiof_spi_priv *, 576 void *, unsigned int, 577 unsigned int), 578 const void *tx_buf, void *rx_buf, 579 unsigned int words, unsigned int bits) 580{ 581 unsigned int fifo_shift; 582 int ret; 583 584 /* limit maximum word transfer to rx/tx fifo size */ 585 if (tx_buf) 586 words = min(words, p->tx_fifo_size); 587 if (rx_buf) 588 words = min(words, p->rx_fifo_size); 589 590 /* the fifo contents need shifting */ 591 fifo_shift = 32 - bits; 592 593 /* default FIFO watermarks for PIO */ 594 sh_msiof_write(p, SIFCTR, 0); 595 596 /* setup msiof transfer mode registers */ 597 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words, 0); 598 sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE); 599 600 /* write tx fifo */ 601 if (tx_buf) 602 tx_fifo(p, tx_buf, words, fifo_shift); 603 604 reinit_completion(&p->done); 605 p->target_aborted = false; 606 607 ret = sh_msiof_spi_start(p, rx_buf); 608 if (ret) { 609 dev_err(&p->pdev->dev, "failed to start hardware\n"); 610 goto stop_ier; 611 } 612 613 /* wait for tx fifo to be emptied / rx fifo to be filled */ 614 ret = sh_msiof_wait_for_completion(p, &p->done); 615 if (ret) 616 goto stop_reset; 617 618 /* read rx fifo */ 619 if (rx_buf) 620 rx_fifo(p, rx_buf, words, fifo_shift); 621 622 /* clear status bits */ 623 sh_msiof_reset_str(p); 624 625 ret = sh_msiof_spi_stop(p, rx_buf); 626 if (ret) { 627 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 628 return ret; 629 } 630 631 return words; 632 633stop_reset: 634 sh_msiof_reset_str(p); 635 sh_msiof_spi_stop(p, rx_buf); 636stop_ier: 637 sh_msiof_write(p, SIIER, 0); 638 return ret; 639} 640 641static void sh_msiof_dma_complete(void *arg) 642{ 643 complete(arg); 644} 645 646static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, 647 void *rx, unsigned int len, 648 unsigned int max_wdlen) 649{ 650 u32 ier_bits = 0; 651 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 652 unsigned int words1, words2; 653 dma_cookie_t cookie; 654 int ret; 655 656 /* First prepare and submit the DMA request(s), as this may fail */ 657 if (rx) { 658 ier_bits |= SIIER_RDREQE | SIIER_RDMAE; 659 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx, 660 p->rx_dma_addr, len, DMA_DEV_TO_MEM, 661 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 662 if (!desc_rx) 663 return -EAGAIN; 664 665 desc_rx->callback = sh_msiof_dma_complete; 666 desc_rx->callback_param = &p->done; 667 cookie = dmaengine_submit(desc_rx); 668 if (dma_submit_error(cookie)) 669 return cookie; 670 } 671 672 if (tx) { 673 ier_bits |= SIIER_TDREQE | SIIER_TDMAE; 674 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev, 675 p->tx_dma_addr, len, DMA_TO_DEVICE); 676 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx, 677 p->tx_dma_addr, len, DMA_MEM_TO_DEV, 678 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 679 if (!desc_tx) { 680 ret = -EAGAIN; 681 goto no_dma_tx; 682 } 683 684 desc_tx->callback = sh_msiof_dma_complete; 685 desc_tx->callback_param = &p->done_txdma; 686 cookie = dmaengine_submit(desc_tx); 687 if (dma_submit_error(cookie)) { 688 ret = cookie; 689 goto no_dma_tx; 690 } 691 } 692 693 /* 1 stage FIFO watermarks for DMA */ 694 sh_msiof_write(p, SIFCTR, 695 FIELD_PREP(SIFCTR_TFWM, SIFCTR_TFWM_1) | 696 FIELD_PREP(SIFCTR_RFWM, SIFCTR_RFWM_1)); 697 698 /* setup msiof transfer mode registers (32-bit words) */ 699 words1 = min(len / 4, max_wdlen); 700 words2 = len / 4 - words1; 701 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, words1, words2); 702 703 sh_msiof_write(p, SIIER, ier_bits); 704 705 reinit_completion(&p->done); 706 if (tx) 707 reinit_completion(&p->done_txdma); 708 p->target_aborted = false; 709 710 /* Now start DMA */ 711 if (rx) 712 dma_async_issue_pending(p->ctlr->dma_rx); 713 if (tx) 714 dma_async_issue_pending(p->ctlr->dma_tx); 715 716 ret = sh_msiof_spi_start(p, rx); 717 if (ret) { 718 dev_err(&p->pdev->dev, "failed to start hardware\n"); 719 goto stop_dma; 720 } 721 722 if (tx) { 723 /* wait for tx DMA completion */ 724 ret = sh_msiof_wait_for_completion(p, &p->done_txdma); 725 if (ret) 726 goto stop_reset; 727 } 728 729 if (rx) { 730 /* wait for rx DMA completion */ 731 ret = sh_msiof_wait_for_completion(p, &p->done); 732 if (ret) 733 goto stop_reset; 734 735 sh_msiof_write(p, SIIER, 0); 736 } else { 737 /* wait for tx fifo to be emptied */ 738 sh_msiof_write(p, SIIER, SIIER_TEOFE); 739 ret = sh_msiof_wait_for_completion(p, &p->done); 740 if (ret) 741 goto stop_reset; 742 } 743 744 /* clear status bits */ 745 sh_msiof_reset_str(p); 746 747 ret = sh_msiof_spi_stop(p, rx); 748 if (ret) { 749 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 750 return ret; 751 } 752 753 if (rx) 754 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev, 755 p->rx_dma_addr, len, DMA_FROM_DEVICE); 756 757 return 0; 758 759stop_reset: 760 sh_msiof_reset_str(p); 761 sh_msiof_spi_stop(p, rx); 762stop_dma: 763 if (tx) 764 dmaengine_terminate_sync(p->ctlr->dma_tx); 765no_dma_tx: 766 if (rx) 767 dmaengine_terminate_sync(p->ctlr->dma_rx); 768 sh_msiof_write(p, SIIER, 0); 769 return ret; 770} 771 772static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) 773{ 774 /* src or dst can be unaligned, but not both */ 775 if ((unsigned long)src & 3) { 776 while (words--) { 777 *dst++ = swab32(get_unaligned(src)); 778 src++; 779 } 780 } else if ((unsigned long)dst & 3) { 781 while (words--) { 782 put_unaligned(swab32(*src++), dst); 783 dst++; 784 } 785 } else { 786 while (words--) 787 *dst++ = swab32(*src++); 788 } 789} 790 791static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) 792{ 793 /* src or dst can be unaligned, but not both */ 794 if ((unsigned long)src & 3) { 795 while (words--) { 796 *dst++ = swahw32(get_unaligned(src)); 797 src++; 798 } 799 } else if ((unsigned long)dst & 3) { 800 while (words--) { 801 put_unaligned(swahw32(*src++), dst); 802 dst++; 803 } 804 } else { 805 while (words--) 806 *dst++ = swahw32(*src++); 807 } 808} 809 810static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) 811{ 812 memcpy(dst, src, words * 4); 813} 814 815static int sh_msiof_transfer_one(struct spi_controller *ctlr, 816 struct spi_device *spi, 817 struct spi_transfer *t) 818{ 819 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 820 unsigned int max_wdlen = FIELD_MAX(SIMDR2_WDLEN1) + 1; 821 void (*copy32)(u32 *, const u32 *, unsigned int); 822 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, unsigned int, 823 unsigned int); 824 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, unsigned int, 825 unsigned int); 826 const void *tx_buf = t->tx_buf; 827 void *rx_buf = t->rx_buf; 828 unsigned int len = t->len; 829 unsigned int bits = t->bits_per_word; 830 unsigned int bytes_per_word; 831 unsigned int words; 832 int n; 833 bool swab; 834 int ret; 835 836 /* reset registers */ 837 sh_msiof_spi_reset_regs(p); 838 839 /* setup clocks (clock already enabled in chipselect()) */ 840 if (!spi_controller_is_target(p->ctlr)) 841 sh_msiof_spi_set_clk_regs(p, t); 842 843 if (tx_buf) 844 max_wdlen = min(max_wdlen, p->tx_fifo_size); 845 if (rx_buf) 846 max_wdlen = min(max_wdlen, p->rx_fifo_size); 847 848 while (ctlr->dma_tx && len > 15) { 849 /* 850 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 851 * words, with byte resp. word swapping. 852 */ 853 unsigned int l = min(round_down(len, 4), 2 * max_wdlen * 4); 854 855 if (bits <= 8) { 856 copy32 = copy_bswap32; 857 } else if (bits <= 16) { 858 copy32 = copy_wswap32; 859 } else { 860 copy32 = copy_plain32; 861 } 862 863 if (tx_buf) 864 copy32(p->tx_dma_page, tx_buf, l / 4); 865 866 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l, max_wdlen); 867 if (ret == -EAGAIN) { 868 dev_warn_once(&p->pdev->dev, 869 "DMA not available, falling back to PIO\n"); 870 break; 871 } 872 if (ret) 873 return ret; 874 875 if (rx_buf) { 876 copy32(rx_buf, p->rx_dma_page, l / 4); 877 rx_buf += l; 878 } 879 if (tx_buf) 880 tx_buf += l; 881 882 len -= l; 883 if (!len) 884 return 0; 885 } 886 887 if (bits <= 8 && len > 15) { 888 bits = 32; 889 swab = true; 890 } else { 891 swab = false; 892 } 893 894 /* setup bytes per word and fifo read/write functions */ 895 if (bits <= 8) { 896 bytes_per_word = 1; 897 tx_fifo = sh_msiof_spi_write_fifo_8; 898 rx_fifo = sh_msiof_spi_read_fifo_8; 899 } else if (bits <= 16) { 900 bytes_per_word = 2; 901 if ((unsigned long)tx_buf & 0x01) 902 tx_fifo = sh_msiof_spi_write_fifo_16u; 903 else 904 tx_fifo = sh_msiof_spi_write_fifo_16; 905 906 if ((unsigned long)rx_buf & 0x01) 907 rx_fifo = sh_msiof_spi_read_fifo_16u; 908 else 909 rx_fifo = sh_msiof_spi_read_fifo_16; 910 } else if (swab) { 911 bytes_per_word = 4; 912 if ((unsigned long)tx_buf & 0x03) 913 tx_fifo = sh_msiof_spi_write_fifo_s32u; 914 else 915 tx_fifo = sh_msiof_spi_write_fifo_s32; 916 917 if ((unsigned long)rx_buf & 0x03) 918 rx_fifo = sh_msiof_spi_read_fifo_s32u; 919 else 920 rx_fifo = sh_msiof_spi_read_fifo_s32; 921 } else { 922 bytes_per_word = 4; 923 if ((unsigned long)tx_buf & 0x03) 924 tx_fifo = sh_msiof_spi_write_fifo_32u; 925 else 926 tx_fifo = sh_msiof_spi_write_fifo_32; 927 928 if ((unsigned long)rx_buf & 0x03) 929 rx_fifo = sh_msiof_spi_read_fifo_32u; 930 else 931 rx_fifo = sh_msiof_spi_read_fifo_32; 932 } 933 934 /* transfer in fifo sized chunks */ 935 words = len / bytes_per_word; 936 937 while (words > 0) { 938 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, 939 words, bits); 940 if (n < 0) 941 return n; 942 943 if (tx_buf) 944 tx_buf += n * bytes_per_word; 945 if (rx_buf) 946 rx_buf += n * bytes_per_word; 947 words -= n; 948 949 if (words == 0 && (len % bytes_per_word)) { 950 words = len % bytes_per_word; 951 bits = t->bits_per_word; 952 bytes_per_word = 1; 953 tx_fifo = sh_msiof_spi_write_fifo_8; 954 rx_fifo = sh_msiof_spi_read_fifo_8; 955 } 956 } 957 958 return 0; 959} 960 961static const struct sh_msiof_chipdata sh_data = { 962 .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32), 963 .tx_fifo_size = 64, 964 .rx_fifo_size = 64, 965 .ctlr_flags = 0, 966 .min_div_pow = 0, 967}; 968 969static const struct sh_msiof_chipdata rcar_gen2_data = { 970 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 971 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 972 .tx_fifo_size = 64, 973 .rx_fifo_size = 128, 974 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 975 .min_div_pow = 0, 976}; 977 978static const struct sh_msiof_chipdata rcar_gen3_data = { 979 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 980 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 981 .tx_fifo_size = 64, 982 .rx_fifo_size = 256, 983 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 984 .min_div_pow = 1, 985}; 986 987static const struct sh_msiof_chipdata rcar_gen4_data = { 988 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 989 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 990 .tx_fifo_size = 256, 991 .rx_fifo_size = 256, 992 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 993 .min_div_pow = 1, 994}; 995 996static const struct sh_msiof_chipdata rcar_r8a7795_data = { 997 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 998 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 999 .tx_fifo_size = 64, 1000 .rx_fifo_size = 256, 1001 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1002 .min_div_pow = 1, 1003 .flags = SH_MSIOF_FLAG_FIXED_DTDL_200, 1004}; 1005 1006static const struct of_device_id sh_msiof_match[] __maybe_unused = { 1007 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 1008 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data }, 1009 { .compatible = "renesas,msiof-r8a7795", .data = &rcar_r8a7795_data }, 1010 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data }, 1011 { .compatible = "renesas,msiof-r8a779a0", .data = &rcar_gen3_data }, 1012 { .compatible = "renesas,msiof-r8a779f0", .data = &rcar_gen3_data }, 1013 { .compatible = "renesas,rcar-gen4-msiof", .data = &rcar_gen4_data }, 1014 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ 1015 { /* sentinel */ } 1016}; 1017MODULE_DEVICE_TABLE(of, sh_msiof_match); 1018 1019#ifdef CONFIG_OF 1020static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1021{ 1022 struct sh_msiof_spi_info *info; 1023 struct device_node *np = dev->of_node; 1024 u32 num_cs = 1; 1025 1026 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 1027 if (!info) 1028 return NULL; 1029 1030 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_TARGET 1031 : MSIOF_SPI_HOST; 1032 1033 /* Parse the MSIOF properties */ 1034 if (info->mode == MSIOF_SPI_HOST) 1035 of_property_read_u32(np, "num-cs", &num_cs); 1036 of_property_read_u32(np, "renesas,tx-fifo-size", 1037 &info->tx_fifo_override); 1038 of_property_read_u32(np, "renesas,rx-fifo-size", 1039 &info->rx_fifo_override); 1040 of_property_read_u32(np, "renesas,dtdl", &info->dtdl); 1041 of_property_read_u32(np, "renesas,syncdl", &info->syncdl); 1042 1043 info->num_chipselect = num_cs; 1044 1045 return info; 1046} 1047#else 1048static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1049{ 1050 return NULL; 1051} 1052#endif 1053 1054static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, 1055 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) 1056{ 1057 dma_cap_mask_t mask; 1058 struct dma_chan *chan; 1059 struct dma_slave_config cfg; 1060 int ret; 1061 1062 dma_cap_zero(mask); 1063 dma_cap_set(DMA_SLAVE, mask); 1064 1065 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 1066 (void *)(unsigned long)id, dev, 1067 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1068 if (!chan) { 1069 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 1070 return NULL; 1071 } 1072 1073 memset(&cfg, 0, sizeof(cfg)); 1074 cfg.direction = dir; 1075 if (dir == DMA_MEM_TO_DEV) { 1076 cfg.dst_addr = port_addr; 1077 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1078 } else { 1079 cfg.src_addr = port_addr; 1080 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1081 } 1082 1083 ret = dmaengine_slave_config(chan, &cfg); 1084 if (ret) { 1085 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1086 dma_release_channel(chan); 1087 return NULL; 1088 } 1089 1090 return chan; 1091} 1092 1093static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) 1094{ 1095 struct platform_device *pdev = p->pdev; 1096 struct device *dev = &pdev->dev; 1097 const struct sh_msiof_spi_info *info = p->info; 1098 unsigned int dma_tx_id, dma_rx_id; 1099 const struct resource *res; 1100 struct spi_controller *ctlr; 1101 struct device *tx_dev, *rx_dev; 1102 1103 if (dev->of_node) { 1104 /* In the OF case we will get the slave IDs from the DT */ 1105 dma_tx_id = 0; 1106 dma_rx_id = 0; 1107 } else if (info && info->dma_tx_id && info->dma_rx_id) { 1108 dma_tx_id = info->dma_tx_id; 1109 dma_rx_id = info->dma_rx_id; 1110 } else { 1111 /* The driver assumes no error */ 1112 return 0; 1113 } 1114 1115 /* The DMA engine uses the second register set, if present */ 1116 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1117 if (!res) 1118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1119 1120 ctlr = p->ctlr; 1121 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1122 dma_tx_id, res->start + SITFDR); 1123 if (!ctlr->dma_tx) 1124 return -ENODEV; 1125 1126 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1127 dma_rx_id, res->start + SIRFDR); 1128 if (!ctlr->dma_rx) 1129 goto free_tx_chan; 1130 1131 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1132 if (!p->tx_dma_page) 1133 goto free_rx_chan; 1134 1135 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1136 if (!p->rx_dma_page) 1137 goto free_tx_page; 1138 1139 tx_dev = ctlr->dma_tx->device->dev; 1140 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1141 DMA_TO_DEVICE); 1142 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1143 goto free_rx_page; 1144 1145 rx_dev = ctlr->dma_rx->device->dev; 1146 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1147 DMA_FROM_DEVICE); 1148 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1149 goto unmap_tx_page; 1150 1151 dev_info(dev, "DMA available"); 1152 return 0; 1153 1154unmap_tx_page: 1155 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); 1156free_rx_page: 1157 free_page((unsigned long)p->rx_dma_page); 1158free_tx_page: 1159 free_page((unsigned long)p->tx_dma_page); 1160free_rx_chan: 1161 dma_release_channel(ctlr->dma_rx); 1162free_tx_chan: 1163 dma_release_channel(ctlr->dma_tx); 1164 ctlr->dma_tx = NULL; 1165 return -ENODEV; 1166} 1167 1168static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1169{ 1170 struct spi_controller *ctlr = p->ctlr; 1171 1172 if (!ctlr->dma_tx) 1173 return; 1174 1175 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE, 1176 DMA_FROM_DEVICE); 1177 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE, 1178 DMA_TO_DEVICE); 1179 free_page((unsigned long)p->rx_dma_page); 1180 free_page((unsigned long)p->tx_dma_page); 1181 dma_release_channel(ctlr->dma_rx); 1182 dma_release_channel(ctlr->dma_tx); 1183} 1184 1185static int sh_msiof_spi_probe(struct platform_device *pdev) 1186{ 1187 struct spi_controller *ctlr; 1188 const struct sh_msiof_chipdata *chipdata; 1189 struct sh_msiof_spi_info *info; 1190 struct sh_msiof_spi_priv *p; 1191 struct device *dev = &pdev->dev; 1192 unsigned long clksrc; 1193 int i; 1194 int ret; 1195 1196 /* Check whether MSIOF is used as I2S mode or SPI mode by checking "port" node */ 1197 struct device_node *port __free(device_node) = of_graph_get_next_port(dev->of_node, NULL); 1198 if (port) /* It was MSIOF-I2S */ 1199 return -ENODEV; 1200 1201 chipdata = of_device_get_match_data(dev); 1202 if (chipdata) { 1203 info = sh_msiof_spi_parse_dt(dev); 1204 } else { 1205 chipdata = (const void *)pdev->id_entry->driver_data; 1206 info = dev_get_platdata(dev); 1207 } 1208 1209 if (!info) { 1210 dev_err(dev, "failed to obtain device info\n"); 1211 return -ENXIO; 1212 } 1213 1214 if (chipdata->flags & SH_MSIOF_FLAG_FIXED_DTDL_200) 1215 info->dtdl = 200; 1216 1217 if (info->mode == MSIOF_SPI_TARGET) 1218 ctlr = spi_alloc_target(dev, sizeof(struct sh_msiof_spi_priv)); 1219 else 1220 ctlr = spi_alloc_host(dev, sizeof(struct sh_msiof_spi_priv)); 1221 if (ctlr == NULL) 1222 return -ENOMEM; 1223 1224 p = spi_controller_get_devdata(ctlr); 1225 1226 platform_set_drvdata(pdev, p); 1227 p->ctlr = ctlr; 1228 p->info = info; 1229 p->min_div_pow = chipdata->min_div_pow; 1230 1231 init_completion(&p->done); 1232 init_completion(&p->done_txdma); 1233 1234 p->clk = devm_clk_get(dev, NULL); 1235 if (IS_ERR(p->clk)) { 1236 dev_err(dev, "cannot get clock\n"); 1237 ret = PTR_ERR(p->clk); 1238 goto err1; 1239 } 1240 1241 i = platform_get_irq(pdev, 0); 1242 if (i < 0) { 1243 ret = i; 1244 goto err1; 1245 } 1246 1247 p->mapbase = devm_platform_ioremap_resource(pdev, 0); 1248 if (IS_ERR(p->mapbase)) { 1249 ret = PTR_ERR(p->mapbase); 1250 goto err1; 1251 } 1252 1253 ret = devm_request_irq(dev, i, sh_msiof_spi_irq, 0, dev_name(dev), p); 1254 if (ret) { 1255 dev_err(dev, "unable to request irq\n"); 1256 goto err1; 1257 } 1258 1259 p->pdev = pdev; 1260 pm_runtime_enable(dev); 1261 1262 /* Platform data may override FIFO sizes */ 1263 p->tx_fifo_size = chipdata->tx_fifo_size; 1264 p->rx_fifo_size = chipdata->rx_fifo_size; 1265 if (p->info->tx_fifo_override) 1266 p->tx_fifo_size = p->info->tx_fifo_override; 1267 if (p->info->rx_fifo_override) 1268 p->rx_fifo_size = p->info->rx_fifo_override; 1269 1270 /* init controller code */ 1271 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1272 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1273 clksrc = clk_get_rate(p->clk); 1274 ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, 1024); 1275 ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, 1 << p->min_div_pow); 1276 ctlr->flags = chipdata->ctlr_flags; 1277 ctlr->bus_num = pdev->id; 1278 ctlr->num_chipselect = p->info->num_chipselect; 1279 ctlr->dev.of_node = dev->of_node; 1280 ctlr->setup = sh_msiof_spi_setup; 1281 ctlr->prepare_message = sh_msiof_prepare_message; 1282 ctlr->target_abort = sh_msiof_target_abort; 1283 ctlr->bits_per_word_mask = chipdata->bits_per_word_mask; 1284 ctlr->auto_runtime_pm = true; 1285 ctlr->transfer_one = sh_msiof_transfer_one; 1286 ctlr->use_gpio_descriptors = true; 1287 ctlr->max_native_cs = MAX_SS; 1288 1289 ret = sh_msiof_request_dma(p); 1290 if (ret < 0) 1291 dev_warn(dev, "DMA not available, using PIO\n"); 1292 1293 ret = devm_spi_register_controller(dev, ctlr); 1294 if (ret < 0) { 1295 dev_err(dev, "devm_spi_register_controller error.\n"); 1296 goto err2; 1297 } 1298 1299 return 0; 1300 1301 err2: 1302 sh_msiof_release_dma(p); 1303 pm_runtime_disable(dev); 1304 err1: 1305 spi_controller_put(ctlr); 1306 return ret; 1307} 1308 1309static void sh_msiof_spi_remove(struct platform_device *pdev) 1310{ 1311 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1312 1313 sh_msiof_release_dma(p); 1314 pm_runtime_disable(&pdev->dev); 1315} 1316 1317static const struct platform_device_id spi_driver_ids[] = { 1318 { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, 1319 {}, 1320}; 1321MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1322 1323static int sh_msiof_spi_suspend(struct device *dev) 1324{ 1325 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1326 1327 return spi_controller_suspend(p->ctlr); 1328} 1329 1330static int sh_msiof_spi_resume(struct device *dev) 1331{ 1332 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1333 1334 return spi_controller_resume(p->ctlr); 1335} 1336 1337static DEFINE_SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend, 1338 sh_msiof_spi_resume); 1339 1340static struct platform_driver sh_msiof_spi_drv = { 1341 .probe = sh_msiof_spi_probe, 1342 .remove = sh_msiof_spi_remove, 1343 .id_table = spi_driver_ids, 1344 .driver = { 1345 .name = "spi_sh_msiof", 1346 .pm = pm_sleep_ptr(&sh_msiof_spi_pm_ops), 1347 .of_match_table = of_match_ptr(sh_msiof_match), 1348 }, 1349}; 1350module_platform_driver(sh_msiof_spi_drv); 1351 1352MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver"); 1353MODULE_AUTHOR("Magnus Damm"); 1354MODULE_LICENSE("GPL v2");
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