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spi-s3c64xx.c
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linux-6.19.14/drivers/spi/spi-s3c64xx.c
1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright (c) 2009 Samsung Electronics Co., Ltd. 4// Jaswinder Singh <jassi.brar@samsung.com> 5 6#include <linux/bitops.h> 7#include <linux/bits.h> 8#include <linux/clk.h> 9#include <linux/delay.h> 10#include <linux/dma-mapping.h> 11#include <linux/dmaengine.h> 12#include <linux/init.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/platform_data/spi-s3c64xx.h> 18#include <linux/platform_device.h> 19#include <linux/pm_runtime.h> 20#include <linux/spi/spi.h> 21#include <linux/types.h> 22 23#define MAX_SPI_PORTS 12 24#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 25#define AUTOSUSPEND_TIMEOUT 2000 26 27/* Registers and bit-fields */ 28 29#define S3C64XX_SPI_CH_CFG 0x00 30#define S3C64XX_SPI_CLK_CFG 0x04 31#define S3C64XX_SPI_MODE_CFG 0x08 32#define S3C64XX_SPI_CS_REG 0x0C 33#define S3C64XX_SPI_INT_EN 0x10 34#define S3C64XX_SPI_STATUS 0x14 35#define S3C64XX_SPI_TX_DATA 0x18 36#define S3C64XX_SPI_RX_DATA 0x1C 37#define S3C64XX_SPI_PACKET_CNT 0x20 38#define S3C64XX_SPI_PENDING_CLR 0x24 39#define S3C64XX_SPI_SWAP_CFG 0x28 40#define S3C64XX_SPI_FB_CLK 0x2C 41 42#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 43#define S3C64XX_SPI_CH_SW_RST (1<<5) 44#define S3C64XX_SPI_CH_SLAVE (1<<4) 45#define S3C64XX_SPI_CPOL_L (1<<3) 46#define S3C64XX_SPI_CPHA_B (1<<2) 47#define S3C64XX_SPI_CH_RXCH_ON (1<<1) 48#define S3C64XX_SPI_CH_TXCH_ON (1<<0) 49 50#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 51#define S3C64XX_SPI_CLKSEL_SRCSHFT 9 52#define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 53#define S3C64XX_SPI_PSR_MASK 0xff 54 55#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 56#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 57#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 58#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 59#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 60#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 61#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 62#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 63#define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) 64#define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 65#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) 66#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 67#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 68#define S3C64XX_SPI_MODE_4BURST (1<<0) 69 70#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) 71#define S3C64XX_SPI_CS_AUTO (1<<1) 72#define S3C64XX_SPI_CS_SIG_INACT (1<<0) 73 74#define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 75#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 76#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 77#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 78#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 79#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 80#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 81 82#define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15) 83#define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6) 84#define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 85#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 86#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 87#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 88#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 89#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 90#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 91 92#define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 93#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) 94 95#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 96#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 97#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 98#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 99#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 100 101#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 102#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 103#define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 104#define S3C64XX_SPI_SWAP_RX_EN (1<<4) 105#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 106#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 107#define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 108#define S3C64XX_SPI_SWAP_TX_EN (1<<0) 109 110#define S3C64XX_SPI_FBCLK_MSK (3<<0) 111 112#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 113#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 114 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 115#define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ 116 __ffs((sdd)->tx_fifomask)) 117#define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ 118 __ffs((sdd)->rx_fifomask)) 119#define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) 120 121#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 122#define S3C64XX_SPI_TRAILCNT_OFF 19 123 124#define S3C64XX_SPI_POLLING_SIZE 32 125 126#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 127#define is_polling(x) (x->cntrlr_info->polling) 128 129#define RXBUSY (1<<2) 130#define TXBUSY (1<<3) 131 132struct s3c64xx_spi_dma_data { 133 struct dma_chan *ch; 134 dma_cookie_t cookie; 135 enum dma_transfer_direction direction; 136}; 137 138/** 139 * struct s3c64xx_spi_port_config - SPI Controller hardware info 140 * @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead. 141 * @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead. 142 * @fifo_depth: depth of the FIFOs. Used by compatibles where all the instances 143 * of the IP define the same FIFO depth. It has higher precedence 144 * than the FIFO depth specified via DT. 145 * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's 146 * length and position. 147 * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's 148 * length and position. 149 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 150 * @clk_div: Internal clock divider 151 * @quirks: Bitmask of known quirks 152 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 153 * @clk_from_cmu: True, if the controller does not include a clock mux and 154 * prescaler unit. 155 * @clk_ioclk: True if clock is present on this device 156 * @has_loopback: True if loopback mode can be supported 157 * @use_32bit_io: True if the SoC allows only 32-bit register accesses. 158 * 159 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 160 * differ in some aspects such as the size of the fifo and spi bus clock 161 * setup. Such differences are specified to the driver using this structure 162 * which is provided as driver data to the driver. 163 */ 164struct s3c64xx_spi_port_config { 165 int fifo_lvl_mask[MAX_SPI_PORTS]; 166 int rx_lvl_offset; 167 unsigned int fifo_depth; 168 u32 rx_fifomask; 169 u32 tx_fifomask; 170 int tx_st_done; 171 int quirks; 172 int clk_div; 173 bool high_speed; 174 bool clk_from_cmu; 175 bool clk_ioclk; 176 bool has_loopback; 177 bool use_32bit_io; 178}; 179 180/** 181 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 182 * @clk: Pointer to the spi clock. 183 * @src_clk: Pointer to the clock used to generate SPI signals. 184 * @ioclk: Pointer to the i/o clock between host and target 185 * @pdev: Pointer to device's platform device data 186 * @host: Pointer to the SPI Protocol host. 187 * @cntrlr_info: Platform specific data for the controller this driver manages. 188 * @lock: Controller specific lock. 189 * @state: Set of FLAGS to indicate status. 190 * @sfr_start: BUS address of SPI controller regs. 191 * @regs: Pointer to ioremap'ed controller registers. 192 * @xfer_completion: To indicate completion of xfer task. 193 * @cur_mode: Stores the active configuration of the controller. 194 * @cur_bpw: Stores the active bits per word settings. 195 * @cur_speed: Current clock speed 196 * @rx_dma: Local receive DMA data (e.g. chan and direction) 197 * @tx_dma: Local transmit DMA data (e.g. chan and direction) 198 * @port_conf: Local SPI port configuration data 199 * @port_id: [DEPRECATED] use @{rx,tx}_fifomask instead. 200 * @fifo_depth: depth of the FIFO. 201 * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's 202 * length and position. 203 * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's 204 * length and position. 205 */ 206struct s3c64xx_spi_driver_data { 207 void __iomem *regs; 208 struct clk *clk; 209 struct clk *src_clk; 210 struct clk *ioclk; 211 struct platform_device *pdev; 212 struct spi_controller *host; 213 struct s3c64xx_spi_info *cntrlr_info; 214 spinlock_t lock; 215 unsigned long sfr_start; 216 struct completion xfer_completion; 217 unsigned state; 218 unsigned cur_mode, cur_bpw; 219 unsigned cur_speed; 220 struct s3c64xx_spi_dma_data rx_dma; 221 struct s3c64xx_spi_dma_data tx_dma; 222 const struct s3c64xx_spi_port_config *port_conf; 223 unsigned int port_id; 224 unsigned int fifo_depth; 225 u32 rx_fifomask; 226 u32 tx_fifomask; 227}; 228 229static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) 230{ 231 void __iomem *regs = sdd->regs; 232 unsigned long loops; 233 u32 val; 234 235 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 236 237 val = readl(regs + S3C64XX_SPI_CH_CFG); 238 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 239 writel(val, regs + S3C64XX_SPI_CH_CFG); 240 241 val = readl(regs + S3C64XX_SPI_CH_CFG); 242 val |= S3C64XX_SPI_CH_SW_RST; 243 val &= ~S3C64XX_SPI_CH_HS_EN; 244 writel(val, regs + S3C64XX_SPI_CH_CFG); 245 246 /* Flush TxFIFO*/ 247 loops = msecs_to_loops(1); 248 do { 249 val = readl(regs + S3C64XX_SPI_STATUS); 250 } while (TX_FIFO_LVL(val, sdd) && --loops); 251 252 if (loops == 0) 253 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 254 255 /* Flush RxFIFO*/ 256 loops = msecs_to_loops(1); 257 do { 258 val = readl(regs + S3C64XX_SPI_STATUS); 259 if (RX_FIFO_LVL(val, sdd)) 260 readl(regs + S3C64XX_SPI_RX_DATA); 261 else 262 break; 263 } while (--loops); 264 265 if (loops == 0) 266 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 267 268 val = readl(regs + S3C64XX_SPI_CH_CFG); 269 val &= ~S3C64XX_SPI_CH_SW_RST; 270 writel(val, regs + S3C64XX_SPI_CH_CFG); 271 272 val = readl(regs + S3C64XX_SPI_MODE_CFG); 273 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 274 writel(val, regs + S3C64XX_SPI_MODE_CFG); 275} 276 277static void s3c64xx_spi_dmacb(void *data) 278{ 279 struct s3c64xx_spi_driver_data *sdd; 280 struct s3c64xx_spi_dma_data *dma = data; 281 unsigned long flags; 282 283 if (dma->direction == DMA_DEV_TO_MEM) 284 sdd = container_of(data, 285 struct s3c64xx_spi_driver_data, rx_dma); 286 else 287 sdd = container_of(data, 288 struct s3c64xx_spi_driver_data, tx_dma); 289 290 spin_lock_irqsave(&sdd->lock, flags); 291 292 if (dma->direction == DMA_DEV_TO_MEM) { 293 sdd->state &= ~RXBUSY; 294 if (!(sdd->state & TXBUSY)) 295 complete(&sdd->xfer_completion); 296 } else { 297 sdd->state &= ~TXBUSY; 298 if (!(sdd->state & RXBUSY)) 299 complete(&sdd->xfer_completion); 300 } 301 302 spin_unlock_irqrestore(&sdd->lock, flags); 303} 304 305static int s3c64xx_prepare_dma(struct s3c64xx_spi_dma_data *dma, 306 struct sg_table *sgt) 307{ 308 struct s3c64xx_spi_driver_data *sdd; 309 struct dma_slave_config config; 310 struct dma_async_tx_descriptor *desc; 311 int ret; 312 313 memset(&config, 0, sizeof(config)); 314 315 if (dma->direction == DMA_DEV_TO_MEM) { 316 sdd = container_of((void *)dma, 317 struct s3c64xx_spi_driver_data, rx_dma); 318 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 319 config.src_addr_width = sdd->cur_bpw / 8; 320 config.src_maxburst = 1; 321 } else { 322 sdd = container_of((void *)dma, 323 struct s3c64xx_spi_driver_data, tx_dma); 324 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 325 config.dst_addr_width = sdd->cur_bpw / 8; 326 config.dst_maxburst = 1; 327 } 328 config.direction = dma->direction; 329 ret = dmaengine_slave_config(dma->ch, &config); 330 if (ret) 331 return ret; 332 333 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 334 dma->direction, DMA_PREP_INTERRUPT); 335 if (!desc) { 336 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", 337 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); 338 return -ENOMEM; 339 } 340 341 desc->callback = s3c64xx_spi_dmacb; 342 desc->callback_param = dma; 343 344 dma->cookie = dmaengine_submit(desc); 345 ret = dma_submit_error(dma->cookie); 346 if (ret) { 347 dev_err(&sdd->pdev->dev, "DMA submission failed"); 348 return ret; 349 } 350 351 dma_async_issue_pending(dma->ch); 352 return 0; 353} 354 355static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) 356{ 357 struct s3c64xx_spi_driver_data *sdd = 358 spi_controller_get_devdata(spi->controller); 359 360 if (sdd->cntrlr_info->no_cs) 361 return; 362 363 if (enable) { 364 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { 365 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 366 } else { 367 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); 368 369 ssel |= (S3C64XX_SPI_CS_AUTO | 370 S3C64XX_SPI_CS_NSC_CNT_2); 371 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); 372 } 373 } else { 374 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 375 writel(S3C64XX_SPI_CS_SIG_INACT, 376 sdd->regs + S3C64XX_SPI_CS_REG); 377 } 378} 379 380static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi) 381{ 382 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); 383 384 if (is_polling(sdd)) 385 return 0; 386 387 /* Requests DMA channels */ 388 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx"); 389 if (IS_ERR(sdd->rx_dma.ch)) { 390 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n"); 391 sdd->rx_dma.ch = NULL; 392 return 0; 393 } 394 395 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx"); 396 if (IS_ERR(sdd->tx_dma.ch)) { 397 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n"); 398 dma_release_channel(sdd->rx_dma.ch); 399 sdd->tx_dma.ch = NULL; 400 sdd->rx_dma.ch = NULL; 401 return 0; 402 } 403 404 spi->dma_rx = sdd->rx_dma.ch; 405 spi->dma_tx = sdd->tx_dma.ch; 406 407 return 0; 408} 409 410static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi) 411{ 412 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); 413 414 if (is_polling(sdd)) 415 return 0; 416 417 /* Releases DMA channels if they are allocated */ 418 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 419 dma_release_channel(sdd->rx_dma.ch); 420 dma_release_channel(sdd->tx_dma.ch); 421 sdd->rx_dma.ch = NULL; 422 sdd->tx_dma.ch = NULL; 423 } 424 425 return 0; 426} 427 428static bool s3c64xx_spi_can_dma(struct spi_controller *host, 429 struct spi_device *spi, 430 struct spi_transfer *xfer) 431{ 432 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 433 434 if (sdd->rx_dma.ch && sdd->tx_dma.ch) 435 return xfer->len >= sdd->fifo_depth; 436 437 return false; 438} 439 440static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr, 441 const void *buffer, unsigned int count) 442{ 443 if (count) { 444 const u8 *buf = buffer; 445 446 do { 447 __raw_writel(*buf++, addr); 448 } while (--count); 449 } 450} 451 452static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr, 453 const void *buffer, unsigned int count) 454{ 455 if (count) { 456 const u16 *buf = buffer; 457 458 do { 459 __raw_writel(*buf++, addr); 460 } while (--count); 461 } 462} 463 464static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, 465 struct spi_transfer *xfer) 466{ 467 void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; 468 const void *buf = xfer->tx_buf; 469 unsigned int len = xfer->len; 470 471 switch (sdd->cur_bpw) { 472 case 32: 473 iowrite32_rep(addr, buf, len / 4); 474 break; 475 case 16: 476 if (sdd->port_conf->use_32bit_io) 477 s3c64xx_iowrite16_32_rep(addr, buf, len / 2); 478 else 479 iowrite16_rep(addr, buf, len / 2); 480 break; 481 default: 482 if (sdd->port_conf->use_32bit_io) 483 s3c64xx_iowrite8_32_rep(addr, buf, len); 484 else 485 iowrite8_rep(addr, buf, len); 486 break; 487 } 488} 489 490static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, 491 struct spi_transfer *xfer, int dma_mode) 492{ 493 void __iomem *regs = sdd->regs; 494 u32 modecfg, chcfg; 495 int ret = 0; 496 497 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 498 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 499 500 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 501 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 502 503 if (dma_mode) { 504 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 505 } else { 506 /* Always shift in data in FIFO, even if xfer is Tx only, 507 * this helps setting PCKT_CNT value for generating clocks 508 * as exactly needed. 509 */ 510 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 511 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 512 | S3C64XX_SPI_PACKET_CNT_EN, 513 regs + S3C64XX_SPI_PACKET_CNT); 514 } 515 516 if (xfer->tx_buf != NULL) { 517 sdd->state |= TXBUSY; 518 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 519 if (dma_mode) { 520 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 521 ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 522 } else { 523 s3c64xx_iowrite_rep(sdd, xfer); 524 } 525 } 526 527 if (xfer->rx_buf != NULL) { 528 sdd->state |= RXBUSY; 529 530 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 531 && !(sdd->cur_mode & SPI_CPHA)) 532 chcfg |= S3C64XX_SPI_CH_HS_EN; 533 534 if (dma_mode) { 535 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 536 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 537 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 538 | S3C64XX_SPI_PACKET_CNT_EN, 539 regs + S3C64XX_SPI_PACKET_CNT); 540 ret = s3c64xx_prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 541 } 542 } 543 544 if (ret) 545 return ret; 546 547 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 548 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 549 550 return 0; 551} 552 553static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 554 int timeout_ms) 555{ 556 void __iomem *regs = sdd->regs; 557 unsigned long val = 1; 558 u32 status; 559 u32 max_fifo = sdd->fifo_depth; 560 561 if (timeout_ms) 562 val = msecs_to_loops(timeout_ms); 563 564 do { 565 status = readl(regs + S3C64XX_SPI_STATUS); 566 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 567 568 /* return the actual received data length */ 569 return RX_FIFO_LVL(status, sdd); 570} 571 572static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 573 struct spi_transfer *xfer) 574{ 575 void __iomem *regs = sdd->regs; 576 unsigned long val; 577 u32 status; 578 int ms; 579 580 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 581 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 582 ms += 30; /* some tolerance */ 583 ms = max(ms, 100); /* minimum timeout */ 584 585 val = msecs_to_jiffies(ms) + 10; 586 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 587 588 /* 589 * If the previous xfer was completed within timeout, then 590 * proceed further else return -ETIMEDOUT. 591 * DmaTx returns after simply writing data in the FIFO, 592 * w/o waiting for real transmission on the bus to finish. 593 * DmaRx returns only after Dma read data from FIFO which 594 * needs bus transmission to finish, so we don't worry if 595 * Xfer involved Rx(with or without Tx). 596 */ 597 if (val && !xfer->rx_buf) { 598 val = msecs_to_loops(10); 599 status = readl(regs + S3C64XX_SPI_STATUS); 600 while ((TX_FIFO_LVL(status, sdd) 601 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 602 && --val) { 603 cpu_relax(); 604 status = readl(regs + S3C64XX_SPI_STATUS); 605 } 606 607 } 608 609 /* If timed out while checking rx/tx status return error */ 610 if (!val) 611 return -ETIMEDOUT; 612 613 return 0; 614} 615 616static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 617 struct spi_transfer *xfer, bool use_irq) 618{ 619 void __iomem *regs = sdd->regs; 620 unsigned long val; 621 u32 status; 622 int loops; 623 u32 cpy_len; 624 u8 *buf; 625 int ms; 626 unsigned long time_us; 627 628 /* microsecs to xfer 'len' bytes @ 'cur_speed' */ 629 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; 630 ms = (time_us / 1000); 631 ms += 10; /* some tolerance */ 632 633 /* sleep during signal transfer time */ 634 status = readl(regs + S3C64XX_SPI_STATUS); 635 if (RX_FIFO_LVL(status, sdd) < xfer->len) 636 usleep_range(time_us / 2, time_us); 637 638 if (use_irq) { 639 val = msecs_to_jiffies(ms); 640 if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) 641 return -ETIMEDOUT; 642 } 643 644 val = msecs_to_loops(ms); 645 do { 646 status = readl(regs + S3C64XX_SPI_STATUS); 647 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 648 649 if (!val) 650 return -EIO; 651 652 /* If it was only Tx */ 653 if (!xfer->rx_buf) { 654 sdd->state &= ~TXBUSY; 655 return 0; 656 } 657 658 /* 659 * If the receive length is bigger than the controller fifo 660 * size, calculate the loops and read the fifo as many times. 661 * loops = length / max fifo size (calculated by using the 662 * fifo mask). 663 * For any size less than the fifo size the below code is 664 * executed atleast once. 665 */ 666 loops = xfer->len / sdd->fifo_depth; 667 buf = xfer->rx_buf; 668 do { 669 /* wait for data to be received in the fifo */ 670 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 671 (loops ? ms : 0)); 672 673 switch (sdd->cur_bpw) { 674 case 32: 675 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 676 buf, cpy_len / 4); 677 break; 678 case 16: 679 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 680 buf, cpy_len / 2); 681 break; 682 default: 683 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 684 buf, cpy_len); 685 break; 686 } 687 688 buf = buf + cpy_len; 689 } while (loops--); 690 sdd->state &= ~RXBUSY; 691 692 return 0; 693} 694 695static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 696{ 697 void __iomem *regs = sdd->regs; 698 int ret; 699 u32 val; 700 int div = sdd->port_conf->clk_div; 701 702 /* Disable Clock */ 703 if (!sdd->port_conf->clk_from_cmu) { 704 val = readl(regs + S3C64XX_SPI_CLK_CFG); 705 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 706 writel(val, regs + S3C64XX_SPI_CLK_CFG); 707 } 708 709 /* Set Polarity and Phase */ 710 val = readl(regs + S3C64XX_SPI_CH_CFG); 711 val &= ~(S3C64XX_SPI_CH_SLAVE | 712 S3C64XX_SPI_CPOL_L | 713 S3C64XX_SPI_CPHA_B); 714 715 if (sdd->cur_mode & SPI_CPOL) 716 val |= S3C64XX_SPI_CPOL_L; 717 718 if (sdd->cur_mode & SPI_CPHA) 719 val |= S3C64XX_SPI_CPHA_B; 720 721 writel(val, regs + S3C64XX_SPI_CH_CFG); 722 723 /* Set Channel & DMA Mode */ 724 val = readl(regs + S3C64XX_SPI_MODE_CFG); 725 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 726 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 727 728 switch (sdd->cur_bpw) { 729 case 32: 730 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 731 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 732 break; 733 case 16: 734 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 735 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 736 break; 737 default: 738 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 739 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 740 break; 741 } 742 743 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) 744 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; 745 else 746 val &= ~S3C64XX_SPI_MODE_SELF_LOOPBACK; 747 748 writel(val, regs + S3C64XX_SPI_MODE_CFG); 749 750 if (sdd->port_conf->clk_from_cmu) { 751 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); 752 if (ret) 753 return ret; 754 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; 755 } else { 756 /* Configure Clock */ 757 val = readl(regs + S3C64XX_SPI_CLK_CFG); 758 val &= ~S3C64XX_SPI_PSR_MASK; 759 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) 760 & S3C64XX_SPI_PSR_MASK); 761 writel(val, regs + S3C64XX_SPI_CLK_CFG); 762 763 /* Enable Clock */ 764 val = readl(regs + S3C64XX_SPI_CLK_CFG); 765 val |= S3C64XX_SPI_ENCLK_ENABLE; 766 writel(val, regs + S3C64XX_SPI_CLK_CFG); 767 } 768 769 return 0; 770} 771 772#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 773 774static int s3c64xx_spi_prepare_message(struct spi_controller *host, 775 struct spi_message *msg) 776{ 777 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 778 struct spi_device *spi = msg->spi; 779 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 780 781 /* Configure feedback delay */ 782 if (!cs) 783 /* No delay if not defined */ 784 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK); 785 else 786 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 787 788 return 0; 789} 790 791static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) 792{ 793 struct spi_controller *ctlr = spi->controller; 794 795 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; 796} 797 798static int s3c64xx_spi_transfer_one(struct spi_controller *host, 799 struct spi_device *spi, 800 struct spi_transfer *xfer) 801{ 802 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 803 const unsigned int fifo_len = sdd->fifo_depth; 804 const void *tx_buf = NULL; 805 void *rx_buf = NULL; 806 int target_len = 0, origin_len = 0; 807 int use_dma = 0; 808 bool use_irq = false; 809 int status; 810 u32 speed; 811 u8 bpw; 812 unsigned long flags; 813 u32 rdy_lv; 814 u32 val; 815 816 reinit_completion(&sdd->xfer_completion); 817 818 /* Only BPW and Speed may change across transfers */ 819 bpw = xfer->bits_per_word; 820 speed = xfer->speed_hz; 821 822 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 823 sdd->cur_bpw = bpw; 824 sdd->cur_speed = speed; 825 sdd->cur_mode = spi->mode; 826 status = s3c64xx_spi_config(sdd); 827 if (status) 828 return status; 829 } 830 831 if (!is_polling(sdd) && xfer->len >= fifo_len && 832 sdd->rx_dma.ch && sdd->tx_dma.ch) { 833 use_dma = 1; 834 } else if (xfer->len >= fifo_len) { 835 tx_buf = xfer->tx_buf; 836 rx_buf = xfer->rx_buf; 837 origin_len = xfer->len; 838 target_len = xfer->len; 839 xfer->len = fifo_len - 1; 840 } 841 842 do { 843 /* transfer size is greater than 32, change to IRQ mode */ 844 if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE) 845 use_irq = true; 846 847 if (use_irq) { 848 reinit_completion(&sdd->xfer_completion); 849 850 rdy_lv = xfer->len; 851 /* Setup RDY_FIFO trigger Level 852 * RDY_LVL = 853 * fifo_lvl up to 64 byte -> N bytes 854 * 128 byte -> RDY_LVL * 2 bytes 855 * 256 byte -> RDY_LVL * 4 bytes 856 */ 857 if (fifo_len == 128) 858 rdy_lv /= 2; 859 else if (fifo_len == 256) 860 rdy_lv /= 4; 861 862 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG); 863 val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL; 864 val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); 865 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); 866 867 /* Enable FIFO_RDY_EN IRQ */ 868 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); 869 writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN), 870 sdd->regs + S3C64XX_SPI_INT_EN); 871 872 } 873 874 spin_lock_irqsave(&sdd->lock, flags); 875 876 /* Pending only which is to be done */ 877 sdd->state &= ~RXBUSY; 878 sdd->state &= ~TXBUSY; 879 880 /* Start the signals */ 881 s3c64xx_spi_set_cs(spi, true); 882 883 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); 884 885 spin_unlock_irqrestore(&sdd->lock, flags); 886 887 if (status) { 888 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); 889 break; 890 } 891 892 if (use_dma) 893 status = s3c64xx_wait_for_dma(sdd, xfer); 894 else 895 status = s3c64xx_wait_for_pio(sdd, xfer, use_irq); 896 897 if (status) { 898 dev_err(&spi->dev, 899 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", 900 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 901 (sdd->state & RXBUSY) ? 'f' : 'p', 902 (sdd->state & TXBUSY) ? 'f' : 'p', 903 xfer->len, use_dma ? 1 : 0, status); 904 905 if (use_dma) { 906 struct dma_tx_state s; 907 908 if (xfer->tx_buf && (sdd->state & TXBUSY)) { 909 dmaengine_pause(sdd->tx_dma.ch); 910 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); 911 dmaengine_terminate_all(sdd->tx_dma.ch); 912 dev_err(&spi->dev, "TX residue: %d\n", s.residue); 913 914 } 915 if (xfer->rx_buf && (sdd->state & RXBUSY)) { 916 dmaengine_pause(sdd->rx_dma.ch); 917 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); 918 dmaengine_terminate_all(sdd->rx_dma.ch); 919 dev_err(&spi->dev, "RX residue: %d\n", s.residue); 920 } 921 } 922 } else { 923 s3c64xx_flush_fifo(sdd); 924 } 925 if (target_len > 0) { 926 target_len -= xfer->len; 927 928 if (xfer->tx_buf) 929 xfer->tx_buf += xfer->len; 930 931 if (xfer->rx_buf) 932 xfer->rx_buf += xfer->len; 933 934 if (target_len >= fifo_len) 935 xfer->len = fifo_len - 1; 936 else 937 xfer->len = target_len; 938 } 939 } while (target_len > 0); 940 941 if (origin_len) { 942 /* Restore original xfer buffers and length */ 943 xfer->tx_buf = tx_buf; 944 xfer->rx_buf = rx_buf; 945 xfer->len = origin_len; 946 } 947 948 return status; 949} 950 951static struct s3c64xx_spi_csinfo *s3c64xx_get_target_ctrldata( 952 struct spi_device *spi) 953{ 954 struct s3c64xx_spi_csinfo *cs; 955 struct device_node *target_np; 956 u32 fb_delay = 0; 957 958 target_np = spi->dev.of_node; 959 if (!target_np) { 960 dev_err(&spi->dev, "device node not found\n"); 961 return ERR_PTR(-EINVAL); 962 } 963 964 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 965 if (!cs) 966 return ERR_PTR(-ENOMEM); 967 968 struct device_node *data_np __free(device_node) = 969 of_get_child_by_name(target_np, "controller-data"); 970 if (!data_np) { 971 dev_info(&spi->dev, "feedback delay set to default (0)\n"); 972 return cs; 973 } 974 975 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 976 cs->fb_delay = fb_delay; 977 return cs; 978} 979 980/* 981 * Here we only check the validity of requested configuration 982 * and save the configuration in a local data-structure. 983 * The controller is actually configured only just before we 984 * get a message to transfer. 985 */ 986static int s3c64xx_spi_setup(struct spi_device *spi) 987{ 988 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 989 struct s3c64xx_spi_driver_data *sdd; 990 int err; 991 int div; 992 993 sdd = spi_controller_get_devdata(spi->controller); 994 if (spi->dev.of_node) { 995 cs = s3c64xx_get_target_ctrldata(spi); 996 spi->controller_data = cs; 997 } 998 999 /* NULL is fine, we just avoid using the FB delay (=0) */ 1000 if (IS_ERR(cs)) { 1001 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0)); 1002 return -ENODEV; 1003 } 1004 1005 if (!spi_get_ctldata(spi)) 1006 spi_set_ctldata(spi, cs); 1007 1008 pm_runtime_get_sync(&sdd->pdev->dev); 1009 1010 div = sdd->port_conf->clk_div; 1011 1012 /* Check if we can provide the requested rate */ 1013 if (!sdd->port_conf->clk_from_cmu) { 1014 u32 psr, speed; 1015 1016 /* Max possible */ 1017 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); 1018 1019 if (spi->max_speed_hz > speed) 1020 spi->max_speed_hz = speed; 1021 1022 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; 1023 psr &= S3C64XX_SPI_PSR_MASK; 1024 if (psr == S3C64XX_SPI_PSR_MASK) 1025 psr--; 1026 1027 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 1028 if (spi->max_speed_hz < speed) { 1029 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 1030 psr++; 1031 } else { 1032 err = -EINVAL; 1033 goto setup_exit; 1034 } 1035 } 1036 1037 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 1038 if (spi->max_speed_hz >= speed) { 1039 spi->max_speed_hz = speed; 1040 } else { 1041 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 1042 spi->max_speed_hz); 1043 err = -EINVAL; 1044 goto setup_exit; 1045 } 1046 } 1047 1048 pm_runtime_put_autosuspend(&sdd->pdev->dev); 1049 s3c64xx_spi_set_cs(spi, false); 1050 1051 return 0; 1052 1053setup_exit: 1054 pm_runtime_put_autosuspend(&sdd->pdev->dev); 1055 /* setup() returns with device de-selected */ 1056 s3c64xx_spi_set_cs(spi, false); 1057 1058 spi_set_ctldata(spi, NULL); 1059 1060 /* This was dynamically allocated on the DT path */ 1061 if (spi->dev.of_node) 1062 kfree(cs); 1063 1064 return err; 1065} 1066 1067static void s3c64xx_spi_cleanup(struct spi_device *spi) 1068{ 1069 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 1070 1071 /* This was dynamically allocated on the DT path */ 1072 if (spi->dev.of_node) 1073 kfree(cs); 1074 1075 spi_set_ctldata(spi, NULL); 1076} 1077 1078static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 1079{ 1080 struct s3c64xx_spi_driver_data *sdd = data; 1081 struct spi_controller *spi = sdd->host; 1082 unsigned int val, clr = 0; 1083 1084 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 1085 1086 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 1087 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 1088 dev_err(&spi->dev, "RX overrun\n"); 1089 } 1090 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 1091 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 1092 dev_err(&spi->dev, "RX underrun\n"); 1093 } 1094 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 1095 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 1096 dev_err(&spi->dev, "TX overrun\n"); 1097 } 1098 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 1099 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1100 dev_err(&spi->dev, "TX underrun\n"); 1101 } 1102 1103 if (val & S3C64XX_SPI_ST_RX_FIFORDY) { 1104 complete(&sdd->xfer_completion); 1105 /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */ 1106 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); 1107 writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN), 1108 sdd->regs + S3C64XX_SPI_INT_EN); 1109 } 1110 1111 /* Clear the pending irq by setting and then clearing it */ 1112 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1113 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1114 1115 return IRQ_HANDLED; 1116} 1117 1118static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) 1119{ 1120 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1121 void __iomem *regs = sdd->regs; 1122 unsigned int val; 1123 1124 sdd->cur_speed = 0; 1125 1126 if (sci->no_cs) 1127 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 1128 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 1129 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); 1130 1131 /* Disable Interrupts - we use Polling if not DMA mode */ 1132 writel(0, regs + S3C64XX_SPI_INT_EN); 1133 1134 if (!sdd->port_conf->clk_from_cmu) 1135 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 1136 regs + S3C64XX_SPI_CLK_CFG); 1137 writel(0, regs + S3C64XX_SPI_MODE_CFG); 1138 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 1139 1140 /* Clear any irq pending bits, should set and clear the bits */ 1141 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 1142 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 1143 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 1144 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1145 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 1146 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 1147 1148 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 1149 1150 val = readl(regs + S3C64XX_SPI_MODE_CFG); 1151 val &= ~S3C64XX_SPI_MODE_4BURST; 1152 val |= (S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1153 writel(val, regs + S3C64XX_SPI_MODE_CFG); 1154 1155 s3c64xx_flush_fifo(sdd); 1156} 1157 1158#ifdef CONFIG_OF 1159static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1160{ 1161 struct s3c64xx_spi_info *sci; 1162 u32 temp; 1163 1164 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 1165 if (!sci) 1166 return ERR_PTR(-ENOMEM); 1167 1168 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 1169 dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 1170 sci->src_clk_nr = 0; 1171 } else { 1172 sci->src_clk_nr = temp; 1173 } 1174 1175 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 1176 dev_dbg(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 1177 sci->num_cs = 1; 1178 } else { 1179 sci->num_cs = temp; 1180 } 1181 1182 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); 1183 sci->polling = !of_property_present(dev->of_node, "dmas"); 1184 1185 return sci; 1186} 1187#else 1188static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1189{ 1190 return dev_get_platdata(dev); 1191} 1192#endif 1193 1194static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1195 struct platform_device *pdev) 1196{ 1197#ifdef CONFIG_OF 1198 if (pdev->dev.of_node) 1199 return of_device_get_match_data(&pdev->dev); 1200#endif 1201 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; 1202} 1203 1204static int s3c64xx_spi_set_port_id(struct platform_device *pdev, 1205 struct s3c64xx_spi_driver_data *sdd) 1206{ 1207 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; 1208 int ret; 1209 1210 if (port_conf->rx_fifomask && port_conf->tx_fifomask) 1211 return 0; 1212 1213 if (pdev->dev.of_node) { 1214 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1215 if (ret < 0) 1216 return dev_err_probe(&pdev->dev, ret, 1217 "Failed to get alias id\n"); 1218 sdd->port_id = ret; 1219 } else { 1220 if (pdev->id < 0) 1221 return dev_err_probe(&pdev->dev, -EINVAL, 1222 "Negative platform ID is not allowed\n"); 1223 sdd->port_id = pdev->id; 1224 } 1225 1226 return 0; 1227} 1228 1229static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) 1230{ 1231 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; 1232 1233 if (port_conf->rx_fifomask) 1234 sdd->rx_fifomask = port_conf->rx_fifomask; 1235 else 1236 sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << 1237 port_conf->rx_lvl_offset; 1238 1239 if (port_conf->tx_fifomask) 1240 sdd->tx_fifomask = port_conf->tx_fifomask; 1241 else 1242 sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << 1243 S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT; 1244} 1245 1246static int s3c64xx_spi_probe(struct platform_device *pdev) 1247{ 1248 struct resource *mem_res; 1249 struct s3c64xx_spi_driver_data *sdd; 1250 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1251 struct spi_controller *host; 1252 int ret, irq; 1253 char clk_name[16]; 1254 1255 if (!sci && pdev->dev.of_node) { 1256 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1257 if (IS_ERR(sci)) 1258 return PTR_ERR(sci); 1259 } 1260 1261 if (!sci) 1262 return dev_err_probe(&pdev->dev, -ENODEV, 1263 "Platform_data missing!\n"); 1264 1265 irq = platform_get_irq(pdev, 0); 1266 if (irq < 0) 1267 return irq; 1268 1269 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd)); 1270 if (!host) 1271 return -ENOMEM; 1272 1273 platform_set_drvdata(pdev, host); 1274 1275 sdd = spi_controller_get_devdata(host); 1276 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1277 sdd->host = host; 1278 sdd->cntrlr_info = sci; 1279 sdd->pdev = pdev; 1280 1281 ret = s3c64xx_spi_set_port_id(pdev, sdd); 1282 if (ret) 1283 return ret; 1284 1285 if (sdd->port_conf->fifo_depth) 1286 sdd->fifo_depth = sdd->port_conf->fifo_depth; 1287 else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", 1288 &sdd->fifo_depth)) 1289 sdd->fifo_depth = FIFO_DEPTH(sdd); 1290 1291 s3c64xx_spi_set_fifomask(sdd); 1292 1293 sdd->cur_bpw = 8; 1294 1295 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1296 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1297 1298 host->dev.of_node = pdev->dev.of_node; 1299 host->bus_num = -1; 1300 host->setup = s3c64xx_spi_setup; 1301 host->cleanup = s3c64xx_spi_cleanup; 1302 host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1303 host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1304 host->prepare_message = s3c64xx_spi_prepare_message; 1305 host->transfer_one = s3c64xx_spi_transfer_one; 1306 host->max_transfer_size = s3c64xx_spi_max_transfer_size; 1307 host->num_chipselect = sci->num_cs; 1308 host->use_gpio_descriptors = true; 1309 host->dma_alignment = 8; 1310 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1311 SPI_BPW_MASK(8); 1312 /* the spi->mode bits understood by this driver: */ 1313 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1314 if (sdd->port_conf->has_loopback) 1315 host->mode_bits |= SPI_LOOP; 1316 host->auto_runtime_pm = true; 1317 if (!is_polling(sdd)) 1318 host->can_dma = s3c64xx_spi_can_dma; 1319 1320 sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); 1321 if (IS_ERR(sdd->regs)) 1322 return PTR_ERR(sdd->regs); 1323 sdd->sfr_start = mem_res->start; 1324 1325 if (sci->cfg_gpio && sci->cfg_gpio()) 1326 return dev_err_probe(&pdev->dev, -EBUSY, 1327 "Unable to config gpio\n"); 1328 1329 /* Setup clocks */ 1330 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi"); 1331 if (IS_ERR(sdd->clk)) 1332 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk), 1333 "Unable to acquire clock 'spi'\n"); 1334 1335 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1336 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name); 1337 if (IS_ERR(sdd->src_clk)) 1338 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk), 1339 "Unable to acquire clock '%s'\n", 1340 clk_name); 1341 1342 if (sdd->port_conf->clk_ioclk) { 1343 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk"); 1344 if (IS_ERR(sdd->ioclk)) 1345 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk), 1346 "Unable to acquire 'ioclk'\n"); 1347 } 1348 1349 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1350 pm_runtime_use_autosuspend(&pdev->dev); 1351 pm_runtime_set_active(&pdev->dev); 1352 pm_runtime_enable(&pdev->dev); 1353 pm_runtime_get_sync(&pdev->dev); 1354 1355 /* Setup Default Mode */ 1356 s3c64xx_spi_hwinit(sdd); 1357 1358 spin_lock_init(&sdd->lock); 1359 init_completion(&sdd->xfer_completion); 1360 1361 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1362 "spi-s3c64xx", sdd); 1363 if (ret != 0) { 1364 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1365 irq, ret); 1366 goto err_pm_put; 1367 } 1368 1369 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1370 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1371 sdd->regs + S3C64XX_SPI_INT_EN); 1372 1373 ret = devm_spi_register_controller(&pdev->dev, host); 1374 if (ret != 0) { 1375 dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret); 1376 goto err_pm_put; 1377 } 1378 1379 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", 1380 host->bus_num, host->num_chipselect); 1381 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", 1382 mem_res, sdd->fifo_depth); 1383 1384 pm_runtime_put_autosuspend(&pdev->dev); 1385 1386 return 0; 1387 1388err_pm_put: 1389 pm_runtime_put_noidle(&pdev->dev); 1390 pm_runtime_disable(&pdev->dev); 1391 pm_runtime_set_suspended(&pdev->dev); 1392 1393 return ret; 1394} 1395 1396static void s3c64xx_spi_remove(struct platform_device *pdev) 1397{ 1398 struct spi_controller *host = platform_get_drvdata(pdev); 1399 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1400 1401 pm_runtime_get_sync(&pdev->dev); 1402 1403 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1404 1405 if (!is_polling(sdd)) { 1406 dma_release_channel(sdd->rx_dma.ch); 1407 dma_release_channel(sdd->tx_dma.ch); 1408 } 1409 1410 pm_runtime_put_noidle(&pdev->dev); 1411 pm_runtime_disable(&pdev->dev); 1412 pm_runtime_set_suspended(&pdev->dev); 1413} 1414 1415#ifdef CONFIG_PM_SLEEP 1416static int s3c64xx_spi_suspend(struct device *dev) 1417{ 1418 struct spi_controller *host = dev_get_drvdata(dev); 1419 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1420 int ret; 1421 1422 ret = spi_controller_suspend(host); 1423 if (ret) 1424 return ret; 1425 1426 ret = pm_runtime_force_suspend(dev); 1427 if (ret < 0) 1428 return ret; 1429 1430 sdd->cur_speed = 0; /* Output Clock is stopped */ 1431 1432 return 0; 1433} 1434 1435static int s3c64xx_spi_resume(struct device *dev) 1436{ 1437 struct spi_controller *host = dev_get_drvdata(dev); 1438 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1439 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1440 int ret; 1441 1442 if (sci->cfg_gpio) 1443 sci->cfg_gpio(); 1444 1445 ret = pm_runtime_force_resume(dev); 1446 if (ret < 0) 1447 return ret; 1448 1449 return spi_controller_resume(host); 1450} 1451#endif /* CONFIG_PM_SLEEP */ 1452 1453#ifdef CONFIG_PM 1454static int s3c64xx_spi_runtime_suspend(struct device *dev) 1455{ 1456 struct spi_controller *host = dev_get_drvdata(dev); 1457 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1458 1459 clk_disable_unprepare(sdd->clk); 1460 clk_disable_unprepare(sdd->src_clk); 1461 clk_disable_unprepare(sdd->ioclk); 1462 1463 return 0; 1464} 1465 1466static int s3c64xx_spi_runtime_resume(struct device *dev) 1467{ 1468 struct spi_controller *host = dev_get_drvdata(dev); 1469 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1470 int ret; 1471 1472 if (sdd->port_conf->clk_ioclk) { 1473 ret = clk_prepare_enable(sdd->ioclk); 1474 if (ret != 0) 1475 return ret; 1476 } 1477 1478 ret = clk_prepare_enable(sdd->src_clk); 1479 if (ret != 0) 1480 goto err_disable_ioclk; 1481 1482 ret = clk_prepare_enable(sdd->clk); 1483 if (ret != 0) 1484 goto err_disable_src_clk; 1485 1486 s3c64xx_spi_hwinit(sdd); 1487 1488 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1489 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1490 sdd->regs + S3C64XX_SPI_INT_EN); 1491 1492 return 0; 1493 1494err_disable_src_clk: 1495 clk_disable_unprepare(sdd->src_clk); 1496err_disable_ioclk: 1497 clk_disable_unprepare(sdd->ioclk); 1498 1499 return ret; 1500} 1501#endif /* CONFIG_PM */ 1502 1503static const struct dev_pm_ops s3c64xx_spi_pm = { 1504 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1505 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1506 s3c64xx_spi_runtime_resume, NULL) 1507}; 1508 1509static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1510 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1511 .fifo_lvl_mask = { 0x7f, 0x7F }, 1512 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1513 .rx_lvl_offset = 13, 1514 .tx_st_done = 21, 1515 .clk_div = 2, 1516}; 1517 1518static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1519 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1520 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1521 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1522 .rx_lvl_offset = 15, 1523 .tx_st_done = 25, 1524 .clk_div = 2, 1525 .high_speed = true, 1526}; 1527 1528static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1529 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1530 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1531 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1532 .rx_lvl_offset = 15, 1533 .tx_st_done = 25, 1534 .clk_div = 2, 1535 .high_speed = true, 1536 .clk_from_cmu = true, 1537 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1538}; 1539 1540static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1541 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1542 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1543 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1544 .rx_lvl_offset = 15, 1545 .tx_st_done = 25, 1546 .clk_div = 2, 1547 .high_speed = true, 1548 .clk_from_cmu = true, 1549 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1550}; 1551 1552static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 1553 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1554 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, 1555 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1556 .rx_lvl_offset = 15, 1557 .tx_st_done = 25, 1558 .clk_div = 2, 1559 .high_speed = true, 1560 .clk_from_cmu = true, 1561 .clk_ioclk = true, 1562 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1563}; 1564 1565static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { 1566 .fifo_depth = 64, 1567 .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, 1568 .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, 1569 .tx_st_done = 25, 1570 .clk_div = 4, 1571 .high_speed = true, 1572 .clk_from_cmu = true, 1573 .has_loopback = true, 1574 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1575}; 1576 1577static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { 1578 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1579 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 1580 0x7f, 0x7f, 0x7f, 0x7f}, 1581 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1582 .rx_lvl_offset = 15, 1583 .tx_st_done = 25, 1584 .clk_div = 4, 1585 .high_speed = true, 1586 .clk_from_cmu = true, 1587 .clk_ioclk = true, 1588 .has_loopback = true, 1589 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1590}; 1591 1592static const struct s3c64xx_spi_port_config fsd_spi_port_config = { 1593 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1594 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, 1595 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1596 .rx_lvl_offset = 15, 1597 .tx_st_done = 25, 1598 .clk_div = 2, 1599 .high_speed = true, 1600 .clk_from_cmu = true, 1601 .clk_ioclk = false, 1602 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1603}; 1604 1605static const struct s3c64xx_spi_port_config gs101_spi_port_config = { 1606 .fifo_depth = 64, 1607 .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, 1608 .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, 1609 .tx_st_done = 25, 1610 .clk_div = 4, 1611 .high_speed = true, 1612 .clk_from_cmu = true, 1613 .has_loopback = true, 1614 .use_32bit_io = true, 1615 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1616}; 1617 1618static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1619 { 1620 .name = "s3c6410-spi", 1621 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1622 }, 1623 { }, 1624}; 1625MODULE_DEVICE_TABLE(platform, s3c64xx_spi_driver_ids); 1626 1627static const struct of_device_id s3c64xx_spi_dt_match[] = { 1628 { .compatible = "google,gs101-spi", 1629 .data = &gs101_spi_port_config, 1630 }, 1631 { .compatible = "samsung,s3c6410-spi", 1632 .data = &s3c6410_spi_port_config, 1633 }, 1634 { .compatible = "samsung,s5pv210-spi", 1635 .data = &s5pv210_spi_port_config, 1636 }, 1637 { .compatible = "samsung,exynos4210-spi", 1638 .data = &exynos4_spi_port_config, 1639 }, 1640 { .compatible = "samsung,exynos7-spi", 1641 .data = &exynos7_spi_port_config, 1642 }, 1643 { .compatible = "samsung,exynos5433-spi", 1644 .data = &exynos5433_spi_port_config, 1645 }, 1646 { .compatible = "samsung,exynos850-spi", 1647 .data = &exynos850_spi_port_config, 1648 }, 1649 { .compatible = "samsung,exynosautov9-spi", 1650 .data = &exynosautov9_spi_port_config, 1651 }, 1652 { .compatible = "tesla,fsd-spi", 1653 .data = &fsd_spi_port_config, 1654 }, 1655 { }, 1656}; 1657MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1658 1659static struct platform_driver s3c64xx_spi_driver = { 1660 .driver = { 1661 .name = "s3c64xx-spi", 1662 .pm = &s3c64xx_spi_pm, 1663 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1664 }, 1665 .probe = s3c64xx_spi_probe, 1666 .remove = s3c64xx_spi_remove, 1667 .id_table = s3c64xx_spi_driver_ids, 1668}; 1669MODULE_ALIAS("platform:s3c64xx-spi"); 1670 1671module_platform_driver(s3c64xx_spi_driver); 1672 1673MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1674MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1675MODULE_LICENSE("GPL");
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