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spi-rockchip-sfc.c
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linux-6.19.14/drivers/spi/spi-rockchip-sfc.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Rockchip Serial Flash Controller Driver 4 * 5 * Copyright (c) 2017-2021, Rockchip Inc. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 * Chris Morgan <macroalpha82@gmail.com> 8 * Jon Lin <Jon.lin@rock-chips.com> 9 */ 10 11#include <linux/bitops.h> 12#include <linux/clk.h> 13#include <linux/completion.h> 14#include <linux/dma-mapping.h> 15#include <linux/iopoll.h> 16#include <linux/interrupt.h> 17#include <linux/mm.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/pinctrl/consumer.h> 21#include <linux/platform_device.h> 22#include <linux/pm_runtime.h> 23#include <linux/slab.h> 24#include <linux/spi/spi-mem.h> 25 26/* System control */ 27#define SFC_CTRL 0x0 28#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) 29#define SFC_CTRL_CMD_BITS_SHIFT 8 30#define SFC_CTRL_ADDR_BITS_SHIFT 10 31#define SFC_CTRL_DATA_BITS_SHIFT 12 32 33/* Interrupt mask */ 34#define SFC_IMR 0x4 35#define SFC_IMR_RX_FULL BIT(0) 36#define SFC_IMR_RX_UFLOW BIT(1) 37#define SFC_IMR_TX_OFLOW BIT(2) 38#define SFC_IMR_TX_EMPTY BIT(3) 39#define SFC_IMR_TRAN_FINISH BIT(4) 40#define SFC_IMR_BUS_ERR BIT(5) 41#define SFC_IMR_NSPI_ERR BIT(6) 42#define SFC_IMR_DMA BIT(7) 43 44/* Interrupt clear */ 45#define SFC_ICLR 0x8 46#define SFC_ICLR_RX_FULL BIT(0) 47#define SFC_ICLR_RX_UFLOW BIT(1) 48#define SFC_ICLR_TX_OFLOW BIT(2) 49#define SFC_ICLR_TX_EMPTY BIT(3) 50#define SFC_ICLR_TRAN_FINISH BIT(4) 51#define SFC_ICLR_BUS_ERR BIT(5) 52#define SFC_ICLR_NSPI_ERR BIT(6) 53#define SFC_ICLR_DMA BIT(7) 54 55/* FIFO threshold level */ 56#define SFC_FTLR 0xc 57#define SFC_FTLR_TX_SHIFT 0 58#define SFC_FTLR_TX_MASK 0x1f 59#define SFC_FTLR_RX_SHIFT 8 60#define SFC_FTLR_RX_MASK 0x1f 61 62/* Reset FSM and FIFO */ 63#define SFC_RCVR 0x10 64#define SFC_RCVR_RESET BIT(0) 65 66/* Enhanced mode */ 67#define SFC_AX 0x14 68 69/* Address Bit number */ 70#define SFC_ABIT 0x18 71 72/* Interrupt status */ 73#define SFC_ISR 0x1c 74#define SFC_ISR_RX_FULL_SHIFT BIT(0) 75#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) 76#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) 77#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) 78#define SFC_ISR_TX_FINISH_SHIFT BIT(4) 79#define SFC_ISR_BUS_ERR_SHIFT BIT(5) 80#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) 81#define SFC_ISR_DMA_SHIFT BIT(7) 82 83/* FIFO status */ 84#define SFC_FSR 0x20 85#define SFC_FSR_TX_IS_FULL BIT(0) 86#define SFC_FSR_TX_IS_EMPTY BIT(1) 87#define SFC_FSR_RX_IS_EMPTY BIT(2) 88#define SFC_FSR_RX_IS_FULL BIT(3) 89#define SFC_FSR_TXLV_MASK GENMASK(12, 8) 90#define SFC_FSR_TXLV_SHIFT 8 91#define SFC_FSR_RXLV_MASK GENMASK(20, 16) 92#define SFC_FSR_RXLV_SHIFT 16 93 94/* FSM status */ 95#define SFC_SR 0x24 96#define SFC_SR_IS_IDLE 0x0 97#define SFC_SR_IS_BUSY 0x1 98 99/* Raw interrupt status */ 100#define SFC_RISR 0x28 101#define SFC_RISR_RX_FULL BIT(0) 102#define SFC_RISR_RX_UNDERFLOW BIT(1) 103#define SFC_RISR_TX_OVERFLOW BIT(2) 104#define SFC_RISR_TX_EMPTY BIT(3) 105#define SFC_RISR_TRAN_FINISH BIT(4) 106#define SFC_RISR_BUS_ERR BIT(5) 107#define SFC_RISR_NSPI_ERR BIT(6) 108#define SFC_RISR_DMA BIT(7) 109 110/* Version */ 111#define SFC_VER 0x2C 112#define SFC_VER_3 0x3 113#define SFC_VER_4 0x4 114#define SFC_VER_5 0x5 115#define SFC_VER_8 0x8 116 117/* Delay line controller register */ 118#define SFC_DLL_CTRL0 0x3C 119#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) 120#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU 121#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU 122 123/* Master trigger */ 124#define SFC_DMA_TRIGGER 0x80 125#define SFC_DMA_TRIGGER_START 1 126 127/* Src or Dst addr for master */ 128#define SFC_DMA_ADDR 0x84 129 130/* Length control register extension 32GB */ 131#define SFC_LEN_CTRL 0x88 132#define SFC_LEN_CTRL_TRB_SEL 1 133#define SFC_LEN_EXT 0x8C 134 135/* Command */ 136#define SFC_CMD 0x100 137#define SFC_CMD_IDX_SHIFT 0 138#define SFC_CMD_DUMMY_SHIFT 8 139#define SFC_CMD_DIR_SHIFT 12 140#define SFC_CMD_DIR_RD 0 141#define SFC_CMD_DIR_WR 1 142#define SFC_CMD_ADDR_SHIFT 14 143#define SFC_CMD_ADDR_0BITS 0 144#define SFC_CMD_ADDR_24BITS 1 145#define SFC_CMD_ADDR_32BITS 2 146#define SFC_CMD_ADDR_XBITS 3 147#define SFC_CMD_TRAN_BYTES_SHIFT 16 148#define SFC_CMD_CS_SHIFT 30 149 150/* Address */ 151#define SFC_ADDR 0x104 152 153/* Data */ 154#define SFC_DATA 0x108 155 156#define SFC_CS1_REG_OFFSET 0x200 157 158#define SFC_MAX_CHIPSELECT_NUM 2 159 160#define SFC_MAX_IOSIZE_VER3 (512 * 31) 161/* Although up to 4GB, 64KB is enough with less mem reserved */ 162#define SFC_MAX_IOSIZE_VER4 (0x10000U) 163 164/* DMA is only enabled for large data transmission */ 165#define SFC_DMA_TRANS_THRETHOLD (0x40) 166 167/* Maximum clock values from datasheet suggest keeping clock value under 168 * 150MHz. No minimum or average value is suggested. 169 */ 170#define SFC_MAX_SPEED (150 * 1000 * 1000) 171 172#define ROCKCHIP_AUTOSUSPEND_DELAY 2000 173 174struct rockchip_sfc { 175 struct device *dev; 176 void __iomem *regbase; 177 struct clk *hclk; 178 struct clk *clk; 179 u32 speed[SFC_MAX_CHIPSELECT_NUM]; 180 /* virtual mapped addr for dma_buffer */ 181 void *buffer; 182 dma_addr_t dma_buffer; 183 struct completion cp; 184 bool use_dma; 185 u32 max_iosize; 186 u16 version; 187 struct spi_controller *host; 188}; 189 190static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 191{ 192 int err; 193 u32 status; 194 195 writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); 196 197 err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, 198 !(status & SFC_RCVR_RESET), 20, 199 jiffies_to_usecs(HZ)); 200 if (err) 201 dev_err(sfc->dev, "SFC reset never finished\n"); 202 203 /* Still need to clear the masked interrupt from RISR */ 204 writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 205 206 dev_dbg(sfc->dev, "reset\n"); 207 208 return err; 209} 210 211static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) 212{ 213 return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); 214} 215 216static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) 217{ 218 return SFC_MAX_IOSIZE_VER3; 219} 220 221static int rockchip_sfc_clk_set_rate(struct rockchip_sfc *sfc, unsigned long speed) 222{ 223 if (sfc->version >= SFC_VER_8) 224 return clk_set_rate(sfc->clk, speed * 2); 225 else 226 return clk_set_rate(sfc->clk, speed); 227} 228 229static unsigned long rockchip_sfc_clk_get_rate(struct rockchip_sfc *sfc) 230{ 231 if (sfc->version >= SFC_VER_8) 232 return clk_get_rate(sfc->clk) / 2; 233 else 234 return clk_get_rate(sfc->clk); 235} 236 237static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask) 238{ 239 u32 reg; 240 241 /* Enable transfer complete interrupt */ 242 reg = readl(sfc->regbase + SFC_IMR); 243 reg &= ~mask; 244 writel(reg, sfc->regbase + SFC_IMR); 245} 246 247static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask) 248{ 249 u32 reg; 250 251 /* Disable transfer finish interrupt */ 252 reg = readl(sfc->regbase + SFC_IMR); 253 reg |= mask; 254 writel(reg, sfc->regbase + SFC_IMR); 255} 256 257static int rockchip_sfc_init(struct rockchip_sfc *sfc) 258{ 259 writel(0, sfc->regbase + SFC_CTRL); 260 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 261 rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF); 262 if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) 263 writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); 264 265 return 0; 266} 267 268static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 269{ 270 int ret = 0; 271 u32 status; 272 273 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 274 status & SFC_FSR_TXLV_MASK, 0, 275 timeout_us); 276 if (ret) { 277 dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); 278 279 return -ETIMEDOUT; 280 } 281 282 return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; 283} 284 285static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) 286{ 287 int ret = 0; 288 u32 status; 289 290 ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, 291 status & SFC_FSR_RXLV_MASK, 0, 292 timeout_us); 293 if (ret) { 294 dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); 295 296 return -ETIMEDOUT; 297 } 298 299 return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; 300} 301 302static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) 303{ 304 if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { 305 /* 306 * SFC not support output DUMMY cycles right after CMD cycles, so 307 * treat it as ADDR cycles. 308 */ 309 op->addr.nbytes = op->dummy.nbytes; 310 op->addr.buswidth = op->dummy.buswidth; 311 op->addr.val = 0xFFFFFFFFF; 312 313 op->dummy.nbytes = 0; 314 } 315} 316 317static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, 318 struct spi_mem *mem, 319 const struct spi_mem_op *op, 320 u32 len) 321{ 322 u32 ctrl = 0, cmd = 0; 323 u8 cs = spi_get_chipselect(mem->spi, 0); 324 325 /* set CMD */ 326 cmd = op->cmd.opcode; 327 ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); 328 329 /* set ADDR */ 330 if (op->addr.nbytes) { 331 if (op->addr.nbytes == 4) { 332 cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; 333 } else if (op->addr.nbytes == 3) { 334 cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; 335 } else { 336 cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; 337 writel(op->addr.nbytes * 8 - 1, 338 sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_ABIT); 339 } 340 341 ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); 342 } 343 344 /* set DUMMY */ 345 if (op->dummy.nbytes) { 346 if (op->dummy.buswidth == 4) 347 cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; 348 else if (op->dummy.buswidth == 2) 349 cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; 350 else 351 cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; 352 } 353 354 /* set DATA */ 355 if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ 356 writel(len, sfc->regbase + SFC_LEN_EXT); 357 else 358 cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; 359 if (len) { 360 if (op->data.dir == SPI_MEM_DATA_OUT) 361 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 362 363 ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); 364 } 365 if (!len && op->addr.nbytes) 366 cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; 367 368 /* set the Controller */ 369 ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; 370 cmd |= cs << SFC_CMD_CS_SHIFT; 371 372 dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", 373 op->addr.nbytes, op->addr.buswidth, 374 op->dummy.nbytes, op->dummy.buswidth); 375 dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", 376 ctrl, cmd, op->addr.val, len); 377 378 writel(ctrl, sfc->regbase + cs * SFC_CS1_REG_OFFSET + SFC_CTRL); 379 writel(cmd, sfc->regbase + SFC_CMD); 380 if (op->addr.nbytes) 381 writel(op->addr.val, sfc->regbase + SFC_ADDR); 382 383 return 0; 384} 385 386static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) 387{ 388 u8 bytes = len & 0x3; 389 u32 dwords; 390 int tx_level; 391 u32 write_words; 392 u32 tmp = 0; 393 394 dwords = len >> 2; 395 while (dwords) { 396 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 397 if (tx_level < 0) 398 return tx_level; 399 write_words = min_t(u32, tx_level, dwords); 400 iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words); 401 buf += write_words << 2; 402 dwords -= write_words; 403 } 404 405 /* write the rest non word aligned bytes */ 406 if (bytes) { 407 tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); 408 if (tx_level < 0) 409 return tx_level; 410 memcpy(&tmp, buf, bytes); 411 writel(tmp, sfc->regbase + SFC_DATA); 412 } 413 414 return len; 415} 416 417static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) 418{ 419 u8 bytes = len & 0x3; 420 u32 dwords; 421 u8 read_words; 422 int rx_level; 423 int tmp; 424 425 /* word aligned access only */ 426 dwords = len >> 2; 427 while (dwords) { 428 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 429 if (rx_level < 0) 430 return rx_level; 431 read_words = min_t(u32, rx_level, dwords); 432 ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words); 433 buf += read_words << 2; 434 dwords -= read_words; 435 } 436 437 /* read the rest non word aligned bytes */ 438 if (bytes) { 439 rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); 440 if (rx_level < 0) 441 return rx_level; 442 tmp = readl(sfc->regbase + SFC_DATA); 443 memcpy(buf, &tmp, bytes); 444 } 445 446 return len; 447} 448 449static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) 450{ 451 writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); 452 writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); 453 writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); 454 455 return len; 456} 457 458static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, 459 const struct spi_mem_op *op, u32 len) 460{ 461 dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); 462 463 if (op->data.dir == SPI_MEM_DATA_OUT) 464 return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); 465 else 466 return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); 467} 468 469static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, 470 const struct spi_mem_op *op, u32 len) 471{ 472 int ret; 473 474 dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); 475 476 if (op->data.dir == SPI_MEM_DATA_OUT) { 477 memcpy(sfc->buffer, op->data.buf.out, len); 478 dma_sync_single_for_device(sfc->dev, sfc->dma_buffer, len, DMA_TO_DEVICE); 479 } 480 481 ret = rockchip_sfc_fifo_transfer_dma(sfc, sfc->dma_buffer, len); 482 if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) { 483 dev_err(sfc->dev, "DMA wait for transfer finish timeout\n"); 484 ret = -ETIMEDOUT; 485 } 486 rockchip_sfc_irq_mask(sfc, SFC_IMR_DMA); 487 488 if (op->data.dir == SPI_MEM_DATA_IN) { 489 dma_sync_single_for_cpu(sfc->dev, sfc->dma_buffer, len, DMA_FROM_DEVICE); 490 memcpy(op->data.buf.in, sfc->buffer, len); 491 } 492 493 return ret; 494} 495 496static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) 497{ 498 int ret = 0; 499 u32 status; 500 501 /* 502 * There is very little data left in fifo, and the controller will 503 * complete the transmission in a short period of time. 504 */ 505 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 506 !(status & SFC_SR_IS_BUSY), 507 0, 10); 508 if (!ret) 509 return 0; 510 511 ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, 512 !(status & SFC_SR_IS_BUSY), 513 20, timeout_us); 514 if (ret) { 515 dev_err(sfc->dev, "wait sfc idle timeout\n"); 516 rockchip_sfc_reset(sfc); 517 518 ret = -EIO; 519 } 520 521 return ret; 522} 523 524static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) 525{ 526 struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller); 527 u32 len = op->data.nbytes; 528 int ret; 529 u8 cs = spi_get_chipselect(mem->spi, 0); 530 531 ret = pm_runtime_get_sync(sfc->dev); 532 if (ret < 0) { 533 pm_runtime_put_noidle(sfc->dev); 534 return ret; 535 } 536 537 if (unlikely(op->max_freq != sfc->speed[cs]) && 538 !has_acpi_companion(sfc->dev)) { 539 ret = rockchip_sfc_clk_set_rate(sfc, op->max_freq); 540 if (ret) 541 goto out; 542 sfc->speed[cs] = op->max_freq; 543 dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", 544 sfc->speed[cs], rockchip_sfc_clk_get_rate(sfc)); 545 } 546 547 rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); 548 rockchip_sfc_xfer_setup(sfc, mem, op, len); 549 if (len) { 550 if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD && !(len & 0x3)) { 551 init_completion(&sfc->cp); 552 rockchip_sfc_irq_unmask(sfc, SFC_IMR_DMA); 553 ret = rockchip_sfc_xfer_data_dma(sfc, op, len); 554 } else { 555 ret = rockchip_sfc_xfer_data_poll(sfc, op, len); 556 } 557 558 if (ret != len) { 559 dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); 560 561 ret = -EIO; 562 goto out; 563 } 564 } 565 566 ret = rockchip_sfc_xfer_done(sfc, 100000); 567out: 568 pm_runtime_put_autosuspend(sfc->dev); 569 570 return ret; 571} 572 573static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 574{ 575 struct rockchip_sfc *sfc = spi_controller_get_devdata(mem->spi->controller); 576 577 op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); 578 579 return 0; 580} 581 582static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { 583 .exec_op = rockchip_sfc_exec_mem_op, 584 .adjust_op_size = rockchip_sfc_adjust_op_size, 585}; 586 587static const struct spi_controller_mem_caps rockchip_sfc_mem_caps = { 588 .per_op_freq = true, 589}; 590 591static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) 592{ 593 struct rockchip_sfc *sfc = dev_id; 594 u32 reg; 595 596 reg = readl(sfc->regbase + SFC_RISR); 597 598 /* Clear interrupt */ 599 writel_relaxed(reg, sfc->regbase + SFC_ICLR); 600 601 if (reg & SFC_RISR_DMA) { 602 complete(&sfc->cp); 603 604 return IRQ_HANDLED; 605 } 606 607 return IRQ_NONE; 608} 609 610static int rockchip_sfc_probe(struct platform_device *pdev) 611{ 612 struct device *dev = &pdev->dev; 613 struct spi_controller *host; 614 struct rockchip_sfc *sfc; 615 int ret; 616 u32 i, val; 617 618 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sfc)); 619 if (!host) 620 return -ENOMEM; 621 622 host->flags = SPI_CONTROLLER_HALF_DUPLEX; 623 host->mem_ops = &rockchip_sfc_mem_ops; 624 host->mem_caps = &rockchip_sfc_mem_caps; 625 host->dev.of_node = pdev->dev.of_node; 626 host->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL; 627 host->max_speed_hz = SFC_MAX_SPEED; 628 host->num_chipselect = SFC_MAX_CHIPSELECT_NUM; 629 630 sfc = spi_controller_get_devdata(host); 631 sfc->dev = dev; 632 sfc->host = host; 633 634 sfc->regbase = devm_platform_ioremap_resource(pdev, 0); 635 if (IS_ERR(sfc->regbase)) 636 return PTR_ERR(sfc->regbase); 637 638 if (!has_acpi_companion(&pdev->dev)) 639 sfc->clk = devm_clk_get(&pdev->dev, "clk_sfc"); 640 if (IS_ERR(sfc->clk)) 641 return dev_err_probe(&pdev->dev, PTR_ERR(sfc->clk), 642 "Failed to get sfc interface clk\n"); 643 644 if (!has_acpi_companion(&pdev->dev)) 645 sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc"); 646 if (IS_ERR(sfc->hclk)) 647 return dev_err_probe(&pdev->dev, PTR_ERR(sfc->hclk), 648 "Failed to get sfc ahb clk\n"); 649 650 if (has_acpi_companion(&pdev->dev)) { 651 ret = device_property_read_u32(&pdev->dev, "clock-frequency", &val); 652 if (ret) 653 return dev_err_probe(&pdev->dev, ret, 654 "Failed to find clock-frequency in ACPI\n"); 655 for (i = 0; i < SFC_MAX_CHIPSELECT_NUM; i++) 656 sfc->speed[i] = val; 657 } 658 659 sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, "rockchip,sfc-no-dma"); 660 661 ret = clk_prepare_enable(sfc->hclk); 662 if (ret) { 663 dev_err(&pdev->dev, "Failed to enable ahb clk\n"); 664 goto err_hclk; 665 } 666 667 ret = clk_prepare_enable(sfc->clk); 668 if (ret) { 669 dev_err(&pdev->dev, "Failed to enable interface clk\n"); 670 goto err_clk; 671 } 672 673 /* Find the irq */ 674 ret = platform_get_irq(pdev, 0); 675 if (ret < 0) 676 goto err_irq; 677 678 ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler, 679 0, pdev->name, sfc); 680 if (ret) { 681 dev_err(dev, "Failed to request irq\n"); 682 goto err_irq; 683 } 684 685 platform_set_drvdata(pdev, sfc); 686 687 ret = rockchip_sfc_init(sfc); 688 if (ret) 689 goto err_irq; 690 691 sfc->version = rockchip_sfc_get_version(sfc); 692 sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); 693 694 pm_runtime_set_autosuspend_delay(dev, ROCKCHIP_AUTOSUSPEND_DELAY); 695 pm_runtime_use_autosuspend(dev); 696 pm_runtime_set_active(dev); 697 pm_runtime_enable(dev); 698 pm_runtime_get_noresume(dev); 699 700 if (sfc->use_dma) { 701 sfc->buffer = (u8 *)__get_free_pages(GFP_KERNEL | GFP_DMA32, 702 get_order(sfc->max_iosize)); 703 if (!sfc->buffer) { 704 ret = -ENOMEM; 705 goto err_dma; 706 } 707 sfc->dma_buffer = dma_map_single(dev, sfc->buffer, 708 sfc->max_iosize, DMA_BIDIRECTIONAL); 709 if (dma_mapping_error(dev, sfc->dma_buffer)) { 710 ret = -ENOMEM; 711 goto err_dma_map; 712 } 713 } 714 715 ret = spi_register_controller(host); 716 if (ret) 717 goto err_register; 718 719 pm_runtime_put_autosuspend(dev); 720 721 return 0; 722err_register: 723 dma_unmap_single(dev, sfc->dma_buffer, sfc->max_iosize, 724 DMA_BIDIRECTIONAL); 725err_dma_map: 726 free_pages((unsigned long)sfc->buffer, get_order(sfc->max_iosize)); 727err_dma: 728 pm_runtime_get_sync(dev); 729 pm_runtime_put_noidle(dev); 730 pm_runtime_disable(dev); 731 pm_runtime_set_suspended(dev); 732 pm_runtime_dont_use_autosuspend(dev); 733err_irq: 734 clk_disable_unprepare(sfc->clk); 735err_clk: 736 clk_disable_unprepare(sfc->hclk); 737err_hclk: 738 return ret; 739} 740 741static void rockchip_sfc_remove(struct platform_device *pdev) 742{ 743 struct rockchip_sfc *sfc = platform_get_drvdata(pdev); 744 struct spi_controller *host = sfc->host; 745 746 spi_unregister_controller(host); 747 dma_unmap_single(&pdev->dev, sfc->dma_buffer, sfc->max_iosize, 748 DMA_BIDIRECTIONAL); 749 free_pages((unsigned long)sfc->buffer, get_order(sfc->max_iosize)); 750 751 clk_disable_unprepare(sfc->clk); 752 clk_disable_unprepare(sfc->hclk); 753} 754 755#ifdef CONFIG_PM 756static int rockchip_sfc_runtime_suspend(struct device *dev) 757{ 758 struct rockchip_sfc *sfc = dev_get_drvdata(dev); 759 760 clk_disable_unprepare(sfc->clk); 761 clk_disable_unprepare(sfc->hclk); 762 763 return 0; 764} 765 766static int rockchip_sfc_runtime_resume(struct device *dev) 767{ 768 struct rockchip_sfc *sfc = dev_get_drvdata(dev); 769 int ret; 770 771 ret = clk_prepare_enable(sfc->hclk); 772 if (ret < 0) 773 return ret; 774 775 ret = clk_prepare_enable(sfc->clk); 776 if (ret < 0) 777 clk_disable_unprepare(sfc->hclk); 778 779 return ret; 780} 781#endif /* CONFIG_PM */ 782 783#ifdef CONFIG_PM_SLEEP 784static int rockchip_sfc_suspend(struct device *dev) 785{ 786 pinctrl_pm_select_sleep_state(dev); 787 788 return pm_runtime_force_suspend(dev); 789} 790 791static int rockchip_sfc_resume(struct device *dev) 792{ 793 struct rockchip_sfc *sfc = dev_get_drvdata(dev); 794 int ret; 795 796 ret = pm_runtime_force_resume(dev); 797 if (ret < 0) 798 return ret; 799 800 pinctrl_pm_select_default_state(dev); 801 802 ret = pm_runtime_get_sync(dev); 803 if (ret < 0) { 804 pm_runtime_put_noidle(dev); 805 return ret; 806 } 807 808 rockchip_sfc_init(sfc); 809 810 pm_runtime_put_autosuspend(dev); 811 812 return 0; 813} 814#endif /* CONFIG_PM_SLEEP */ 815 816static const struct dev_pm_ops rockchip_sfc_pm_ops = { 817 SET_RUNTIME_PM_OPS(rockchip_sfc_runtime_suspend, 818 rockchip_sfc_runtime_resume, NULL) 819 SET_SYSTEM_SLEEP_PM_OPS(rockchip_sfc_suspend, rockchip_sfc_resume) 820}; 821 822static const struct of_device_id rockchip_sfc_dt_ids[] = { 823 { .compatible = "rockchip,sfc"}, 824 { /* sentinel */ } 825}; 826MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids); 827 828static struct platform_driver rockchip_sfc_driver = { 829 .driver = { 830 .name = "rockchip-sfc", 831 .of_match_table = rockchip_sfc_dt_ids, 832 .pm = &rockchip_sfc_pm_ops, 833 }, 834 .probe = rockchip_sfc_probe, 835 .remove = rockchip_sfc_remove, 836}; 837module_platform_driver(rockchip_sfc_driver); 838 839MODULE_LICENSE("GPL v2"); 840MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver"); 841MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); 842MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>"); 843MODULE_AUTHOR("Jon Lin <Jon.lin@rock-chips.com>");
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