spi-qpic-snand.c

   1/*
   2 * SPDX-License-Identifier: GPL-2.0
   3 *
   4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   5 *
   6 * Authors:
   7 *	Md Sadre Alam <quic_mdalam@quicinc.com>
   8 *	Sricharan R <quic_srichara@quicinc.com>
   9 *	Varadarajan Narayanan <quic_varada@quicinc.com>
  10 */
  11#include <linux/bitops.h>
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/dmaengine.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/dma/qcom_adm.h>
  17#include <linux/dma/qcom_bam_dma.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/platform_device.h>
  21#include <linux/slab.h>
  22#include <linux/mtd/nand-qpic-common.h>
  23#include <linux/mtd/spinand.h>
  24#include <linux/bitfield.h>
  25
  26#define NAND_FLASH_SPI_CFG		0xc0
  27#define NAND_NUM_ADDR_CYCLES		0xc4
  28#define NAND_BUSY_CHECK_WAIT_CNT	0xc8
  29#define NAND_FLASH_FEATURES		0xf64
  30
  31/* QSPI NAND config reg bits */
  32#define LOAD_CLK_CNTR_INIT_EN		BIT(28)
  33#define CLK_CNTR_INIT_VAL_VEC		0x924
  34#define CLK_CNTR_INIT_VAL_VEC_MASK	GENMASK(27, 16)
  35#define FEA_STATUS_DEV_ADDR		0xc0
  36#define FEA_STATUS_DEV_ADDR_MASK	GENMASK(15, 8)
  37#define SPI_CFG				BIT(0)
  38#define SPI_NUM_ADDR			0xDA4DB
  39#define SPI_WAIT_CNT			0x10
  40#define QPIC_QSPI_NUM_CS		1
  41#define SPI_TRANSFER_MODE_x1		BIT(29)
  42#define SPI_TRANSFER_MODE_x4		(3 << 29)
  43#define SPI_WP				BIT(28)
  44#define SPI_HOLD			BIT(27)
  45#define QPIC_SET_FEATURE		BIT(31)
  46
  47#define SPINAND_RESET			0xff
  48#define SPINAND_READID			0x9f
  49#define SPINAND_GET_FEATURE		0x0f
  50#define SPINAND_SET_FEATURE		0x1f
  51#define SPINAND_READ			0x13
  52#define SPINAND_ERASE			0xd8
  53#define SPINAND_WRITE_EN		0x06
  54#define SPINAND_PROGRAM_EXECUTE		0x10
  55#define SPINAND_PROGRAM_LOAD		0x84
  56
  57#define ACC_FEATURE			0xe
  58#define BAD_BLOCK_MARKER_SIZE		0x2
  59#define OOB_BUF_SIZE			128
  60#define ecceng_to_qspi(eng)		container_of(eng, struct qpic_spi_nand, ecc_eng)
  61
  62struct snandc_read_status {
  63	__le32 snandc_flash;
  64	__le32 snandc_buffer;
  65	__le32 snandc_erased_cw;
  66};
  67
  68/*
  69 * ECC state struct
  70 * @corrected:		ECC corrected
  71 * @bitflips:		Max bit flip
  72 * @failed:		ECC failed
  73 */
  74struct qcom_ecc_stats {
  75	u32 corrected;
  76	u32 bitflips;
  77	u32 failed;
  78};
  79
  80struct qpic_ecc {
  81	int ecc_bytes_hw;
  82	int spare_bytes;
  83	int bbm_size;
  84	int ecc_mode;
  85	int bytes;
  86	int steps;
  87	int step_size;
  88	int strength;
  89	int cw_size;
  90	int cw_data;
  91	u32 cfg0;
  92	u32 cfg1;
  93	u32 cfg0_raw;
  94	u32 cfg1_raw;
  95	u32 ecc_buf_cfg;
  96	u32 ecc_bch_cfg;
  97	bool bch_enabled;
  98};
  99
 100struct qpic_spi_nand {
 101	struct qcom_nand_controller *snandc;
 102	struct spi_controller *ctlr;
 103	struct mtd_info *mtd;
 104	struct clk *iomacro_clk;
 105	struct qpic_ecc *ecc;
 106	struct qcom_ecc_stats ecc_stats;
 107	struct nand_ecc_engine ecc_eng;
 108	u8 *data_buf;
 109	u8 *oob_buf;
 110	__le32 addr1;
 111	__le32 addr2;
 112	__le32 cmd;
 113	u32 num_cw;
 114	bool oob_rw;
 115	bool page_rw;
 116	bool raw_rw;
 117};
 118
 119static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
 120					int reg, int cw_offset, int read_size,
 121					int is_last_read_loc)
 122{
 123	__le32 locreg_val;
 124	u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
 125		  FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
 126		  FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
 127
 128	locreg_val = cpu_to_le32(val);
 129
 130	if (reg == NAND_READ_LOCATION_0)
 131		snandc->regs->read_location0 = locreg_val;
 132	else if (reg == NAND_READ_LOCATION_1)
 133		snandc->regs->read_location1 = locreg_val;
 134	else if (reg == NAND_READ_LOCATION_2)
 135		snandc->regs->read_location2 = locreg_val;
 136	else if (reg == NAND_READ_LOCATION_3)
 137		snandc->regs->read_location3 = locreg_val;
 138}
 139
 140static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
 141				       int reg, int cw_offset, int read_size,
 142				       int is_last_read_loc)
 143{
 144	__le32 locreg_val;
 145	u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
 146		  FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
 147		  FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
 148
 149	locreg_val = cpu_to_le32(val);
 150
 151	if (reg == NAND_READ_LOCATION_LAST_CW_0)
 152		snandc->regs->read_location_last0 = locreg_val;
 153	else if (reg == NAND_READ_LOCATION_LAST_CW_1)
 154		snandc->regs->read_location_last1 = locreg_val;
 155	else if (reg == NAND_READ_LOCATION_LAST_CW_2)
 156		snandc->regs->read_location_last2 = locreg_val;
 157	else if (reg == NAND_READ_LOCATION_LAST_CW_3)
 158		snandc->regs->read_location_last3 = locreg_val;
 159}
 160
 161static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
 162{
 163	struct nand_ecc_engine *eng = nand->ecc.engine;
 164	struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
 165
 166	return qspi->snandc;
 167}
 168
 169static int qcom_spi_init(struct qcom_nand_controller *snandc)
 170{
 171	u32 snand_cfg_val = 0x0;
 172	int ret;
 173
 174	snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
 175			FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
 176			FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
 177			FIELD_PREP(SPI_CFG, 0);
 178
 179	snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
 180	snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
 181	snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
 182
 183	qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
 184
 185	snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
 186	snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
 187
 188	qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
 189
 190	qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
 191	qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
 192			   NAND_BAM_NEXT_SGL);
 193
 194	ret = qcom_submit_descs(snandc);
 195	if (ret) {
 196		dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
 197		return ret;
 198	}
 199
 200	return ret;
 201}
 202
 203static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
 204				  struct mtd_oob_region *oobregion)
 205{
 206	struct nand_device *nand = mtd_to_nanddev(mtd);
 207	struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
 208	struct qpic_ecc *qecc = snandc->qspi->ecc;
 209
 210	switch (section) {
 211	case 0:
 212		oobregion->offset = 0;
 213		oobregion->length = qecc->bytes * (qecc->steps - 1) +
 214				    qecc->bbm_size;
 215		return 0;
 216	case 1:
 217		oobregion->offset = qecc->bytes * (qecc->steps - 1) +
 218				    qecc->bbm_size +
 219				    qecc->steps * 4;
 220		oobregion->length = mtd->oobsize - oobregion->offset;
 221		return 0;
 222	}
 223
 224	return -ERANGE;
 225}
 226
 227static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
 228				   struct mtd_oob_region *oobregion)
 229{
 230	struct nand_device *nand = mtd_to_nanddev(mtd);
 231	struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
 232	struct qpic_ecc *qecc = snandc->qspi->ecc;
 233
 234	if (section)
 235		return -ERANGE;
 236
 237	oobregion->length = qecc->steps * 4;
 238	oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
 239
 240	return 0;
 241}
 242
 243static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
 244	.ecc = qcom_spi_ooblayout_ecc,
 245	.free = qcom_spi_ooblayout_free,
 246};
 247
 248static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
 249{
 250	struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
 251	struct nand_ecc_props *reqs = &nand->ecc.requirements;
 252	struct nand_ecc_props *user = &nand->ecc.user_conf;
 253	struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
 254	struct mtd_info *mtd = nanddev_to_mtd(nand);
 255	int cwperpage, bad_block_byte, ret;
 256	struct qpic_ecc *ecc_cfg;
 257
 258	cwperpage = mtd->writesize / NANDC_STEP_SIZE;
 259	snandc->qspi->num_cw = cwperpage;
 260
 261	ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
 262	if (!ecc_cfg)
 263		return -ENOMEM;
 264
 265	if (user->step_size && user->strength) {
 266		ecc_cfg->step_size = user->step_size;
 267		ecc_cfg->strength = user->strength;
 268	} else if (reqs->step_size && reqs->strength) {
 269		ecc_cfg->step_size = reqs->step_size;
 270		ecc_cfg->strength = reqs->strength;
 271	} else {
 272		/* use defaults */
 273		ecc_cfg->step_size = NANDC_STEP_SIZE;
 274		ecc_cfg->strength = 4;
 275	}
 276
 277	if (ecc_cfg->step_size != NANDC_STEP_SIZE) {
 278		dev_err(snandc->dev,
 279			"only %u bytes ECC step size is supported\n",
 280			NANDC_STEP_SIZE);
 281		ret = -EOPNOTSUPP;
 282		goto err_free_ecc_cfg;
 283	}
 284
 285	switch (ecc_cfg->strength) {
 286	case 4:
 287		ecc_cfg->ecc_mode = ECC_MODE_4BIT;
 288		ecc_cfg->ecc_bytes_hw = 7;
 289		ecc_cfg->spare_bytes = 4;
 290		break;
 291
 292	case 8:
 293		ecc_cfg->ecc_mode = ECC_MODE_8BIT;
 294		ecc_cfg->ecc_bytes_hw = 13;
 295		ecc_cfg->spare_bytes = 2;
 296		break;
 297
 298	default:
 299		dev_err(snandc->dev,
 300			"only 4 or 8 bits ECC strength is supported\n");
 301		ret = -EOPNOTSUPP;
 302		goto err_free_ecc_cfg;
 303	}
 304
 305	snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize,
 306					GFP_KERNEL);
 307	if (!snandc->qspi->oob_buf) {
 308		ret = -ENOMEM;
 309		goto err_free_ecc_cfg;
 310	}
 311
 312	memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
 313
 314	nand->ecc.ctx.priv = ecc_cfg;
 315	snandc->qspi->mtd = mtd;
 316
 317	ecc_cfg->bbm_size = 1;
 318	ecc_cfg->bch_enabled = true;
 319	ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
 320
 321	ecc_cfg->steps = cwperpage;
 322	ecc_cfg->cw_data = 516;
 323	ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
 324	bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
 325
 326	mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
 327
 328	/*
 329	 * Free the temporary BAM transaction allocated initially by
 330	 * qcom_nandc_alloc(), and allocate a new one based on the
 331	 * updated max_cwperpage value.
 332	 */
 333	qcom_free_bam_transaction(snandc);
 334
 335	snandc->max_cwperpage = cwperpage;
 336
 337	snandc->bam_txn = qcom_alloc_bam_transaction(snandc);
 338	if (!snandc->bam_txn) {
 339		dev_err(snandc->dev, "failed to allocate BAM transaction\n");
 340		ret = -ENOMEM;
 341		goto err_free_ecc_cfg;
 342	}
 343
 344	ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
 345			FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
 346			FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
 347			FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
 348			FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
 349			FIELD_PREP(STATUS_BFR_READ, 0) |
 350			FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
 351			FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
 352
 353	ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
 354			FIELD_PREP(CS_ACTIVE_BSY, 0) |
 355			FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
 356			FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
 357			FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
 358			FIELD_PREP(WIDE_FLASH, 0) |
 359			FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
 360
 361	ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
 362			    FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
 363			    FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
 364			    FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
 365
 366	ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
 367			    FIELD_PREP(CS_ACTIVE_BSY, 0) |
 368			    FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
 369			    FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
 370			    FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
 371			    FIELD_PREP(WIDE_FLASH, 0) |
 372			    FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
 373
 374	ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
 375			       FIELD_PREP(ECC_SW_RESET, 0) |
 376			       FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
 377			       FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
 378			       FIELD_PREP(ECC_MODE_MASK, ecc_cfg->ecc_mode) |
 379			       FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
 380
 381	ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
 382
 383	conf->step_size = ecc_cfg->step_size;
 384	conf->strength = ecc_cfg->strength;
 385
 386	snandc->regs->clrflashstatus = cpu_to_le32(FS_READY_BSY_N);
 387	snandc->regs->clrreadstatus = cpu_to_le32(0xc0);
 388	snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
 389	snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
 390
 391	dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
 392		ecc_cfg->strength, ecc_cfg->step_size);
 393
 394	return 0;
 395
 396err_free_ecc_cfg:
 397	kfree(ecc_cfg);
 398	return ret;
 399}
 400
 401static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
 402{
 403	struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
 404
 405	kfree(ecc_cfg);
 406}
 407
 408static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
 409						 struct nand_page_io_req *req)
 410{
 411	struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
 412	struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
 413
 414	snandc->qspi->ecc = ecc_cfg;
 415	snandc->qspi->raw_rw = false;
 416	snandc->qspi->oob_rw = false;
 417	snandc->qspi->page_rw = false;
 418
 419	if (req->datalen)
 420		snandc->qspi->page_rw = true;
 421
 422	if (req->ooblen)
 423		snandc->qspi->oob_rw = true;
 424
 425	if (req->mode == MTD_OPS_RAW)
 426		snandc->qspi->raw_rw = true;
 427
 428	return 0;
 429}
 430
 431static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
 432						struct nand_page_io_req *req)
 433{
 434	struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
 435	struct mtd_info *mtd = nanddev_to_mtd(nand);
 436
 437	if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
 438		return 0;
 439
 440	if (snandc->qspi->ecc_stats.failed)
 441		mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
 442	else
 443		mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
 444
 445	if (snandc->qspi->ecc_stats.failed)
 446		return -EBADMSG;
 447	else
 448		return snandc->qspi->ecc_stats.bitflips;
 449}
 450
 451static const struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
 452	.init_ctx = qcom_spi_ecc_init_ctx_pipelined,
 453	.cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
 454	.prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
 455	.finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
 456};
 457
 458/* helper to configure location register values */
 459static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
 460				  int cw_offset, int read_size, int is_last_read_loc)
 461{
 462	int reg_base = NAND_READ_LOCATION_0;
 463	int num_cw = snandc->qspi->num_cw;
 464
 465	if (cw == (num_cw - 1))
 466		reg_base = NAND_READ_LOCATION_LAST_CW_0;
 467
 468	reg_base += reg * 4;
 469
 470	if (cw == (num_cw - 1))
 471		return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
 472						  read_size, is_last_read_loc);
 473	else
 474		return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
 475						   read_size, is_last_read_loc);
 476}
 477
 478static void
 479qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
 480{
 481	__le32 *reg = &snandc->regs->read_location0;
 482	int num_cw = snandc->qspi->num_cw;
 483
 484	qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
 485	if (cw == (num_cw - 1)) {
 486		reg = &snandc->regs->read_location_last0;
 487		qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
 488				   NAND_BAM_NEXT_SGL);
 489	}
 490
 491	qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 492	qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 493
 494	if (use_ecc) {
 495		qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
 496		qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
 497				  NAND_BAM_NEXT_SGL);
 498	} else {
 499		qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1,
 500				  NAND_BAM_NEXT_SGL);
 501	}
 502}
 503
 504static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
 505{
 506	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
 507	int ret;
 508
 509	snandc->buf_count = 0;
 510	snandc->buf_start = 0;
 511	qcom_clear_read_regs(snandc);
 512	qcom_clear_bam_transaction(snandc);
 513
 514	snandc->regs->cmd = snandc->qspi->cmd;
 515	snandc->regs->addr0 = snandc->qspi->addr1;
 516	snandc->regs->addr1 = snandc->qspi->addr2;
 517	snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
 518					 FIELD_PREP(CW_PER_PAGE_MASK, 0));
 519	snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
 520	snandc->regs->exec = cpu_to_le32(1);
 521
 522	qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
 523	qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
 524	qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 525
 526	ret = qcom_submit_descs(snandc);
 527	if (ret) {
 528		dev_err(snandc->dev, "failure to erase block\n");
 529		return ret;
 530	}
 531
 532	return 0;
 533}
 534
 535static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
 536						bool use_ecc, int cw)
 537{
 538	__le32 *reg = &snandc->regs->read_location0;
 539	int num_cw = snandc->qspi->num_cw;
 540
 541	qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
 542	qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
 543	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
 544			   NAND_ERASED_CW_DETECT_CFG, 1, 0);
 545	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
 546			   NAND_ERASED_CW_DETECT_CFG, 1,
 547			   NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
 548
 549	if (cw == (num_cw - 1)) {
 550		reg = &snandc->regs->read_location_last0;
 551		qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
 552	}
 553	qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 554	qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 555
 556	qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
 557}
 558
 559static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
 560{
 561	int i;
 562
 563	qcom_nandc_dev_to_mem(snandc, true);
 564
 565	for (i = 0; i < cw_cnt; i++) {
 566		u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
 567
 568		if (flash & (FS_OP_ERR | FS_MPU_ERR))
 569			return -EIO;
 570	}
 571
 572	return 0;
 573}
 574
 575static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
 576				 const struct spi_mem_op *op)
 577{
 578	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
 579	struct mtd_info *mtd = snandc->qspi->mtd;
 580	int size, ret = 0;
 581	int col,  bbpos;
 582	u32 cfg0, cfg1, ecc_bch_cfg;
 583	u32 num_cw = snandc->qspi->num_cw;
 584
 585	qcom_clear_bam_transaction(snandc);
 586	qcom_clear_read_regs(snandc);
 587
 588	size = ecc_cfg->cw_size;
 589	col = ecc_cfg->cw_size * (num_cw - 1);
 590
 591	memset(snandc->data_buffer, 0xff, size);
 592	snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
 593	snandc->regs->addr1 = snandc->qspi->addr2;
 594
 595	cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
 596	       FIELD_PREP(CW_PER_PAGE_MASK, 0);
 597	cfg1 = ecc_cfg->cfg1_raw;
 598	ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
 599
 600	snandc->regs->cmd = snandc->qspi->cmd;
 601	snandc->regs->cfg0 = cpu_to_le32(cfg0);
 602	snandc->regs->cfg1 = cpu_to_le32(cfg1);
 603	snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
 604	snandc->regs->exec = cpu_to_le32(1);
 605
 606	qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
 607
 608	qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
 609
 610	qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
 611
 612	ret = qcom_submit_descs(snandc);
 613	if (ret) {
 614		dev_err(snandc->dev, "failed to read last cw\n");
 615		return ret;
 616	}
 617
 618	ret = qcom_spi_check_raw_flash_errors(snandc, 1);
 619	if (ret)
 620		return ret;
 621
 622	bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
 623
 624	/*
 625	 * TODO: The SPINAND code expects two bad block marker bytes
 626	 * at the beginning of the OOB area, but the OOB layout used by
 627	 * the driver has only one. Duplicate that for now in order to
 628	 * avoid certain blocks to be marked as bad.
 629	 *
 630	 * This can be removed once single-byte bad block marker support
 631	 * gets implemented in the SPINAND code.
 632	 */
 633	snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
 634
 635	memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
 636
 637	return ret;
 638}
 639
 640static int qcom_spi_check_error(struct qcom_nand_controller *snandc)
 641{
 642	struct snandc_read_status *buf;
 643	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
 644	int i, num_cw = snandc->qspi->num_cw;
 645	bool flash_op_err = false, erased;
 646	unsigned int max_bitflips = 0;
 647	unsigned int uncorrectable_cws = 0;
 648
 649	snandc->qspi->ecc_stats.failed = 0;
 650	snandc->qspi->ecc_stats.corrected = 0;
 651
 652	qcom_nandc_dev_to_mem(snandc, true);
 653	buf = (struct snandc_read_status *)snandc->reg_read_buf;
 654
 655	for (i = 0; i < num_cw; i++, buf++) {
 656		u32 flash, buffer, erased_cw;
 657
 658		flash = le32_to_cpu(buf->snandc_flash);
 659		buffer = le32_to_cpu(buf->snandc_buffer);
 660		erased_cw = le32_to_cpu(buf->snandc_erased_cw);
 661
 662		if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
 663			if (ecc_cfg->bch_enabled)
 664				erased = (erased_cw & ERASED_CW) == ERASED_CW;
 665			else
 666				erased = false;
 667
 668			if (!erased)
 669				uncorrectable_cws |= BIT(i);
 670
 671		} else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
 672			flash_op_err = true;
 673		} else {
 674			unsigned int stat;
 675
 676			stat = buffer & BS_CORRECTABLE_ERR_MSK;
 677
 678			/*
 679			 * The exact number of the corrected bits is
 680			 * unknown because the hardware only reports the
 681			 * number of the corrected bytes.
 682			 *
 683			 * Since we have no better solution at the moment,
 684			 * report that value as the number of bit errors
 685			 * despite that it is inaccurate in most cases.
 686			 */
 687			if (stat && stat != ecc_cfg->strength)
 688				dev_warn_once(snandc->dev,
 689					      "Warning: due to hw limitation, the reported number of the corrected bits may be inaccurate\n");
 690
 691			snandc->qspi->ecc_stats.corrected += stat;
 692			max_bitflips = max(max_bitflips, stat);
 693		}
 694	}
 695
 696	if (flash_op_err)
 697		return -EIO;
 698
 699	if (!uncorrectable_cws)
 700		snandc->qspi->ecc_stats.bitflips = max_bitflips;
 701	else
 702		snandc->qspi->ecc_stats.failed++;
 703
 704	return 0;
 705}
 706
 707static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
 708				u8 *oob_buf, int cw)
 709{
 710	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
 711	struct mtd_info *mtd = snandc->qspi->mtd;
 712	int data_size1, data_size2, oob_size1, oob_size2;
 713	int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
 714	int raw_cw = cw;
 715	u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
 716	int col;
 717
 718	snandc->buf_count = 0;
 719	snandc->buf_start = 0;
 720	qcom_clear_read_regs(snandc);
 721	qcom_clear_bam_transaction(snandc);
 722	raw_cw = num_cw - 1;
 723
 724	cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
 725	       FIELD_PREP(CW_PER_PAGE_MASK, 0);
 726	cfg1 = ecc_cfg->cfg1_raw;
 727	ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
 728
 729	col = ecc_cfg->cw_size * cw;
 730
 731	snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
 732	snandc->regs->addr1 = snandc->qspi->addr2;
 733	snandc->regs->cmd = snandc->qspi->cmd;
 734	snandc->regs->cfg0 = cpu_to_le32(cfg0);
 735	snandc->regs->cfg1 = cpu_to_le32(cfg1);
 736	snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
 737	snandc->regs->exec = cpu_to_le32(1);
 738
 739	qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
 740
 741	qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
 742	qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
 743	qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
 744
 745	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
 746			   NAND_ERASED_CW_DETECT_CFG, 1, 0);
 747	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
 748			   NAND_ERASED_CW_DETECT_CFG, 1,
 749			   NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
 750
 751	data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
 752	oob_size1 = ecc_cfg->bbm_size;
 753
 754	if (cw == (num_cw - 1)) {
 755		data_size2 = NANDC_STEP_SIZE - data_size1 -
 756			     ((num_cw - 1) * 4);
 757		oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
 758			    ecc_cfg->spare_bytes;
 759	} else {
 760		data_size2 = ecc_cfg->cw_data - data_size1;
 761		oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
 762	}
 763
 764	qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
 765	read_loc += data_size1;
 766
 767	qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
 768	read_loc += oob_size1;
 769
 770	qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
 771	read_loc += data_size2;
 772
 773	qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
 774
 775	qcom_spi_config_cw_read(snandc, false, raw_cw);
 776
 777	qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
 778	reg_off += data_size1;
 779
 780	qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
 781	reg_off += oob_size1;
 782
 783	qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
 784	reg_off += data_size2;
 785
 786	qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
 787
 788	ret = qcom_submit_descs(snandc);
 789	if (ret) {
 790		dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
 791		return ret;
 792	}
 793
 794	return qcom_spi_check_raw_flash_errors(snandc, 1);
 795}
 796
 797static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
 798				  const struct spi_mem_op *op)
 799{
 800	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
 801	u8 *data_buf = NULL, *oob_buf = NULL;
 802	int ret, cw;
 803	u32 num_cw = snandc->qspi->num_cw;
 804
 805	if (snandc->qspi->page_rw)
 806		data_buf = op->data.buf.in;
 807
 808	oob_buf = snandc->qspi->oob_buf;
 809	memset(oob_buf, 0xff, OOB_BUF_SIZE);
 810
 811	for (cw = 0; cw < num_cw; cw++) {
 812		ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
 813		if (ret)
 814			return ret;
 815
 816		if (data_buf)
 817			data_buf += ecc_cfg->cw_data;
 818		if (oob_buf)
 819			oob_buf += ecc_cfg->bytes;
 820	}
 821
 822	return 0;
 823}
 824
 825static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
 826				  const struct spi_mem_op *op)
 827{
 828	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
 829	u8 *data_buf = NULL, *oob_buf = NULL;
 830	int ret, i;
 831	u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
 832
 833	data_buf = op->data.buf.in;
 834	oob_buf = snandc->qspi->oob_buf;
 835
 836	snandc->buf_count = 0;
 837	snandc->buf_start = 0;
 838	qcom_clear_read_regs(snandc);
 839
 840	cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
 841	       FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
 842	cfg1 = ecc_cfg->cfg1;
 843	ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
 844
 845	snandc->regs->addr0 = snandc->qspi->addr1;
 846	snandc->regs->addr1 = snandc->qspi->addr2;
 847	snandc->regs->cmd = snandc->qspi->cmd;
 848	snandc->regs->cfg0 = cpu_to_le32(cfg0);
 849	snandc->regs->cfg1 = cpu_to_le32(cfg1);
 850	snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
 851	snandc->regs->exec = cpu_to_le32(1);
 852
 853	qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
 854
 855	qcom_clear_bam_transaction(snandc);
 856
 857	qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
 858	qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
 859	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
 860			   NAND_ERASED_CW_DETECT_CFG, 1, 0);
 861	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
 862			   NAND_ERASED_CW_DETECT_CFG, 1,
 863			   NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
 864
 865	for (i = 0; i < num_cw; i++) {
 866		int data_size, oob_size;
 867
 868		if (i == (num_cw - 1)) {
 869			data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
 870			oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
 871				    ecc_cfg->spare_bytes;
 872		} else {
 873			data_size = ecc_cfg->cw_data;
 874			oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
 875		}
 876
 877		if (data_buf && oob_buf) {
 878			qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
 879			qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
 880		} else if (data_buf) {
 881			qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
 882		} else {
 883			qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
 884		}
 885
 886		qcom_spi_config_cw_read(snandc, true, i);
 887
 888		if (data_buf)
 889			qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
 890					   data_size, 0);
 891		if (oob_buf) {
 892			int j;
 893
 894			for (j = 0; j < ecc_cfg->bbm_size; j++)
 895				*oob_buf++ = 0xff;
 896
 897			qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
 898					   oob_buf, oob_size, 0);
 899		}
 900
 901		if (data_buf)
 902			data_buf += data_size;
 903		if (oob_buf)
 904			oob_buf += oob_size;
 905	}
 906
 907	ret = qcom_submit_descs(snandc);
 908	if (ret) {
 909		dev_err(snandc->dev, "failure to read page\n");
 910		return ret;
 911	}
 912
 913	return qcom_spi_check_error(snandc);
 914}
 915
 916static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
 917				  const struct spi_mem_op *op)
 918{
 919	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
 920	u8 *oob_buf = NULL;
 921	int ret, i;
 922	u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
 923
 924	oob_buf = op->data.buf.in;
 925
 926	snandc->buf_count = 0;
 927	snandc->buf_start = 0;
 928	qcom_clear_read_regs(snandc);
 929	qcom_clear_bam_transaction(snandc);
 930
 931	cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
 932	       FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
 933	cfg1 = ecc_cfg->cfg1;
 934	ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
 935
 936	snandc->regs->addr0 = snandc->qspi->addr1;
 937	snandc->regs->addr1 = snandc->qspi->addr2;
 938	snandc->regs->cmd = snandc->qspi->cmd;
 939	snandc->regs->cfg0 = cpu_to_le32(cfg0);
 940	snandc->regs->cfg1 = cpu_to_le32(cfg1);
 941	snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
 942	snandc->regs->exec = cpu_to_le32(1);
 943
 944	qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
 945
 946	qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
 947	qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
 948	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
 949			   NAND_ERASED_CW_DETECT_CFG, 1, 0);
 950	qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
 951			   NAND_ERASED_CW_DETECT_CFG, 1,
 952			   NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
 953
 954	for (i = 0; i < num_cw; i++) {
 955		int data_size, oob_size;
 956
 957		if (i == (num_cw - 1)) {
 958			data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
 959			oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
 960				    ecc_cfg->spare_bytes;
 961		} else {
 962			data_size = ecc_cfg->cw_data;
 963			oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
 964		}
 965
 966		qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
 967
 968		qcom_spi_config_cw_read(snandc, true, i);
 969
 970		if (oob_buf) {
 971			int j;
 972
 973			for (j = 0; j < ecc_cfg->bbm_size; j++)
 974				*oob_buf++ = 0xff;
 975
 976			qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
 977					   oob_buf, oob_size, 0);
 978		}
 979
 980		if (oob_buf)
 981			oob_buf += oob_size;
 982	}
 983
 984	ret = qcom_submit_descs(snandc);
 985	if (ret) {
 986		dev_err(snandc->dev, "failure to read oob\n");
 987		return ret;
 988	}
 989
 990	return qcom_spi_check_error(snandc);
 991}
 992
 993static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
 994			      const struct spi_mem_op *op)
 995{
 996	if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
 997		return qcom_spi_read_page_raw(snandc, op);
 998
 999	if (snandc->qspi->page_rw)
1000		return qcom_spi_read_page_ecc(snandc, op);
1001
1002	if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
1003		return qcom_spi_read_last_cw(snandc, op);
1004
1005	if (snandc->qspi->oob_rw)
1006		return qcom_spi_read_page_oob(snandc, op);
1007
1008	return 0;
1009}
1010
1011static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
1012{
1013	qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1014	qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1015	qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
1016			   1, NAND_BAM_NEXT_SGL);
1017}
1018
1019static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1020{
1021	qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1022	qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1023	qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1024
1025	qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1026	qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1027			   NAND_BAM_NEXT_SGL);
1028}
1029
1030static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1031				const struct spi_mem_op *op)
1032{
1033	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1034	struct mtd_info *mtd = snandc->qspi->mtd;
1035	u8 *data_buf = NULL, *oob_buf = NULL;
1036	int i, ret;
1037	int num_cw = snandc->qspi->num_cw;
1038	u32 cfg0, cfg1, ecc_bch_cfg;
1039
1040	cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
1041	       FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1042	cfg1 = ecc_cfg->cfg1_raw;
1043	ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1044
1045	data_buf = snandc->qspi->data_buf;
1046
1047	oob_buf = snandc->qspi->oob_buf;
1048	memset(oob_buf, 0xff, OOB_BUF_SIZE);
1049
1050	snandc->buf_count = 0;
1051	snandc->buf_start = 0;
1052	qcom_clear_read_regs(snandc);
1053	qcom_clear_bam_transaction(snandc);
1054
1055	snandc->regs->addr0 = snandc->qspi->addr1;
1056	snandc->regs->addr1 = snandc->qspi->addr2;
1057	snandc->regs->cmd = snandc->qspi->cmd;
1058	snandc->regs->cfg0 = cpu_to_le32(cfg0);
1059	snandc->regs->cfg1 = cpu_to_le32(cfg1);
1060	snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1061	snandc->regs->exec = cpu_to_le32(1);
1062
1063	qcom_spi_config_page_write(snandc);
1064
1065	for (i = 0; i < num_cw; i++) {
1066		int data_size1, data_size2, oob_size1, oob_size2;
1067		int reg_off = FLASH_BUF_ACC;
1068
1069		data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1070		oob_size1 = ecc_cfg->bbm_size;
1071
1072		if (i == (num_cw - 1)) {
1073			data_size2 = NANDC_STEP_SIZE - data_size1 -
1074				     ((num_cw - 1) << 2);
1075			oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1076				    ecc_cfg->spare_bytes;
1077		} else {
1078			data_size2 = ecc_cfg->cw_data - data_size1;
1079			oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1080		}
1081
1082		qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1083				    NAND_BAM_NO_EOT);
1084		reg_off += data_size1;
1085		data_buf += data_size1;
1086
1087		qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1088				    NAND_BAM_NO_EOT);
1089		oob_buf += oob_size1;
1090		reg_off += oob_size1;
1091
1092		qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1093				    NAND_BAM_NO_EOT);
1094		reg_off += data_size2;
1095		data_buf += data_size2;
1096
1097		qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1098		oob_buf += oob_size2;
1099
1100		qcom_spi_config_cw_write(snandc);
1101	}
1102
1103	ret = qcom_submit_descs(snandc);
1104	if (ret) {
1105		dev_err(snandc->dev, "failure to write raw page\n");
1106		return ret;
1107	}
1108
1109	return 0;
1110}
1111
1112static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1113				const struct spi_mem_op *op)
1114{
1115	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1116	u8 *data_buf = NULL, *oob_buf = NULL;
1117	int i, ret;
1118	int num_cw = snandc->qspi->num_cw;
1119	u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1120
1121	cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1122	       FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
1123	cfg1 = ecc_cfg->cfg1;
1124	ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1125	ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1126
1127	if (snandc->qspi->data_buf)
1128		data_buf = snandc->qspi->data_buf;
1129
1130	oob_buf = snandc->qspi->oob_buf;
1131
1132	snandc->buf_count = 0;
1133	snandc->buf_start = 0;
1134	qcom_clear_read_regs(snandc);
1135	qcom_clear_bam_transaction(snandc);
1136
1137	snandc->regs->addr0 = snandc->qspi->addr1;
1138	snandc->regs->addr1 = snandc->qspi->addr2;
1139	snandc->regs->cmd = snandc->qspi->cmd;
1140	snandc->regs->cfg0 = cpu_to_le32(cfg0);
1141	snandc->regs->cfg1 = cpu_to_le32(cfg1);
1142	snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1143	snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1144	snandc->regs->exec = cpu_to_le32(1);
1145
1146	qcom_spi_config_page_write(snandc);
1147
1148	for (i = 0; i < num_cw; i++) {
1149		int data_size, oob_size;
1150
1151		if (i == (num_cw - 1)) {
1152			data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1153			oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1154				    ecc_cfg->spare_bytes;
1155		} else {
1156			data_size = ecc_cfg->cw_data;
1157			oob_size = ecc_cfg->bytes;
1158		}
1159
1160		if (data_buf)
1161			qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1162					    i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1163
1164		if (i == (num_cw - 1)) {
1165			if (oob_buf) {
1166				oob_buf += ecc_cfg->bbm_size;
1167				qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1168						    oob_buf, oob_size, 0);
1169			}
1170		}
1171
1172		qcom_spi_config_cw_write(snandc);
1173
1174		if (data_buf)
1175			data_buf += data_size;
1176		if (oob_buf)
1177			oob_buf += oob_size;
1178	}
1179
1180	ret = qcom_submit_descs(snandc);
1181	if (ret) {
1182		dev_err(snandc->dev, "failure to write page\n");
1183		return ret;
1184	}
1185
1186	return 0;
1187}
1188
1189static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1190				const struct spi_mem_op *op)
1191{
1192	struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1193	u8 *oob_buf = NULL;
1194	int ret, col, data_size, oob_size;
1195	int num_cw = snandc->qspi->num_cw;
1196	u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1197
1198	cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
1199	       FIELD_PREP(CW_PER_PAGE_MASK, 0);
1200	cfg1 = ecc_cfg->cfg1;
1201	ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1202	ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1203
1204	col = ecc_cfg->cw_size * (num_cw - 1);
1205
1206	oob_buf = snandc->qspi->data_buf;
1207
1208	snandc->buf_count = 0;
1209	snandc->buf_start = 0;
1210	qcom_clear_read_regs(snandc);
1211	qcom_clear_bam_transaction(snandc);
1212	snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1213	snandc->regs->addr1 = snandc->qspi->addr2;
1214	snandc->regs->cmd = snandc->qspi->cmd;
1215	snandc->regs->cfg0 = cpu_to_le32(cfg0);
1216	snandc->regs->cfg1 = cpu_to_le32(cfg1);
1217	snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1218	snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1219	snandc->regs->exec = cpu_to_le32(1);
1220
1221	/* calculate the data and oob size for the last codeword/step */
1222	data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1223	oob_size = snandc->qspi->mtd->oobavail;
1224
1225	memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1226	/* override new oob content to last codeword */
1227	mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1228				    oob_buf, 0, snandc->qspi->mtd->oobavail);
1229	qcom_spi_config_page_write(snandc);
1230	qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1231	qcom_spi_config_cw_write(snandc);
1232
1233	ret = qcom_submit_descs(snandc);
1234	if (ret) {
1235		dev_err(snandc->dev, "failure to write oob\n");
1236		return ret;
1237	}
1238
1239	return 0;
1240}
1241
1242static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1243				    const struct spi_mem_op *op)
1244{
1245	if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1246		return qcom_spi_program_raw(snandc, op);
1247
1248	if (snandc->qspi->page_rw)
1249		return qcom_spi_program_ecc(snandc, op);
1250
1251	if (snandc->qspi->oob_rw)
1252		return qcom_spi_program_oob(snandc, op);
1253
1254	return 0;
1255}
1256
1257static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
1258{
1259	switch (opcode) {
1260	case SPINAND_RESET:
1261		*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1262		break;
1263	case SPINAND_READID:
1264		*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1265		break;
1266	case SPINAND_GET_FEATURE:
1267		*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1268		break;
1269	case SPINAND_SET_FEATURE:
1270		*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1271			QPIC_SET_FEATURE);
1272		break;
1273	case SPINAND_READ:
1274		if (snandc->qspi->raw_rw) {
1275			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1276					SPI_WP | SPI_HOLD | OP_PAGE_READ);
1277		} else {
1278			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1279					SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1280		}
1281
1282		break;
1283	case SPINAND_ERASE:
1284		*cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1285			SPI_HOLD | SPI_TRANSFER_MODE_x1;
1286		break;
1287	case SPINAND_WRITE_EN:
1288		*cmd = SPINAND_WRITE_EN;
1289		break;
1290	case SPINAND_PROGRAM_EXECUTE:
1291		*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1292				SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1293		break;
1294	case SPINAND_PROGRAM_LOAD:
1295		*cmd = SPINAND_PROGRAM_LOAD;
1296		break;
1297	default:
1298		dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1299		return -EOPNOTSUPP;
1300	}
1301
1302	return 0;
1303}
1304
1305static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1306			       const struct spi_mem_op *op)
1307{
1308	int ret;
1309	u32 cmd;
1310
1311	ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1312	if (ret < 0)
1313		return ret;
1314
1315	if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1316		snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1317
1318	return 0;
1319}
1320
1321static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1322				 const struct spi_mem_op *op)
1323{
1324	u32 cmd;
1325	int ret, opcode;
1326
1327	ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1328	if (ret < 0)
1329		return ret;
1330
1331	opcode = op->cmd.opcode;
1332
1333	switch (opcode) {
1334	case SPINAND_WRITE_EN:
1335		return 0;
1336	case SPINAND_PROGRAM_EXECUTE:
1337		snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1338		snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1339		snandc->qspi->cmd = cpu_to_le32(cmd);
1340		return qcom_spi_program_execute(snandc, op);
1341	case SPINAND_READ:
1342		snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1343		snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff);
1344		snandc->qspi->cmd = cpu_to_le32(cmd);
1345		return 0;
1346	case SPINAND_ERASE:
1347		snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16);
1348		snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xffff);
1349		snandc->qspi->cmd = cpu_to_le32(cmd);
1350		return qcom_spi_block_erase(snandc);
1351	default:
1352		break;
1353	}
1354
1355	snandc->buf_count = 0;
1356	snandc->buf_start = 0;
1357	qcom_clear_read_regs(snandc);
1358	qcom_clear_bam_transaction(snandc);
1359
1360	snandc->regs->cmd = cpu_to_le32(cmd);
1361	snandc->regs->exec = cpu_to_le32(1);
1362	snandc->regs->addr0 = cpu_to_le32(op->addr.val);
1363	snandc->regs->addr1 = cpu_to_le32(0);
1364
1365	qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1366	qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1367
1368	ret = qcom_submit_descs(snandc);
1369	if (ret)
1370		dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1371
1372	return ret;
1373}
1374
1375static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1376{
1377	int ret, val, opcode;
1378	bool copy = false, copy_ftr = false;
1379
1380	ret = qcom_spi_send_cmdaddr(snandc, op);
1381	if (ret)
1382		return ret;
1383
1384	snandc->buf_count = 0;
1385	snandc->buf_start = 0;
1386	qcom_clear_read_regs(snandc);
1387	qcom_clear_bam_transaction(snandc);
1388	opcode = op->cmd.opcode;
1389
1390	switch (opcode) {
1391	case SPINAND_READID:
1392		snandc->buf_count = 4;
1393		qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1394		copy = true;
1395		break;
1396	case SPINAND_GET_FEATURE:
1397		snandc->buf_count = 4;
1398		qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1399		copy_ftr = true;
1400		break;
1401	case SPINAND_SET_FEATURE:
1402		snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1403		qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1404				   NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1405		break;
1406	case SPINAND_PROGRAM_EXECUTE:
1407	case SPINAND_WRITE_EN:
1408	case SPINAND_RESET:
1409	case SPINAND_ERASE:
1410	case SPINAND_READ:
1411		return 0;
1412	default:
1413		return -EOPNOTSUPP;
1414	}
1415
1416	ret = qcom_submit_descs(snandc);
1417	if (ret) {
1418		dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1419		return ret;
1420	}
1421
1422	if (copy) {
1423		qcom_nandc_dev_to_mem(snandc, true);
1424		memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1425	}
1426
1427	if (copy_ftr) {
1428		qcom_nandc_dev_to_mem(snandc, true);
1429		val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1430		val >>= 8;
1431		memcpy(op->data.buf.in, &val, snandc->buf_count);
1432	}
1433
1434	return 0;
1435}
1436
1437static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1438{
1439	if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1440		return false;
1441
1442	if (op->data.dir == SPI_MEM_DATA_IN) {
1443		if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1444			return true;
1445
1446		if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1447			return true;
1448
1449	} else if (op->data.dir == SPI_MEM_DATA_OUT) {
1450		if (op->data.buswidth == 4)
1451			return true;
1452		if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1453			return true;
1454	}
1455
1456	return false;
1457}
1458
1459static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1460{
1461	if (!spi_mem_default_supports_op(mem, op))
1462		return false;
1463
1464	if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1465		return false;
1466
1467	if (qcom_spi_is_page_op(op))
1468		return true;
1469
1470	return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1471		(!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1472		(!op->data.nbytes || op->data.buswidth == 1));
1473}
1474
1475static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1476{
1477	struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1478
1479	dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1480		op->addr.val, op->addr.buswidth, op->addr.nbytes,
1481		op->data.buswidth, op->data.nbytes);
1482
1483	if (qcom_spi_is_page_op(op)) {
1484		if (op->data.dir == SPI_MEM_DATA_IN)
1485			return qcom_spi_read_page(snandc, op);
1486		if (op->data.dir == SPI_MEM_DATA_OUT)
1487			return qcom_spi_write_page(snandc, op);
1488	} else {
1489		return qcom_spi_io_op(snandc, op);
1490	}
1491
1492	return 0;
1493}
1494
1495static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1496	.supports_op = qcom_spi_supports_op,
1497	.exec_op = qcom_spi_exec_op,
1498};
1499
1500static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1501	.ecc = true,
1502};
1503
1504static int qcom_spi_probe(struct platform_device *pdev)
1505{
1506	struct device *dev = &pdev->dev;
1507	struct spi_controller *ctlr;
1508	struct qcom_nand_controller *snandc;
1509	struct qpic_spi_nand *qspi;
1510	struct qpic_ecc *ecc;
1511	struct resource *res;
1512	const void *dev_data;
1513	int ret;
1514
1515	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1516	if (!ecc)
1517		return -ENOMEM;
1518
1519	qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1520	if (!qspi)
1521		return -ENOMEM;
1522
1523	ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1524	if (!ctlr)
1525		return -ENOMEM;
1526
1527	platform_set_drvdata(pdev, ctlr);
1528
1529	snandc = spi_controller_get_devdata(ctlr);
1530	qspi->snandc = snandc;
1531
1532	snandc->dev = dev;
1533	snandc->qspi = qspi;
1534	snandc->qspi->ctlr = ctlr;
1535	snandc->qspi->ecc = ecc;
1536
1537	dev_data = of_device_get_match_data(dev);
1538	if (!dev_data) {
1539		dev_err(&pdev->dev, "failed to get device data\n");
1540		return -ENODEV;
1541	}
1542
1543	snandc->props = dev_data;
1544
1545	snandc->core_clk = devm_clk_get_enabled(dev, "core");
1546	if (IS_ERR(snandc->core_clk))
1547		return PTR_ERR(snandc->core_clk);
1548
1549	snandc->aon_clk = devm_clk_get_enabled(dev, "aon");
1550	if (IS_ERR(snandc->aon_clk))
1551		return PTR_ERR(snandc->aon_clk);
1552
1553	snandc->qspi->iomacro_clk = devm_clk_get_enabled(dev, "iom");
1554	if (IS_ERR(snandc->qspi->iomacro_clk))
1555		return PTR_ERR(snandc->qspi->iomacro_clk);
1556
1557	snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1558	if (IS_ERR(snandc->base))
1559		return PTR_ERR(snandc->base);
1560
1561	snandc->base_phys = res->start;
1562	snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1563					    DMA_BIDIRECTIONAL, 0);
1564	if (dma_mapping_error(dev, snandc->base_dma))
1565		return -ENXIO;
1566
1567	ret = qcom_nandc_alloc(snandc);
1568	if (ret)
1569		goto err_snand_alloc;
1570
1571	ret = qcom_spi_init(snandc);
1572	if (ret)
1573		goto err_spi_init;
1574
1575	/* setup ECC engine */
1576	snandc->qspi->ecc_eng.dev = &pdev->dev;
1577	snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1578	snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1579	snandc->qspi->ecc_eng.priv = snandc;
1580
1581	ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1582	if (ret) {
1583		dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1584		goto err_spi_init;
1585	}
1586
1587	ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1588	ctlr->mem_ops = &qcom_spi_mem_ops;
1589	ctlr->mem_caps = &qcom_spi_mem_caps;
1590	ctlr->dev.of_node = pdev->dev.of_node;
1591	ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1592			    SPI_TX_QUAD | SPI_RX_QUAD;
1593
1594	ret = spi_register_controller(ctlr);
1595	if (ret) {
1596		dev_err(&pdev->dev, "spi_register_controller failed.\n");
1597		goto err_register_controller;
1598	}
1599
1600	return 0;
1601
1602err_register_controller:
1603	nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
1604err_spi_init:
1605	qcom_nandc_unalloc(snandc);
1606err_snand_alloc:
1607	dma_unmap_resource(dev, res->start, resource_size(res),
1608			   DMA_BIDIRECTIONAL, 0);
1609	return ret;
1610}
1611
1612static void qcom_spi_remove(struct platform_device *pdev)
1613{
1614	struct spi_controller *ctlr = platform_get_drvdata(pdev);
1615	struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1616	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1617
1618	spi_unregister_controller(ctlr);
1619	nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
1620	qcom_nandc_unalloc(snandc);
1621	dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1622			   DMA_BIDIRECTIONAL, 0);
1623}
1624
1625static const struct qcom_nandc_props ipq9574_snandc_props = {
1626	.dev_cmd_reg_start = 0x7000,
1627	.bam_offset = 0x30000,
1628	.supports_bam = true,
1629};
1630
1631static const struct of_device_id qcom_snandc_of_match[] = {
1632	{
1633		.compatible = "qcom,ipq9574-snand",
1634		.data = &ipq9574_snandc_props,
1635	},
1636	{}
1637};
1638MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1639
1640static struct platform_driver qcom_spi_driver = {
1641	.driver = {
1642		.name		= "qcom_snand",
1643		.of_match_table = qcom_snandc_of_match,
1644	},
1645	.probe = qcom_spi_probe,
1646	.remove = qcom_spi_remove,
1647};
1648module_platform_driver(qcom_spi_driver);
1649
1650MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1651MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1652MODULE_LICENSE("GPL");
1653