spi-pl022.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
   4 *
   5 * Copyright (C) 2008-2012 ST-Ericsson AB
   6 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
   7 *
   8 * Author: Linus Walleij <linus.walleij@stericsson.com>
   9 *
  10 * Initial version inspired by:
  11 *	linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
  12 * Initial adoption to PL022 by:
  13 *      Sachin Verma <sachin.verma@st.com>
  14 */
  15
  16#include <linux/init.h>
  17#include <linux/module.h>
  18#include <linux/device.h>
  19#include <linux/ioport.h>
  20#include <linux/errno.h>
  21#include <linux/interrupt.h>
  22#include <linux/spi/spi.h>
  23#include <linux/delay.h>
  24#include <linux/clk.h>
  25#include <linux/err.h>
  26#include <linux/amba/bus.h>
  27#include <linux/amba/pl022.h>
  28#include <linux/io.h>
  29#include <linux/slab.h>
  30#include <linux/dmaengine.h>
  31#include <linux/dma-mapping.h>
  32#include <linux/scatterlist.h>
  33#include <linux/pm_runtime.h>
  34#include <linux/of.h>
  35#include <linux/pinctrl/consumer.h>
  36#include <linux/minmax.h>
  37
  38/*
  39 * This macro is used to define some register default values.
  40 * reg is masked with mask, the OR:ed with an (again masked)
  41 * val shifted sb steps to the left.
  42 */
  43#define SSP_WRITE_BITS(reg, val, mask, sb) \
  44 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
  45
  46/*
  47 * This macro is also used to define some default values.
  48 * It will just shift val by sb steps to the left and mask
  49 * the result with mask.
  50 */
  51#define GEN_MASK_BITS(val, mask, sb) \
  52 (((val)<<(sb)) & (mask))
  53
  54#define DRIVE_TX		0
  55#define DO_NOT_DRIVE_TX		1
  56
  57#define DO_NOT_QUEUE_DMA	0
  58#define QUEUE_DMA		1
  59
  60#define RX_TRANSFER		1
  61#define TX_TRANSFER		2
  62
  63/*
  64 * Macros to access SSP Registers with their offsets
  65 */
  66#define SSP_CR0(r)	(r + 0x000)
  67#define SSP_CR1(r)	(r + 0x004)
  68#define SSP_DR(r)	(r + 0x008)
  69#define SSP_SR(r)	(r + 0x00C)
  70#define SSP_CPSR(r)	(r + 0x010)
  71#define SSP_IMSC(r)	(r + 0x014)
  72#define SSP_RIS(r)	(r + 0x018)
  73#define SSP_MIS(r)	(r + 0x01C)
  74#define SSP_ICR(r)	(r + 0x020)
  75#define SSP_DMACR(r)	(r + 0x024)
  76#define SSP_CSR(r)	(r + 0x030) /* vendor extension */
  77#define SSP_ITCR(r)	(r + 0x080)
  78#define SSP_ITIP(r)	(r + 0x084)
  79#define SSP_ITOP(r)	(r + 0x088)
  80#define SSP_TDR(r)	(r + 0x08C)
  81
  82#define SSP_PID0(r)	(r + 0xFE0)
  83#define SSP_PID1(r)	(r + 0xFE4)
  84#define SSP_PID2(r)	(r + 0xFE8)
  85#define SSP_PID3(r)	(r + 0xFEC)
  86
  87#define SSP_CID0(r)	(r + 0xFF0)
  88#define SSP_CID1(r)	(r + 0xFF4)
  89#define SSP_CID2(r)	(r + 0xFF8)
  90#define SSP_CID3(r)	(r + 0xFFC)
  91
  92/*
  93 * SSP Control Register 0  - SSP_CR0
  94 */
  95#define SSP_CR0_MASK_DSS	(0x0FUL << 0)
  96#define SSP_CR0_MASK_FRF	(0x3UL << 4)
  97#define SSP_CR0_MASK_SPO	(0x1UL << 6)
  98#define SSP_CR0_MASK_SPH	(0x1UL << 7)
  99#define SSP_CR0_MASK_SCR	(0xFFUL << 8)
 100
 101/*
 102 * The ST version of this block moves som bits
 103 * in SSP_CR0 and extends it to 32 bits
 104 */
 105#define SSP_CR0_MASK_DSS_ST	(0x1FUL << 0)
 106#define SSP_CR0_MASK_HALFDUP_ST	(0x1UL << 5)
 107#define SSP_CR0_MASK_CSS_ST	(0x1FUL << 16)
 108#define SSP_CR0_MASK_FRF_ST	(0x3UL << 21)
 109
 110/*
 111 * SSP Control Register 0  - SSP_CR1
 112 */
 113#define SSP_CR1_MASK_LBM	(0x1UL << 0)
 114#define SSP_CR1_MASK_SSE	(0x1UL << 1)
 115#define SSP_CR1_MASK_MS		(0x1UL << 2)
 116#define SSP_CR1_MASK_SOD	(0x1UL << 3)
 117
 118/*
 119 * The ST version of this block adds some bits
 120 * in SSP_CR1
 121 */
 122#define SSP_CR1_MASK_RENDN_ST	(0x1UL << 4)
 123#define SSP_CR1_MASK_TENDN_ST	(0x1UL << 5)
 124#define SSP_CR1_MASK_MWAIT_ST	(0x1UL << 6)
 125#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
 126#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
 127/* This one is only in the PL023 variant */
 128#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
 129
 130/*
 131 * SSP Status Register - SSP_SR
 132 */
 133#define SSP_SR_MASK_TFE		(0x1UL << 0) /* Transmit FIFO empty */
 134#define SSP_SR_MASK_TNF		(0x1UL << 1) /* Transmit FIFO not full */
 135#define SSP_SR_MASK_RNE		(0x1UL << 2) /* Receive FIFO not empty */
 136#define SSP_SR_MASK_RFF		(0x1UL << 3) /* Receive FIFO full */
 137#define SSP_SR_MASK_BSY		(0x1UL << 4) /* Busy Flag */
 138
 139/*
 140 * SSP Clock Prescale Register  - SSP_CPSR
 141 */
 142#define SSP_CPSR_MASK_CPSDVSR	(0xFFUL << 0)
 143
 144/*
 145 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
 146 */
 147#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
 148#define SSP_IMSC_MASK_RTIM  (0x1UL << 1) /* Receive timeout Interrupt mask */
 149#define SSP_IMSC_MASK_RXIM  (0x1UL << 2) /* Receive FIFO Interrupt mask */
 150#define SSP_IMSC_MASK_TXIM  (0x1UL << 3) /* Transmit FIFO Interrupt mask */
 151
 152/*
 153 * SSP Raw Interrupt Status Register - SSP_RIS
 154 */
 155/* Receive Overrun Raw Interrupt status */
 156#define SSP_RIS_MASK_RORRIS		(0x1UL << 0)
 157/* Receive Timeout Raw Interrupt status */
 158#define SSP_RIS_MASK_RTRIS		(0x1UL << 1)
 159/* Receive FIFO Raw Interrupt status */
 160#define SSP_RIS_MASK_RXRIS		(0x1UL << 2)
 161/* Transmit FIFO Raw Interrupt status */
 162#define SSP_RIS_MASK_TXRIS		(0x1UL << 3)
 163
 164/*
 165 * SSP Masked Interrupt Status Register - SSP_MIS
 166 */
 167/* Receive Overrun Masked Interrupt status */
 168#define SSP_MIS_MASK_RORMIS		(0x1UL << 0)
 169/* Receive Timeout Masked Interrupt status */
 170#define SSP_MIS_MASK_RTMIS		(0x1UL << 1)
 171/* Receive FIFO Masked Interrupt status */
 172#define SSP_MIS_MASK_RXMIS		(0x1UL << 2)
 173/* Transmit FIFO Masked Interrupt status */
 174#define SSP_MIS_MASK_TXMIS		(0x1UL << 3)
 175
 176/*
 177 * SSP Interrupt Clear Register - SSP_ICR
 178 */
 179/* Receive Overrun Raw Clear Interrupt bit */
 180#define SSP_ICR_MASK_RORIC		(0x1UL << 0)
 181/* Receive Timeout Clear Interrupt bit */
 182#define SSP_ICR_MASK_RTIC		(0x1UL << 1)
 183
 184/*
 185 * SSP DMA Control Register - SSP_DMACR
 186 */
 187/* Receive DMA Enable bit */
 188#define SSP_DMACR_MASK_RXDMAE		(0x1UL << 0)
 189/* Transmit DMA Enable bit */
 190#define SSP_DMACR_MASK_TXDMAE		(0x1UL << 1)
 191
 192/*
 193 * SSP Chip Select Control Register - SSP_CSR
 194 * (vendor extension)
 195 */
 196#define SSP_CSR_CSVALUE_MASK		(0x1FUL << 0)
 197
 198/*
 199 * SSP Integration Test control Register - SSP_ITCR
 200 */
 201#define SSP_ITCR_MASK_ITEN		(0x1UL << 0)
 202#define SSP_ITCR_MASK_TESTFIFO		(0x1UL << 1)
 203
 204/*
 205 * SSP Integration Test Input Register - SSP_ITIP
 206 */
 207#define ITIP_MASK_SSPRXD		 (0x1UL << 0)
 208#define ITIP_MASK_SSPFSSIN		 (0x1UL << 1)
 209#define ITIP_MASK_SSPCLKIN		 (0x1UL << 2)
 210#define ITIP_MASK_RXDMAC		 (0x1UL << 3)
 211#define ITIP_MASK_TXDMAC		 (0x1UL << 4)
 212#define ITIP_MASK_SSPTXDIN		 (0x1UL << 5)
 213
 214/*
 215 * SSP Integration Test output Register - SSP_ITOP
 216 */
 217#define ITOP_MASK_SSPTXD		 (0x1UL << 0)
 218#define ITOP_MASK_SSPFSSOUT		 (0x1UL << 1)
 219#define ITOP_MASK_SSPCLKOUT		 (0x1UL << 2)
 220#define ITOP_MASK_SSPOEn		 (0x1UL << 3)
 221#define ITOP_MASK_SSPCTLOEn		 (0x1UL << 4)
 222#define ITOP_MASK_RORINTR		 (0x1UL << 5)
 223#define ITOP_MASK_RTINTR		 (0x1UL << 6)
 224#define ITOP_MASK_RXINTR		 (0x1UL << 7)
 225#define ITOP_MASK_TXINTR		 (0x1UL << 8)
 226#define ITOP_MASK_INTR			 (0x1UL << 9)
 227#define ITOP_MASK_RXDMABREQ		 (0x1UL << 10)
 228#define ITOP_MASK_RXDMASREQ		 (0x1UL << 11)
 229#define ITOP_MASK_TXDMABREQ		 (0x1UL << 12)
 230#define ITOP_MASK_TXDMASREQ		 (0x1UL << 13)
 231
 232/*
 233 * SSP Test Data Register - SSP_TDR
 234 */
 235#define TDR_MASK_TESTDATA		(0xFFFFFFFF)
 236
 237/*
 238 * Message State
 239 * we use the spi_message.state (void *) pointer to
 240 * hold a single state value, that's why all this
 241 * (void *) casting is done here.
 242 */
 243#define STATE_START			((void *) 0)
 244#define STATE_RUNNING			((void *) 1)
 245#define STATE_DONE			((void *) 2)
 246#define STATE_ERROR			((void *) -1)
 247#define STATE_TIMEOUT			((void *) -2)
 248
 249/*
 250 * SSP State - Whether Enabled or Disabled
 251 */
 252#define SSP_DISABLED			(0)
 253#define SSP_ENABLED			(1)
 254
 255/*
 256 * SSP DMA State - Whether DMA Enabled or Disabled
 257 */
 258#define SSP_DMA_DISABLED		(0)
 259#define SSP_DMA_ENABLED			(1)
 260
 261/*
 262 * SSP Clock Defaults
 263 */
 264#define SSP_DEFAULT_CLKRATE 0x2
 265#define SSP_DEFAULT_PRESCALE 0x40
 266
 267/*
 268 * SSP Clock Parameter ranges
 269 */
 270#define CPSDVR_MIN 0x02
 271#define CPSDVR_MAX 0xFE
 272#define SCR_MIN 0x00
 273#define SCR_MAX 0xFF
 274
 275/*
 276 * SSP Interrupt related Macros
 277 */
 278#define DEFAULT_SSP_REG_IMSC  0x0UL
 279#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
 280#define ENABLE_ALL_INTERRUPTS ( \
 281	SSP_IMSC_MASK_RORIM | \
 282	SSP_IMSC_MASK_RTIM | \
 283	SSP_IMSC_MASK_RXIM | \
 284	SSP_IMSC_MASK_TXIM \
 285)
 286
 287#define CLEAR_ALL_INTERRUPTS  0x3
 288
 289#define SPI_POLLING_TIMEOUT 1000
 290
 291/*
 292 * The type of reading going on this chip
 293 */
 294enum ssp_reading {
 295	READING_NULL,
 296	READING_U8,
 297	READING_U16,
 298	READING_U32
 299};
 300
 301/*
 302 * The type of writing going on this chip
 303 */
 304enum ssp_writing {
 305	WRITING_NULL,
 306	WRITING_U8,
 307	WRITING_U16,
 308	WRITING_U32
 309};
 310
 311/**
 312 * struct vendor_data - vendor-specific config parameters
 313 * for PL022 derivates
 314 * @fifodepth: depth of FIFOs (both)
 315 * @max_bpw: maximum number of bits per word
 316 * @unidir: supports unidirection transfers
 317 * @extended_cr: 32 bit wide control register 0 with extra
 318 * features and extra features in CR1 as found in the ST variants
 319 * @pl023: supports a subset of the ST extensions called "PL023"
 320 * @loopback: supports loopback mode
 321 * @internal_cs_ctrl: supports chip select control register
 322 */
 323struct vendor_data {
 324	int fifodepth;
 325	int max_bpw;
 326	bool unidir;
 327	bool extended_cr;
 328	bool pl023;
 329	bool loopback;
 330	bool internal_cs_ctrl;
 331};
 332
 333/**
 334 * struct pl022 - This is the private SSP driver data structure
 335 * @adev: AMBA device model hookup
 336 * @vendor: vendor data for the IP block
 337 * @phybase: the physical memory where the SSP device resides
 338 * @virtbase: the virtual memory where the SSP is mapped
 339 * @clk: outgoing clock "SPICLK" for the SPI bus
 340 * @host: SPI framework hookup
 341 * @host_info: controller-specific data from machine setup
 342 * @cur_transfer: Pointer to current spi_transfer
 343 * @cur_chip: pointer to current clients chip(assigned from controller_state)
 344 * @tx: current position in TX buffer to be read
 345 * @tx_end: end position in TX buffer to be read
 346 * @rx: current position in RX buffer to be written
 347 * @rx_end: end position in RX buffer to be written
 348 * @read: the type of read currently going on
 349 * @write: the type of write currently going on
 350 * @exp_fifo_level: expected FIFO level
 351 * @rx_lev_trig: receive FIFO watermark level which triggers IRQ
 352 * @tx_lev_trig: transmit FIFO watermark level which triggers IRQ
 353 * @dma_rx_channel: optional channel for RX DMA
 354 * @dma_tx_channel: optional channel for TX DMA
 355 * @sgt_rx: scattertable for the RX transfer
 356 * @sgt_tx: scattertable for the TX transfer
 357 * @dummypage: a dummy page used for driving data on the bus with DMA
 358 * @dma_running: indicates whether DMA is in operation
 359 * @cur_cs: current chip select index
 360 */
 361struct pl022 {
 362	struct amba_device		*adev;
 363	struct vendor_data		*vendor;
 364	resource_size_t			phybase;
 365	void __iomem			*virtbase;
 366	struct clk			*clk;
 367	struct spi_controller		*host;
 368	struct pl022_ssp_controller	*host_info;
 369	struct spi_transfer		*cur_transfer;
 370	struct chip_data		*cur_chip;
 371	void				*tx;
 372	void				*tx_end;
 373	void				*rx;
 374	void				*rx_end;
 375	enum ssp_reading		read;
 376	enum ssp_writing		write;
 377	u32				exp_fifo_level;
 378	enum ssp_rx_level_trig		rx_lev_trig;
 379	enum ssp_tx_level_trig		tx_lev_trig;
 380	/* DMA settings */
 381#ifdef CONFIG_DMA_ENGINE
 382	struct dma_chan			*dma_rx_channel;
 383	struct dma_chan			*dma_tx_channel;
 384	struct sg_table			sgt_rx;
 385	struct sg_table			sgt_tx;
 386	char				*dummypage;
 387	bool				dma_running;
 388#endif
 389	int cur_cs;
 390};
 391
 392/**
 393 * struct chip_data - To maintain runtime state of SSP for each client chip
 394 * @cr0: Value of control register CR0 of SSP - on later ST variants this
 395 *       register is 32 bits wide rather than just 16
 396 * @cr1: Value of control register CR1 of SSP
 397 * @dmacr: Value of DMA control Register of SSP
 398 * @cpsr: Value of Clock prescale register
 399 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
 400 * @enable_dma: Whether to enable DMA or not
 401 * @read: function ptr to be used to read when doing xfer for this chip
 402 * @write: function ptr to be used to write when doing xfer for this chip
 403 * @xfer_type: polling/interrupt/DMA
 404 *
 405 * Runtime state of the SSP controller, maintained per chip,
 406 * This would be set according to the current message that would be served
 407 */
 408struct chip_data {
 409	u32 cr0;
 410	u16 cr1;
 411	u16 dmacr;
 412	u16 cpsr;
 413	u8 n_bytes;
 414	bool enable_dma;
 415	enum ssp_reading read;
 416	enum ssp_writing write;
 417	int xfer_type;
 418};
 419
 420/**
 421 * internal_cs_control - Control chip select signals via SSP_CSR.
 422 * @pl022: SSP driver private data structure
 423 * @enable: select/delect the chip
 424 *
 425 * Used on controller with internal chip select control via SSP_CSR register
 426 * (vendor extension). Each of the 5 LSB in the register controls one chip
 427 * select signal.
 428 */
 429static void internal_cs_control(struct pl022 *pl022, bool enable)
 430{
 431	u32 tmp;
 432
 433	tmp = readw(SSP_CSR(pl022->virtbase));
 434	if (enable)
 435		tmp &= ~BIT(pl022->cur_cs);
 436	else
 437		tmp |= BIT(pl022->cur_cs);
 438	writew(tmp, SSP_CSR(pl022->virtbase));
 439}
 440
 441static void pl022_cs_control(struct spi_device *spi, bool enable)
 442{
 443	struct pl022 *pl022 = spi_controller_get_devdata(spi->controller);
 444	if (pl022->vendor->internal_cs_ctrl)
 445		internal_cs_control(pl022, enable);
 446}
 447
 448/**
 449 * flush - flush the FIFO to reach a clean state
 450 * @pl022: SSP driver private data structure
 451 */
 452static int flush(struct pl022 *pl022)
 453{
 454	unsigned long limit = loops_per_jiffy << 1;
 455
 456	dev_dbg(&pl022->adev->dev, "flush\n");
 457	do {
 458		while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 459			readw(SSP_DR(pl022->virtbase));
 460	} while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
 461
 462	pl022->exp_fifo_level = 0;
 463
 464	return limit;
 465}
 466
 467/**
 468 * restore_state - Load configuration of current chip
 469 * @pl022: SSP driver private data structure
 470 */
 471static void restore_state(struct pl022 *pl022)
 472{
 473	struct chip_data *chip = pl022->cur_chip;
 474
 475	if (pl022->vendor->extended_cr)
 476		writel(chip->cr0, SSP_CR0(pl022->virtbase));
 477	else
 478		writew(chip->cr0, SSP_CR0(pl022->virtbase));
 479	writew(chip->cr1, SSP_CR1(pl022->virtbase));
 480	writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
 481	writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
 482	writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
 483	writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 484}
 485
 486/*
 487 * Default SSP Register Values
 488 */
 489#define DEFAULT_SSP_REG_CR0 ( \
 490	GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0)	| \
 491	GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
 492	GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 493	GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 494	GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
 495)
 496
 497/* ST versions have slightly different bit layout */
 498#define DEFAULT_SSP_REG_CR0_ST ( \
 499	GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0)	| \
 500	GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
 501	GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 502	GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 503	GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
 504	GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16)	| \
 505	GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
 506)
 507
 508/* The PL023 version is slightly different again */
 509#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
 510	GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0)	| \
 511	GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
 512	GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
 513	GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
 514)
 515
 516#define DEFAULT_SSP_REG_CR1 ( \
 517	GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
 518	GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
 519	GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
 520	GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
 521)
 522
 523/* ST versions extend this register to use all 16 bits */
 524#define DEFAULT_SSP_REG_CR1_ST ( \
 525	DEFAULT_SSP_REG_CR1 | \
 526	GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
 527	GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
 528	GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
 529	GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
 530	GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
 531)
 532
 533/*
 534 * The PL023 variant has further differences: no loopback mode, no microwire
 535 * support, and a new clock feedback delay setting.
 536 */
 537#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
 538	GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
 539	GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
 540	GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
 541	GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
 542	GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
 543	GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
 544	GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
 545	GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
 546)
 547
 548#define DEFAULT_SSP_REG_CPSR ( \
 549	GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
 550)
 551
 552#define DEFAULT_SSP_REG_DMACR (\
 553	GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
 554	GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
 555)
 556
 557/**
 558 * load_ssp_default_config - Load default configuration for SSP
 559 * @pl022: SSP driver private data structure
 560 */
 561static void load_ssp_default_config(struct pl022 *pl022)
 562{
 563	if (pl022->vendor->pl023) {
 564		writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
 565		writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
 566	} else if (pl022->vendor->extended_cr) {
 567		writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
 568		writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
 569	} else {
 570		writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
 571		writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
 572	}
 573	writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
 574	writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
 575	writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
 576	writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
 577}
 578
 579/*
 580 * This will write to TX and read from RX according to the parameters
 581 * set in pl022.
 582 */
 583static void readwriter(struct pl022 *pl022)
 584{
 585
 586	/*
 587	 * The FIFO depth is different between primecell variants.
 588	 * I believe filling in too much in the FIFO might cause
 589	 * errons in 8bit wide transfers on ARM variants (just 8 words
 590	 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
 591	 *
 592	 * To prevent this issue, the TX FIFO is only filled to the
 593	 * unused RX FIFO fill length, regardless of what the TX
 594	 * FIFO status flag indicates.
 595	 */
 596	dev_dbg(&pl022->adev->dev,
 597		"%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
 598		__func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
 599
 600	/* Read as much as you can */
 601	while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 602	       && (pl022->rx < pl022->rx_end)) {
 603		switch (pl022->read) {
 604		case READING_NULL:
 605			readw(SSP_DR(pl022->virtbase));
 606			break;
 607		case READING_U8:
 608			*(u8 *) (pl022->rx) =
 609				readw(SSP_DR(pl022->virtbase)) & 0xFFU;
 610			break;
 611		case READING_U16:
 612			*(u16 *) (pl022->rx) =
 613				(u16) readw(SSP_DR(pl022->virtbase));
 614			break;
 615		case READING_U32:
 616			*(u32 *) (pl022->rx) =
 617				readl(SSP_DR(pl022->virtbase));
 618			break;
 619		}
 620		pl022->rx += (pl022->cur_chip->n_bytes);
 621		pl022->exp_fifo_level--;
 622	}
 623	/*
 624	 * Write as much as possible up to the RX FIFO size
 625	 */
 626	while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
 627	       && (pl022->tx < pl022->tx_end)) {
 628		switch (pl022->write) {
 629		case WRITING_NULL:
 630			writew(0x0, SSP_DR(pl022->virtbase));
 631			break;
 632		case WRITING_U8:
 633			writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
 634			break;
 635		case WRITING_U16:
 636			writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
 637			break;
 638		case WRITING_U32:
 639			writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
 640			break;
 641		}
 642		pl022->tx += (pl022->cur_chip->n_bytes);
 643		pl022->exp_fifo_level++;
 644		/*
 645		 * This inner reader takes care of things appearing in the RX
 646		 * FIFO as we're transmitting. This will happen a lot since the
 647		 * clock starts running when you put things into the TX FIFO,
 648		 * and then things are continuously clocked into the RX FIFO.
 649		 */
 650		while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
 651		       && (pl022->rx < pl022->rx_end)) {
 652			switch (pl022->read) {
 653			case READING_NULL:
 654				readw(SSP_DR(pl022->virtbase));
 655				break;
 656			case READING_U8:
 657				*(u8 *) (pl022->rx) =
 658					readw(SSP_DR(pl022->virtbase)) & 0xFFU;
 659				break;
 660			case READING_U16:
 661				*(u16 *) (pl022->rx) =
 662					(u16) readw(SSP_DR(pl022->virtbase));
 663				break;
 664			case READING_U32:
 665				*(u32 *) (pl022->rx) =
 666					readl(SSP_DR(pl022->virtbase));
 667				break;
 668			}
 669			pl022->rx += (pl022->cur_chip->n_bytes);
 670			pl022->exp_fifo_level--;
 671		}
 672	}
 673	/*
 674	 * When we exit here the TX FIFO should be full and the RX FIFO
 675	 * should be empty
 676	 */
 677}
 678
 679/*
 680 * This DMA functionality is only compiled in if we have
 681 * access to the generic DMA devices/DMA engine.
 682 */
 683#ifdef CONFIG_DMA_ENGINE
 684static void unmap_free_dma_scatter(struct pl022 *pl022)
 685{
 686	/* Unmap and free the SG tables */
 687	dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
 688		     pl022->sgt_tx.nents, DMA_TO_DEVICE);
 689	dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
 690		     pl022->sgt_rx.nents, DMA_FROM_DEVICE);
 691	sg_free_table(&pl022->sgt_rx);
 692	sg_free_table(&pl022->sgt_tx);
 693}
 694
 695static void dma_callback(void *data)
 696{
 697	struct pl022 *pl022 = data;
 698
 699	BUG_ON(!pl022->sgt_rx.sgl);
 700
 701#ifdef VERBOSE_DEBUG
 702	/*
 703	 * Optionally dump out buffers to inspect contents, this is
 704	 * good if you want to convince yourself that the loopback
 705	 * read/write contents are the same, when adopting to a new
 706	 * DMA engine.
 707	 */
 708	{
 709		struct scatterlist *sg;
 710		unsigned int i;
 711
 712		dma_sync_sg_for_cpu(&pl022->adev->dev,
 713				    pl022->sgt_rx.sgl,
 714				    pl022->sgt_rx.nents,
 715				    DMA_FROM_DEVICE);
 716
 717		for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
 718			dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
 719			print_hex_dump(KERN_ERR, "SPI RX: ",
 720				       DUMP_PREFIX_OFFSET,
 721				       16,
 722				       1,
 723				       sg_virt(sg),
 724				       sg_dma_len(sg),
 725				       1);
 726		}
 727		for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
 728			dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
 729			print_hex_dump(KERN_ERR, "SPI TX: ",
 730				       DUMP_PREFIX_OFFSET,
 731				       16,
 732				       1,
 733				       sg_virt(sg),
 734				       sg_dma_len(sg),
 735				       1);
 736		}
 737	}
 738#endif
 739
 740	unmap_free_dma_scatter(pl022);
 741
 742	spi_finalize_current_transfer(pl022->host);
 743}
 744
 745static void setup_dma_scatter(struct pl022 *pl022,
 746			      void *buffer,
 747			      unsigned int length,
 748			      struct sg_table *sgtab)
 749{
 750	struct scatterlist *sg;
 751	int bytesleft = length;
 752	void *bufp = buffer;
 753	int mapbytes;
 754	int i;
 755
 756	if (buffer) {
 757		for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
 758			/*
 759			 * If there are less bytes left than what fits
 760			 * in the current page (plus page alignment offset)
 761			 * we just feed in this, else we stuff in as much
 762			 * as we can.
 763			 */
 764			mapbytes = min_t(int, bytesleft,
 765					 PAGE_SIZE - offset_in_page(bufp));
 766
 767			sg_set_page(sg, virt_to_page(bufp),
 768				    mapbytes, offset_in_page(bufp));
 769			bufp += mapbytes;
 770			bytesleft -= mapbytes;
 771			dev_dbg(&pl022->adev->dev,
 772				"set RX/TX target page @ %p, %d bytes, %d left\n",
 773				bufp, mapbytes, bytesleft);
 774		}
 775	} else {
 776		/* Map the dummy buffer on every page */
 777		for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
 778			mapbytes = min_t(int, bytesleft, PAGE_SIZE);
 779			sg_set_page(sg, virt_to_page(pl022->dummypage),
 780				    mapbytes, 0);
 781			bytesleft -= mapbytes;
 782			dev_dbg(&pl022->adev->dev,
 783				"set RX/TX to dummy page %d bytes, %d left\n",
 784				mapbytes, bytesleft);
 785
 786		}
 787	}
 788	BUG_ON(bytesleft);
 789}
 790
 791/**
 792 * configure_dma - configures the channels for the next transfer
 793 * @pl022: SSP driver's private data structure
 794 */
 795static int configure_dma(struct pl022 *pl022)
 796{
 797	struct dma_slave_config rx_conf = {
 798		.src_addr = SSP_DR(pl022->phybase),
 799		.direction = DMA_DEV_TO_MEM,
 800		.device_fc = false,
 801	};
 802	struct dma_slave_config tx_conf = {
 803		.dst_addr = SSP_DR(pl022->phybase),
 804		.direction = DMA_MEM_TO_DEV,
 805		.device_fc = false,
 806	};
 807	unsigned int pages;
 808	int ret;
 809	int rx_sglen, tx_sglen;
 810	struct dma_chan *rxchan = pl022->dma_rx_channel;
 811	struct dma_chan *txchan = pl022->dma_tx_channel;
 812	struct dma_async_tx_descriptor *rxdesc;
 813	struct dma_async_tx_descriptor *txdesc;
 814
 815	/* Check that the channels are available */
 816	if (!rxchan || !txchan)
 817		return -ENODEV;
 818
 819	/*
 820	 * If supplied, the DMA burstsize should equal the FIFO trigger level.
 821	 * Notice that the DMA engine uses one-to-one mapping. Since we can
 822	 * not trigger on 2 elements this needs explicit mapping rather than
 823	 * calculation.
 824	 */
 825	switch (pl022->rx_lev_trig) {
 826	case SSP_RX_1_OR_MORE_ELEM:
 827		rx_conf.src_maxburst = 1;
 828		break;
 829	case SSP_RX_4_OR_MORE_ELEM:
 830		rx_conf.src_maxburst = 4;
 831		break;
 832	case SSP_RX_8_OR_MORE_ELEM:
 833		rx_conf.src_maxburst = 8;
 834		break;
 835	case SSP_RX_16_OR_MORE_ELEM:
 836		rx_conf.src_maxburst = 16;
 837		break;
 838	case SSP_RX_32_OR_MORE_ELEM:
 839		rx_conf.src_maxburst = 32;
 840		break;
 841	default:
 842		rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
 843		break;
 844	}
 845
 846	switch (pl022->tx_lev_trig) {
 847	case SSP_TX_1_OR_MORE_EMPTY_LOC:
 848		tx_conf.dst_maxburst = 1;
 849		break;
 850	case SSP_TX_4_OR_MORE_EMPTY_LOC:
 851		tx_conf.dst_maxburst = 4;
 852		break;
 853	case SSP_TX_8_OR_MORE_EMPTY_LOC:
 854		tx_conf.dst_maxburst = 8;
 855		break;
 856	case SSP_TX_16_OR_MORE_EMPTY_LOC:
 857		tx_conf.dst_maxburst = 16;
 858		break;
 859	case SSP_TX_32_OR_MORE_EMPTY_LOC:
 860		tx_conf.dst_maxburst = 32;
 861		break;
 862	default:
 863		tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
 864		break;
 865	}
 866
 867	switch (pl022->read) {
 868	case READING_NULL:
 869		/* Use the same as for writing */
 870		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 871		break;
 872	case READING_U8:
 873		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 874		break;
 875	case READING_U16:
 876		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 877		break;
 878	case READING_U32:
 879		rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 880		break;
 881	}
 882
 883	switch (pl022->write) {
 884	case WRITING_NULL:
 885		/* Use the same as for reading */
 886		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
 887		break;
 888	case WRITING_U8:
 889		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 890		break;
 891	case WRITING_U16:
 892		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 893		break;
 894	case WRITING_U32:
 895		tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 896		break;
 897	}
 898
 899	/* SPI peculiarity: we need to read and write the same width */
 900	if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
 901		rx_conf.src_addr_width = tx_conf.dst_addr_width;
 902	if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
 903		tx_conf.dst_addr_width = rx_conf.src_addr_width;
 904	BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
 905
 906	dmaengine_slave_config(rxchan, &rx_conf);
 907	dmaengine_slave_config(txchan, &tx_conf);
 908
 909	/* Create sglists for the transfers */
 910	pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
 911	dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
 912
 913	ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
 914	if (ret)
 915		goto err_alloc_rx_sg;
 916
 917	ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
 918	if (ret)
 919		goto err_alloc_tx_sg;
 920
 921	/* Fill in the scatterlists for the RX+TX buffers */
 922	setup_dma_scatter(pl022, pl022->rx,
 923			  pl022->cur_transfer->len, &pl022->sgt_rx);
 924	setup_dma_scatter(pl022, pl022->tx,
 925			  pl022->cur_transfer->len, &pl022->sgt_tx);
 926
 927	/* Map DMA buffers */
 928	rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
 929			   pl022->sgt_rx.nents, DMA_FROM_DEVICE);
 930	if (!rx_sglen)
 931		goto err_rx_sgmap;
 932
 933	tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
 934			   pl022->sgt_tx.nents, DMA_TO_DEVICE);
 935	if (!tx_sglen)
 936		goto err_tx_sgmap;
 937
 938	/* Send both scatterlists */
 939	rxdesc = dmaengine_prep_slave_sg(rxchan,
 940				      pl022->sgt_rx.sgl,
 941				      rx_sglen,
 942				      DMA_DEV_TO_MEM,
 943				      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 944	if (!rxdesc)
 945		goto err_rxdesc;
 946
 947	txdesc = dmaengine_prep_slave_sg(txchan,
 948				      pl022->sgt_tx.sgl,
 949				      tx_sglen,
 950				      DMA_MEM_TO_DEV,
 951				      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 952	if (!txdesc)
 953		goto err_txdesc;
 954
 955	/* Put the callback on the RX transfer only, that should finish last */
 956	rxdesc->callback = dma_callback;
 957	rxdesc->callback_param = pl022;
 958
 959	/* Submit and fire RX and TX with TX last so we're ready to read! */
 960	dmaengine_submit(rxdesc);
 961	dmaengine_submit(txdesc);
 962	dma_async_issue_pending(rxchan);
 963	dma_async_issue_pending(txchan);
 964	pl022->dma_running = true;
 965
 966	return 0;
 967
 968err_txdesc:
 969	dmaengine_terminate_all(txchan);
 970err_rxdesc:
 971	dmaengine_terminate_all(rxchan);
 972	dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
 973		     pl022->sgt_tx.nents, DMA_TO_DEVICE);
 974err_tx_sgmap:
 975	dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
 976		     pl022->sgt_rx.nents, DMA_FROM_DEVICE);
 977err_rx_sgmap:
 978	sg_free_table(&pl022->sgt_tx);
 979err_alloc_tx_sg:
 980	sg_free_table(&pl022->sgt_rx);
 981err_alloc_rx_sg:
 982	return -ENOMEM;
 983}
 984
 985static int pl022_dma_probe(struct pl022 *pl022)
 986{
 987	dma_cap_mask_t mask;
 988
 989	/* Try to acquire a generic DMA engine slave channel */
 990	dma_cap_zero(mask);
 991	dma_cap_set(DMA_SLAVE, mask);
 992	/*
 993	 * We need both RX and TX channels to do DMA, else do none
 994	 * of them.
 995	 */
 996	pl022->dma_rx_channel = dma_request_channel(mask,
 997					    pl022->host_info->dma_filter,
 998					    pl022->host_info->dma_rx_param);
 999	if (!pl022->dma_rx_channel) {
1000		dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1001		goto err_no_rxchan;
1002	}
1003
1004	pl022->dma_tx_channel = dma_request_channel(mask,
1005					    pl022->host_info->dma_filter,
1006					    pl022->host_info->dma_tx_param);
1007	if (!pl022->dma_tx_channel) {
1008		dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1009		goto err_no_txchan;
1010	}
1011
1012	pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1013	if (!pl022->dummypage)
1014		goto err_no_dummypage;
1015
1016	dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1017		 dma_chan_name(pl022->dma_rx_channel),
1018		 dma_chan_name(pl022->dma_tx_channel));
1019
1020	return 0;
1021
1022err_no_dummypage:
1023	dma_release_channel(pl022->dma_tx_channel);
1024err_no_txchan:
1025	dma_release_channel(pl022->dma_rx_channel);
1026	pl022->dma_rx_channel = NULL;
1027err_no_rxchan:
1028	dev_err(&pl022->adev->dev,
1029			"Failed to work in dma mode, work without dma!\n");
1030	return -ENODEV;
1031}
1032
1033static int pl022_dma_autoprobe(struct pl022 *pl022)
1034{
1035	struct device *dev = &pl022->adev->dev;
1036	struct dma_chan *chan;
1037	int err;
1038
1039	/* automatically configure DMA channels from platform, normally using DT */
1040	chan = dma_request_chan(dev, "rx");
1041	if (IS_ERR(chan)) {
1042		err = PTR_ERR(chan);
1043		goto err_no_rxchan;
1044	}
1045
1046	pl022->dma_rx_channel = chan;
1047
1048	chan = dma_request_chan(dev, "tx");
1049	if (IS_ERR(chan)) {
1050		err = PTR_ERR(chan);
1051		goto err_no_txchan;
1052	}
1053
1054	pl022->dma_tx_channel = chan;
1055
1056	pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1057	if (!pl022->dummypage) {
1058		err = -ENOMEM;
1059		goto err_no_dummypage;
1060	}
1061
1062	return 0;
1063
1064err_no_dummypage:
1065	dma_release_channel(pl022->dma_tx_channel);
1066	pl022->dma_tx_channel = NULL;
1067err_no_txchan:
1068	dma_release_channel(pl022->dma_rx_channel);
1069	pl022->dma_rx_channel = NULL;
1070err_no_rxchan:
1071	return err;
1072}
1073
1074static void terminate_dma(struct pl022 *pl022)
1075{
1076	if (!pl022->dma_running)
1077		return;
1078
1079	struct dma_chan *rxchan = pl022->dma_rx_channel;
1080	struct dma_chan *txchan = pl022->dma_tx_channel;
1081
1082	dmaengine_terminate_all(rxchan);
1083	dmaengine_terminate_all(txchan);
1084	unmap_free_dma_scatter(pl022);
1085	pl022->dma_running = false;
1086}
1087
1088static void pl022_dma_remove(struct pl022 *pl022)
1089{
1090	terminate_dma(pl022);
1091	if (pl022->dma_tx_channel)
1092		dma_release_channel(pl022->dma_tx_channel);
1093	if (pl022->dma_rx_channel)
1094		dma_release_channel(pl022->dma_rx_channel);
1095	kfree(pl022->dummypage);
1096}
1097
1098#else
1099static inline int configure_dma(struct pl022 *pl022)
1100{
1101	return -ENODEV;
1102}
1103
1104static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1105{
1106	return 0;
1107}
1108
1109static inline int pl022_dma_probe(struct pl022 *pl022)
1110{
1111	return 0;
1112}
1113
1114static inline void terminate_dma(struct pl022 *pl022)
1115{
1116}
1117
1118static inline void pl022_dma_remove(struct pl022 *pl022)
1119{
1120}
1121#endif
1122
1123/**
1124 * pl022_interrupt_handler - Interrupt handler for SSP controller
1125 * @irq: IRQ number
1126 * @dev_id: Local device data
1127 *
1128 * This function handles interrupts generated for an interrupt based transfer.
1129 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1130 * current message's state as STATE_ERROR and schedule the tasklet
1131 * pump_transfers which will do the postprocessing of the current message by
1132 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1133 * more data, and writes data in TX FIFO till it is not full. If we complete
1134 * the transfer we move to the next transfer and schedule the tasklet.
1135 */
1136static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1137{
1138	struct pl022 *pl022 = dev_id;
1139	u16 irq_status = 0;
1140	/* Read the Interrupt Status Register */
1141	irq_status = readw(SSP_MIS(pl022->virtbase));
1142
1143	if (unlikely(!irq_status))
1144		return IRQ_NONE;
1145
1146	/*
1147	 * This handles the FIFO interrupts, the timeout
1148	 * interrupts are flatly ignored, they cannot be
1149	 * trusted.
1150	 */
1151	if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1152		/*
1153		 * Overrun interrupt - bail out since our Data has been
1154		 * corrupted
1155		 */
1156		dev_err(&pl022->adev->dev, "FIFO overrun\n");
1157		if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1158			dev_err(&pl022->adev->dev,
1159				"RXFIFO is full\n");
1160
1161		/*
1162		 * Disable and clear interrupts, disable SSP,
1163		 * mark message with bad status so it can be
1164		 * retried.
1165		 */
1166		writew(DISABLE_ALL_INTERRUPTS,
1167		       SSP_IMSC(pl022->virtbase));
1168		writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1169		writew((readw(SSP_CR1(pl022->virtbase)) &
1170			(~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1171		pl022->cur_transfer->error |= SPI_TRANS_FAIL_IO;
1172		spi_finalize_current_transfer(pl022->host);
1173		return IRQ_HANDLED;
1174	}
1175
1176	readwriter(pl022);
1177
1178	if (pl022->tx == pl022->tx_end) {
1179		/* Disable Transmit interrupt, enable receive interrupt */
1180		writew((readw(SSP_IMSC(pl022->virtbase)) &
1181		       ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
1182		       SSP_IMSC(pl022->virtbase));
1183	}
1184
1185	/*
1186	 * Since all transactions must write as much as shall be read,
1187	 * we can conclude the entire transaction once RX is complete.
1188	 * At this point, all TX will always be finished.
1189	 */
1190	if (pl022->rx >= pl022->rx_end) {
1191		writew(DISABLE_ALL_INTERRUPTS,
1192		       SSP_IMSC(pl022->virtbase));
1193		writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1194		if (unlikely(pl022->rx > pl022->rx_end)) {
1195			dev_warn(&pl022->adev->dev, "read %u surplus "
1196				 "bytes (did you request an odd "
1197				 "number of bytes on a 16bit bus?)\n",
1198				 (u32) (pl022->rx - pl022->rx_end));
1199		}
1200		spi_finalize_current_transfer(pl022->host);
1201		return IRQ_HANDLED;
1202	}
1203
1204	return IRQ_HANDLED;
1205}
1206
1207/*
1208 * This sets up the pointers to memory for the next message to
1209 * send out on the SPI bus.
1210 */
1211static int set_up_next_transfer(struct pl022 *pl022,
1212				struct spi_transfer *transfer)
1213{
1214	int residue;
1215
1216	/* Sanity check the message for this bus width */
1217	residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1218	if (unlikely(residue != 0)) {
1219		dev_err(&pl022->adev->dev,
1220			"message of %u bytes to transmit but the current "
1221			"chip bus has a data width of %u bytes!\n",
1222			pl022->cur_transfer->len,
1223			pl022->cur_chip->n_bytes);
1224		dev_err(&pl022->adev->dev, "skipping this message\n");
1225		return -EIO;
1226	}
1227	pl022->tx = (void *)transfer->tx_buf;
1228	pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1229	pl022->rx = (void *)transfer->rx_buf;
1230	pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1231	pl022->write =
1232	    pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1233	pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1234	return 0;
1235}
1236
1237static int do_interrupt_dma_transfer(struct pl022 *pl022)
1238{
1239	int ret;
1240
1241	/*
1242	 * Default is to enable all interrupts except RX -
1243	 * this will be enabled once TX is complete
1244	 */
1245	u32 irqflags = (u32)(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM);
1246
1247	ret = set_up_next_transfer(pl022, pl022->cur_transfer);
1248	if (ret)
1249		return ret;
1250
1251	/* If we're using DMA, set up DMA here */
1252	if (pl022->cur_chip->enable_dma) {
1253		/* Configure DMA transfer */
1254		if (configure_dma(pl022)) {
1255			dev_dbg(&pl022->adev->dev,
1256				"configuration of DMA failed, fall back to interrupt mode\n");
1257			goto err_config_dma;
1258		}
1259		/* Disable interrupts in DMA mode, IRQ from DMA controller */
1260		irqflags = DISABLE_ALL_INTERRUPTS;
1261	}
1262err_config_dma:
1263	/* Enable SSP, turn on interrupts */
1264	writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1265	       SSP_CR1(pl022->virtbase));
1266	writew(irqflags, SSP_IMSC(pl022->virtbase));
1267	return 1;
1268}
1269
1270static void print_current_status(struct pl022 *pl022)
1271{
1272	u32 read_cr0;
1273	u16 read_cr1, read_dmacr, read_sr;
1274
1275	if (pl022->vendor->extended_cr)
1276		read_cr0 = readl(SSP_CR0(pl022->virtbase));
1277	else
1278		read_cr0 = readw(SSP_CR0(pl022->virtbase));
1279	read_cr1 = readw(SSP_CR1(pl022->virtbase));
1280	read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1281	read_sr = readw(SSP_SR(pl022->virtbase));
1282
1283	dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
1284	dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
1285	dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
1286	dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
1287	dev_warn(&pl022->adev->dev,
1288			"spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
1289			pl022->exp_fifo_level,
1290			pl022->vendor->fifodepth);
1291
1292}
1293
1294static int do_polling_transfer(struct pl022 *pl022)
1295{
1296	int ret;
1297	unsigned long time, timeout;
1298
1299	/* Configuration Changing Per Transfer */
1300	ret = set_up_next_transfer(pl022, pl022->cur_transfer);
1301	if (ret)
1302		return ret;
1303	/* Flush FIFOs and enable SSP */
1304	flush(pl022);
1305	writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1306		SSP_CR1(pl022->virtbase));
1307
1308	dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1309
1310	timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1311	while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1312		time = jiffies;
1313		readwriter(pl022);
1314		if (time_after(time, timeout)) {
1315			dev_warn(&pl022->adev->dev,
1316			"%s: timeout!\n", __func__);
1317			print_current_status(pl022);
1318			return -ETIMEDOUT;
1319		}
1320		cpu_relax();
1321	}
1322
1323	return 0;
1324}
1325
1326static int pl022_transfer_one(struct spi_controller *host, struct spi_device *spi,
1327			      struct spi_transfer *transfer)
1328{
1329	struct pl022 *pl022 = spi_controller_get_devdata(host);
1330
1331	pl022->cur_transfer = transfer;
1332
1333	/* Setup the SPI using the per chip configuration */
1334	pl022->cur_chip = spi_get_ctldata(spi);
1335	pl022->cur_cs = spi_get_chipselect(spi, 0);
1336
1337	restore_state(pl022);
1338	flush(pl022);
1339
1340	if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1341		return do_polling_transfer(pl022);
1342	else
1343		return do_interrupt_dma_transfer(pl022);
1344}
1345
1346static void pl022_handle_err(struct spi_controller *ctlr, struct spi_message *message)
1347{
1348	struct pl022 *pl022 = spi_controller_get_devdata(ctlr);
1349
1350	terminate_dma(pl022);
1351	writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1352	writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1353}
1354
1355static int pl022_unprepare_transfer_hardware(struct spi_controller *host)
1356{
1357	struct pl022 *pl022 = spi_controller_get_devdata(host);
1358
1359	/* nothing more to do - disable spi/ssp and power off */
1360	writew((readw(SSP_CR1(pl022->virtbase)) &
1361		(~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1362
1363	return 0;
1364}
1365
1366static int verify_controller_parameters(struct pl022 *pl022,
1367				struct pl022_config_chip const *chip_info)
1368{
1369	if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1370	    || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1371		dev_err(&pl022->adev->dev,
1372			"interface is configured incorrectly\n");
1373		return -EINVAL;
1374	}
1375	if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1376	    (!pl022->vendor->unidir)) {
1377		dev_err(&pl022->adev->dev,
1378			"unidirectional mode not supported in this "
1379			"hardware version\n");
1380		return -EINVAL;
1381	}
1382	if ((chip_info->hierarchy != SSP_MASTER)
1383	    && (chip_info->hierarchy != SSP_SLAVE)) {
1384		dev_err(&pl022->adev->dev,
1385			"hierarchy is configured incorrectly\n");
1386		return -EINVAL;
1387	}
1388	if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1389	    && (chip_info->com_mode != DMA_TRANSFER)
1390	    && (chip_info->com_mode != POLLING_TRANSFER)) {
1391		dev_err(&pl022->adev->dev,
1392			"Communication mode is configured incorrectly\n");
1393		return -EINVAL;
1394	}
1395	switch (chip_info->rx_lev_trig) {
1396	case SSP_RX_1_OR_MORE_ELEM:
1397	case SSP_RX_4_OR_MORE_ELEM:
1398	case SSP_RX_8_OR_MORE_ELEM:
1399		/* These are always OK, all variants can handle this */
1400		break;
1401	case SSP_RX_16_OR_MORE_ELEM:
1402		if (pl022->vendor->fifodepth < 16) {
1403			dev_err(&pl022->adev->dev,
1404			"RX FIFO Trigger Level is configured incorrectly\n");
1405			return -EINVAL;
1406		}
1407		break;
1408	case SSP_RX_32_OR_MORE_ELEM:
1409		if (pl022->vendor->fifodepth < 32) {
1410			dev_err(&pl022->adev->dev,
1411			"RX FIFO Trigger Level is configured incorrectly\n");
1412			return -EINVAL;
1413		}
1414		break;
1415	default:
1416		dev_err(&pl022->adev->dev,
1417			"RX FIFO Trigger Level is configured incorrectly\n");
1418		return -EINVAL;
1419	}
1420	switch (chip_info->tx_lev_trig) {
1421	case SSP_TX_1_OR_MORE_EMPTY_LOC:
1422	case SSP_TX_4_OR_MORE_EMPTY_LOC:
1423	case SSP_TX_8_OR_MORE_EMPTY_LOC:
1424		/* These are always OK, all variants can handle this */
1425		break;
1426	case SSP_TX_16_OR_MORE_EMPTY_LOC:
1427		if (pl022->vendor->fifodepth < 16) {
1428			dev_err(&pl022->adev->dev,
1429			"TX FIFO Trigger Level is configured incorrectly\n");
1430			return -EINVAL;
1431		}
1432		break;
1433	case SSP_TX_32_OR_MORE_EMPTY_LOC:
1434		if (pl022->vendor->fifodepth < 32) {
1435			dev_err(&pl022->adev->dev,
1436			"TX FIFO Trigger Level is configured incorrectly\n");
1437			return -EINVAL;
1438		}
1439		break;
1440	default:
1441		dev_err(&pl022->adev->dev,
1442			"TX FIFO Trigger Level is configured incorrectly\n");
1443		return -EINVAL;
1444	}
1445	if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1446		if ((chip_info->ctrl_len < SSP_BITS_4)
1447		    || (chip_info->ctrl_len > SSP_BITS_32)) {
1448			dev_err(&pl022->adev->dev,
1449				"CTRL LEN is configured incorrectly\n");
1450			return -EINVAL;
1451		}
1452		if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1453		    && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1454			dev_err(&pl022->adev->dev,
1455				"Wait State is configured incorrectly\n");
1456			return -EINVAL;
1457		}
1458		/* Half duplex is only available in the ST Micro version */
1459		if (pl022->vendor->extended_cr) {
1460			if ((chip_info->duplex !=
1461			     SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1462			    && (chip_info->duplex !=
1463				SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1464				dev_err(&pl022->adev->dev,
1465					"Microwire duplex mode is configured incorrectly\n");
1466				return -EINVAL;
1467			}
1468		} else {
1469			if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) {
1470				dev_err(&pl022->adev->dev,
1471					"Microwire half duplex mode requested,"
1472					" but this is only available in the"
1473					" ST version of PL022\n");
1474				return -EINVAL;
1475			}
1476		}
1477	}
1478	return 0;
1479}
1480
1481static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1482{
1483	return rate / (cpsdvsr * (1 + scr));
1484}
1485
1486static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1487				    ssp_clock_params * clk_freq)
1488{
1489	/* Lets calculate the frequency parameters */
1490	u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1491	u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1492		best_scr = 0, tmp, found = 0;
1493
1494	rate = clk_get_rate(pl022->clk);
1495	/* cpsdvscr = 2 & scr 0 */
1496	max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
1497	/* cpsdvsr = 254 & scr = 255 */
1498	min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
1499
1500	if (freq > max_tclk)
1501		dev_warn(&pl022->adev->dev,
1502			"Max speed that can be programmed is %d Hz, you requested %d\n",
1503			max_tclk, freq);
1504
1505	if (freq < min_tclk) {
1506		dev_err(&pl022->adev->dev,
1507			"Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1508			freq, min_tclk);
1509		return -EINVAL;
1510	}
1511
1512	/*
1513	 * best_freq will give closest possible available rate (<= requested
1514	 * freq) for all values of scr & cpsdvsr.
1515	 */
1516	while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1517		while (scr <= SCR_MAX) {
1518			tmp = spi_rate(rate, cpsdvsr, scr);
1519
1520			if (tmp > freq) {
1521				/* we need lower freq */
1522				scr++;
1523				continue;
1524			}
1525
1526			/*
1527			 * If found exact value, mark found and break.
1528			 * If found more closer value, update and break.
1529			 */
1530			if (tmp > best_freq) {
1531				best_freq = tmp;
1532				best_cpsdvsr = cpsdvsr;
1533				best_scr = scr;
1534
1535				if (tmp == freq)
1536					found = 1;
1537			}
1538			/*
1539			 * increased scr will give lower rates, which are not
1540			 * required
1541			 */
1542			break;
1543		}
1544		cpsdvsr += 2;
1545		scr = SCR_MIN;
1546	}
1547
1548	WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1549			freq);
1550
1551	clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1552	clk_freq->scr = (u8) (best_scr & 0xFF);
1553	dev_dbg(&pl022->adev->dev,
1554		"SSP Target Frequency is: %u, Effective Frequency is %u\n",
1555		freq, best_freq);
1556	dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1557		clk_freq->cpsdvsr, clk_freq->scr);
1558
1559	return 0;
1560}
1561
1562/*
1563 * A piece of default chip info unless the platform
1564 * supplies it.
1565 */
1566static const struct pl022_config_chip pl022_default_chip_info = {
1567	.com_mode = INTERRUPT_TRANSFER,
1568	.iface = SSP_INTERFACE_MOTOROLA_SPI,
1569	.hierarchy = SSP_MASTER,
1570	.slave_tx_disable = DO_NOT_DRIVE_TX,
1571	.rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1572	.tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1573	.ctrl_len = SSP_BITS_8,
1574	.wait_state = SSP_MWIRE_WAIT_ZERO,
1575	.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1576};
1577
1578/**
1579 * pl022_setup - setup function registered to SPI host framework
1580 * @spi: spi device which is requesting setup
1581 *
1582 * This function is registered to the SPI framework for this SPI host
1583 * controller. If it is the first time when setup is called by this device,
1584 * this function will initialize the runtime state for this chip and save
1585 * the same in the device structure. Else it will update the runtime info
1586 * with the updated chip info. Nothing is really being written to the
1587 * controller hardware here, that is not done until the actual transfer
1588 * commence.
1589 */
1590static int pl022_setup(struct spi_device *spi)
1591{
1592	struct pl022_config_chip const *chip_info;
1593	struct pl022_config_chip chip_info_dt;
1594	struct chip_data *chip;
1595	struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
1596	int status = 0;
1597	struct pl022 *pl022 = spi_controller_get_devdata(spi->controller);
1598	unsigned int bits = spi->bits_per_word;
1599	u32 tmp;
1600	struct device_node *np = spi->dev.of_node;
1601
1602	if (!spi->max_speed_hz)
1603		return -EINVAL;
1604
1605	/* Get controller_state if one is supplied */
1606	chip = spi_get_ctldata(spi);
1607
1608	if (chip == NULL) {
1609		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1610		if (!chip)
1611			return -ENOMEM;
1612		dev_dbg(&spi->dev,
1613			"allocated memory for controller's runtime state\n");
1614	}
1615
1616	/* Get controller data if one is supplied */
1617	chip_info = spi->controller_data;
1618
1619	if (chip_info == NULL) {
1620		if (np) {
1621			chip_info_dt = pl022_default_chip_info;
1622
1623			chip_info_dt.hierarchy = SSP_MASTER;
1624			of_property_read_u32(np, "pl022,interface",
1625				&chip_info_dt.iface);
1626			of_property_read_u32(np, "pl022,com-mode",
1627				&chip_info_dt.com_mode);
1628			of_property_read_u32(np, "pl022,rx-level-trig",
1629				&chip_info_dt.rx_lev_trig);
1630			of_property_read_u32(np, "pl022,tx-level-trig",
1631				&chip_info_dt.tx_lev_trig);
1632			of_property_read_u32(np, "pl022,ctrl-len",
1633				&chip_info_dt.ctrl_len);
1634			of_property_read_u32(np, "pl022,wait-state",
1635				&chip_info_dt.wait_state);
1636			of_property_read_u32(np, "pl022,duplex",
1637				&chip_info_dt.duplex);
1638
1639			chip_info = &chip_info_dt;
1640		} else {
1641			chip_info = &pl022_default_chip_info;
1642			/* spi_board_info.controller_data not is supplied */
1643			dev_dbg(&spi->dev,
1644				"using default controller_data settings\n");
1645		}
1646	} else
1647		dev_dbg(&spi->dev,
1648			"using user supplied controller_data settings\n");
1649
1650	/*
1651	 * We can override with custom divisors, else we use the board
1652	 * frequency setting
1653	 */
1654	if ((0 == chip_info->clk_freq.cpsdvsr)
1655	    && (0 == chip_info->clk_freq.scr)) {
1656		status = calculate_effective_freq(pl022,
1657						  spi->max_speed_hz,
1658						  &clk_freq);
1659		if (status < 0)
1660			goto err_config_params;
1661	} else {
1662		memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1663		if ((clk_freq.cpsdvsr % 2) != 0)
1664			clk_freq.cpsdvsr =
1665				clk_freq.cpsdvsr - 1;
1666	}
1667	if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1668	    || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
1669		status = -EINVAL;
1670		dev_err(&spi->dev,
1671			"cpsdvsr is configured incorrectly\n");
1672		goto err_config_params;
1673	}
1674
1675	status = verify_controller_parameters(pl022, chip_info);
1676	if (status) {
1677		dev_err(&spi->dev, "controller data is incorrect");
1678		goto err_config_params;
1679	}
1680
1681	pl022->rx_lev_trig = chip_info->rx_lev_trig;
1682	pl022->tx_lev_trig = chip_info->tx_lev_trig;
1683
1684	/* Now set controller state based on controller data */
1685	chip->xfer_type = chip_info->com_mode;
1686
1687	/* Check bits per word with vendor specific range */
1688	if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1689		status = -ENOTSUPP;
1690		dev_err(&spi->dev, "illegal data size for this controller!\n");
1691		dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1692				pl022->vendor->max_bpw);
1693		goto err_config_params;
1694	} else if (bits <= 8) {
1695		dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
1696		chip->n_bytes = 1;
1697		chip->read = READING_U8;
1698		chip->write = WRITING_U8;
1699	} else if (bits <= 16) {
1700		dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1701		chip->n_bytes = 2;
1702		chip->read = READING_U16;
1703		chip->write = WRITING_U16;
1704	} else {
1705		dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1706		chip->n_bytes = 4;
1707		chip->read = READING_U32;
1708		chip->write = WRITING_U32;
1709	}
1710
1711	/* Now Initialize all register settings required for this chip */
1712	chip->cr0 = 0;
1713	chip->cr1 = 0;
1714	chip->dmacr = 0;
1715	chip->cpsr = 0;
1716	if ((chip_info->com_mode == DMA_TRANSFER)
1717	    && ((pl022->host_info)->enable_dma)) {
1718		chip->enable_dma = true;
1719		dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1720		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1721			       SSP_DMACR_MASK_RXDMAE, 0);
1722		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1723			       SSP_DMACR_MASK_TXDMAE, 1);
1724	} else {
1725		chip->enable_dma = false;
1726		dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1727		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1728			       SSP_DMACR_MASK_RXDMAE, 0);
1729		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1730			       SSP_DMACR_MASK_TXDMAE, 1);
1731	}
1732
1733	chip->cpsr = clk_freq.cpsdvsr;
1734
1735	/* Special setup for the ST micro extended control registers */
1736	if (pl022->vendor->extended_cr) {
1737		u32 etx;
1738
1739		if (pl022->vendor->pl023) {
1740			/* These bits are only in the PL023 */
1741			SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1742				       SSP_CR1_MASK_FBCLKDEL_ST, 13);
1743		} else {
1744			/* These bits are in the PL022 but not PL023 */
1745			SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1746				       SSP_CR0_MASK_HALFDUP_ST, 5);
1747			SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1748				       SSP_CR0_MASK_CSS_ST, 16);
1749			SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1750				       SSP_CR0_MASK_FRF_ST, 21);
1751			SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1752				       SSP_CR1_MASK_MWAIT_ST, 6);
1753		}
1754		SSP_WRITE_BITS(chip->cr0, bits - 1,
1755			       SSP_CR0_MASK_DSS_ST, 0);
1756
1757		if (spi->mode & SPI_LSB_FIRST) {
1758			tmp = SSP_RX_LSB;
1759			etx = SSP_TX_LSB;
1760		} else {
1761			tmp = SSP_RX_MSB;
1762			etx = SSP_TX_MSB;
1763		}
1764		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1765		SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
1766		SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1767			       SSP_CR1_MASK_RXIFLSEL_ST, 7);
1768		SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1769			       SSP_CR1_MASK_TXIFLSEL_ST, 10);
1770	} else {
1771		SSP_WRITE_BITS(chip->cr0, bits - 1,
1772			       SSP_CR0_MASK_DSS, 0);
1773		SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1774			       SSP_CR0_MASK_FRF, 4);
1775	}
1776
1777	/* Stuff that is common for all versions */
1778	if (spi->mode & SPI_CPOL)
1779		tmp = SSP_CLK_POL_IDLE_HIGH;
1780	else
1781		tmp = SSP_CLK_POL_IDLE_LOW;
1782	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1783
1784	if (spi->mode & SPI_CPHA)
1785		tmp = SSP_CLK_SECOND_EDGE;
1786	else
1787		tmp = SSP_CLK_FIRST_EDGE;
1788	SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
1789
1790	SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
1791	/* Loopback is available on all versions except PL023 */
1792	if (pl022->vendor->loopback) {
1793		if (spi->mode & SPI_LOOP)
1794			tmp = LOOPBACK_ENABLED;
1795		else
1796			tmp = LOOPBACK_DISABLED;
1797		SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
1798	}
1799	SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
1800	SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
1801	SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
1802		3);
1803
1804	/* Save controller_state */
1805	spi_set_ctldata(spi, chip);
1806	return status;
1807 err_config_params:
1808	spi_set_ctldata(spi, NULL);
1809	kfree(chip);
1810	return status;
1811}
1812
1813/**
1814 * pl022_cleanup - cleanup function registered to SPI host framework
1815 * @spi: spi device which is requesting cleanup
1816 *
1817 * This function is registered to the SPI framework for this SPI host
1818 * controller. It will free the runtime state of chip.
1819 */
1820static void pl022_cleanup(struct spi_device *spi)
1821{
1822	struct chip_data *chip = spi_get_ctldata(spi);
1823
1824	spi_set_ctldata(spi, NULL);
1825	kfree(chip);
1826}
1827
1828static struct pl022_ssp_controller *
1829pl022_platform_data_dt_get(struct device *dev)
1830{
1831	struct device_node *np = dev->of_node;
1832	struct pl022_ssp_controller *pd;
1833
1834	if (!np) {
1835		dev_err(dev, "no dt node defined\n");
1836		return NULL;
1837	}
1838
1839	pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
1840	if (!pd)
1841		return NULL;
1842
1843	pd->bus_id = -1;
1844	of_property_read_u32(np, "pl022,autosuspend-delay",
1845			     &pd->autosuspend_delay);
1846	pd->rt = of_property_read_bool(np, "pl022,rt");
1847
1848	return pd;
1849}
1850
1851static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
1852{
1853	struct device *dev = &adev->dev;
1854	struct pl022_ssp_controller *platform_info =
1855			dev_get_platdata(&adev->dev);
1856	struct spi_controller *host;
1857	struct pl022 *pl022 = NULL;	/*Data for this driver */
1858	int status = 0;
1859
1860	dev_info(&adev->dev,
1861		 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
1862	if (!platform_info && IS_ENABLED(CONFIG_OF))
1863		platform_info = pl022_platform_data_dt_get(dev);
1864
1865	if (!platform_info) {
1866		dev_err(dev, "probe: no platform data defined\n");
1867		return -ENODEV;
1868	}
1869
1870	/* Allocate host with space for data */
1871	host = spi_alloc_host(dev, sizeof(struct pl022));
1872	if (host == NULL) {
1873		dev_err(&adev->dev, "probe - cannot alloc SPI host\n");
1874		return -ENOMEM;
1875	}
1876
1877	pl022 = spi_controller_get_devdata(host);
1878	pl022->host = host;
1879	pl022->host_info = platform_info;
1880	pl022->adev = adev;
1881	pl022->vendor = id->data;
1882
1883	/*
1884	 * Bus Number Which has been Assigned to this SSP controller
1885	 * on this board
1886	 */
1887	host->bus_num = platform_info->bus_id;
1888	host->cleanup = pl022_cleanup;
1889	host->setup = pl022_setup;
1890	host->auto_runtime_pm = true;
1891	host->transfer_one = pl022_transfer_one;
1892	host->set_cs = pl022_cs_control;
1893	host->handle_err = pl022_handle_err;
1894	host->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
1895	host->rt = platform_info->rt;
1896	host->dev.of_node = dev->of_node;
1897	host->use_gpio_descriptors = true;
1898
1899	/*
1900	 * Supports mode 0-3, loopback, and active low CS. Transfers are
1901	 * always MS bit first on the original pl022.
1902	 */
1903	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1904	if (pl022->vendor->extended_cr)
1905		host->mode_bits |= SPI_LSB_FIRST;
1906
1907	dev_dbg(&adev->dev, "BUSNO: %d\n", host->bus_num);
1908
1909	status = amba_request_regions(adev, NULL);
1910	if (status)
1911		goto err_no_ioregion;
1912
1913	pl022->phybase = adev->res.start;
1914	pl022->virtbase = devm_ioremap(dev, adev->res.start,
1915				       resource_size(&adev->res));
1916	if (pl022->virtbase == NULL) {
1917		status = -ENOMEM;
1918		goto err_no_ioremap;
1919	}
1920	dev_info(&adev->dev, "mapped registers from %pa to %p\n",
1921		&adev->res.start, pl022->virtbase);
1922
1923	pl022->clk = devm_clk_get_enabled(&adev->dev, NULL);
1924	if (IS_ERR(pl022->clk)) {
1925		status = PTR_ERR(pl022->clk);
1926		dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
1927		goto err_no_clk;
1928	}
1929
1930	/* Disable SSP */
1931	writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
1932	       SSP_CR1(pl022->virtbase));
1933	load_ssp_default_config(pl022);
1934
1935	status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
1936				  0, "pl022", pl022);
1937	if (status < 0) {
1938		dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
1939		goto err_no_irq;
1940	}
1941
1942	/* Get DMA channels, try autoconfiguration first */
1943	status = pl022_dma_autoprobe(pl022);
1944	if (status == -EPROBE_DEFER) {
1945		dev_dbg(dev, "deferring probe to get DMA channel\n");
1946		goto err_no_irq;
1947	}
1948
1949	/* If that failed, use channels from platform_info */
1950	if (status == 0)
1951		platform_info->enable_dma = 1;
1952	else if (platform_info->enable_dma) {
1953		status = pl022_dma_probe(pl022);
1954		if (status != 0)
1955			platform_info->enable_dma = 0;
1956	}
1957
1958	/* Register with the SPI framework */
1959	amba_set_drvdata(adev, pl022);
1960	status = devm_spi_register_controller(&adev->dev, host);
1961	if (status != 0) {
1962		dev_err_probe(&adev->dev, status,
1963			      "problem registering spi host\n");
1964		goto err_spi_register;
1965	}
1966	dev_dbg(dev, "probe succeeded\n");
1967
1968	/* let runtime pm put suspend */
1969	if (platform_info->autosuspend_delay > 0) {
1970		dev_info(&adev->dev,
1971			"will use autosuspend for runtime pm, delay %dms\n",
1972			platform_info->autosuspend_delay);
1973		pm_runtime_set_autosuspend_delay(dev,
1974			platform_info->autosuspend_delay);
1975		pm_runtime_use_autosuspend(dev);
1976	}
1977	pm_runtime_put(dev);
1978
1979	return 0;
1980
1981 err_spi_register:
1982	if (platform_info->enable_dma)
1983		pl022_dma_remove(pl022);
1984 err_no_irq:
1985 err_no_clk:
1986 err_no_ioremap:
1987	amba_release_regions(adev);
1988 err_no_ioregion:
1989	spi_controller_put(host);
1990	return status;
1991}
1992
1993static void
1994pl022_remove(struct amba_device *adev)
1995{
1996	struct pl022 *pl022 = amba_get_drvdata(adev);
1997
1998	if (!pl022)
1999		return;
2000
2001	/*
2002	 * undo pm_runtime_put() in probe.  I assume that we're not
2003	 * accessing the primecell here.
2004	 */
2005	pm_runtime_get_noresume(&adev->dev);
2006
2007	load_ssp_default_config(pl022);
2008	if (pl022->host_info->enable_dma)
2009		pl022_dma_remove(pl022);
2010
2011	amba_release_regions(adev);
2012}
2013
2014#ifdef CONFIG_PM_SLEEP
2015static int pl022_suspend(struct device *dev)
2016{
2017	struct pl022 *pl022 = dev_get_drvdata(dev);
2018	int ret;
2019
2020	ret = spi_controller_suspend(pl022->host);
2021	if (ret)
2022		return ret;
2023
2024	ret = pm_runtime_force_suspend(dev);
2025	if (ret) {
2026		spi_controller_resume(pl022->host);
2027		return ret;
2028	}
2029
2030	pinctrl_pm_select_sleep_state(dev);
2031
2032	dev_dbg(dev, "suspended\n");
2033	return 0;
2034}
2035
2036static int pl022_resume(struct device *dev)
2037{
2038	struct pl022 *pl022 = dev_get_drvdata(dev);
2039	int ret;
2040
2041	ret = pm_runtime_force_resume(dev);
2042	if (ret)
2043		dev_err(dev, "problem resuming\n");
2044
2045	/* Start the queue running */
2046	ret = spi_controller_resume(pl022->host);
2047	if (!ret)
2048		dev_dbg(dev, "resumed\n");
2049
2050	return ret;
2051}
2052#endif
2053
2054#ifdef CONFIG_PM
2055static int pl022_runtime_suspend(struct device *dev)
2056{
2057	struct pl022 *pl022 = dev_get_drvdata(dev);
2058
2059	clk_disable_unprepare(pl022->clk);
2060	pinctrl_pm_select_idle_state(dev);
2061
2062	return 0;
2063}
2064
2065static int pl022_runtime_resume(struct device *dev)
2066{
2067	struct pl022 *pl022 = dev_get_drvdata(dev);
2068
2069	pinctrl_pm_select_default_state(dev);
2070	clk_prepare_enable(pl022->clk);
2071
2072	return 0;
2073}
2074#endif
2075
2076static const struct dev_pm_ops pl022_dev_pm_ops = {
2077	SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2078	SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2079};
2080
2081static struct vendor_data vendor_arm = {
2082	.fifodepth = 8,
2083	.max_bpw = 16,
2084	.unidir = false,
2085	.extended_cr = false,
2086	.pl023 = false,
2087	.loopback = true,
2088	.internal_cs_ctrl = false,
2089};
2090
2091static struct vendor_data vendor_st = {
2092	.fifodepth = 32,
2093	.max_bpw = 32,
2094	.unidir = false,
2095	.extended_cr = true,
2096	.pl023 = false,
2097	.loopback = true,
2098	.internal_cs_ctrl = false,
2099};
2100
2101static struct vendor_data vendor_st_pl023 = {
2102	.fifodepth = 32,
2103	.max_bpw = 32,
2104	.unidir = false,
2105	.extended_cr = true,
2106	.pl023 = true,
2107	.loopback = false,
2108	.internal_cs_ctrl = false,
2109};
2110
2111static struct vendor_data vendor_lsi = {
2112	.fifodepth = 8,
2113	.max_bpw = 16,
2114	.unidir = false,
2115	.extended_cr = false,
2116	.pl023 = false,
2117	.loopback = true,
2118	.internal_cs_ctrl = true,
2119};
2120
2121static const struct amba_id pl022_ids[] = {
2122	{
2123		/*
2124		 * ARM PL022 variant, this has a 16bit wide
2125		 * and 8 locations deep TX/RX FIFO
2126		 */
2127		.id	= 0x00041022,
2128		.mask	= 0x000fffff,
2129		.data	= &vendor_arm,
2130	},
2131	{
2132		/*
2133		 * ST Micro derivative, this has 32bit wide
2134		 * and 32 locations deep TX/RX FIFO
2135		 */
2136		.id	= 0x01080022,
2137		.mask	= 0xffffffff,
2138		.data	= &vendor_st,
2139	},
2140	{
2141		/*
2142		 * ST-Ericsson derivative "PL023" (this is not
2143		 * an official ARM number), this is a PL022 SSP block
2144		 * stripped to SPI mode only, it has 32bit wide
2145		 * and 32 locations deep TX/RX FIFO but no extended
2146		 * CR0/CR1 register
2147		 */
2148		.id	= 0x00080023,
2149		.mask	= 0xffffffff,
2150		.data	= &vendor_st_pl023,
2151	},
2152	{
2153		/*
2154		 * PL022 variant that has a chip select control register whih
2155		 * allows control of 5 output signals nCS[0:4].
2156		 */
2157		.id	= 0x000b6022,
2158		.mask	= 0x000fffff,
2159		.data	= &vendor_lsi,
2160	},
2161	{ 0, 0 },
2162};
2163
2164MODULE_DEVICE_TABLE(amba, pl022_ids);
2165
2166static struct amba_driver pl022_driver = {
2167	.drv = {
2168		.name	= "ssp-pl022",
2169		.pm	= &pl022_dev_pm_ops,
2170	},
2171	.id_table	= pl022_ids,
2172	.probe		= pl022_probe,
2173	.remove		= pl022_remove,
2174};
2175
2176static int __init pl022_init(void)
2177{
2178	return amba_driver_register(&pl022_driver);
2179}
2180subsys_initcall(pl022_init);
2181
2182static void __exit pl022_exit(void)
2183{
2184	amba_driver_unregister(&pl022_driver);
2185}
2186module_exit(pl022_exit);
2187
2188MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2189MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2190MODULE_LICENSE("GPL");