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spi-pci1xxxx.c
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linux-6.19.14/drivers/spi/spi-pci1xxxx.c
1// SPDX-License-Identifier: GPL-2.0 2// PCI1xxxx SPI driver 3// Copyright (C) 2022 Microchip Technology Inc. 4// Authors: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> 5// Kumaravel Thiagarajan <Kumaravel.Thiagarajan@microchip.com> 6 7 8#include <linux/bitfield.h> 9#include <linux/delay.h> 10#include <linux/dma-mapping.h> 11#include <linux/iopoll.h> 12#include <linux/irq.h> 13#include <linux/module.h> 14#include <linux/msi.h> 15#include <linux/pci_regs.h> 16#include <linux/pci.h> 17#include <linux/spinlock.h> 18#include <linux/spi/spi.h> 19#include "internals.h" 20 21#define DRV_NAME "spi-pci1xxxx" 22 23#define SYS_FREQ_DEFAULT (62500000) 24 25#define PCI1XXXX_SPI_MAX_CLOCK_HZ (30000000) 26#define PCI1XXXX_SPI_CLK_25MHZ (25000000) 27#define PCI1XXXX_SPI_CLK_20MHZ (20000000) 28#define PCI1XXXX_SPI_CLK_15MHZ (15000000) 29#define PCI1XXXX_SPI_CLK_12MHZ (12000000) 30#define PCI1XXXX_SPI_CLK_10MHZ (10000000) 31#define PCI1XXXX_SPI_MIN_CLOCK_HZ (2000000) 32 33#define PCI1XXXX_SPI_BUFFER_SIZE (320) 34 35#define SPI_MST_CTL_DEVSEL_MASK (GENMASK(27, 25)) 36#define SPI_MST_CTL_CMD_LEN_MASK (GENMASK(16, 8)) 37#define SPI_MST_CTL_SPEED_MASK (GENMASK(7, 5)) 38#define SPI_MSI_VECTOR_SEL_MASK (GENMASK(4, 4)) 39 40#define SPI_MST_CTL_FORCE_CE (BIT(4)) 41#define SPI_MST_CTL_MODE_SEL (BIT(2)) 42#define SPI_MST_CTL_GO (BIT(0)) 43 44#define SPI_PERI_ADDR_BASE (0x160000) 45#define SPI_SYSTEM_ADDR_BASE (0x2000) 46#define SPI_MST1_ADDR_BASE (0x800) 47 48#define DEV_REV_REG (SPI_SYSTEM_ADDR_BASE + 0x00) 49#define SPI_SYSLOCK_REG (SPI_SYSTEM_ADDR_BASE + 0xA0) 50#define SPI_CONFIG_PERI_ENABLE_REG (SPI_SYSTEM_ADDR_BASE + 0x108) 51 52#define SPI_PERI_ENBLE_PF_MASK (GENMASK(17, 16)) 53#define DEV_REV_MASK (GENMASK(7, 0)) 54 55#define SPI_SYSLOCK BIT(4) 56#define SPI0 (0) 57#define SPI1 (1) 58 59/* DMA Related Registers */ 60#define SPI_DMA_ADDR_BASE (0x1000) 61#define SPI_DMA_GLOBAL_WR_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x0C) 62#define SPI_DMA_WR_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x10) 63#define SPI_DMA_GLOBAL_RD_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x2C) 64#define SPI_DMA_RD_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x30) 65#define SPI_DMA_INTR_WR_STS (SPI_DMA_ADDR_BASE + 0x4C) 66#define SPI_DMA_WR_INT_MASK (SPI_DMA_ADDR_BASE + 0x54) 67#define SPI_DMA_INTR_WR_CLR (SPI_DMA_ADDR_BASE + 0x58) 68#define SPI_DMA_ERR_WR_STS (SPI_DMA_ADDR_BASE + 0x5C) 69#define SPI_DMA_INTR_IMWR_WDONE_LOW (SPI_DMA_ADDR_BASE + 0x60) 70#define SPI_DMA_INTR_IMWR_WDONE_HIGH (SPI_DMA_ADDR_BASE + 0x64) 71#define SPI_DMA_INTR_IMWR_WABORT_LOW (SPI_DMA_ADDR_BASE + 0x68) 72#define SPI_DMA_INTR_IMWR_WABORT_HIGH (SPI_DMA_ADDR_BASE + 0x6C) 73#define SPI_DMA_INTR_WR_IMWR_DATA (SPI_DMA_ADDR_BASE + 0x70) 74#define SPI_DMA_INTR_RD_STS (SPI_DMA_ADDR_BASE + 0xA0) 75#define SPI_DMA_RD_INT_MASK (SPI_DMA_ADDR_BASE + 0xA8) 76#define SPI_DMA_INTR_RD_CLR (SPI_DMA_ADDR_BASE + 0xAC) 77#define SPI_DMA_ERR_RD_STS (SPI_DMA_ADDR_BASE + 0xB8) 78#define SPI_DMA_INTR_IMWR_RDONE_LOW (SPI_DMA_ADDR_BASE + 0xCC) 79#define SPI_DMA_INTR_IMWR_RDONE_HIGH (SPI_DMA_ADDR_BASE + 0xD0) 80#define SPI_DMA_INTR_IMWR_RABORT_LOW (SPI_DMA_ADDR_BASE + 0xD4) 81#define SPI_DMA_INTR_IMWR_RABORT_HIGH (SPI_DMA_ADDR_BASE + 0xD8) 82#define SPI_DMA_INTR_RD_IMWR_DATA (SPI_DMA_ADDR_BASE + 0xDC) 83 84#define SPI_DMA_CH0_WR_BASE (SPI_DMA_ADDR_BASE + 0x200) 85#define SPI_DMA_CH0_RD_BASE (SPI_DMA_ADDR_BASE + 0x300) 86#define SPI_DMA_CH1_WR_BASE (SPI_DMA_ADDR_BASE + 0x400) 87#define SPI_DMA_CH1_RD_BASE (SPI_DMA_ADDR_BASE + 0x500) 88 89#define SPI_DMA_CH_CTL1_OFFSET (0x00) 90#define SPI_DMA_CH_XFER_LEN_OFFSET (0x08) 91#define SPI_DMA_CH_SAR_LO_OFFSET (0x0C) 92#define SPI_DMA_CH_SAR_HI_OFFSET (0x10) 93#define SPI_DMA_CH_DAR_LO_OFFSET (0x14) 94#define SPI_DMA_CH_DAR_HI_OFFSET (0x18) 95 96#define SPI_DMA_CH0_DONE_INT BIT(0) 97#define SPI_DMA_CH1_DONE_INT BIT(1) 98#define SPI_DMA_CH0_ABORT_INT BIT(16) 99#define SPI_DMA_CH1_ABORT_INT BIT(17) 100#define SPI_DMA_DONE_INT_MASK(x) (1 << (x)) 101#define SPI_DMA_ABORT_INT_MASK(x) (1 << (16 + (x))) 102#define DMA_CH_CONTROL_LIE BIT(3) 103#define DMA_CH_CONTROL_RIE BIT(4) 104#define DMA_INTR_EN (DMA_CH_CONTROL_RIE | DMA_CH_CONTROL_LIE) 105 106/* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */ 107 108#define SPI_MST_CMD_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x00) 109#define SPI_MST_RSP_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x200) 110#define SPI_MST_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x400) 111#define SPI_MST_EVENT_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x420) 112#define SPI_MST_EVENT_MASK_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x424) 113#define SPI_MST_PAD_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x460) 114#define SPIALERT_MST_DB_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x464) 115#define SPIALERT_MST_VAL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x468) 116#define SPI_PCI_CTRL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x480) 117 118#define PCI1XXXX_IRQ_FLAGS (IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE) 119#define SPI_MAX_DATA_LEN 320 120 121#define PCI1XXXX_SPI_TIMEOUT (msecs_to_jiffies(100)) 122#define SYSLOCK_RETRY_CNT (1000) 123#define SPI_DMA_ENGINE_EN (0x1) 124#define SPI_DMA_ENGINE_DIS (0x0) 125 126#define SPI_INTR BIT(8) 127#define SPI_FORCE_CE BIT(4) 128 129#define SPI_CHIP_SEL_COUNT 7 130#define VENDOR_ID_MCHP 0x1055 131 132#define SPI_SUSPEND_CONFIG 0x101 133#define SPI_RESUME_CONFIG 0x203 134 135#define NUM_VEC_PER_INST 3 136 137struct pci1xxxx_spi_internal { 138 u8 hw_inst; 139 u8 clkdiv; 140 int irq[NUM_VEC_PER_INST]; 141 int mode; 142 bool spi_xfer_in_progress; 143 atomic_t dma_completion_count; 144 void *rx_buf; 145 bool dma_aborted_rd; 146 u32 bytes_recvd; 147 u32 tx_sgl_len; 148 u32 rx_sgl_len; 149 struct scatterlist *tx_sgl, *rx_sgl; 150 bool dma_aborted_wr; 151 struct completion spi_xfer_done; 152 struct spi_controller *spi_host; 153 struct pci1xxxx_spi *parent; 154 struct spi_transfer *xfer; 155 struct { 156 unsigned int dev_sel : 3; 157 unsigned int msi_vector_sel : 1; 158 } prev_val; 159}; 160 161struct pci1xxxx_spi { 162 struct pci_dev *dev; 163 u8 total_hw_instances; 164 u8 dev_rev; 165 void __iomem *reg_base; 166 void __iomem *dma_offset_bar; 167 /* lock to safely access the DMA RD registers in isr */ 168 spinlock_t dma_rd_reg_lock; 169 /* lock to safely access the DMA RD registers in isr */ 170 spinlock_t dma_wr_reg_lock; 171 bool can_dma; 172 struct pci1xxxx_spi_internal *spi_int[] __counted_by(total_hw_instances); 173}; 174 175static const struct pci_device_id pci1xxxx_spi_pci_id_table[] = { 176 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, 177 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, 178 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, 179 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01}, 180 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, 181 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, 182 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, 183 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01}, 184 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, 185 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, 186 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, 187 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01}, 188 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, 189 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, 190 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, 191 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01}, 192 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, 193 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, 194 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, 195 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01}, 196 { 0, } 197}; 198 199MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table); 200 201static irqreturn_t pci1xxxx_spi_isr_dma_rd(int irq, void *dev); 202static irqreturn_t pci1xxxx_spi_isr_dma_wr(int irq, void *dev); 203 204static int pci1xxxx_set_sys_lock(struct pci1xxxx_spi *par) 205{ 206 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG); 207 return readl(par->reg_base + SPI_SYSLOCK_REG); 208} 209 210static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_spi *par) 211{ 212 u32 regval; 213 214 return readx_poll_timeout(pci1xxxx_set_sys_lock, par, regval, 215 (regval & SPI_SYSLOCK), 100, 216 SYSLOCK_RETRY_CNT * 100); 217} 218 219static void pci1xxxx_release_sys_lock(struct pci1xxxx_spi *par) 220{ 221 writel(0x0, par->reg_base + SPI_SYSLOCK_REG); 222} 223 224static int pci1xxxx_check_spi_can_dma(struct pci1xxxx_spi *spi_bus, int hw_inst, int num_vector) 225{ 226 struct pci_dev *pdev = spi_bus->dev; 227 u32 pf_num; 228 u32 regval; 229 int ret; 230 231 if (num_vector != hw_inst * NUM_VEC_PER_INST) 232 return -EOPNOTSUPP; 233 234 /* 235 * DEV REV Registers is a system register, HW Syslock bit 236 * should be acquired before accessing the register 237 */ 238 ret = pci1xxxx_acquire_sys_lock(spi_bus); 239 if (ret) { 240 dev_err(&pdev->dev, "Error failed to acquire syslock\n"); 241 return ret; 242 } 243 244 regval = readl(spi_bus->reg_base + DEV_REV_REG); 245 spi_bus->dev_rev = regval & DEV_REV_MASK; 246 if (spi_bus->dev_rev >= 0xC0) { 247 regval = readl(spi_bus->reg_base + 248 SPI_CONFIG_PERI_ENABLE_REG); 249 pf_num = regval & SPI_PERI_ENBLE_PF_MASK; 250 } 251 252 pci1xxxx_release_sys_lock(spi_bus); 253 254 /* 255 * DMA is supported only from C0 and SPI can use DMA only if 256 * it is mapped to PF0 257 */ 258 if (spi_bus->dev_rev < 0xC0 || pf_num) 259 return -EOPNOTSUPP; 260 261 spi_bus->dma_offset_bar = pcim_iomap(pdev, 2, pci_resource_len(pdev, 2)); 262 if (!spi_bus->dma_offset_bar) { 263 dev_warn(&pdev->dev, "Error failed to map dma bar, will operate in PIO mode\n"); 264 return -EOPNOTSUPP; 265 } 266 267 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 268 dev_warn(&pdev->dev, "Error failed to set DMA mask, will operate in PIO mode\n"); 269 pcim_iounmap(pdev, spi_bus->dma_offset_bar); 270 spi_bus->dma_offset_bar = NULL; 271 return -EOPNOTSUPP; 272 } 273 274 return 0; 275} 276 277static void pci1xxxx_spi_dma_config(struct pci1xxxx_spi *spi_bus) 278{ 279 struct pci1xxxx_spi_internal *spi_sub_ptr; 280 u8 iter, irq_index; 281 struct msi_msg msi; 282 u32 regval; 283 u16 data; 284 285 irq_index = spi_bus->total_hw_instances; 286 for (iter = 0; iter < spi_bus->total_hw_instances; iter++) { 287 spi_sub_ptr = spi_bus->spi_int[iter]; 288 get_cached_msi_msg(spi_sub_ptr->irq[1], &msi); 289 if (iter == 0) { 290 writel(msi.address_hi, spi_bus->dma_offset_bar + 291 SPI_DMA_INTR_IMWR_WDONE_HIGH); 292 writel(msi.address_hi, spi_bus->dma_offset_bar + 293 SPI_DMA_INTR_IMWR_WABORT_HIGH); 294 writel(msi.address_hi, spi_bus->dma_offset_bar + 295 SPI_DMA_INTR_IMWR_RDONE_HIGH); 296 writel(msi.address_hi, spi_bus->dma_offset_bar + 297 SPI_DMA_INTR_IMWR_RABORT_HIGH); 298 writel(msi.address_lo, spi_bus->dma_offset_bar + 299 SPI_DMA_INTR_IMWR_WDONE_LOW); 300 writel(msi.address_lo, spi_bus->dma_offset_bar + 301 SPI_DMA_INTR_IMWR_WABORT_LOW); 302 writel(msi.address_lo, spi_bus->dma_offset_bar + 303 SPI_DMA_INTR_IMWR_RDONE_LOW); 304 writel(msi.address_lo, spi_bus->dma_offset_bar + 305 SPI_DMA_INTR_IMWR_RABORT_LOW); 306 writel(0, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA); 307 writel(0, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA); 308 } 309 regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA); 310 data = msi.data + irq_index; 311 writel((regval | (data << (iter * 16))), spi_bus->dma_offset_bar + 312 SPI_DMA_INTR_WR_IMWR_DATA); 313 regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA); 314 irq_index++; 315 316 data = msi.data + irq_index; 317 regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA); 318 writel(regval | (data << (iter * 16)), spi_bus->dma_offset_bar + 319 SPI_DMA_INTR_RD_IMWR_DATA); 320 regval = readl(spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA); 321 irq_index++; 322 } 323} 324 325static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int hw_inst, int num_vector) 326{ 327 struct pci1xxxx_spi_internal *spi_sub_ptr; 328 u8 iter, irq_index; 329 int ret; 330 331 irq_index = hw_inst; 332 ret = pci1xxxx_check_spi_can_dma(spi_bus, hw_inst, num_vector); 333 if (ret) 334 return ret; 335 336 spin_lock_init(&spi_bus->dma_rd_reg_lock); 337 spin_lock_init(&spi_bus->dma_wr_reg_lock); 338 writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN); 339 writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN); 340 341 for (iter = 0; iter < hw_inst; iter++) { 342 spi_sub_ptr = spi_bus->spi_int[iter]; 343 spi_sub_ptr->irq[1] = pci_irq_vector(spi_bus->dev, irq_index); 344 ret = devm_request_irq(&spi_bus->dev->dev, spi_sub_ptr->irq[1], 345 pci1xxxx_spi_isr_dma_wr, PCI1XXXX_IRQ_FLAGS, 346 pci_name(spi_bus->dev), spi_sub_ptr); 347 if (ret < 0) 348 return ret; 349 350 irq_index++; 351 352 spi_sub_ptr->irq[2] = pci_irq_vector(spi_bus->dev, irq_index); 353 ret = devm_request_irq(&spi_bus->dev->dev, spi_sub_ptr->irq[2], 354 pci1xxxx_spi_isr_dma_rd, PCI1XXXX_IRQ_FLAGS, 355 pci_name(spi_bus->dev), spi_sub_ptr); 356 if (ret < 0) 357 return ret; 358 359 irq_index++; 360 } 361 pci1xxxx_spi_dma_config(spi_bus); 362 dma_set_max_seg_size(&spi_bus->dev->dev, PCI1XXXX_SPI_BUFFER_SIZE); 363 spi_bus->can_dma = true; 364 return 0; 365} 366 367static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable) 368{ 369 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi->controller); 370 struct pci1xxxx_spi *par = p->parent; 371 u32 regval; 372 373 /* Set the DEV_SEL bits of the SPI_MST_CTL_REG */ 374 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); 375 if (!enable) { 376 regval |= SPI_FORCE_CE; 377 regval &= ~SPI_MST_CTL_DEVSEL_MASK; 378 regval |= (spi_get_chipselect(spi, 0) << 25); 379 } else { 380 regval &= ~SPI_FORCE_CE; 381 } 382 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); 383} 384 385static u8 pci1xxxx_get_clock_div(struct pci1xxxx_spi *par, u32 hz) 386{ 387 u8 val = 0; 388 389 if (hz >= PCI1XXXX_SPI_MAX_CLOCK_HZ) 390 val = 2; 391 else if (par->dev_rev >= 0xC0 && hz >= PCI1XXXX_SPI_CLK_25MHZ) 392 val = 1; 393 else if ((hz < PCI1XXXX_SPI_MAX_CLOCK_HZ) && (hz >= PCI1XXXX_SPI_CLK_20MHZ)) 394 val = 3; 395 else if ((hz < PCI1XXXX_SPI_CLK_20MHZ) && (hz >= PCI1XXXX_SPI_CLK_15MHZ)) 396 val = 4; 397 else if ((hz < PCI1XXXX_SPI_CLK_15MHZ) && (hz >= PCI1XXXX_SPI_CLK_12MHZ)) 398 val = 5; 399 else if ((hz < PCI1XXXX_SPI_CLK_12MHZ) && (hz >= PCI1XXXX_SPI_CLK_10MHZ)) 400 val = 6; 401 else if ((hz < PCI1XXXX_SPI_CLK_10MHZ) && (hz >= PCI1XXXX_SPI_MIN_CLOCK_HZ)) 402 val = 7; 403 else 404 val = 2; 405 406 return val; 407} 408 409static void pci1xxxx_spi_setup_dma_to_io(struct pci1xxxx_spi_internal *p, 410 dma_addr_t dma_addr, u32 len) 411{ 412 void __iomem *base; 413 414 if (!p->hw_inst) 415 base = p->parent->dma_offset_bar + SPI_DMA_CH0_RD_BASE; 416 else 417 base = p->parent->dma_offset_bar + SPI_DMA_CH1_RD_BASE; 418 419 writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET); 420 writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET); 421 writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_SAR_LO_OFFSET); 422 writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_SAR_HI_OFFSET); 423 /* Updated SPI Command Registers */ 424 writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)), 425 base + SPI_DMA_CH_DAR_LO_OFFSET); 426 writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)), 427 base + SPI_DMA_CH_DAR_HI_OFFSET); 428} 429 430static void pci1xxxx_spi_setup_dma_from_io(struct pci1xxxx_spi_internal *p, 431 dma_addr_t dma_addr, u32 len) 432{ 433 void *base; 434 435 if (!p->hw_inst) 436 base = p->parent->dma_offset_bar + SPI_DMA_CH0_WR_BASE; 437 else 438 base = p->parent->dma_offset_bar + SPI_DMA_CH1_WR_BASE; 439 440 writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET); 441 writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET); 442 writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_DAR_LO_OFFSET); 443 writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_DAR_HI_OFFSET); 444 writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)), 445 base + SPI_DMA_CH_SAR_LO_OFFSET); 446 writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)), 447 base + SPI_DMA_CH_SAR_HI_OFFSET); 448} 449 450static void pci1xxxx_spi_setup(struct pci1xxxx_spi *par, u8 hw_inst, u32 mode, 451 u8 clkdiv, u32 len) 452{ 453 u32 regval; 454 455 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); 456 regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK | 457 SPI_MST_CTL_SPEED_MASK); 458 459 if (mode == SPI_MODE_3) 460 regval |= SPI_MST_CTL_MODE_SEL; 461 462 regval |= FIELD_PREP(SPI_MST_CTL_CMD_LEN_MASK, len); 463 regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv); 464 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); 465} 466 467static void pci1xxxx_start_spi_xfer(struct pci1xxxx_spi_internal *p) 468{ 469 u32 regval; 470 471 atomic_set(&p->dma_completion_count, 0); 472 regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); 473 regval |= SPI_MST_CTL_GO; 474 writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); 475} 476 477static int pci1xxxx_spi_transfer_with_io(struct spi_controller *spi_ctlr, 478 struct spi_device *spi, struct spi_transfer *xfer) 479{ 480 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr); 481 struct pci1xxxx_spi *par = p->parent; 482 int len, loop_iter, transfer_len; 483 unsigned long bytes_transfered; 484 unsigned long bytes_recvd; 485 unsigned long loop_count; 486 u8 *rx_buf, result; 487 const u8 *tx_buf; 488 u32 regval; 489 u8 clkdiv; 490 491 p->spi_xfer_in_progress = true; 492 p->bytes_recvd = 0; 493 clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz); 494 tx_buf = xfer->tx_buf; 495 rx_buf = xfer->rx_buf; 496 transfer_len = xfer->len; 497 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 498 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 499 500 if (tx_buf) { 501 bytes_transfered = 0; 502 bytes_recvd = 0; 503 loop_count = transfer_len / SPI_MAX_DATA_LEN; 504 if (transfer_len % SPI_MAX_DATA_LEN != 0) 505 loop_count += 1; 506 507 for (loop_iter = 0; loop_iter < loop_count; loop_iter++) { 508 len = SPI_MAX_DATA_LEN; 509 if ((transfer_len % SPI_MAX_DATA_LEN != 0) && 510 (loop_iter == loop_count - 1)) 511 len = transfer_len % SPI_MAX_DATA_LEN; 512 513 reinit_completion(&p->spi_xfer_done); 514 memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst), 515 &tx_buf[bytes_transfered], len); 516 bytes_transfered += len; 517 pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len); 518 pci1xxxx_start_spi_xfer(p); 519 520 /* Wait for DMA_TERM interrupt */ 521 result = wait_for_completion_timeout(&p->spi_xfer_done, 522 PCI1XXXX_SPI_TIMEOUT); 523 if (!result) 524 return -ETIMEDOUT; 525 526 if (rx_buf) { 527 memcpy_fromio(&rx_buf[bytes_recvd], par->reg_base + 528 SPI_MST_RSP_BUF_OFFSET(p->hw_inst), len); 529 bytes_recvd += len; 530 } 531 } 532 } 533 p->spi_xfer_in_progress = false; 534 535 return 0; 536} 537 538static int pci1xxxx_spi_transfer_with_dma(struct spi_controller *spi_ctlr, 539 struct spi_device *spi, 540 struct spi_transfer *xfer) 541{ 542 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr); 543 struct pci1xxxx_spi *par = p->parent; 544 dma_addr_t tx_dma_addr = 0; 545 int ret = 0; 546 u32 regval; 547 548 p->spi_xfer_in_progress = true; 549 p->tx_sgl = xfer->tx_sg.sgl; 550 p->rx_sgl = xfer->rx_sg.sgl; 551 p->rx_buf = xfer->rx_buf; 552 atomic_set(&p->dma_completion_count, 1); 553 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 554 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 555 556 if (!xfer->tx_buf || !p->tx_sgl) { 557 ret = -EINVAL; 558 goto error; 559 } 560 p->xfer = xfer; 561 p->mode = spi->mode; 562 p->clkdiv = pci1xxxx_get_clock_div(par, xfer->speed_hz); 563 p->bytes_recvd = 0; 564 p->rx_buf = xfer->rx_buf; 565 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 566 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 567 568 tx_dma_addr = sg_dma_address(p->tx_sgl); 569 p->tx_sgl_len = sg_dma_len(p->tx_sgl); 570 pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); 571 pci1xxxx_spi_setup_dma_to_io(p, (tx_dma_addr), p->tx_sgl_len); 572 writel(p->hw_inst, par->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG); 573 574 reinit_completion(&p->spi_xfer_done); 575 /* Wait for DMA_TERM interrupt */ 576 ret = wait_for_completion_timeout(&p->spi_xfer_done, PCI1XXXX_SPI_TIMEOUT); 577 if (!ret) { 578 ret = -ETIMEDOUT; 579 if (p->dma_aborted_rd) { 580 writel(SPI_DMA_ENGINE_DIS, 581 par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN); 582 /* 583 * DMA ENGINE reset takes time if any TLP 584 * completeion in progress, should wait 585 * till DMA Engine reset is completed. 586 */ 587 ret = readl_poll_timeout(par->dma_offset_bar + 588 SPI_DMA_GLOBAL_RD_ENGINE_EN, regval, 589 (regval == 0x0), 0, USEC_PER_MSEC); 590 if (ret) { 591 ret = -ECANCELED; 592 goto error; 593 } 594 writel(SPI_DMA_ENGINE_EN, 595 par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN); 596 p->dma_aborted_rd = false; 597 ret = -ECANCELED; 598 } 599 if (p->dma_aborted_wr) { 600 writel(SPI_DMA_ENGINE_DIS, 601 par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN); 602 603 /* 604 * DMA ENGINE reset takes time if any TLP 605 * completeion in progress, should wait 606 * till DMA Engine reset is completed. 607 */ 608 ret = readl_poll_timeout(par->dma_offset_bar + 609 SPI_DMA_GLOBAL_WR_ENGINE_EN, regval, 610 (regval == 0x0), 0, USEC_PER_MSEC); 611 if (ret) { 612 ret = -ECANCELED; 613 goto error; 614 } 615 616 writel(SPI_DMA_ENGINE_EN, 617 par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN); 618 p->dma_aborted_wr = false; 619 ret = -ECANCELED; 620 } 621 goto error; 622 } 623 ret = 0; 624 625error: 626 p->spi_xfer_in_progress = false; 627 628 return ret; 629} 630 631static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr, 632 struct spi_device *spi, struct spi_transfer *xfer) 633{ 634 if (spi_xfer_is_dma_mapped(spi_ctlr, spi, xfer)) 635 return pci1xxxx_spi_transfer_with_dma(spi_ctlr, spi, xfer); 636 else 637 return pci1xxxx_spi_transfer_with_io(spi_ctlr, spi, xfer); 638} 639 640static irqreturn_t pci1xxxx_spi_isr_io(int irq, void *dev) 641{ 642 struct pci1xxxx_spi_internal *p = dev; 643 irqreturn_t spi_int_fired = IRQ_NONE; 644 u32 regval; 645 646 /* Clear the SPI GO_BIT Interrupt */ 647 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 648 if (regval & SPI_INTR) { 649 /* Clear xfer_done */ 650 if (p->parent->can_dma && p->rx_buf) 651 writel(p->hw_inst, p->parent->dma_offset_bar + 652 SPI_DMA_WR_DOORBELL_REG); 653 else 654 complete(&p->parent->spi_int[p->hw_inst]->spi_xfer_done); 655 spi_int_fired = IRQ_HANDLED; 656 } 657 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 658 return spi_int_fired; 659} 660 661static void pci1xxxx_spi_setup_next_dma_to_io_transfer(struct pci1xxxx_spi_internal *p) 662{ 663 dma_addr_t tx_dma_addr = 0; 664 u32 prev_len; 665 666 p->tx_sgl = sg_next(p->tx_sgl); 667 if (p->tx_sgl) { 668 tx_dma_addr = sg_dma_address(p->tx_sgl); 669 prev_len = p->tx_sgl_len; 670 p->tx_sgl_len = sg_dma_len(p->tx_sgl); 671 pci1xxxx_spi_setup_dma_to_io(p, tx_dma_addr, p->tx_sgl_len); 672 writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG); 673 if (prev_len != p->tx_sgl_len) 674 pci1xxxx_spi_setup(p->parent, 675 p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len); 676 } 677} 678 679static void pci1xxxx_spi_setup_next_dma_from_io_transfer(struct pci1xxxx_spi_internal *p) 680{ 681 dma_addr_t rx_dma_addr = 0; 682 683 if (p->rx_sgl) { 684 rx_dma_addr = sg_dma_address(p->rx_sgl); 685 p->rx_sgl_len = sg_dma_len(p->rx_sgl); 686 pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len); 687 writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG); 688 } 689} 690 691static irqreturn_t pci1xxxx_spi_isr_dma_rd(int irq, void *dev) 692{ 693 struct pci1xxxx_spi_internal *p = dev; 694 irqreturn_t spi_int_fired = IRQ_NONE; 695 unsigned long flags; 696 u32 regval; 697 698 /* Clear the DMA RD INT and start spi xfer*/ 699 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS); 700 if (regval) { 701 if (regval & SPI_DMA_DONE_INT_MASK(p->hw_inst)) { 702 /* Start the SPI transfer only if both DMA read and write are completed */ 703 if (atomic_inc_return(&p->dma_completion_count) == 2) 704 pci1xxxx_start_spi_xfer(p); 705 spi_int_fired = IRQ_HANDLED; 706 } 707 if (regval & SPI_DMA_ABORT_INT_MASK(p->hw_inst)) { 708 p->dma_aborted_rd = true; 709 spi_int_fired = IRQ_HANDLED; 710 } 711 spin_lock_irqsave(&p->parent->dma_rd_reg_lock, flags); 712 writel((SPI_DMA_DONE_INT_MASK(p->hw_inst) | SPI_DMA_ABORT_INT_MASK(p->hw_inst)), 713 p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR); 714 spin_unlock_irqrestore(&p->parent->dma_rd_reg_lock, flags); 715 } 716 return spi_int_fired; 717} 718 719static irqreturn_t pci1xxxx_spi_isr_dma_wr(int irq, void *dev) 720{ 721 struct pci1xxxx_spi_internal *p = dev; 722 irqreturn_t spi_int_fired = IRQ_NONE; 723 unsigned long flags; 724 u32 regval; 725 726 /* Clear the DMA WR INT */ 727 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS); 728 if (regval) { 729 if (regval & SPI_DMA_DONE_INT_MASK(p->hw_inst)) { 730 spi_int_fired = IRQ_HANDLED; 731 if (sg_is_last(p->rx_sgl)) { 732 complete(&p->spi_xfer_done); 733 } else { 734 p->rx_sgl = sg_next(p->rx_sgl); 735 if (atomic_inc_return(&p->dma_completion_count) == 2) 736 pci1xxxx_start_spi_xfer(p); 737 } 738 739 } 740 if (regval & SPI_DMA_ABORT_INT_MASK(p->hw_inst)) { 741 p->dma_aborted_wr = true; 742 spi_int_fired = IRQ_HANDLED; 743 } 744 spin_lock_irqsave(&p->parent->dma_wr_reg_lock, flags); 745 writel((SPI_DMA_DONE_INT_MASK(p->hw_inst) | SPI_DMA_ABORT_INT_MASK(p->hw_inst)), 746 p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR); 747 spin_unlock_irqrestore(&p->parent->dma_wr_reg_lock, flags); 748 } 749 return spi_int_fired; 750} 751 752static irqreturn_t pci1xxxx_spi_isr_dma(int irq, void *dev) 753{ 754 struct pci1xxxx_spi_internal *p = dev; 755 irqreturn_t spi_int_fired = IRQ_NONE; 756 u32 regval; 757 758 /* Clear the SPI GO_BIT Interrupt */ 759 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 760 if (regval & SPI_INTR) { 761 pci1xxxx_spi_setup_next_dma_from_io_transfer(p); 762 pci1xxxx_spi_setup_next_dma_to_io_transfer(p); 763 spi_int_fired = IRQ_HANDLED; 764 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); 765 } 766 return spi_int_fired; 767} 768 769static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev) 770{ 771 struct pci1xxxx_spi_internal *p = dev; 772 773 if (p->spi_host->can_dma(p->spi_host, NULL, p->xfer)) 774 return pci1xxxx_spi_isr_dma(irq, dev); 775 else 776 return pci1xxxx_spi_isr_io(irq, dev); 777} 778 779static irqreturn_t pci1xxxx_spi_shared_isr(int irq, void *dev) 780{ 781 struct pci1xxxx_spi *par = dev; 782 u8 i = 0; 783 784 for (i = 0; i < par->total_hw_instances; i++) 785 pci1xxxx_spi_isr(irq, par->spi_int[i]); 786 787 return IRQ_HANDLED; 788} 789 790static bool pci1xxxx_spi_can_dma(struct spi_controller *host, 791 struct spi_device *spi, 792 struct spi_transfer *xfer) 793{ 794 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(host); 795 struct pci1xxxx_spi *par = p->parent; 796 797 return par->can_dma; 798} 799 800static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 801{ 802 u8 hw_inst_cnt, iter, start, only_sec_inst; 803 struct pci1xxxx_spi_internal *spi_sub_ptr; 804 struct device *dev = &pdev->dev; 805 struct pci1xxxx_spi *spi_bus; 806 struct spi_controller *spi_host; 807 int num_vector = 0; 808 u32 regval; 809 int ret; 810 811 hw_inst_cnt = ent->driver_data & 0x0f; 812 start = (ent->driver_data & 0xf0) >> 4; 813 if (start == 1) 814 only_sec_inst = 1; 815 else 816 only_sec_inst = 0; 817 818 spi_bus = devm_kzalloc(&pdev->dev, 819 struct_size(spi_bus, spi_int, hw_inst_cnt), 820 GFP_KERNEL); 821 if (!spi_bus) 822 return -ENOMEM; 823 824 spi_bus->dev = pdev; 825 spi_bus->total_hw_instances = hw_inst_cnt; 826 pci_set_master(pdev); 827 828 for (iter = 0; iter < hw_inst_cnt; iter++) { 829 spi_bus->spi_int[iter] = devm_kzalloc(&pdev->dev, 830 sizeof(struct pci1xxxx_spi_internal), 831 GFP_KERNEL); 832 if (!spi_bus->spi_int[iter]) 833 return -ENOMEM; 834 spi_sub_ptr = spi_bus->spi_int[iter]; 835 spi_sub_ptr->spi_host = devm_spi_alloc_host(dev, sizeof(struct spi_controller)); 836 if (!spi_sub_ptr->spi_host) 837 return -ENOMEM; 838 839 spi_sub_ptr->parent = spi_bus; 840 spi_sub_ptr->spi_xfer_in_progress = false; 841 842 if (!iter) { 843 ret = pcim_enable_device(pdev); 844 if (ret) 845 return -ENOMEM; 846 847 ret = pcim_request_all_regions(pdev, DRV_NAME); 848 if (ret) 849 return -ENOMEM; 850 851 spi_bus->reg_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); 852 if (!spi_bus->reg_base) 853 return -EINVAL; 854 855 num_vector = pci_alloc_irq_vectors(pdev, 1, hw_inst_cnt * NUM_VEC_PER_INST, 856 PCI_IRQ_INTX | PCI_IRQ_MSI); 857 if (num_vector < 0) { 858 dev_err(&pdev->dev, "Error allocating MSI vectors\n"); 859 return num_vector; 860 } 861 862 init_completion(&spi_sub_ptr->spi_xfer_done); 863 /* Initialize Interrupts - SPI_INT */ 864 regval = readl(spi_bus->reg_base + 865 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); 866 regval &= ~SPI_INTR; 867 writel(regval, spi_bus->reg_base + 868 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); 869 spi_sub_ptr->irq[0] = pci_irq_vector(pdev, 0); 870 871 if (num_vector >= hw_inst_cnt) 872 ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq[0], 873 pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS, 874 pci_name(pdev), spi_sub_ptr); 875 else 876 ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq[0], 877 pci1xxxx_spi_shared_isr, 878 PCI1XXXX_IRQ_FLAGS | IRQF_SHARED, 879 pci_name(pdev), spi_bus); 880 if (ret < 0) { 881 dev_err(&pdev->dev, "Unable to request irq : %d", 882 spi_sub_ptr->irq[0]); 883 return -ENODEV; 884 } 885 886 /* This register is only applicable for 1st instance */ 887 regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); 888 if (!only_sec_inst) 889 regval |= (BIT(4)); 890 else 891 regval &= ~(BIT(4)); 892 893 writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); 894 } 895 896 spi_sub_ptr->hw_inst = start++; 897 898 if (iter == 1) { 899 init_completion(&spi_sub_ptr->spi_xfer_done); 900 /* Initialize Interrupts - SPI_INT */ 901 regval = readl(spi_bus->reg_base + 902 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); 903 regval &= ~SPI_INTR; 904 writel(regval, spi_bus->reg_base + 905 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); 906 if (num_vector >= hw_inst_cnt) { 907 spi_sub_ptr->irq[0] = pci_irq_vector(pdev, iter); 908 ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq[0], 909 pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS, 910 pci_name(pdev), spi_sub_ptr); 911 if (ret < 0) { 912 dev_err(&pdev->dev, "Unable to request irq : %d", 913 spi_sub_ptr->irq[0]); 914 return -ENODEV; 915 } 916 } 917 } 918 919 spi_host = spi_sub_ptr->spi_host; 920 spi_host->num_chipselect = SPI_CHIP_SEL_COUNT; 921 spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL | 922 SPI_TX_DUAL | SPI_LOOP; 923 spi_host->can_dma = pci1xxxx_spi_can_dma; 924 spi_host->transfer_one = pci1xxxx_spi_transfer_one; 925 926 spi_host->set_cs = pci1xxxx_spi_set_cs; 927 spi_host->bits_per_word_mask = SPI_BPW_MASK(8); 928 spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ; 929 spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ; 930 spi_host->flags = SPI_CONTROLLER_MUST_TX; 931 spi_controller_set_devdata(spi_host, spi_sub_ptr); 932 ret = devm_spi_register_controller(dev, spi_host); 933 if (ret) 934 return ret; 935 } 936 ret = pci1xxxx_spi_dma_init(spi_bus, hw_inst_cnt, num_vector); 937 if (ret && ret != -EOPNOTSUPP) 938 return ret; 939 940 pci_set_drvdata(pdev, spi_bus); 941 942 return 0; 943} 944 945static void store_restore_config(struct pci1xxxx_spi *spi_ptr, 946 struct pci1xxxx_spi_internal *spi_sub_ptr, 947 u8 inst, bool store) 948{ 949 u32 regval; 950 951 if (store) { 952 regval = readl(spi_ptr->reg_base + 953 SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst)); 954 regval &= SPI_MST_CTL_DEVSEL_MASK; 955 spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7; 956 regval = readl(spi_ptr->reg_base + 957 SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst)); 958 regval &= SPI_MSI_VECTOR_SEL_MASK; 959 spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1; 960 } else { 961 regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); 962 regval &= ~SPI_MST_CTL_DEVSEL_MASK; 963 regval |= (spi_sub_ptr->prev_val.dev_sel << 25); 964 writel(regval, 965 spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); 966 writel((spi_sub_ptr->prev_val.msi_vector_sel << 4), 967 spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst)); 968 } 969} 970 971static int pci1xxxx_spi_resume(struct device *dev) 972{ 973 struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev); 974 struct pci1xxxx_spi_internal *spi_sub_ptr; 975 u32 regval = SPI_RESUME_CONFIG; 976 u8 iter; 977 978 for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) { 979 spi_sub_ptr = spi_ptr->spi_int[iter]; 980 spi_controller_resume(spi_sub_ptr->spi_host); 981 writel(regval, spi_ptr->reg_base + 982 SPI_MST_EVENT_MASK_REG_OFFSET(iter)); 983 984 /* Restore config at resume */ 985 store_restore_config(spi_ptr, spi_sub_ptr, iter, 0); 986 } 987 988 return 0; 989} 990 991static int pci1xxxx_spi_suspend(struct device *dev) 992{ 993 struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev); 994 struct pci1xxxx_spi_internal *spi_sub_ptr; 995 u32 reg1 = SPI_SUSPEND_CONFIG; 996 u8 iter; 997 998 for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) { 999 spi_sub_ptr = spi_ptr->spi_int[iter]; 1000 1001 while (spi_sub_ptr->spi_xfer_in_progress) 1002 msleep(20); 1003 1004 /* Store existing config before suspend */ 1005 store_restore_config(spi_ptr, spi_sub_ptr, iter, 1); 1006 spi_controller_suspend(spi_sub_ptr->spi_host); 1007 writel(reg1, spi_ptr->reg_base + 1008 SPI_MST_EVENT_MASK_REG_OFFSET(iter)); 1009 } 1010 1011 return 0; 1012} 1013 1014static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend, 1015 pci1xxxx_spi_resume); 1016 1017static struct pci_driver pci1xxxx_spi_driver = { 1018 .name = DRV_NAME, 1019 .id_table = pci1xxxx_spi_pci_id_table, 1020 .probe = pci1xxxx_spi_probe, 1021 .driver = { 1022 .pm = pm_sleep_ptr(&spi_pm_ops), 1023 }, 1024}; 1025 1026module_pci_driver(pci1xxxx_spi_driver); 1027 1028MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx SPI bus driver"); 1029MODULE_AUTHOR("Tharun Kumar P<tharunkumar.pasumarthi@microchip.com>"); 1030MODULE_AUTHOR("Kumaravel Thiagarajan<kumaravel.thiagarajan@microchip.com>"); 1031MODULE_LICENSE("GPL v2");
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