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spi-nxp-fspi.c
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linux-6.19.14/drivers/spi/spi-nxp-fspi.c
1// SPDX-License-Identifier: GPL-2.0+ 2 3/* 4 * NXP FlexSPI(FSPI) controller driver. 5 * 6 * Copyright 2019-2020 NXP 7 * Copyright 2020 Puresoftware Ltd. 8 * 9 * FlexSPI is a flexsible SPI host controller which supports two SPI 10 * channels and up to 4 external devices. Each channel supports 11 * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional 12 * data lines). 13 * 14 * FlexSPI controller is driven by the LUT(Look-up Table) registers 15 * LUT registers are a look-up-table for sequences of instructions. 16 * A valid sequence consists of four LUT registers. 17 * Maximum 32 LUT sequences can be programmed simultaneously. 18 * 19 * LUTs are being created at run-time based on the commands passed 20 * from the spi-mem framework, thus using single LUT index. 21 * 22 * Software triggered Flash read/write access by IP Bus. 23 * 24 * Memory mapped read access by AHB Bus. 25 * 26 * Based on SPI MEM interface and spi-fsl-qspi.c driver. 27 * 28 * Author: 29 * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> 30 * Boris Brezillon <bbrezillon@kernel.org> 31 * Frieder Schrempf <frieder.schrempf@kontron.de> 32 */ 33 34#include <linux/acpi.h> 35#include <linux/bitops.h> 36#include <linux/bitfield.h> 37#include <linux/clk.h> 38#include <linux/completion.h> 39#include <linux/delay.h> 40#include <linux/err.h> 41#include <linux/errno.h> 42#include <linux/interrupt.h> 43#include <linux/io.h> 44#include <linux/iopoll.h> 45#include <linux/jiffies.h> 46#include <linux/kernel.h> 47#include <linux/module.h> 48#include <linux/mutex.h> 49#include <linux/of.h> 50#include <linux/platform_device.h> 51#include <linux/pinctrl/consumer.h> 52#include <linux/pm_runtime.h> 53#include <linux/pm_qos.h> 54#include <linux/regmap.h> 55#include <linux/sizes.h> 56#include <linux/sys_soc.h> 57 58#include <linux/mfd/syscon.h> 59#include <linux/spi/spi.h> 60#include <linux/spi/spi-mem.h> 61 62/* runtime pm timeout */ 63#define FSPI_RPM_TIMEOUT 50 /* 50ms */ 64 65/* Registers used by the driver */ 66#define FSPI_MCR0 0x00 67#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24) 68#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16) 69#define FSPI_MCR0_LEARN_EN BIT(15) 70#define FSPI_MCR0_SCRFRUN_EN BIT(14) 71#define FSPI_MCR0_OCTCOMB_EN BIT(13) 72#define FSPI_MCR0_DOZE_EN BIT(12) 73#define FSPI_MCR0_HSEN BIT(11) 74#define FSPI_MCR0_SERCLKDIV BIT(8) 75#define FSPI_MCR0_ATDF_EN BIT(7) 76#define FSPI_MCR0_ARDF_EN BIT(6) 77#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) 78#define FSPI_MCR0_END_CFG(x) ((x) << 2) 79#define FSPI_MCR0_MDIS BIT(1) 80#define FSPI_MCR0_SWRST BIT(0) 81 82#define FSPI_MCR1 0x04 83#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16) 84#define FSPI_MCR1_AHB_TIMEOUT(x) (x) 85 86#define FSPI_MCR2 0x08 87#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24) 88#define FSPI_MCR2_SAMEDEVICEEN BIT(15) 89#define FSPI_MCR2_CLRLRPHS BIT(14) 90#define FSPI_MCR2_ABRDATSZ BIT(8) 91#define FSPI_MCR2_ABRLEARN BIT(7) 92#define FSPI_MCR2_ABR_READ BIT(6) 93#define FSPI_MCR2_ABRWRITE BIT(5) 94#define FSPI_MCR2_ABRDUMMY BIT(4) 95#define FSPI_MCR2_ABR_MODE BIT(3) 96#define FSPI_MCR2_ABRCADDR BIT(2) 97#define FSPI_MCR2_ABRRADDR BIT(1) 98#define FSPI_MCR2_ABR_CMD BIT(0) 99 100#define FSPI_AHBCR 0x0c 101#define FSPI_AHBCR_RDADDROPT BIT(6) 102#define FSPI_AHBCR_PREF_EN BIT(5) 103#define FSPI_AHBCR_BUFF_EN BIT(4) 104#define FSPI_AHBCR_CACH_EN BIT(3) 105#define FSPI_AHBCR_CLRTXBUF BIT(2) 106#define FSPI_AHBCR_CLRRXBUF BIT(1) 107#define FSPI_AHBCR_PAR_EN BIT(0) 108 109#define FSPI_INTEN 0x10 110#define FSPI_INTEN_SCLKSBWR BIT(9) 111#define FSPI_INTEN_SCLKSBRD BIT(8) 112#define FSPI_INTEN_DATALRNFL BIT(7) 113#define FSPI_INTEN_IPTXWE BIT(6) 114#define FSPI_INTEN_IPRXWA BIT(5) 115#define FSPI_INTEN_AHBCMDERR BIT(4) 116#define FSPI_INTEN_IPCMDERR BIT(3) 117#define FSPI_INTEN_AHBCMDGE BIT(2) 118#define FSPI_INTEN_IPCMDGE BIT(1) 119#define FSPI_INTEN_IPCMDDONE BIT(0) 120 121#define FSPI_INTR 0x14 122#define FSPI_INTR_SCLKSBWR BIT(9) 123#define FSPI_INTR_SCLKSBRD BIT(8) 124#define FSPI_INTR_DATALRNFL BIT(7) 125#define FSPI_INTR_IPTXWE BIT(6) 126#define FSPI_INTR_IPRXWA BIT(5) 127#define FSPI_INTR_AHBCMDERR BIT(4) 128#define FSPI_INTR_IPCMDERR BIT(3) 129#define FSPI_INTR_AHBCMDGE BIT(2) 130#define FSPI_INTR_IPCMDGE BIT(1) 131#define FSPI_INTR_IPCMDDONE BIT(0) 132 133#define FSPI_LUTKEY 0x18 134#define FSPI_LUTKEY_VALUE 0x5AF05AF0 135 136#define FSPI_LCKCR 0x1C 137 138#define FSPI_LCKER_LOCK 0x1 139#define FSPI_LCKER_UNLOCK 0x2 140 141#define FSPI_BUFXCR_INVALID_MSTRID 0xE 142#define FSPI_AHBRX_BUF0CR0 0x20 143#define FSPI_AHBRX_BUF1CR0 0x24 144#define FSPI_AHBRX_BUF2CR0 0x28 145#define FSPI_AHBRX_BUF3CR0 0x2C 146#define FSPI_AHBRX_BUF4CR0 0x30 147#define FSPI_AHBRX_BUF5CR0 0x34 148#define FSPI_AHBRX_BUF6CR0 0x38 149#define FSPI_AHBRX_BUF7CR0 0x3C 150#define FSPI_AHBRXBUF0CR7_PREF BIT(31) 151 152#define FSPI_AHBRX_BUF0CR1 0x40 153#define FSPI_AHBRX_BUF1CR1 0x44 154#define FSPI_AHBRX_BUF2CR1 0x48 155#define FSPI_AHBRX_BUF3CR1 0x4C 156#define FSPI_AHBRX_BUF4CR1 0x50 157#define FSPI_AHBRX_BUF5CR1 0x54 158#define FSPI_AHBRX_BUF6CR1 0x58 159#define FSPI_AHBRX_BUF7CR1 0x5C 160 161#define FSPI_FLSHA1CR0 0x60 162#define FSPI_FLSHA2CR0 0x64 163#define FSPI_FLSHB1CR0 0x68 164#define FSPI_FLSHB2CR0 0x6C 165#define FSPI_FLSHXCR0_SZ_KB 10 166#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB) 167 168#define FSPI_FLSHA1CR1 0x70 169#define FSPI_FLSHA2CR1 0x74 170#define FSPI_FLSHB1CR1 0x78 171#define FSPI_FLSHB2CR1 0x7C 172#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16) 173#define FSPI_FLSHXCR1_CAS(x) ((x) << 11) 174#define FSPI_FLSHXCR1_WA BIT(10) 175#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5) 176#define FSPI_FLSHXCR1_TCSS(x) (x) 177 178#define FSPI_FLSHA1CR2 0x80 179#define FSPI_FLSHA2CR2 0x84 180#define FSPI_FLSHB1CR2 0x88 181#define FSPI_FLSHB2CR2 0x8C 182#define FSPI_FLSHXCR2_CLRINSP BIT(24) 183#define FSPI_FLSHXCR2_AWRWAIT BIT(16) 184#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13 185#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8 186#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5 187#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0 188 189#define FSPI_IPCR0 0xA0 190 191#define FSPI_IPCR1 0xA4 192#define FSPI_IPCR1_IPAREN BIT(31) 193#define FSPI_IPCR1_SEQNUM_SHIFT 24 194#define FSPI_IPCR1_SEQID_SHIFT 16 195#define FSPI_IPCR1_IDATSZ(x) (x) 196 197#define FSPI_IPCMD 0xB0 198#define FSPI_IPCMD_TRG BIT(0) 199 200#define FSPI_DLPR 0xB4 201 202#define FSPI_IPRXFCR 0xB8 203#define FSPI_IPRXFCR_CLR BIT(0) 204#define FSPI_IPRXFCR_DMA_EN BIT(1) 205#define FSPI_IPRXFCR_WMRK(x) ((x) << 2) 206 207#define FSPI_IPTXFCR 0xBC 208#define FSPI_IPTXFCR_CLR BIT(0) 209#define FSPI_IPTXFCR_DMA_EN BIT(1) 210#define FSPI_IPTXFCR_WMRK(x) ((x) << 2) 211 212#define FSPI_DLLACR 0xC0 213#define FSPI_DLLACR_OVRDEN BIT(8) 214#define FSPI_DLLACR_SLVDLY(x) ((x) << 3) 215#define FSPI_DLLACR_DLLRESET BIT(1) 216#define FSPI_DLLACR_DLLEN BIT(0) 217 218#define FSPI_DLLBCR 0xC4 219#define FSPI_DLLBCR_OVRDEN BIT(8) 220#define FSPI_DLLBCR_SLVDLY(x) ((x) << 3) 221#define FSPI_DLLBCR_DLLRESET BIT(1) 222#define FSPI_DLLBCR_DLLEN BIT(0) 223 224#define FSPI_STS0 0xE0 225#define FSPI_STS0_DLPHB(x) ((x) << 8) 226#define FSPI_STS0_DLPHA(x) ((x) << 4) 227#define FSPI_STS0_CMD_SRC(x) ((x) << 2) 228#define FSPI_STS0_ARB_IDLE BIT(1) 229#define FSPI_STS0_SEQ_IDLE BIT(0) 230 231#define FSPI_STS1 0xE4 232#define FSPI_STS1_IP_ERRCD(x) ((x) << 24) 233#define FSPI_STS1_IP_ERRID(x) ((x) << 16) 234#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8) 235#define FSPI_STS1_AHB_ERRID(x) (x) 236 237#define FSPI_STS2 0xE8 238#define FSPI_STS2_BREFLOCK BIT(17) 239#define FSPI_STS2_BSLVLOCK BIT(16) 240#define FSPI_STS2_AREFLOCK BIT(1) 241#define FSPI_STS2_ASLVLOCK BIT(0) 242#define FSPI_STS2_AB_LOCK (FSPI_STS2_BREFLOCK | \ 243 FSPI_STS2_BSLVLOCK | \ 244 FSPI_STS2_AREFLOCK | \ 245 FSPI_STS2_ASLVLOCK) 246 247#define FSPI_AHBSPNST 0xEC 248#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16) 249#define FSPI_AHBSPNST_BUFID(x) ((x) << 1) 250#define FSPI_AHBSPNST_ACTIVE BIT(0) 251 252#define FSPI_IPRXFSTS 0xF0 253#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16) 254#define FSPI_IPRXFSTS_FILL(x) (x) 255 256#define FSPI_IPTXFSTS 0xF4 257#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16) 258#define FSPI_IPTXFSTS_FILL(x) (x) 259 260#define FSPI_RFDR 0x100 261#define FSPI_TFDR 0x180 262 263#define FSPI_LUT_BASE 0x200 264 265/* register map end */ 266 267/* Instruction set for the LUT register. */ 268#define LUT_STOP 0x00 269#define LUT_CMD 0x01 270#define LUT_ADDR 0x02 271#define LUT_CADDR_SDR 0x03 272#define LUT_MODE 0x04 273#define LUT_MODE2 0x05 274#define LUT_MODE4 0x06 275#define LUT_MODE8 0x07 276#define LUT_NXP_WRITE 0x08 277#define LUT_NXP_READ 0x09 278#define LUT_LEARN_SDR 0x0A 279#define LUT_DATSZ_SDR 0x0B 280#define LUT_DUMMY 0x0C 281#define LUT_DUMMY_RWDS_SDR 0x0D 282#define LUT_JMP_ON_CS 0x1F 283#define LUT_CMD_DDR 0x21 284#define LUT_ADDR_DDR 0x22 285#define LUT_CADDR_DDR 0x23 286#define LUT_MODE_DDR 0x24 287#define LUT_MODE2_DDR 0x25 288#define LUT_MODE4_DDR 0x26 289#define LUT_MODE8_DDR 0x27 290#define LUT_WRITE_DDR 0x28 291#define LUT_READ_DDR 0x29 292#define LUT_LEARN_DDR 0x2A 293#define LUT_DATSZ_DDR 0x2B 294#define LUT_DUMMY_DDR 0x2C 295#define LUT_DUMMY_RWDS_DDR 0x2D 296 297/* 298 * Calculate number of required PAD bits for LUT register. 299 * 300 * The pad stands for the number of IO lines [0:7]. 301 * For example, the octal read needs eight IO lines, 302 * so you should use LUT_PAD(8). This macro 303 * returns 3 i.e. use eight (2^3) IP lines for read. 304 */ 305#define LUT_PAD(x) (fls(x) - 1) 306 307/* 308 * Macro for constructing the LUT entries with the following 309 * register layout: 310 * 311 * --------------------------------------------------- 312 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 313 * --------------------------------------------------- 314 */ 315#define PAD_SHIFT 8 316#define INSTR_SHIFT 10 317#define OPRND_SHIFT 16 318 319/* Macros for constructing the LUT register. */ 320#define LUT_DEF(idx, ins, pad, opr) \ 321 ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \ 322 (opr)) << (((idx) % 2) * OPRND_SHIFT)) 323 324#define POLL_TOUT 5000 325#define NXP_FSPI_MAX_CHIPSELECT 4 326#define NXP_FSPI_MIN_IOMAP SZ_4M 327 328#define DCFG_RCWSR1 0x100 329#define SYS_PLL_RAT GENMASK(6, 2) 330 331/* Access flash memory using IP bus only */ 332#define FSPI_QUIRK_USE_IP_ONLY BIT(0) 333/* Disable DTR */ 334#define FSPI_QUIRK_DISABLE_DTR BIT(1) 335 336struct nxp_fspi_devtype_data { 337 unsigned int rxfifo; 338 unsigned int txfifo; 339 unsigned int ahb_buf_size; 340 unsigned int quirks; 341 unsigned int lut_num; 342 bool little_endian; 343}; 344 345static struct nxp_fspi_devtype_data lx2160a_data = { 346 .rxfifo = SZ_512, /* (64 * 64 bits) */ 347 .txfifo = SZ_1K, /* (128 * 64 bits) */ 348 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 349 .quirks = FSPI_QUIRK_DISABLE_DTR, 350 .lut_num = 32, 351 .little_endian = true, /* little-endian */ 352}; 353 354static struct nxp_fspi_devtype_data imx8mm_data = { 355 .rxfifo = SZ_512, /* (64 * 64 bits) */ 356 .txfifo = SZ_1K, /* (128 * 64 bits) */ 357 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 358 .quirks = 0, 359 .lut_num = 32, 360 .little_endian = true, /* little-endian */ 361}; 362 363static struct nxp_fspi_devtype_data imx8qxp_data = { 364 .rxfifo = SZ_512, /* (64 * 64 bits) */ 365 .txfifo = SZ_1K, /* (128 * 64 bits) */ 366 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 367 .quirks = 0, 368 .lut_num = 32, 369 .little_endian = true, /* little-endian */ 370}; 371 372static struct nxp_fspi_devtype_data imx8dxl_data = { 373 .rxfifo = SZ_512, /* (64 * 64 bits) */ 374 .txfifo = SZ_1K, /* (128 * 64 bits) */ 375 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 376 .quirks = FSPI_QUIRK_USE_IP_ONLY, 377 .lut_num = 32, 378 .little_endian = true, /* little-endian */ 379}; 380 381static struct nxp_fspi_devtype_data imx8ulp_data = { 382 .rxfifo = SZ_512, /* (64 * 64 bits) */ 383 .txfifo = SZ_1K, /* (128 * 64 bits) */ 384 .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ 385 .quirks = 0, 386 .lut_num = 16, 387 .little_endian = true, /* little-endian */ 388}; 389 390struct nxp_fspi { 391 void __iomem *iobase; 392 void __iomem *ahb_addr; 393 u32 memmap_phy; 394 u32 memmap_phy_size; 395 u32 memmap_start; 396 u32 memmap_len; 397 struct clk *clk, *clk_en; 398 struct device *dev; 399 struct completion c; 400 struct nxp_fspi_devtype_data *devtype_data; 401 struct mutex lock; 402 struct pm_qos_request pm_qos_req; 403 int selected; 404#define FSPI_NEED_INIT BIT(0) 405#define FSPI_DTR_MODE BIT(1) 406 int flags; 407 /* save the previous operation clock rate */ 408 unsigned long pre_op_rate; 409 /* the max clock rate fspi output to device */ 410 unsigned long max_rate; 411}; 412 413static inline int needs_ip_only(struct nxp_fspi *f) 414{ 415 return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; 416} 417 418/* 419 * R/W functions for big- or little-endian registers: 420 * The FSPI controller's endianness is independent of 421 * the CPU core's endianness. So far, although the CPU 422 * core is little-endian the FSPI controller can use 423 * big-endian or little-endian. 424 */ 425static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr) 426{ 427 if (f->devtype_data->little_endian) 428 iowrite32(val, addr); 429 else 430 iowrite32be(val, addr); 431} 432 433static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) 434{ 435 if (f->devtype_data->little_endian) 436 return ioread32(addr); 437 else 438 return ioread32be(addr); 439} 440 441static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id) 442{ 443 struct nxp_fspi *f = dev_id; 444 u32 reg; 445 446 /* clear interrupt */ 447 reg = fspi_readl(f, f->iobase + FSPI_INTR); 448 fspi_writel(f, FSPI_INTR_IPCMDDONE, f->iobase + FSPI_INTR); 449 450 if (reg & FSPI_INTR_IPCMDDONE) 451 complete(&f->c); 452 453 return IRQ_HANDLED; 454} 455 456static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) 457{ 458 switch (width) { 459 case 1: 460 case 2: 461 case 4: 462 case 8: 463 return 0; 464 } 465 466 return -ENOTSUPP; 467} 468 469static bool nxp_fspi_supports_op(struct spi_mem *mem, 470 const struct spi_mem_op *op) 471{ 472 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 473 int ret; 474 475 ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth); 476 477 if (op->addr.nbytes) 478 ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth); 479 480 if (op->dummy.nbytes) 481 ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth); 482 483 if (op->data.nbytes) 484 ret |= nxp_fspi_check_buswidth(f, op->data.buswidth); 485 486 if (ret) 487 return false; 488 489 /* 490 * The number of address bytes should be equal to or less than 4 bytes. 491 */ 492 if (op->addr.nbytes > 4) 493 return false; 494 495 /* 496 * If requested address value is greater than controller assigned 497 * memory mapped space, return error as it didn't fit in the range 498 * of assigned address space. 499 */ 500 if (op->addr.val >= f->memmap_phy_size) 501 return false; 502 503 /* Max 64 dummy clock cycles supported */ 504 if (op->dummy.buswidth && 505 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 506 return false; 507 508 /* Max data length, check controller limits and alignment */ 509 if (op->data.dir == SPI_MEM_DATA_IN && 510 (op->data.nbytes > f->devtype_data->ahb_buf_size || 511 (op->data.nbytes > f->devtype_data->rxfifo - 4 && 512 !IS_ALIGNED(op->data.nbytes, 8)))) 513 return false; 514 515 if (op->data.dir == SPI_MEM_DATA_OUT && 516 op->data.nbytes > f->devtype_data->txfifo) 517 return false; 518 519 return spi_mem_default_supports_op(mem, op); 520} 521 522/* Instead of busy looping invoke readl_poll_timeout functionality. */ 523static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base, 524 u32 mask, u32 delay_us, 525 u32 timeout_us, bool c) 526{ 527 u32 reg; 528 529 if (!f->devtype_data->little_endian) 530 mask = (u32)cpu_to_be32(mask); 531 532 if (c) 533 return readl_poll_timeout(base, reg, (reg & mask), 534 delay_us, timeout_us); 535 else 536 return readl_poll_timeout(base, reg, !(reg & mask), 537 delay_us, timeout_us); 538} 539 540/* 541 * If the target device content being changed by Write/Erase, need to 542 * invalidate the AHB buffer. This can be achieved by doing the reset 543 * of controller after setting MCR0[SWRESET] bit. 544 */ 545static inline void nxp_fspi_invalid(struct nxp_fspi *f) 546{ 547 u32 reg; 548 int ret; 549 550 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 551 fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0); 552 553 /* w1c register, wait unit clear */ 554 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 555 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 556 WARN_ON(ret); 557} 558 559static void nxp_fspi_prepare_lut(struct nxp_fspi *f, 560 const struct spi_mem_op *op) 561{ 562 void __iomem *base = f->iobase; 563 u32 lutval[4] = {}; 564 int lutidx = 1, i; 565 u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4; 566 u32 target_lut_reg; 567 568 /* cmd */ 569 if (op->cmd.dtr) { 570 lutval[0] |= LUT_DEF(0, LUT_CMD_DDR, LUT_PAD(op->cmd.buswidth), 571 op->cmd.opcode >> 8); 572 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_CMD_DDR, 573 LUT_PAD(op->cmd.buswidth), 574 op->cmd.opcode & 0xFF); 575 lutidx++; 576 } else { 577 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 578 op->cmd.opcode); 579 } 580 581 /* addr bytes */ 582 if (op->addr.nbytes) { 583 lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? LUT_ADDR_DDR : LUT_ADDR, 584 LUT_PAD(op->addr.buswidth), 585 op->addr.nbytes * 8); 586 lutidx++; 587 } 588 589 /* dummy bytes, if needed */ 590 if (op->dummy.nbytes) { 591 lutval[lutidx / 2] |= LUT_DEF(lutidx, op->dummy.dtr ? LUT_DUMMY_DDR : LUT_DUMMY, 592 /* 593 * Due to FlexSPI controller limitation number of PAD for dummy 594 * buswidth needs to be programmed as equal to data buswidth. 595 */ 596 LUT_PAD(op->data.buswidth), 597 op->dummy.nbytes * 8 / 598 op->dummy.buswidth); 599 lutidx++; 600 } 601 602 /* read/write data bytes */ 603 if (op->data.nbytes) { 604 lutval[lutidx / 2] |= LUT_DEF(lutidx, 605 op->data.dir == SPI_MEM_DATA_IN ? 606 (op->data.dtr ? LUT_READ_DDR : LUT_NXP_READ) : 607 (op->data.dtr ? LUT_WRITE_DDR : LUT_NXP_WRITE), 608 LUT_PAD(op->data.buswidth), 609 0); 610 lutidx++; 611 } 612 613 /* stop condition. */ 614 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 615 616 /* unlock LUT */ 617 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 618 fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR); 619 620 /* fill LUT */ 621 for (i = 0; i < ARRAY_SIZE(lutval); i++) { 622 target_lut_reg = FSPI_LUT_BASE + lut_offset + i * 4; 623 fspi_writel(f, lutval[i], base + target_lut_reg); 624 } 625 626 dev_dbg(f->dev, "CMD[%02x] lutval[0:%08x 1:%08x 2:%08x 3:%08x], size: 0x%08x\n", 627 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes); 628 629 /* lock LUT */ 630 fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY); 631 fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR); 632} 633 634static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f) 635{ 636 int ret; 637 638 if (is_acpi_node(dev_fwnode(f->dev))) 639 return 0; 640 641 ret = clk_prepare_enable(f->clk_en); 642 if (ret) 643 return ret; 644 645 ret = clk_prepare_enable(f->clk); 646 if (ret) { 647 clk_disable_unprepare(f->clk_en); 648 return ret; 649 } 650 651 return 0; 652} 653 654static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f) 655{ 656 if (is_acpi_node(dev_fwnode(f->dev))) 657 return; 658 659 clk_disable_unprepare(f->clk); 660 clk_disable_unprepare(f->clk_en); 661 662 return; 663} 664 665/* 666 * Sample Clock source selection for Flash Reading 667 * Four modes defined by fspi: 668 * mode 0: Dummy Read strobe generated by FlexSPI Controller 669 * and loopback internally 670 * mode 1: Dummy Read strobe generated by FlexSPI Controller 671 * and loopback from DQS pad 672 * mode 2: Reserved 673 * mode 3: Flash provided Read strobe and input from DQS pad 674 * 675 * fspi default use mode 0 after reset 676 */ 677static void nxp_fspi_select_rx_sample_clk_source(struct nxp_fspi *f, 678 bool op_is_dtr) 679{ 680 u32 reg; 681 682 /* 683 * For 8D-8D-8D mode, need to use mode 3 (Flash provided Read 684 * strobe and input from DQS pad), otherwise read operaton may 685 * meet issue. 686 * This mode require flash device connect the DQS pad on board. 687 * For other modes, still use mode 0, keep align with before. 688 * spi_nor_suspend will disable 8D-8D-8D mode, also need to 689 * change the mode back to mode 0. 690 */ 691 reg = fspi_readl(f, f->iobase + FSPI_MCR0); 692 if (op_is_dtr) { 693 reg |= FSPI_MCR0_RXCLKSRC(3); 694 f->max_rate = 166000000; 695 } else { /*select mode 0 */ 696 reg &= ~FSPI_MCR0_RXCLKSRC(3); 697 f->max_rate = 66000000; 698 } 699 fspi_writel(f, reg, f->iobase + FSPI_MCR0); 700} 701 702static void nxp_fspi_dll_calibration(struct nxp_fspi *f) 703{ 704 int ret; 705 706 /* Reset the DLL, set the DLLRESET to 1 and then set to 0 */ 707 fspi_writel(f, FSPI_DLLACR_DLLRESET, f->iobase + FSPI_DLLACR); 708 fspi_writel(f, FSPI_DLLBCR_DLLRESET, f->iobase + FSPI_DLLBCR); 709 fspi_writel(f, 0, f->iobase + FSPI_DLLACR); 710 fspi_writel(f, 0, f->iobase + FSPI_DLLBCR); 711 712 /* 713 * Enable the DLL calibration mode. 714 * The delay target for slave delay line is: 715 * ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock. 716 * When clock rate > 100MHz, recommend SLVDLYTARGET is 0xF, which 717 * means half of clock cycle of reference clock. 718 */ 719 fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(0xF), 720 f->iobase + FSPI_DLLACR); 721 fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(0xF), 722 f->iobase + FSPI_DLLBCR); 723 724 /* Wait to get REF/SLV lock */ 725 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_STS2, FSPI_STS2_AB_LOCK, 726 0, POLL_TOUT, true); 727 if (ret) 728 dev_warn(f->dev, "DLL lock failed, please fix it!\n"); 729 730 /* 731 * For ERR050272, DLL lock status bit is not accurate, 732 * wait for 4us more as a workaround. 733 */ 734 udelay(4); 735} 736 737/* 738 * Config the DLL register to default value, enable the target clock delay 739 * line delay cell override mode, and use 1 fixed delay cell in DLL delay 740 * chain, this is the suggested setting when clock rate < 100MHz. 741 */ 742static void nxp_fspi_dll_override(struct nxp_fspi *f) 743{ 744 fspi_writel(f, FSPI_DLLACR_OVRDEN, f->iobase + FSPI_DLLACR); 745 fspi_writel(f, FSPI_DLLBCR_OVRDEN, f->iobase + FSPI_DLLBCR); 746} 747 748/* 749 * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0 750 * register and start base address of the target device. 751 * 752 * (Higher address) 753 * -------- <-- FLSHB2CR0 754 * | B2 | 755 * | | 756 * B2 start address --> -------- <-- FLSHB1CR0 757 * | B1 | 758 * | | 759 * B1 start address --> -------- <-- FLSHA2CR0 760 * | A2 | 761 * | | 762 * A2 start address --> -------- <-- FLSHA1CR0 763 * | A1 | 764 * | | 765 * A1 start address --> -------- (Lower address) 766 * 767 * 768 * Start base address defines the starting address range for given CS and 769 * FSPI_FLSHXXCR0 defines the size of the target device connected at given CS. 770 * 771 * But, different targets are having different combinations of number of CS, 772 * some targets only have single CS or two CS covering controller's full 773 * memory mapped space area. 774 * Thus, implementation is being done as independent of the size and number 775 * of the connected target device. 776 * Assign controller memory mapped space size as the size to the connected 777 * target device. 778 * Mark FLSHxxCR0 as zero initially and then assign value only to the selected 779 * chip-select Flash configuration register. 780 * 781 * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the 782 * memory mapped size of the controller. 783 * Value for rest of the CS FLSHxxCR0 register would be zero. 784 * 785 */ 786static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi, 787 const struct spi_mem_op *op) 788{ 789 /* flexspi only support one DTR mode: 8D-8D-8D */ 790 bool op_is_dtr = op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr; 791 unsigned long rate = op->max_freq; 792 int ret; 793 uint64_t size_kb; 794 795 /* 796 * Return when following condition all meet, 797 * 1, if previously selected target device is same as current 798 * requested target device. 799 * 2, the DTR or STR mode do not change. 800 * 3, previous operation max rate equals current one. 801 * 802 * For other case, need to re-config. 803 */ 804 if ((f->selected == spi_get_chipselect(spi, 0)) && 805 (!!(f->flags & FSPI_DTR_MODE) == op_is_dtr) && 806 (f->pre_op_rate == op->max_freq)) 807 return; 808 809 /* Reset FLSHxxCR0 registers */ 810 fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0); 811 fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0); 812 fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0); 813 fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0); 814 815 /* Assign controller memory mapped space as size, KBytes, of flash. */ 816 size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size); 817 818 fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 + 819 4 * spi_get_chipselect(spi, 0)); 820 821 dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0)); 822 823 nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr); 824 rate = min(f->max_rate, op->max_freq); 825 826 if (op_is_dtr) { 827 f->flags |= FSPI_DTR_MODE; 828 /* For DTR mode, flexspi will default div 2 and output to device. 829 * so here to config the root clock to 2 * device rate. 830 */ 831 rate = rate * 2; 832 } else { 833 f->flags &= ~FSPI_DTR_MODE; 834 } 835 836 nxp_fspi_clk_disable_unprep(f); 837 838 ret = clk_set_rate(f->clk, rate); 839 if (ret) 840 return; 841 842 ret = nxp_fspi_clk_prep_enable(f); 843 if (ret) 844 return; 845 846 /* 847 * If clock rate > 100MHz, then switch from DLL override mode to 848 * DLL calibration mode. 849 */ 850 if (rate > 100000000) 851 nxp_fspi_dll_calibration(f); 852 else 853 nxp_fspi_dll_override(f); 854 855 f->pre_op_rate = op->max_freq; 856 857 f->selected = spi_get_chipselect(spi, 0); 858} 859 860static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) 861{ 862 u32 start = op->addr.val; 863 u32 len = op->data.nbytes; 864 865 /* if necessary, ioremap before AHB read */ 866 if ((!f->ahb_addr) || start < f->memmap_start || 867 start + len > f->memmap_start + f->memmap_len) { 868 if (f->ahb_addr) 869 iounmap(f->ahb_addr); 870 871 f->memmap_start = start; 872 f->memmap_len = max_t(u32, len, NXP_FSPI_MIN_IOMAP); 873 874 f->ahb_addr = ioremap(f->memmap_phy + f->memmap_start, 875 f->memmap_len); 876 877 if (!f->ahb_addr) { 878 dev_err(f->dev, "failed to alloc memory\n"); 879 return -ENOMEM; 880 } 881 } 882 883 /* Read out the data directly from the AHB buffer. */ 884 memcpy_fromio(op->data.buf.in, 885 f->ahb_addr + start - f->memmap_start, len); 886 887 return 0; 888} 889 890static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, 891 const struct spi_mem_op *op) 892{ 893 void __iomem *base = f->iobase; 894 int i, ret; 895 u8 *buf = (u8 *) op->data.buf.out; 896 897 /* clear the TX FIFO. */ 898 fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR); 899 900 /* 901 * Default value of water mark level is 8 bytes, hence in single 902 * write request controller can write max 8 bytes of data. 903 */ 904 905 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) { 906 /* Wait for TXFIFO empty */ 907 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 908 FSPI_INTR_IPTXWE, 0, 909 POLL_TOUT, true); 910 WARN_ON(ret); 911 912 fspi_writel(f, *(u32 *) (buf + i), base + FSPI_TFDR); 913 fspi_writel(f, *(u32 *) (buf + i + 4), base + FSPI_TFDR + 4); 914 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 915 } 916 917 if (i < op->data.nbytes) { 918 u32 data = 0; 919 int j; 920 int remaining = op->data.nbytes - i; 921 /* Wait for TXFIFO empty */ 922 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 923 FSPI_INTR_IPTXWE, 0, 924 POLL_TOUT, true); 925 WARN_ON(ret); 926 927 for (j = 0; j < ALIGN(remaining, 4); j += 4) { 928 memcpy(&data, buf + i + j, min_t(int, 4, remaining - j)); 929 fspi_writel(f, data, base + FSPI_TFDR + j); 930 } 931 fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR); 932 } 933} 934 935static void nxp_fspi_read_rxfifo(struct nxp_fspi *f, 936 const struct spi_mem_op *op) 937{ 938 void __iomem *base = f->iobase; 939 int i, ret; 940 int len = op->data.nbytes; 941 u8 *buf = (u8 *) op->data.buf.in; 942 943 /* 944 * Default value of water mark level is 8 bytes, hence in single 945 * read request controller can read max 8 bytes of data. 946 */ 947 for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) { 948 /* Wait for RXFIFO available */ 949 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 950 FSPI_INTR_IPRXWA, 0, 951 POLL_TOUT, true); 952 WARN_ON(ret); 953 954 *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR); 955 *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4); 956 /* move the FIFO pointer */ 957 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 958 } 959 960 if (i < len) { 961 u32 tmp; 962 int size, j; 963 964 buf = op->data.buf.in + i; 965 /* Wait for RXFIFO available */ 966 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR, 967 FSPI_INTR_IPRXWA, 0, 968 POLL_TOUT, true); 969 WARN_ON(ret); 970 971 len = op->data.nbytes - i; 972 for (j = 0; j < op->data.nbytes - i; j += 4) { 973 tmp = fspi_readl(f, base + FSPI_RFDR + j); 974 size = min(len, 4); 975 memcpy(buf + j, &tmp, size); 976 len -= size; 977 } 978 } 979 980 /* invalid the RXFIFO */ 981 fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR); 982 /* move the FIFO pointer */ 983 fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR); 984} 985 986static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op) 987{ 988 void __iomem *base = f->iobase; 989 int seqnum = 0; 990 int err = 0; 991 u32 reg, seqid_lut; 992 993 reg = fspi_readl(f, base + FSPI_IPRXFCR); 994 /* invalid RXFIFO first */ 995 reg &= ~FSPI_IPRXFCR_DMA_EN; 996 reg = reg | FSPI_IPRXFCR_CLR; 997 fspi_writel(f, reg, base + FSPI_IPRXFCR); 998 999 init_completion(&f->c); 1000 1001 fspi_writel(f, op->addr.val, base + FSPI_IPCR0); 1002 /* 1003 * Always start the sequence at the same index since we update 1004 * the LUT at each exec_op() call. And also specify the DATA 1005 * length, since it's has not been specified in the LUT. 1006 */ 1007 seqid_lut = f->devtype_data->lut_num - 1; 1008 fspi_writel(f, op->data.nbytes | 1009 (seqid_lut << FSPI_IPCR1_SEQID_SHIFT) | 1010 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT), 1011 base + FSPI_IPCR1); 1012 1013 /* Trigger the LUT now. */ 1014 fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD); 1015 1016 /* Wait for the interrupt. */ 1017 if (!wait_for_completion_timeout(&f->c, msecs_to_jiffies(1000))) 1018 err = -ETIMEDOUT; 1019 1020 /* Invoke IP data read, if request is of data read. */ 1021 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 1022 nxp_fspi_read_rxfifo(f, op); 1023 1024 return err; 1025} 1026 1027static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 1028{ 1029 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 1030 int err = 0; 1031 1032 guard(mutex)(&f->lock); 1033 1034 err = pm_runtime_get_sync(f->dev); 1035 if (err < 0) { 1036 dev_err(f->dev, "Failed to enable clock %d\n", __LINE__); 1037 return err; 1038 } 1039 1040 /* Wait for controller being ready. */ 1041 err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0, 1042 FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true); 1043 WARN_ON(err); 1044 1045 nxp_fspi_select_mem(f, mem->spi, op); 1046 1047 nxp_fspi_prepare_lut(f, op); 1048 /* 1049 * If we have large chunks of data, we read them through the AHB bus by 1050 * accessing the mapped memory. In all other cases we use IP commands 1051 * to access the flash. Read via AHB bus may be corrupted due to 1052 * existence of an errata and therefore discard AHB read in such cases. 1053 */ 1054 if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && 1055 op->data.dir == SPI_MEM_DATA_IN && 1056 !needs_ip_only(f)) { 1057 err = nxp_fspi_read_ahb(f, op); 1058 } else { 1059 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 1060 nxp_fspi_fill_txfifo(f, op); 1061 1062 err = nxp_fspi_do_op(f, op); 1063 } 1064 1065 /* Invalidate the data in the AHB buffer. */ 1066 nxp_fspi_invalid(f); 1067 1068 pm_runtime_put_autosuspend(f->dev); 1069 1070 return err; 1071} 1072 1073static int nxp_fspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 1074{ 1075 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 1076 1077 if (op->data.dir == SPI_MEM_DATA_OUT) { 1078 if (op->data.nbytes > f->devtype_data->txfifo) 1079 op->data.nbytes = f->devtype_data->txfifo; 1080 } else { 1081 if (op->data.nbytes > f->devtype_data->ahb_buf_size) 1082 op->data.nbytes = f->devtype_data->ahb_buf_size; 1083 else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) 1084 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 1085 } 1086 1087 /* Limit data bytes to RX FIFO in case of IP read only */ 1088 if (op->data.dir == SPI_MEM_DATA_IN && 1089 needs_ip_only(f) && 1090 op->data.nbytes > f->devtype_data->rxfifo) 1091 op->data.nbytes = f->devtype_data->rxfifo; 1092 1093 return 0; 1094} 1095 1096static void erratum_err050568(struct nxp_fspi *f) 1097{ 1098 static const struct soc_device_attribute ls1028a_soc_attr[] = { 1099 { .family = "QorIQ LS1028A" }, 1100 { /* sentinel */ } 1101 }; 1102 struct regmap *map; 1103 u32 val, sys_pll_ratio; 1104 int ret; 1105 1106 /* Check for LS1028A family */ 1107 if (!soc_device_match(ls1028a_soc_attr)) { 1108 dev_dbg(f->dev, "Errata applicable only for LS1028A\n"); 1109 return; 1110 } 1111 1112 map = syscon_regmap_lookup_by_compatible("fsl,ls1028a-dcfg"); 1113 if (IS_ERR(map)) { 1114 dev_err(f->dev, "No syscon regmap\n"); 1115 goto err; 1116 } 1117 1118 ret = regmap_read(map, DCFG_RCWSR1, &val); 1119 if (ret < 0) 1120 goto err; 1121 1122 sys_pll_ratio = FIELD_GET(SYS_PLL_RAT, val); 1123 dev_dbg(f->dev, "val: 0x%08x, sys_pll_ratio: %d\n", val, sys_pll_ratio); 1124 1125 /* Use IP bus only if platform clock is 300MHz */ 1126 if (sys_pll_ratio == 3) 1127 f->devtype_data->quirks |= FSPI_QUIRK_USE_IP_ONLY; 1128 1129 return; 1130 1131err: 1132 dev_err(f->dev, "Errata cannot be executed. Read via IP bus may not work\n"); 1133} 1134 1135static int nxp_fspi_default_setup(struct nxp_fspi *f) 1136{ 1137 void __iomem *base = f->iobase; 1138 int ret, i; 1139 u32 reg, seqid_lut; 1140 1141 /* disable and unprepare clock to avoid glitch pass to controller */ 1142 nxp_fspi_clk_disable_unprep(f); 1143 1144 /* the default frequency, we will change it later if necessary. */ 1145 ret = clk_set_rate(f->clk, 20000000); 1146 if (ret) 1147 return ret; 1148 1149 ret = nxp_fspi_clk_prep_enable(f); 1150 if (ret) 1151 return ret; 1152 1153 /* 1154 * ERR050568: Flash access by FlexSPI AHB command may not work with 1155 * platform frequency equal to 300 MHz on LS1028A. 1156 * LS1028A reuses LX2160A compatible entry. Make errata applicable for 1157 * Layerscape LS1028A platform. 1158 */ 1159 if (of_device_is_compatible(f->dev->of_node, "nxp,lx2160a-fspi")) 1160 erratum_err050568(f); 1161 1162 /* Reset the module */ 1163 /* w1c register, wait unit clear */ 1164 ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0, 1165 FSPI_MCR0_SWRST, 0, POLL_TOUT, false); 1166 WARN_ON(ret); 1167 1168 /* Disable the module */ 1169 fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0); 1170 1171 nxp_fspi_dll_override(f); 1172 1173 /* enable module */ 1174 fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | 1175 FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, 1176 base + FSPI_MCR0); 1177 1178 /* 1179 * Disable same device enable bit and configure all target devices 1180 * independently. 1181 */ 1182 reg = fspi_readl(f, f->iobase + FSPI_MCR2); 1183 reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN); 1184 fspi_writel(f, reg, base + FSPI_MCR2); 1185 1186 /* AHB configuration for access buffer 0~7. */ 1187 for (i = 0; i < 7; i++) 1188 fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i); 1189 1190 /* 1191 * Set ADATSZ with the maximum AHB buffer size to improve the read 1192 * performance. 1193 */ 1194 fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 | 1195 FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0); 1196 1197 /* prefetch and no start address alignment limitation */ 1198 fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT, 1199 base + FSPI_AHBCR); 1200 1201 /* Reset the FLSHxCR1 registers. */ 1202 reg = FSPI_FLSHXCR1_TCSH(0x3) | FSPI_FLSHXCR1_TCSS(0x3); 1203 fspi_writel(f, reg, base + FSPI_FLSHA1CR1); 1204 fspi_writel(f, reg, base + FSPI_FLSHA2CR1); 1205 fspi_writel(f, reg, base + FSPI_FLSHB1CR1); 1206 fspi_writel(f, reg, base + FSPI_FLSHB2CR1); 1207 1208 /* 1209 * The driver only uses one single LUT entry, that is updated on 1210 * each call of exec_op(). Index 0 is preset at boot with a basic 1211 * read operation, so let's use the last entry. 1212 */ 1213 seqid_lut = f->devtype_data->lut_num - 1; 1214 /* AHB Read - Set lut sequence ID for all CS. */ 1215 fspi_writel(f, seqid_lut, base + FSPI_FLSHA1CR2); 1216 fspi_writel(f, seqid_lut, base + FSPI_FLSHA2CR2); 1217 fspi_writel(f, seqid_lut, base + FSPI_FLSHB1CR2); 1218 fspi_writel(f, seqid_lut, base + FSPI_FLSHB2CR2); 1219 1220 f->selected = -1; 1221 1222 /* enable the interrupt */ 1223 fspi_writel(f, FSPI_INTEN_IPCMDDONE, base + FSPI_INTEN); 1224 1225 return 0; 1226} 1227 1228static const char *nxp_fspi_get_name(struct spi_mem *mem) 1229{ 1230 struct nxp_fspi *f = spi_controller_get_devdata(mem->spi->controller); 1231 struct device *dev = &mem->spi->dev; 1232 const char *name; 1233 1234 // Set custom name derived from the platform_device of the controller. 1235 if (of_get_available_child_count(f->dev->of_node) == 1) 1236 return dev_name(f->dev); 1237 1238 name = devm_kasprintf(dev, GFP_KERNEL, 1239 "%s-%d", dev_name(f->dev), 1240 spi_get_chipselect(mem->spi, 0)); 1241 1242 if (!name) { 1243 dev_err(dev, "failed to get memory for custom flash name\n"); 1244 return ERR_PTR(-ENOMEM); 1245 } 1246 1247 return name; 1248} 1249 1250static const struct spi_controller_mem_ops nxp_fspi_mem_ops = { 1251 .adjust_op_size = nxp_fspi_adjust_op_size, 1252 .supports_op = nxp_fspi_supports_op, 1253 .exec_op = nxp_fspi_exec_op, 1254 .get_name = nxp_fspi_get_name, 1255}; 1256 1257static const struct spi_controller_mem_caps nxp_fspi_mem_caps = { 1258 .dtr = true, 1259 .swap16 = false, 1260 .per_op_freq = true, 1261}; 1262 1263static const struct spi_controller_mem_caps nxp_fspi_mem_caps_disable_dtr = { 1264 .dtr = false, 1265 .per_op_freq = true, 1266}; 1267 1268static void nxp_fspi_cleanup(void *data) 1269{ 1270 struct nxp_fspi *f = data; 1271 1272 /* enable clock first since there is register access */ 1273 pm_runtime_get_sync(f->dev); 1274 1275 /* disable the hardware */ 1276 fspi_writel(f, FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0); 1277 1278 pm_runtime_disable(f->dev); 1279 pm_runtime_put_noidle(f->dev); 1280 nxp_fspi_clk_disable_unprep(f); 1281 1282 if (f->ahb_addr) 1283 iounmap(f->ahb_addr); 1284} 1285 1286static int nxp_fspi_probe(struct platform_device *pdev) 1287{ 1288 struct spi_controller *ctlr; 1289 struct device *dev = &pdev->dev; 1290 struct fwnode_handle *fwnode = dev_fwnode(dev); 1291 struct resource *res; 1292 struct nxp_fspi *f; 1293 int ret, irq; 1294 u32 reg; 1295 1296 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*f)); 1297 if (!ctlr) 1298 return -ENOMEM; 1299 1300 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | 1301 SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; 1302 1303 f = spi_controller_get_devdata(ctlr); 1304 f->dev = dev; 1305 f->devtype_data = (struct nxp_fspi_devtype_data *)device_get_match_data(dev); 1306 if (!f->devtype_data) 1307 return -ENODEV; 1308 1309 platform_set_drvdata(pdev, f); 1310 1311 /* find the resources - configuration register address space */ 1312 if (is_acpi_node(fwnode)) 1313 f->iobase = devm_platform_ioremap_resource(pdev, 0); 1314 else 1315 f->iobase = devm_platform_ioremap_resource_byname(pdev, "fspi_base"); 1316 if (IS_ERR(f->iobase)) 1317 return PTR_ERR(f->iobase); 1318 1319 /* find the resources - controller memory mapped space */ 1320 if (is_acpi_node(fwnode)) 1321 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1322 else 1323 res = platform_get_resource_byname(pdev, 1324 IORESOURCE_MEM, "fspi_mmap"); 1325 if (!res) 1326 return -ENODEV; 1327 1328 /* assign memory mapped starting address and mapped size. */ 1329 f->memmap_phy = res->start; 1330 f->memmap_phy_size = resource_size(res); 1331 1332 /* find the clocks */ 1333 if (is_of_node(fwnode)) { 1334 f->clk_en = devm_clk_get(dev, "fspi_en"); 1335 if (IS_ERR(f->clk_en)) 1336 return PTR_ERR(f->clk_en); 1337 1338 f->clk = devm_clk_get(dev, "fspi"); 1339 if (IS_ERR(f->clk)) 1340 return PTR_ERR(f->clk); 1341 } 1342 1343 /* find the irq */ 1344 irq = platform_get_irq(pdev, 0); 1345 if (irq < 0) 1346 return dev_err_probe(dev, irq, "Failed to get irq source"); 1347 1348 pm_runtime_enable(dev); 1349 pm_runtime_set_autosuspend_delay(dev, FSPI_RPM_TIMEOUT); 1350 pm_runtime_use_autosuspend(dev); 1351 1352 /* enable clock */ 1353 ret = pm_runtime_get_sync(f->dev); 1354 if (ret < 0) 1355 return dev_err_probe(dev, ret, "Failed to enable clock"); 1356 1357 /* Clear potential interrupts */ 1358 reg = fspi_readl(f, f->iobase + FSPI_INTR); 1359 if (reg) 1360 fspi_writel(f, reg, f->iobase + FSPI_INTR); 1361 1362 nxp_fspi_default_setup(f); 1363 1364 ret = pm_runtime_put_sync(dev); 1365 if (ret < 0) 1366 return dev_err_probe(dev, ret, "Failed to disable clock"); 1367 1368 ret = devm_request_irq(dev, irq, 1369 nxp_fspi_irq_handler, 0, pdev->name, f); 1370 if (ret) 1371 return dev_err_probe(dev, ret, "Failed to request irq\n"); 1372 1373 ret = devm_mutex_init(dev, &f->lock); 1374 if (ret) 1375 return dev_err_probe(dev, ret, "Failed to initialize lock\n"); 1376 1377 ctlr->bus_num = -1; 1378 ctlr->num_chipselect = NXP_FSPI_MAX_CHIPSELECT; 1379 ctlr->mem_ops = &nxp_fspi_mem_ops; 1380 1381 if (f->devtype_data->quirks & FSPI_QUIRK_DISABLE_DTR) 1382 ctlr->mem_caps = &nxp_fspi_mem_caps_disable_dtr; 1383 else 1384 ctlr->mem_caps = &nxp_fspi_mem_caps; 1385 1386 device_set_node(&ctlr->dev, fwnode); 1387 1388 ret = devm_add_action_or_reset(dev, nxp_fspi_cleanup, f); 1389 if (ret) 1390 return ret; 1391 1392 return devm_spi_register_controller(&pdev->dev, ctlr); 1393} 1394 1395static int nxp_fspi_runtime_suspend(struct device *dev) 1396{ 1397 struct nxp_fspi *f = dev_get_drvdata(dev); 1398 1399 nxp_fspi_clk_disable_unprep(f); 1400 1401 return 0; 1402} 1403 1404static int nxp_fspi_runtime_resume(struct device *dev) 1405{ 1406 struct nxp_fspi *f = dev_get_drvdata(dev); 1407 int ret; 1408 1409 ret = nxp_fspi_clk_prep_enable(f); 1410 if (ret) 1411 return ret; 1412 1413 if (f->flags & FSPI_NEED_INIT) { 1414 nxp_fspi_default_setup(f); 1415 ret = pinctrl_pm_select_default_state(dev); 1416 if (ret) 1417 dev_err(dev, "select flexspi default pinctrl failed!\n"); 1418 f->flags &= ~FSPI_NEED_INIT; 1419 } 1420 1421 return ret; 1422} 1423 1424static int nxp_fspi_suspend(struct device *dev) 1425{ 1426 struct nxp_fspi *f = dev_get_drvdata(dev); 1427 int ret; 1428 1429 ret = pinctrl_pm_select_sleep_state(dev); 1430 if (ret) { 1431 dev_err(dev, "select flexspi sleep pinctrl failed!\n"); 1432 return ret; 1433 } 1434 1435 f->flags |= FSPI_NEED_INIT; 1436 1437 return pm_runtime_force_suspend(dev); 1438} 1439 1440static const struct dev_pm_ops nxp_fspi_pm_ops = { 1441 RUNTIME_PM_OPS(nxp_fspi_runtime_suspend, nxp_fspi_runtime_resume, NULL) 1442 SYSTEM_SLEEP_PM_OPS(nxp_fspi_suspend, pm_runtime_force_resume) 1443}; 1444 1445static const struct of_device_id nxp_fspi_dt_ids[] = { 1446 { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, 1447 { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, 1448 { .compatible = "nxp,imx8mp-fspi", .data = (void *)&imx8mm_data, }, 1449 { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, 1450 { .compatible = "nxp,imx8dxl-fspi", .data = (void *)&imx8dxl_data, }, 1451 { .compatible = "nxp,imx8ulp-fspi", .data = (void *)&imx8ulp_data, }, 1452 { /* sentinel */ } 1453}; 1454MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); 1455 1456#ifdef CONFIG_ACPI 1457static const struct acpi_device_id nxp_fspi_acpi_ids[] = { 1458 { "NXP0009", .driver_data = (kernel_ulong_t)&lx2160a_data, }, 1459 {} 1460}; 1461MODULE_DEVICE_TABLE(acpi, nxp_fspi_acpi_ids); 1462#endif 1463 1464static struct platform_driver nxp_fspi_driver = { 1465 .driver = { 1466 .name = "nxp-fspi", 1467 .of_match_table = nxp_fspi_dt_ids, 1468 .acpi_match_table = ACPI_PTR(nxp_fspi_acpi_ids), 1469 .pm = pm_ptr(&nxp_fspi_pm_ops), 1470 }, 1471 .probe = nxp_fspi_probe, 1472}; 1473module_platform_driver(nxp_fspi_driver); 1474 1475MODULE_DESCRIPTION("NXP FSPI Controller Driver"); 1476MODULE_AUTHOR("NXP Semiconductor"); 1477MODULE_AUTHOR("Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>"); 1478MODULE_AUTHOR("Boris Brezillon <bbrezillon@kernel.org>"); 1479MODULE_AUTHOR("Frieder Schrempf <frieder.schrempf@kontron.de>"); 1480MODULE_LICENSE("GPL v2");
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