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spi-microchip-core-qspi.c
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linux-6.19.14/drivers/spi/spi-microchip-core-qspi.c
1// SPDX-License-Identifier: (GPL-2.0) 2/* 3 * Microchip coreQSPI QSPI controller driver 4 * 5 * Copyright (C) 2018-2022 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> 8 * 9 */ 10 11#include <linux/clk.h> 12#include <linux/err.h> 13#include <linux/init.h> 14#include <linux/interrupt.h> 15#include <linux/io.h> 16#include <linux/iopoll.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/of_irq.h> 20#include <linux/platform_device.h> 21#include <linux/spi/spi.h> 22#include <linux/spi/spi-mem.h> 23 24/* 25 * QSPI Control register mask defines 26 */ 27#define CONTROL_ENABLE BIT(0) 28#define CONTROL_MASTER BIT(1) 29#define CONTROL_XIP BIT(2) 30#define CONTROL_XIPADDR BIT(3) 31#define CONTROL_CLKIDLE BIT(10) 32#define CONTROL_SAMPLE_MASK GENMASK(12, 11) 33#define CONTROL_MODE0 BIT(13) 34#define CONTROL_MODE12_MASK GENMASK(15, 14) 35#define CONTROL_MODE12_EX_RO BIT(14) 36#define CONTROL_MODE12_EX_RW BIT(15) 37#define CONTROL_MODE12_FULL GENMASK(15, 14) 38#define CONTROL_FLAGSX4 BIT(16) 39#define CONTROL_CLKRATE_MASK GENMASK(27, 24) 40#define CONTROL_CLKRATE_SHIFT 24 41 42/* 43 * QSPI Frames register mask defines 44 */ 45#define FRAMES_TOTALBYTES_MASK GENMASK(15, 0) 46#define FRAMES_CMDBYTES_MASK GENMASK(24, 16) 47#define FRAMES_CMDBYTES_SHIFT 16 48#define FRAMES_SHIFT 25 49#define FRAMES_IDLE_MASK GENMASK(29, 26) 50#define FRAMES_IDLE_SHIFT 26 51#define FRAMES_FLAGBYTE BIT(30) 52#define FRAMES_FLAGWORD BIT(31) 53 54/* 55 * QSPI Interrupt Enable register mask defines 56 */ 57#define IEN_TXDONE BIT(0) 58#define IEN_RXDONE BIT(1) 59#define IEN_RXAVAILABLE BIT(2) 60#define IEN_TXAVAILABLE BIT(3) 61#define IEN_RXFIFOEMPTY BIT(4) 62#define IEN_TXFIFOFULL BIT(5) 63 64/* 65 * QSPI Status register mask defines 66 */ 67#define STATUS_TXDONE BIT(0) 68#define STATUS_RXDONE BIT(1) 69#define STATUS_RXAVAILABLE BIT(2) 70#define STATUS_TXAVAILABLE BIT(3) 71#define STATUS_RXFIFOEMPTY BIT(4) 72#define STATUS_TXFIFOFULL BIT(5) 73#define STATUS_READY BIT(7) 74#define STATUS_FLAGSX4 BIT(8) 75#define STATUS_MASK GENMASK(8, 0) 76 77#define BYTESUPPER_MASK GENMASK(31, 16) 78#define BYTESLOWER_MASK GENMASK(15, 0) 79 80#define MAX_DIVIDER 16 81#define MIN_DIVIDER 0 82#define MAX_DATA_CMD_LEN 256 83 84/* QSPI ready time out value */ 85#define TIMEOUT_MS 500 86 87/* 88 * QSPI Register offsets. 89 */ 90#define REG_CONTROL (0x00) 91#define REG_FRAMES (0x04) 92#define REG_IEN (0x0c) 93#define REG_STATUS (0x10) 94#define REG_DIRECT_ACCESS (0x14) 95#define REG_UPPER_ACCESS (0x18) 96#define REG_RX_DATA (0x40) 97#define REG_TX_DATA (0x44) 98#define REG_X4_RX_DATA (0x48) 99#define REG_X4_TX_DATA (0x4c) 100#define REG_FRAMESUP (0x50) 101 102/** 103 * struct mchp_coreqspi - Defines qspi driver instance 104 * @regs: Virtual address of the QSPI controller registers 105 * @clk: QSPI Operating clock 106 * @data_completion: completion structure 107 * @op_lock: lock access to the device 108 * @txbuf: TX buffer 109 * @rxbuf: RX buffer 110 * @irq: IRQ number 111 * @tx_len: Number of bytes left to transfer 112 * @rx_len: Number of bytes left to receive 113 */ 114struct mchp_coreqspi { 115 void __iomem *regs; 116 struct clk *clk; 117 struct completion data_completion; 118 struct mutex op_lock; /* lock access to the device */ 119 u8 *txbuf; 120 u8 *rxbuf; 121 int irq; 122 int tx_len; 123 int rx_len; 124}; 125 126static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_mem_op *op) 127{ 128 u32 control = readl_relaxed(qspi->regs + REG_CONTROL); 129 130 /* 131 * The operating mode can be configured based on the command that needs to be send. 132 * bits[15:14]: Sets whether multiple bit SPI operates in normal, extended or full modes. 133 * 00: Normal (single DQ0 TX and single DQ1 RX lines) 134 * 01: Extended RO (command and address bytes on DQ0 only) 135 * 10: Extended RW (command byte on DQ0 only) 136 * 11: Full. (command and address are on all DQ lines) 137 * bit[13]: Sets whether multiple bit SPI uses 2 or 4 bits of data 138 * 0: 2-bits (BSPI) 139 * 1: 4-bits (QSPI) 140 */ 141 if (op->data.buswidth == 4 || op->data.buswidth == 2) { 142 control &= ~CONTROL_MODE12_MASK; 143 if (op->cmd.buswidth == 1 && (op->addr.buswidth == 1 || op->addr.buswidth == 0)) 144 control |= CONTROL_MODE12_EX_RO; 145 else if (op->cmd.buswidth == 1) 146 control |= CONTROL_MODE12_EX_RW; 147 else 148 control |= CONTROL_MODE12_FULL; 149 150 control |= CONTROL_MODE0; 151 } else { 152 control &= ~(CONTROL_MODE12_MASK | 153 CONTROL_MODE0); 154 } 155 156 writel_relaxed(control, qspi->regs + REG_CONTROL); 157 158 return 0; 159} 160 161static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) 162{ 163 u32 control, data; 164 165 if (!qspi->rx_len) 166 return; 167 168 control = readl_relaxed(qspi->regs + REG_CONTROL); 169 170 /* 171 * Read 4-bytes from the SPI FIFO in single transaction and then read 172 * the reamaining data byte wise. 173 */ 174 control |= CONTROL_FLAGSX4; 175 writel_relaxed(control, qspi->regs + REG_CONTROL); 176 177 while (qspi->rx_len >= 4) { 178 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) 179 ; 180 data = readl_relaxed(qspi->regs + REG_X4_RX_DATA); 181 *(u32 *)qspi->rxbuf = data; 182 qspi->rxbuf += 4; 183 qspi->rx_len -= 4; 184 } 185 186 control &= ~CONTROL_FLAGSX4; 187 writel_relaxed(control, qspi->regs + REG_CONTROL); 188 189 while (qspi->rx_len--) { 190 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) 191 ; 192 data = readl_relaxed(qspi->regs + REG_RX_DATA); 193 *qspi->rxbuf++ = (data & 0xFF); 194 } 195} 196 197static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi) 198{ 199 u32 control, data; 200 201 control = readl_relaxed(qspi->regs + REG_CONTROL); 202 control |= CONTROL_FLAGSX4; 203 writel_relaxed(control, qspi->regs + REG_CONTROL); 204 205 while (qspi->tx_len >= 4) { 206 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) 207 ; 208 data = *(u32 *)qspi->txbuf; 209 qspi->txbuf += 4; 210 qspi->tx_len -= 4; 211 writel_relaxed(data, qspi->regs + REG_X4_TX_DATA); 212 } 213 214 control &= ~CONTROL_FLAGSX4; 215 writel_relaxed(control, qspi->regs + REG_CONTROL); 216 217 while (qspi->tx_len--) { 218 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) 219 ; 220 data = *qspi->txbuf++; 221 writel_relaxed(data, qspi->regs + REG_TX_DATA); 222 } 223} 224 225static inline void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi) 226{ 227 u32 control, data; 228 229 qspi->rx_len = qspi->tx_len; 230 231 control = readl_relaxed(qspi->regs + REG_CONTROL); 232 control |= CONTROL_FLAGSX4; 233 writel_relaxed(control, qspi->regs + REG_CONTROL); 234 235 while (qspi->tx_len >= 4) { 236 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) 237 ; 238 239 data = qspi->txbuf ? *((u32 *)qspi->txbuf) : 0xaa; 240 if (qspi->txbuf) 241 qspi->txbuf += 4; 242 qspi->tx_len -= 4; 243 writel_relaxed(data, qspi->regs + REG_X4_TX_DATA); 244 245 /* 246 * The rx FIFO is twice the size of the tx FIFO, so there is 247 * no requirement to block transmission if receive data is not 248 * ready, and it is fine to let the tx FIFO completely fill 249 * without reading anything from the rx FIFO. Once the tx FIFO 250 * has been filled and becomes non-full due to a transmission 251 * occurring there will always be something to receive. 252 * IOW, this is safe as TX_FIFO_SIZE + 4 < 2 * TX_FIFO_SIZE 253 */ 254 if (qspi->rx_len >= 4) { 255 if (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXAVAILABLE) { 256 data = readl_relaxed(qspi->regs + REG_X4_RX_DATA); 257 *(u32 *)qspi->rxbuf = data; 258 qspi->rxbuf += 4; 259 qspi->rx_len -= 4; 260 } 261 } 262 } 263 264 /* 265 * Since transmission is not being blocked by clearing the rx FIFO, 266 * loop here until all received data "leaked" by the loop above has 267 * been dealt with. 268 */ 269 while (qspi->rx_len >= 4) { 270 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) 271 ; 272 data = readl_relaxed(qspi->regs + REG_X4_RX_DATA); 273 *(u32 *)qspi->rxbuf = data; 274 qspi->rxbuf += 4; 275 qspi->rx_len -= 4; 276 } 277 278 /* 279 * Since rx_len and tx_len must be < 4 bytes at this point, there's no 280 * concern about overflowing the rx or tx FIFOs any longer. It's 281 * therefore safe to loop over the remainder of the transmit data before 282 * handling the remaining receive data. 283 */ 284 if (!qspi->tx_len) 285 return; 286 287 control &= ~CONTROL_FLAGSX4; 288 writel_relaxed(control, qspi->regs + REG_CONTROL); 289 290 while (qspi->tx_len--) { 291 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) 292 ; 293 data = qspi->txbuf ? *qspi->txbuf : 0xaa; 294 qspi->txbuf++; 295 writel_relaxed(data, qspi->regs + REG_TX_DATA); 296 } 297 298 while (qspi->rx_len--) { 299 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) 300 ; 301 data = readl_relaxed(qspi->regs + REG_RX_DATA); 302 *qspi->rxbuf++ = (data & 0xFF); 303 } 304} 305 306static void mchp_coreqspi_enable_ints(struct mchp_coreqspi *qspi) 307{ 308 u32 mask = IEN_TXDONE | 309 IEN_RXDONE | 310 IEN_RXAVAILABLE; 311 312 writel_relaxed(mask, qspi->regs + REG_IEN); 313} 314 315static void mchp_coreqspi_disable_ints(struct mchp_coreqspi *qspi) 316{ 317 writel_relaxed(0, qspi->regs + REG_IEN); 318} 319 320static irqreturn_t mchp_coreqspi_isr(int irq, void *dev_id) 321{ 322 struct mchp_coreqspi *qspi = (struct mchp_coreqspi *)dev_id; 323 irqreturn_t ret = IRQ_NONE; 324 int intfield = readl_relaxed(qspi->regs + REG_STATUS) & STATUS_MASK; 325 326 if (intfield == 0) 327 return ret; 328 329 if (intfield & IEN_TXDONE) { 330 writel_relaxed(IEN_TXDONE, qspi->regs + REG_STATUS); 331 ret = IRQ_HANDLED; 332 } 333 334 if (intfield & IEN_RXAVAILABLE) { 335 writel_relaxed(IEN_RXAVAILABLE, qspi->regs + REG_STATUS); 336 mchp_coreqspi_read_op(qspi); 337 ret = IRQ_HANDLED; 338 } 339 340 if (intfield & IEN_RXDONE) { 341 writel_relaxed(IEN_RXDONE, qspi->regs + REG_STATUS); 342 complete(&qspi->data_completion); 343 ret = IRQ_HANDLED; 344 } 345 346 return ret; 347} 348 349static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_device *spi, 350 u32 max_freq) 351{ 352 unsigned long clk_hz; 353 u32 control, baud_rate_val = 0; 354 355 clk_hz = clk_get_rate(qspi->clk); 356 if (!clk_hz) 357 return -EINVAL; 358 359 baud_rate_val = DIV_ROUND_UP(clk_hz, 2 * max_freq); 360 if (baud_rate_val > MAX_DIVIDER || baud_rate_val < MIN_DIVIDER) { 361 dev_err(&spi->dev, 362 "could not configure the clock for spi clock %d Hz & system clock %ld Hz\n", 363 max_freq, clk_hz); 364 return -EINVAL; 365 } 366 367 control = readl_relaxed(qspi->regs + REG_CONTROL); 368 control &= ~CONTROL_CLKRATE_MASK; 369 control |= baud_rate_val << CONTROL_CLKRATE_SHIFT; 370 writel_relaxed(control, qspi->regs + REG_CONTROL); 371 control = readl_relaxed(qspi->regs + REG_CONTROL); 372 373 if ((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) 374 control |= CONTROL_CLKIDLE; 375 else 376 control &= ~CONTROL_CLKIDLE; 377 378 writel_relaxed(control, qspi->regs + REG_CONTROL); 379 380 return 0; 381} 382 383static int mchp_coreqspi_setup_op(struct spi_device *spi_dev) 384{ 385 struct spi_controller *ctlr = spi_dev->controller; 386 struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr); 387 u32 control = readl_relaxed(qspi->regs + REG_CONTROL); 388 389 control |= (CONTROL_MASTER | CONTROL_ENABLE); 390 control &= ~CONTROL_CLKIDLE; 391 writel_relaxed(control, qspi->regs + REG_CONTROL); 392 393 return 0; 394} 395 396static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op) 397{ 398 u32 idle_cycles = 0; 399 int total_bytes, cmd_bytes, frames, ctrl; 400 401 cmd_bytes = op->cmd.nbytes + op->addr.nbytes; 402 total_bytes = cmd_bytes + op->data.nbytes; 403 404 /* 405 * As per the coreQSPI IP spec,the number of command and data bytes are 406 * controlled by the frames register for each SPI sequence. This supports 407 * the SPI flash memory read and writes sequences as below. so configure 408 * the cmd and total bytes accordingly. 409 * --------------------------------------------------------------------- 410 * TOTAL BYTES | CMD BYTES | What happens | 411 * ______________________________________________________________________ 412 * | | | 413 * 1 | 1 | The SPI core will transmit a single byte | 414 * | | and receive data is discarded | 415 * | | | 416 * 1 | 0 | The SPI core will transmit a single byte | 417 * | | and return a single byte | 418 * | | | 419 * 10 | 4 | The SPI core will transmit 4 command | 420 * | | bytes discarding the receive data and | 421 * | | transmits 6 dummy bytes returning the 6 | 422 * | | received bytes and return a single byte | 423 * | | | 424 * 10 | 10 | The SPI core will transmit 10 command | 425 * | | | 426 * 10 | 0 | The SPI core will transmit 10 command | 427 * | | bytes and returning 10 received bytes | 428 * ______________________________________________________________________ 429 */ 430 if (!(op->data.dir == SPI_MEM_DATA_IN)) 431 cmd_bytes = total_bytes; 432 433 frames = total_bytes & BYTESUPPER_MASK; 434 writel_relaxed(frames, qspi->regs + REG_FRAMESUP); 435 frames = total_bytes & BYTESLOWER_MASK; 436 frames |= cmd_bytes << FRAMES_CMDBYTES_SHIFT; 437 438 if (op->dummy.buswidth) 439 idle_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; 440 441 frames |= idle_cycles << FRAMES_IDLE_SHIFT; 442 ctrl = readl_relaxed(qspi->regs + REG_CONTROL); 443 444 if (ctrl & CONTROL_MODE12_MASK) 445 frames |= (1 << FRAMES_SHIFT); 446 447 frames |= FRAMES_FLAGWORD; 448 writel_relaxed(frames, qspi->regs + REG_FRAMES); 449} 450 451static int mchp_coreqspi_wait_for_ready(struct mchp_coreqspi *qspi) 452{ 453 u32 status; 454 455 return readl_poll_timeout(qspi->regs + REG_STATUS, status, 456 (status & STATUS_READY), 0, 457 TIMEOUT_MS); 458} 459 460static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 461{ 462 struct mchp_coreqspi *qspi = spi_controller_get_devdata 463 (mem->spi->controller); 464 u32 address = op->addr.val; 465 u8 opcode = op->cmd.opcode; 466 u8 opaddr[5]; 467 int err, i; 468 469 mutex_lock(&qspi->op_lock); 470 err = mchp_coreqspi_wait_for_ready(qspi); 471 if (err) { 472 dev_err(&mem->spi->dev, "Timeout waiting on QSPI ready.\n"); 473 goto error; 474 } 475 476 err = mchp_coreqspi_setup_clock(qspi, mem->spi, op->max_freq); 477 if (err) 478 goto error; 479 480 err = mchp_coreqspi_set_mode(qspi, op); 481 if (err) 482 goto error; 483 484 reinit_completion(&qspi->data_completion); 485 mchp_coreqspi_config_op(qspi, op); 486 if (op->cmd.opcode) { 487 qspi->txbuf = &opcode; 488 qspi->rxbuf = NULL; 489 qspi->tx_len = op->cmd.nbytes; 490 qspi->rx_len = 0; 491 mchp_coreqspi_write_op(qspi); 492 } 493 494 qspi->txbuf = &opaddr[0]; 495 if (op->addr.nbytes) { 496 for (i = 0; i < op->addr.nbytes; i++) 497 qspi->txbuf[i] = address >> (8 * (op->addr.nbytes - i - 1)); 498 499 qspi->rxbuf = NULL; 500 qspi->tx_len = op->addr.nbytes; 501 qspi->rx_len = 0; 502 mchp_coreqspi_write_op(qspi); 503 } 504 505 if (op->data.nbytes) { 506 if (op->data.dir == SPI_MEM_DATA_OUT) { 507 qspi->txbuf = (u8 *)op->data.buf.out; 508 qspi->rxbuf = NULL; 509 qspi->rx_len = 0; 510 qspi->tx_len = op->data.nbytes; 511 mchp_coreqspi_write_op(qspi); 512 } else { 513 qspi->txbuf = NULL; 514 qspi->rxbuf = (u8 *)op->data.buf.in; 515 qspi->rx_len = op->data.nbytes; 516 qspi->tx_len = 0; 517 } 518 } 519 520 mchp_coreqspi_enable_ints(qspi); 521 522 if (!wait_for_completion_timeout(&qspi->data_completion, msecs_to_jiffies(1000))) 523 err = -ETIMEDOUT; 524 525error: 526 mutex_unlock(&qspi->op_lock); 527 mchp_coreqspi_disable_ints(qspi); 528 529 return err; 530} 531 532static bool mchp_coreqspi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) 533{ 534 if (!spi_mem_default_supports_op(mem, op)) 535 return false; 536 537 if ((op->data.buswidth == 4 || op->data.buswidth == 2) && 538 (op->cmd.buswidth == 1 && (op->addr.buswidth == 1 || op->addr.buswidth == 0))) { 539 /* 540 * If the command and address are on DQ0 only, then this 541 * controller doesn't support sending data on dual and 542 * quad lines. but it supports reading data on dual and 543 * quad lines with same configuration as command and 544 * address on DQ0. 545 * i.e. The control register[15:13] :EX_RO(read only) is 546 * meant only for the command and address are on DQ0 but 547 * not to write data, it is just to read. 548 * Ex: 0x34h is Quad Load Program Data which is not 549 * supported. Then the spi-mem layer will iterate over 550 * each command and it will chose the supported one. 551 */ 552 if (op->data.dir == SPI_MEM_DATA_OUT) 553 return false; 554 } 555 556 return true; 557} 558 559static int mchp_coreqspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 560{ 561 if (op->data.dir == SPI_MEM_DATA_OUT || op->data.dir == SPI_MEM_DATA_IN) { 562 if (op->data.nbytes > MAX_DATA_CMD_LEN) 563 op->data.nbytes = MAX_DATA_CMD_LEN; 564 } 565 566 return 0; 567} 568 569static const struct spi_controller_mem_ops mchp_coreqspi_mem_ops = { 570 .adjust_op_size = mchp_coreqspi_adjust_op_size, 571 .supports_op = mchp_coreqspi_supports_op, 572 .exec_op = mchp_coreqspi_exec_op, 573}; 574 575static const struct spi_controller_mem_caps mchp_coreqspi_mem_caps = { 576 .per_op_freq = true, 577}; 578 579static int mchp_coreqspi_unprepare_message(struct spi_controller *ctlr, struct spi_message *m) 580{ 581 struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr); 582 583 /* 584 * This delay is required for the driver to function correctly, 585 * but no explanation has been determined for why it is required. 586 */ 587 udelay(750); 588 589 mutex_unlock(&qspi->op_lock); 590 591 return 0; 592} 593 594static int mchp_coreqspi_prepare_message(struct spi_controller *ctlr, struct spi_message *m) 595{ 596 struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr); 597 struct spi_transfer *t = NULL; 598 u32 control, frames; 599 u32 total_bytes = 0, cmd_bytes = 0, idle_cycles = 0; 600 int ret; 601 bool quad = false, dual = false; 602 603 mutex_lock(&qspi->op_lock); 604 ret = mchp_coreqspi_wait_for_ready(qspi); 605 if (ret) { 606 mutex_unlock(&qspi->op_lock); 607 dev_err(&ctlr->dev, "Timeout waiting on QSPI ready.\n"); 608 return ret; 609 } 610 611 ret = mchp_coreqspi_setup_clock(qspi, m->spi, m->spi->max_speed_hz); 612 if (ret) { 613 mutex_unlock(&qspi->op_lock); 614 return ret; 615 } 616 617 control = readl_relaxed(qspi->regs + REG_CONTROL); 618 control &= ~(CONTROL_MODE12_MASK | CONTROL_MODE0); 619 writel_relaxed(control, qspi->regs + REG_CONTROL); 620 621 reinit_completion(&qspi->data_completion); 622 623 list_for_each_entry(t, &m->transfers, transfer_list) { 624 total_bytes += t->len; 625 if (!cmd_bytes && !(t->tx_buf && t->rx_buf)) 626 cmd_bytes = t->len; 627 if (!t->rx_buf) 628 cmd_bytes = total_bytes; 629 if (t->tx_nbits == SPI_NBITS_QUAD || t->rx_nbits == SPI_NBITS_QUAD) 630 quad = true; 631 else if (t->tx_nbits == SPI_NBITS_DUAL || t->rx_nbits == SPI_NBITS_DUAL) 632 dual = true; 633 } 634 635 control = readl_relaxed(qspi->regs + REG_CONTROL); 636 if (quad) { 637 control |= (CONTROL_MODE0 | CONTROL_MODE12_EX_RW); 638 } else if (dual) { 639 control &= ~CONTROL_MODE0; 640 control |= CONTROL_MODE12_FULL; 641 } else { 642 control &= ~(CONTROL_MODE12_MASK | CONTROL_MODE0); 643 } 644 writel_relaxed(control, qspi->regs + REG_CONTROL); 645 646 frames = total_bytes & BYTESUPPER_MASK; 647 writel_relaxed(frames, qspi->regs + REG_FRAMESUP); 648 frames = total_bytes & BYTESLOWER_MASK; 649 frames |= cmd_bytes << FRAMES_CMDBYTES_SHIFT; 650 frames |= idle_cycles << FRAMES_IDLE_SHIFT; 651 control = readl_relaxed(qspi->regs + REG_CONTROL); 652 if (control & CONTROL_MODE12_MASK) 653 frames |= (1 << FRAMES_SHIFT); 654 655 frames |= FRAMES_FLAGWORD; 656 writel_relaxed(frames, qspi->regs + REG_FRAMES); 657 658 return 0; 659}; 660 661static int mchp_coreqspi_transfer_one(struct spi_controller *ctlr, struct spi_device *spi, 662 struct spi_transfer *t) 663{ 664 struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr); 665 666 qspi->tx_len = t->len; 667 668 if (t->tx_buf) 669 qspi->txbuf = (u8 *)t->tx_buf; 670 671 if (!t->rx_buf) { 672 mchp_coreqspi_write_op(qspi); 673 } else { 674 qspi->rxbuf = (u8 *)t->rx_buf; 675 qspi->rx_len = t->len; 676 mchp_coreqspi_write_read_op(qspi); 677 } 678 679 return 0; 680} 681 682static int mchp_coreqspi_probe(struct platform_device *pdev) 683{ 684 struct spi_controller *ctlr; 685 struct mchp_coreqspi *qspi; 686 struct device *dev = &pdev->dev; 687 struct device_node *np = dev->of_node; 688 int ret; 689 690 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*qspi)); 691 if (!ctlr) 692 return -ENOMEM; 693 694 qspi = spi_controller_get_devdata(ctlr); 695 platform_set_drvdata(pdev, qspi); 696 697 qspi->regs = devm_platform_ioremap_resource(pdev, 0); 698 if (IS_ERR(qspi->regs)) 699 return dev_err_probe(&pdev->dev, PTR_ERR(qspi->regs), 700 "failed to map registers\n"); 701 702 qspi->clk = devm_clk_get_enabled(&pdev->dev, NULL); 703 if (IS_ERR(qspi->clk)) 704 return dev_err_probe(&pdev->dev, PTR_ERR(qspi->clk), 705 "could not get clock\n"); 706 707 init_completion(&qspi->data_completion); 708 mutex_init(&qspi->op_lock); 709 710 qspi->irq = platform_get_irq(pdev, 0); 711 if (qspi->irq < 0) 712 return qspi->irq; 713 714 ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr, 715 IRQF_SHARED, pdev->name, qspi); 716 if (ret) { 717 dev_err(&pdev->dev, "request_irq failed %d\n", ret); 718 return ret; 719 } 720 721 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); 722 ctlr->mem_ops = &mchp_coreqspi_mem_ops; 723 ctlr->mem_caps = &mchp_coreqspi_mem_caps; 724 ctlr->setup = mchp_coreqspi_setup_op; 725 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | 726 SPI_TX_DUAL | SPI_TX_QUAD; 727 ctlr->dev.of_node = np; 728 ctlr->min_speed_hz = clk_get_rate(qspi->clk) / 30; 729 ctlr->prepare_message = mchp_coreqspi_prepare_message; 730 ctlr->unprepare_message = mchp_coreqspi_unprepare_message; 731 ctlr->transfer_one = mchp_coreqspi_transfer_one; 732 ctlr->num_chipselect = 2; 733 ctlr->use_gpio_descriptors = true; 734 735 ret = devm_spi_register_controller(&pdev->dev, ctlr); 736 if (ret) 737 return dev_err_probe(&pdev->dev, ret, 738 "spi_register_controller failed\n"); 739 740 return 0; 741} 742 743static void mchp_coreqspi_remove(struct platform_device *pdev) 744{ 745 struct mchp_coreqspi *qspi = platform_get_drvdata(pdev); 746 u32 control = readl_relaxed(qspi->regs + REG_CONTROL); 747 748 mchp_coreqspi_disable_ints(qspi); 749 control &= ~CONTROL_ENABLE; 750 writel_relaxed(control, qspi->regs + REG_CONTROL); 751} 752 753static const struct of_device_id mchp_coreqspi_of_match[] = { 754 { .compatible = "microchip,coreqspi-rtl-v2" }, 755 { /* sentinel */ } 756}; 757MODULE_DEVICE_TABLE(of, mchp_coreqspi_of_match); 758 759static struct platform_driver mchp_coreqspi_driver = { 760 .probe = mchp_coreqspi_probe, 761 .driver = { 762 .name = "microchip,coreqspi", 763 .of_match_table = mchp_coreqspi_of_match, 764 }, 765 .remove = mchp_coreqspi_remove, 766}; 767module_platform_driver(mchp_coreqspi_driver); 768 769MODULE_AUTHOR("Naga Sureshkumar Relli <nagasuresh.relli@microchip.com"); 770MODULE_DESCRIPTION("Microchip coreQSPI QSPI controller driver"); 771MODULE_LICENSE("GPL");
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