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spi-imx.c
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linux-6.19.14/drivers/spi/spi-imx.c
1// SPDX-License-Identifier: GPL-2.0+ 2// Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3// Copyright (C) 2008 Juergen Beisert 4 5#include <linux/bits.h> 6#include <linux/bitfield.h> 7#include <linux/clk.h> 8#include <linux/completion.h> 9#include <linux/delay.h> 10#include <linux/dmaengine.h> 11#include <linux/dma-mapping.h> 12#include <linux/err.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/irq.h> 16#include <linux/kernel.h> 17#include <linux/math.h> 18#include <linux/math64.h> 19#include <linux/module.h> 20#include <linux/overflow.h> 21#include <linux/pinctrl/consumer.h> 22#include <linux/platform_device.h> 23#include <linux/pm_runtime.h> 24#include <linux/slab.h> 25#include <linux/spi/spi.h> 26#include <linux/types.h> 27#include <linux/of.h> 28#include <linux/property.h> 29 30#include <linux/dma/imx-dma.h> 31 32#define DRIVER_NAME "spi_imx" 33 34static bool use_dma = true; 35module_param(use_dma, bool, 0644); 36MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)"); 37 38/* define polling limits */ 39static unsigned int polling_limit_us = 30; 40module_param(polling_limit_us, uint, 0664); 41MODULE_PARM_DESC(polling_limit_us, 42 "time in us to run a transfer in polling mode\n"); 43 44#define MXC_RPM_TIMEOUT 2000 /* 2000ms */ 45#define MXC_SPI_DEFAULT_SPEED 500000 /* 500KHz */ 46 47#define MXC_CSPIRXDATA 0x00 48#define MXC_CSPITXDATA 0x04 49#define MXC_CSPICTRL 0x08 50#define MXC_CSPIINT 0x0c 51#define MXC_RESET 0x1c 52 53/* generic defines to abstract from the different register layouts */ 54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ 55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ 56#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */ 57 58/* The maximum bytes that a sdma BD can transfer. */ 59#define MAX_SDMA_BD_BYTES (1 << 15) 60#define MX51_ECSPI_CTRL_MAX_BURST 512 61/* The maximum bytes that IMX53_ECSPI can transfer in target mode.*/ 62#define MX53_MAX_TRANSFER_BYTES 512 63 64enum spi_imx_devtype { 65 IMX1_CSPI, 66 IMX21_CSPI, 67 IMX27_CSPI, 68 IMX31_CSPI, 69 IMX35_CSPI, /* CSPI on all i.mx except above */ 70 IMX51_ECSPI, /* ECSPI on i.mx51 */ 71 IMX53_ECSPI, /* ECSPI on i.mx53 and later */ 72}; 73 74struct spi_imx_data; 75 76struct spi_imx_devtype_data { 77 void (*intctrl)(struct spi_imx_data *spi_imx, int enable); 78 int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg); 79 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi, 80 struct spi_transfer *t); 81 void (*trigger)(struct spi_imx_data *spi_imx); 82 int (*rx_available)(struct spi_imx_data *spi_imx); 83 void (*reset)(struct spi_imx_data *spi_imx); 84 void (*setup_wml)(struct spi_imx_data *spi_imx); 85 void (*disable)(struct spi_imx_data *spi_imx); 86 bool has_dmamode; 87 bool has_targetmode; 88 unsigned int fifo_size; 89 bool dynamic_burst; 90 /* 91 * ERR009165 fixed or not: 92 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf 93 */ 94 bool tx_glitch_fixed; 95 enum spi_imx_devtype devtype; 96}; 97 98struct spi_imx_data { 99 struct spi_controller *controller; 100 struct device *dev; 101 102 struct completion xfer_done; 103 void __iomem *base; 104 unsigned long base_phys; 105 106 struct clk *clk_per; 107 struct clk *clk_ipg; 108 unsigned long spi_clk; 109 unsigned int spi_bus_clk; 110 111 unsigned int bits_per_word; 112 unsigned int spi_drctl; 113 114 unsigned int count, remainder; 115 void (*tx)(struct spi_imx_data *spi_imx); 116 void (*rx)(struct spi_imx_data *spi_imx); 117 void *rx_buf; 118 const void *tx_buf; 119 unsigned int txfifo; /* number of words pushed in tx FIFO */ 120 unsigned int dynamic_burst; 121 bool rx_only; 122 123 /* Target mode */ 124 bool target_mode; 125 bool target_aborted; 126 unsigned int target_burst; 127 128 /* DMA */ 129 bool usedma; 130 u32 wml; 131 struct completion dma_rx_completion; 132 struct completion dma_tx_completion; 133 134 const struct spi_imx_devtype_data *devtype_data; 135}; 136 137static inline int is_imx27_cspi(struct spi_imx_data *d) 138{ 139 return d->devtype_data->devtype == IMX27_CSPI; 140} 141 142static inline int is_imx35_cspi(struct spi_imx_data *d) 143{ 144 return d->devtype_data->devtype == IMX35_CSPI; 145} 146 147static inline int is_imx51_ecspi(struct spi_imx_data *d) 148{ 149 return d->devtype_data->devtype == IMX51_ECSPI; 150} 151 152static inline int is_imx53_ecspi(struct spi_imx_data *d) 153{ 154 return d->devtype_data->devtype == IMX53_ECSPI; 155} 156 157#define MXC_SPI_BUF_RX(type) \ 158static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ 159{ \ 160 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ 161 \ 162 if (spi_imx->rx_buf) { \ 163 *(type *)spi_imx->rx_buf = val; \ 164 spi_imx->rx_buf += sizeof(type); \ 165 } \ 166 \ 167 spi_imx->remainder -= sizeof(type); \ 168} 169 170#define MXC_SPI_BUF_TX(type) \ 171static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ 172{ \ 173 type val = 0; \ 174 \ 175 if (spi_imx->tx_buf) { \ 176 val = *(type *)spi_imx->tx_buf; \ 177 spi_imx->tx_buf += sizeof(type); \ 178 } \ 179 \ 180 spi_imx->count -= sizeof(type); \ 181 \ 182 writel(val, spi_imx->base + MXC_CSPITXDATA); \ 183} 184 185MXC_SPI_BUF_RX(u8) 186MXC_SPI_BUF_TX(u8) 187MXC_SPI_BUF_RX(u16) 188MXC_SPI_BUF_TX(u16) 189MXC_SPI_BUF_RX(u32) 190MXC_SPI_BUF_TX(u32) 191 192/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set 193 * (which is currently not the case in this driver) 194 */ 195static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, 196 256, 384, 512, 768, 1024}; 197 198/* MX21, MX27 */ 199static unsigned int spi_imx_clkdiv_1(unsigned int fin, 200 unsigned int fspi, unsigned int max, unsigned int *fres) 201{ 202 int i; 203 204 for (i = 2; i < max; i++) 205 if (fspi * mxc_clkdivs[i] >= fin) 206 break; 207 208 *fres = fin / mxc_clkdivs[i]; 209 return i; 210} 211 212/* MX1, MX31, MX35, MX51 CSPI */ 213static unsigned int spi_imx_clkdiv_2(unsigned int fin, 214 unsigned int fspi, unsigned int *fres) 215{ 216 int i, div = 4; 217 218 for (i = 0; i < 7; i++) { 219 if (fspi * div >= fin) 220 goto out; 221 div <<= 1; 222 } 223 224out: 225 *fres = fin / div; 226 return i; 227} 228 229static int spi_imx_bytes_per_word(const int bits_per_word) 230{ 231 if (bits_per_word <= 8) 232 return 1; 233 else if (bits_per_word <= 16) 234 return 2; 235 else 236 return 4; 237} 238 239static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi, 240 struct spi_transfer *transfer) 241{ 242 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 243 244 if (!use_dma || controller->fallback) 245 return false; 246 247 if (!controller->dma_rx) 248 return false; 249 250 if (spi_imx->target_mode) 251 return false; 252 253 if (transfer->len < spi_imx->devtype_data->fifo_size) 254 return false; 255 256 spi_imx->dynamic_burst = 0; 257 258 return true; 259} 260 261/* 262 * Note the number of natively supported chip selects for MX51 is 4. Some 263 * devices may have less actual SS pins but the register map supports 4. When 264 * using gpio chip selects the cs values passed into the macros below can go 265 * outside the range 0 - 3. We therefore need to limit the cs value to avoid 266 * corrupting bits outside the allocated locations. 267 * 268 * The simplest way to do this is to just mask the cs bits to 2 bits. This 269 * still allows all 4 native chip selects to work as well as gpio chip selects 270 * (which can use any of the 4 chip select configurations). 271 */ 272 273#define MX51_ECSPI_CTRL 0x08 274#define MX51_ECSPI_CTRL_ENABLE (1 << 0) 275#define MX51_ECSPI_CTRL_XCH (1 << 2) 276#define MX51_ECSPI_CTRL_SMC (1 << 3) 277#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) 278#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) 279#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 280#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 281#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18) 282#define MX51_ECSPI_CTRL_BL_OFFSET 20 283#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) 284 285#define MX51_ECSPI_CONFIG 0x0c 286#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0)) 287#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4)) 288#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8)) 289#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12)) 290#define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16)) 291#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20)) 292 293#define MX51_ECSPI_INT 0x10 294#define MX51_ECSPI_INT_TEEN (1 << 0) 295#define MX51_ECSPI_INT_RREN (1 << 3) 296#define MX51_ECSPI_INT_RDREN (1 << 4) 297 298#define MX51_ECSPI_DMA 0x14 299#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f) 300#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16) 301#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24) 302 303#define MX51_ECSPI_DMA_TEDEN (1 << 7) 304#define MX51_ECSPI_DMA_RXDEN (1 << 23) 305#define MX51_ECSPI_DMA_RXTDEN (1 << 31) 306 307#define MX51_ECSPI_STAT 0x18 308#define MX51_ECSPI_STAT_RR (1 << 3) 309 310#define MX51_ECSPI_PERIOD 0x1c 311#define MX51_ECSPI_PERIOD_MASK 0x7fff 312/* 313 * As measured on the i.MX6, the SPI host controller inserts a 4 SPI-Clock 314 * (SCLK) delay after each burst if the PERIOD reg is 0x0. This value will be 315 * called MX51_ECSPI_PERIOD_MIN_DELAY_SCK. 316 * 317 * If the PERIOD register is != 0, the controller inserts a delay of 318 * MX51_ECSPI_PERIOD_MIN_DELAY_SCK + register value + 1 SCLK after each burst. 319 */ 320#define MX51_ECSPI_PERIOD_MIN_DELAY_SCK 4 321 322#define MX51_ECSPI_TESTREG 0x20 323#define MX51_ECSPI_TESTREG_LBC BIT(31) 324 325static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) 326{ 327 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); 328 329 if (spi_imx->rx_buf) { 330#ifdef __LITTLE_ENDIAN 331 unsigned int bytes_per_word; 332 333 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 334 if (bytes_per_word == 1) 335 swab32s(&val); 336 else if (bytes_per_word == 2) 337 swahw32s(&val); 338#endif 339 *(u32 *)spi_imx->rx_buf = val; 340 spi_imx->rx_buf += sizeof(u32); 341 } 342 343 spi_imx->remainder -= sizeof(u32); 344} 345 346static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) 347{ 348 int unaligned; 349 u32 val; 350 351 unaligned = spi_imx->remainder % 4; 352 353 if (!unaligned) { 354 spi_imx_buf_rx_swap_u32(spi_imx); 355 return; 356 } 357 358 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 359 spi_imx_buf_rx_u16(spi_imx); 360 return; 361 } 362 363 val = readl(spi_imx->base + MXC_CSPIRXDATA); 364 365 while (unaligned--) { 366 if (spi_imx->rx_buf) { 367 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; 368 spi_imx->rx_buf++; 369 } 370 spi_imx->remainder--; 371 } 372} 373 374static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) 375{ 376 u32 val = 0; 377#ifdef __LITTLE_ENDIAN 378 unsigned int bytes_per_word; 379#endif 380 381 if (spi_imx->tx_buf) { 382 val = *(u32 *)spi_imx->tx_buf; 383 spi_imx->tx_buf += sizeof(u32); 384 } 385 386 spi_imx->count -= sizeof(u32); 387#ifdef __LITTLE_ENDIAN 388 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 389 390 if (bytes_per_word == 1) 391 swab32s(&val); 392 else if (bytes_per_word == 2) 393 swahw32s(&val); 394#endif 395 writel(val, spi_imx->base + MXC_CSPITXDATA); 396} 397 398static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) 399{ 400 int unaligned; 401 u32 val = 0; 402 403 unaligned = spi_imx->count % 4; 404 405 if (!unaligned) { 406 spi_imx_buf_tx_swap_u32(spi_imx); 407 return; 408 } 409 410 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { 411 spi_imx_buf_tx_u16(spi_imx); 412 return; 413 } 414 415 while (unaligned--) { 416 if (spi_imx->tx_buf) { 417 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); 418 spi_imx->tx_buf++; 419 } 420 spi_imx->count--; 421 } 422 423 writel(val, spi_imx->base + MXC_CSPITXDATA); 424} 425 426static void mx53_ecspi_rx_target(struct spi_imx_data *spi_imx) 427{ 428 u32 val = readl(spi_imx->base + MXC_CSPIRXDATA); 429#ifdef __LITTLE_ENDIAN 430 unsigned int bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 431 432 if (bytes_per_word == 1) 433 swab32s(&val); 434 else if (bytes_per_word == 2) 435 swahw32s(&val); 436#endif 437 if (spi_imx->rx_buf) { 438 int n_bytes = spi_imx->target_burst % sizeof(val); 439 440 if (!n_bytes) 441 n_bytes = sizeof(val); 442 443 memcpy(spi_imx->rx_buf, 444 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); 445 446 spi_imx->rx_buf += n_bytes; 447 spi_imx->target_burst -= n_bytes; 448 } 449 450 spi_imx->remainder -= sizeof(u32); 451} 452 453static void mx53_ecspi_tx_target(struct spi_imx_data *spi_imx) 454{ 455 u32 val = 0; 456 int n_bytes = spi_imx->count % sizeof(val); 457#ifdef __LITTLE_ENDIAN 458 unsigned int bytes_per_word; 459#endif 460 461 if (!n_bytes) 462 n_bytes = sizeof(val); 463 464 if (spi_imx->tx_buf) { 465 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, 466 spi_imx->tx_buf, n_bytes); 467 spi_imx->tx_buf += n_bytes; 468 } 469 470 spi_imx->count -= n_bytes; 471 472#ifdef __LITTLE_ENDIAN 473 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); 474 if (bytes_per_word == 1) 475 swab32s(&val); 476 else if (bytes_per_word == 2) 477 swahw32s(&val); 478#endif 479 writel(val, spi_imx->base + MXC_CSPITXDATA); 480} 481 482/* MX51 eCSPI */ 483static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 484 unsigned int fspi, unsigned int *fres) 485{ 486 /* 487 * there are two 4-bit dividers, the pre-divider divides by 488 * $pre, the post-divider by 2^$post 489 */ 490 unsigned int pre, post; 491 unsigned int fin = spi_imx->spi_clk; 492 493 fspi = min(fspi, fin); 494 495 post = fls(fin) - fls(fspi); 496 if (fin > fspi << post) 497 post++; 498 499 /* now we have: (fin <= fspi << post) with post being minimal */ 500 501 post = max(4U, post) - 4; 502 if (unlikely(post > 0xf)) { 503 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", 504 fspi, fin); 505 return 0xff; 506 } 507 508 pre = DIV_ROUND_UP(fin, fspi << post) - 1; 509 510 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", 511 __func__, fin, fspi, post, pre); 512 513 /* Resulting frequency for the SCLK line. */ 514 *fres = (fin / (pre + 1)) >> post; 515 516 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | 517 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); 518} 519 520static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) 521{ 522 unsigned int val = 0; 523 524 if (enable & MXC_INT_TE) 525 val |= MX51_ECSPI_INT_TEEN; 526 527 if (enable & MXC_INT_RR) 528 val |= MX51_ECSPI_INT_RREN; 529 530 if (enable & MXC_INT_RDR) 531 val |= MX51_ECSPI_INT_RDREN; 532 533 writel(val, spi_imx->base + MX51_ECSPI_INT); 534} 535 536static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) 537{ 538 u32 reg; 539 540 if (spi_imx->usedma) { 541 reg = readl(spi_imx->base + MX51_ECSPI_DMA); 542 reg |= MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN; 543 writel(reg, spi_imx->base + MX51_ECSPI_DMA); 544 } else { 545 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); 546 reg |= MX51_ECSPI_CTRL_XCH; 547 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); 548 } 549} 550 551static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) 552{ 553 u32 ctrl; 554 555 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 556 ctrl &= ~MX51_ECSPI_CTRL_ENABLE; 557 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 558} 559 560static int mx51_ecspi_channel(const struct spi_device *spi) 561{ 562 if (!spi_get_csgpiod(spi, 0)) 563 return spi_get_chipselect(spi, 0); 564 return spi->controller->unused_native_cs; 565} 566 567static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, 568 struct spi_message *msg) 569{ 570 struct spi_device *spi = msg->spi; 571 struct spi_transfer *xfer; 572 u32 ctrl = MX51_ECSPI_CTRL_ENABLE; 573 u32 min_speed_hz = ~0U; 574 u32 testreg, delay; 575 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 576 u32 current_cfg = cfg; 577 int channel = mx51_ecspi_channel(spi); 578 579 /* set Host or Target mode */ 580 if (spi_imx->target_mode) 581 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK; 582 else 583 ctrl |= MX51_ECSPI_CTRL_MODE_MASK; 584 585 /* 586 * Enable SPI_RDY handling (falling edge/level triggered). 587 */ 588 if (spi->mode & SPI_READY) 589 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); 590 591 /* set chip select to use */ 592 ctrl |= MX51_ECSPI_CTRL_CS(channel); 593 594 /* 595 * The ctrl register must be written first, with the EN bit set other 596 * registers must not be written to. 597 */ 598 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 599 600 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); 601 if (spi->mode & SPI_LOOP) 602 testreg |= MX51_ECSPI_TESTREG_LBC; 603 else 604 testreg &= ~MX51_ECSPI_TESTREG_LBC; 605 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); 606 607 /* 608 * eCSPI burst completion by Chip Select signal in Target mode 609 * is not functional for imx53 Soc, config SPI burst completed when 610 * BURST_LENGTH + 1 bits are received 611 */ 612 if (spi_imx->target_mode) 613 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel); 614 else 615 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel); 616 617 if (spi->mode & SPI_CPOL) { 618 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel); 619 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel); 620 } else { 621 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel); 622 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel); 623 } 624 625 if (spi->mode & SPI_MOSI_IDLE_LOW) 626 cfg |= MX51_ECSPI_CONFIG_DATACTL(channel); 627 else 628 cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel); 629 630 if (spi->mode & SPI_CS_HIGH) 631 cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel); 632 else 633 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel); 634 635 if (cfg == current_cfg) 636 return 0; 637 638 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 639 640 /* 641 * Wait until the changes in the configuration register CONFIGREG 642 * propagate into the hardware. It takes exactly one tick of the 643 * SCLK clock, but we will wait two SCLK clock just to be sure. The 644 * effect of the delay it takes for the hardware to apply changes 645 * is noticable if the SCLK clock run very slow. In such a case, if 646 * the polarity of SCLK should be inverted, the GPIO ChipSelect might 647 * be asserted before the SCLK polarity changes, which would disrupt 648 * the SPI communication as the device on the other end would consider 649 * the change of SCLK polarity as a clock tick already. 650 * 651 * Because spi_imx->spi_bus_clk is only set in prepare_message 652 * callback, iterate over all the transfers in spi_message, find the 653 * one with lowest bus frequency, and use that bus frequency for the 654 * delay calculation. In case all transfers have speed_hz == 0, then 655 * min_speed_hz is ~0 and the resulting delay is zero. 656 */ 657 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 658 if (!xfer->speed_hz) 659 continue; 660 min_speed_hz = min(xfer->speed_hz, min_speed_hz); 661 } 662 663 delay = (2 * 1000000) / min_speed_hz; 664 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */ 665 udelay(delay); 666 else /* SCLK is _very_ slow */ 667 usleep_range(delay, delay + 10); 668 669 return 0; 670} 671 672static void mx51_configure_cpha(struct spi_imx_data *spi_imx, 673 struct spi_device *spi) 674{ 675 bool cpha = (spi->mode & SPI_CPHA); 676 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; 677 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); 678 int channel = mx51_ecspi_channel(spi); 679 680 /* Flip cpha logical value iff flip_cpha */ 681 cpha ^= flip_cpha; 682 683 if (cpha) 684 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel); 685 else 686 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel); 687 688 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); 689} 690 691static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx, 692 struct spi_device *spi, struct spi_transfer *t) 693{ 694 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 695 u64 word_delay_sck; 696 u32 clk; 697 698 /* Clear BL field and set the right value */ 699 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 700 if (spi_imx->target_mode) 701 ctrl |= (spi_imx->target_burst * 8 - 1) 702 << MX51_ECSPI_CTRL_BL_OFFSET; 703 else { 704 ctrl |= (spi_imx->bits_per_word - 1) 705 << MX51_ECSPI_CTRL_BL_OFFSET; 706 } 707 708 /* set clock speed */ 709 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET | 710 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET); 711 712 if (!spi_imx->target_mode) { 713 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); 714 spi_imx->spi_bus_clk = clk; 715 } 716 717 mx51_configure_cpha(spi_imx, spi); 718 719 /* 720 * ERR009165: work in XHC mode instead of SMC as PIO on the chips 721 * before i.mx6ul. 722 */ 723 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed) 724 ctrl |= MX51_ECSPI_CTRL_SMC; 725 else 726 ctrl &= ~MX51_ECSPI_CTRL_SMC; 727 728 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 729 730 /* calculate word delay in SPI Clock (SCLK) cycles */ 731 if (t->word_delay.value == 0) { 732 word_delay_sck = 0; 733 } else if (t->word_delay.unit == SPI_DELAY_UNIT_SCK) { 734 word_delay_sck = t->word_delay.value; 735 736 if (word_delay_sck <= MX51_ECSPI_PERIOD_MIN_DELAY_SCK) 737 word_delay_sck = 0; 738 else if (word_delay_sck <= MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1) 739 word_delay_sck = 1; 740 else 741 word_delay_sck -= MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1; 742 } else { 743 int word_delay_ns; 744 745 word_delay_ns = spi_delay_to_ns(&t->word_delay, t); 746 if (word_delay_ns < 0) 747 return word_delay_ns; 748 749 if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC, 750 MX51_ECSPI_PERIOD_MIN_DELAY_SCK, 751 spi_imx->spi_bus_clk)) { 752 word_delay_sck = 0; 753 } else if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC, 754 MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1, 755 spi_imx->spi_bus_clk)) { 756 word_delay_sck = 1; 757 } else { 758 word_delay_ns -= mul_u64_u32_div(NSEC_PER_SEC, 759 MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1, 760 spi_imx->spi_bus_clk); 761 762 word_delay_sck = DIV_U64_ROUND_UP((u64)word_delay_ns * spi_imx->spi_bus_clk, 763 NSEC_PER_SEC); 764 } 765 } 766 767 if (!FIELD_FIT(MX51_ECSPI_PERIOD_MASK, word_delay_sck)) 768 return -EINVAL; 769 770 writel(FIELD_PREP(MX51_ECSPI_PERIOD_MASK, word_delay_sck), 771 spi_imx->base + MX51_ECSPI_PERIOD); 772 773 return 0; 774} 775 776static void mx51_setup_wml(struct spi_imx_data *spi_imx) 777{ 778 u32 tx_wml = 0; 779 780 if (spi_imx->devtype_data->tx_glitch_fixed) 781 tx_wml = spi_imx->wml; 782 /* 783 * Configure the DMA register: setup the watermark 784 * and enable DMA request. 785 */ 786 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | 787 MX51_ECSPI_DMA_TX_WML(tx_wml) | 788 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | 789 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); 790} 791 792static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) 793{ 794 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; 795} 796 797static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) 798{ 799 /* drain receive buffer */ 800 while (mx51_ecspi_rx_available(spi_imx)) 801 readl(spi_imx->base + MXC_CSPIRXDATA); 802} 803 804#define MX31_INTREG_TEEN (1 << 0) 805#define MX31_INTREG_RREN (1 << 3) 806 807#define MX31_CSPICTRL_ENABLE (1 << 0) 808#define MX31_CSPICTRL_HOST (1 << 1) 809#define MX31_CSPICTRL_XCH (1 << 2) 810#define MX31_CSPICTRL_SMC (1 << 3) 811#define MX31_CSPICTRL_POL (1 << 4) 812#define MX31_CSPICTRL_PHA (1 << 5) 813#define MX31_CSPICTRL_SSCTL (1 << 6) 814#define MX31_CSPICTRL_SSPOL (1 << 7) 815#define MX31_CSPICTRL_BC_SHIFT 8 816#define MX35_CSPICTRL_BL_SHIFT 20 817#define MX31_CSPICTRL_CS_SHIFT 24 818#define MX35_CSPICTRL_CS_SHIFT 12 819#define MX31_CSPICTRL_DR_SHIFT 16 820 821#define MX31_CSPI_DMAREG 0x10 822#define MX31_DMAREG_RH_DEN (1<<4) 823#define MX31_DMAREG_TH_DEN (1<<1) 824 825#define MX31_CSPISTATUS 0x14 826#define MX31_STATUS_RR (1 << 3) 827 828#define MX31_CSPI_TESTREG 0x1C 829#define MX31_TEST_LBC (1 << 14) 830 831/* These functions also work for the i.MX35, but be aware that 832 * the i.MX35 has a slightly different register layout for bits 833 * we do not use here. 834 */ 835static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) 836{ 837 unsigned int val = 0; 838 839 if (enable & MXC_INT_TE) 840 val |= MX31_INTREG_TEEN; 841 if (enable & MXC_INT_RR) 842 val |= MX31_INTREG_RREN; 843 844 writel(val, spi_imx->base + MXC_CSPIINT); 845} 846 847static void mx31_trigger(struct spi_imx_data *spi_imx) 848{ 849 unsigned int reg; 850 851 reg = readl(spi_imx->base + MXC_CSPICTRL); 852 reg |= MX31_CSPICTRL_XCH; 853 writel(reg, spi_imx->base + MXC_CSPICTRL); 854} 855 856static int mx31_prepare_message(struct spi_imx_data *spi_imx, 857 struct spi_message *msg) 858{ 859 return 0; 860} 861 862static int mx31_prepare_transfer(struct spi_imx_data *spi_imx, 863 struct spi_device *spi, struct spi_transfer *t) 864{ 865 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST; 866 unsigned int clk; 867 868 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 869 MX31_CSPICTRL_DR_SHIFT; 870 spi_imx->spi_bus_clk = clk; 871 872 if (is_imx35_cspi(spi_imx)) { 873 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; 874 reg |= MX31_CSPICTRL_SSCTL; 875 } else { 876 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; 877 } 878 879 if (spi->mode & SPI_CPHA) 880 reg |= MX31_CSPICTRL_PHA; 881 if (spi->mode & SPI_CPOL) 882 reg |= MX31_CSPICTRL_POL; 883 if (spi->mode & SPI_CS_HIGH) 884 reg |= MX31_CSPICTRL_SSPOL; 885 if (!spi_get_csgpiod(spi, 0)) 886 reg |= (spi_get_chipselect(spi, 0)) << 887 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 888 MX31_CSPICTRL_CS_SHIFT); 889 890 if (spi_imx->usedma) 891 reg |= MX31_CSPICTRL_SMC; 892 893 writel(reg, spi_imx->base + MXC_CSPICTRL); 894 895 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); 896 if (spi->mode & SPI_LOOP) 897 reg |= MX31_TEST_LBC; 898 else 899 reg &= ~MX31_TEST_LBC; 900 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); 901 902 if (spi_imx->usedma) { 903 /* 904 * configure DMA requests when RXFIFO is half full and 905 * when TXFIFO is half empty 906 */ 907 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN, 908 spi_imx->base + MX31_CSPI_DMAREG); 909 } 910 911 return 0; 912} 913 914static int mx31_rx_available(struct spi_imx_data *spi_imx) 915{ 916 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; 917} 918 919static void mx31_reset(struct spi_imx_data *spi_imx) 920{ 921 /* drain receive buffer */ 922 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) 923 readl(spi_imx->base + MXC_CSPIRXDATA); 924} 925 926#define MX21_INTREG_RR (1 << 4) 927#define MX21_INTREG_TEEN (1 << 9) 928#define MX21_INTREG_RREN (1 << 13) 929 930#define MX21_CSPICTRL_POL (1 << 5) 931#define MX21_CSPICTRL_PHA (1 << 6) 932#define MX21_CSPICTRL_SSPOL (1 << 8) 933#define MX21_CSPICTRL_XCH (1 << 9) 934#define MX21_CSPICTRL_ENABLE (1 << 10) 935#define MX21_CSPICTRL_HOST (1 << 11) 936#define MX21_CSPICTRL_DR_SHIFT 14 937#define MX21_CSPICTRL_CS_SHIFT 19 938 939static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) 940{ 941 unsigned int val = 0; 942 943 if (enable & MXC_INT_TE) 944 val |= MX21_INTREG_TEEN; 945 if (enable & MXC_INT_RR) 946 val |= MX21_INTREG_RREN; 947 948 writel(val, spi_imx->base + MXC_CSPIINT); 949} 950 951static void mx21_trigger(struct spi_imx_data *spi_imx) 952{ 953 unsigned int reg; 954 955 reg = readl(spi_imx->base + MXC_CSPICTRL); 956 reg |= MX21_CSPICTRL_XCH; 957 writel(reg, spi_imx->base + MXC_CSPICTRL); 958} 959 960static int mx21_prepare_message(struct spi_imx_data *spi_imx, 961 struct spi_message *msg) 962{ 963 return 0; 964} 965 966static int mx21_prepare_transfer(struct spi_imx_data *spi_imx, 967 struct spi_device *spi, struct spi_transfer *t) 968{ 969 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST; 970 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; 971 unsigned int clk; 972 973 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) 974 << MX21_CSPICTRL_DR_SHIFT; 975 spi_imx->spi_bus_clk = clk; 976 977 reg |= spi_imx->bits_per_word - 1; 978 979 if (spi->mode & SPI_CPHA) 980 reg |= MX21_CSPICTRL_PHA; 981 if (spi->mode & SPI_CPOL) 982 reg |= MX21_CSPICTRL_POL; 983 if (spi->mode & SPI_CS_HIGH) 984 reg |= MX21_CSPICTRL_SSPOL; 985 if (!spi_get_csgpiod(spi, 0)) 986 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT; 987 988 writel(reg, spi_imx->base + MXC_CSPICTRL); 989 990 return 0; 991} 992 993static int mx21_rx_available(struct spi_imx_data *spi_imx) 994{ 995 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; 996} 997 998static void mx21_reset(struct spi_imx_data *spi_imx) 999{ 1000 writel(1, spi_imx->base + MXC_RESET); 1001} 1002 1003#define MX1_INTREG_RR (1 << 3) 1004#define MX1_INTREG_TEEN (1 << 8) 1005#define MX1_INTREG_RREN (1 << 11) 1006 1007#define MX1_CSPICTRL_POL (1 << 4) 1008#define MX1_CSPICTRL_PHA (1 << 5) 1009#define MX1_CSPICTRL_XCH (1 << 8) 1010#define MX1_CSPICTRL_ENABLE (1 << 9) 1011#define MX1_CSPICTRL_HOST (1 << 10) 1012#define MX1_CSPICTRL_DR_SHIFT 13 1013 1014static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) 1015{ 1016 unsigned int val = 0; 1017 1018 if (enable & MXC_INT_TE) 1019 val |= MX1_INTREG_TEEN; 1020 if (enable & MXC_INT_RR) 1021 val |= MX1_INTREG_RREN; 1022 1023 writel(val, spi_imx->base + MXC_CSPIINT); 1024} 1025 1026static void mx1_trigger(struct spi_imx_data *spi_imx) 1027{ 1028 unsigned int reg; 1029 1030 reg = readl(spi_imx->base + MXC_CSPICTRL); 1031 reg |= MX1_CSPICTRL_XCH; 1032 writel(reg, spi_imx->base + MXC_CSPICTRL); 1033} 1034 1035static int mx1_prepare_message(struct spi_imx_data *spi_imx, 1036 struct spi_message *msg) 1037{ 1038 return 0; 1039} 1040 1041static int mx1_prepare_transfer(struct spi_imx_data *spi_imx, 1042 struct spi_device *spi, struct spi_transfer *t) 1043{ 1044 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST; 1045 unsigned int clk; 1046 1047 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << 1048 MX1_CSPICTRL_DR_SHIFT; 1049 spi_imx->spi_bus_clk = clk; 1050 1051 reg |= spi_imx->bits_per_word - 1; 1052 1053 if (spi->mode & SPI_CPHA) 1054 reg |= MX1_CSPICTRL_PHA; 1055 if (spi->mode & SPI_CPOL) 1056 reg |= MX1_CSPICTRL_POL; 1057 1058 writel(reg, spi_imx->base + MXC_CSPICTRL); 1059 1060 return 0; 1061} 1062 1063static int mx1_rx_available(struct spi_imx_data *spi_imx) 1064{ 1065 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; 1066} 1067 1068static void mx1_reset(struct spi_imx_data *spi_imx) 1069{ 1070 writel(1, spi_imx->base + MXC_RESET); 1071} 1072 1073static struct spi_imx_devtype_data imx1_cspi_devtype_data = { 1074 .intctrl = mx1_intctrl, 1075 .prepare_message = mx1_prepare_message, 1076 .prepare_transfer = mx1_prepare_transfer, 1077 .trigger = mx1_trigger, 1078 .rx_available = mx1_rx_available, 1079 .reset = mx1_reset, 1080 .fifo_size = 8, 1081 .has_dmamode = false, 1082 .dynamic_burst = false, 1083 .has_targetmode = false, 1084 .devtype = IMX1_CSPI, 1085}; 1086 1087static struct spi_imx_devtype_data imx21_cspi_devtype_data = { 1088 .intctrl = mx21_intctrl, 1089 .prepare_message = mx21_prepare_message, 1090 .prepare_transfer = mx21_prepare_transfer, 1091 .trigger = mx21_trigger, 1092 .rx_available = mx21_rx_available, 1093 .reset = mx21_reset, 1094 .fifo_size = 8, 1095 .has_dmamode = false, 1096 .dynamic_burst = false, 1097 .has_targetmode = false, 1098 .devtype = IMX21_CSPI, 1099}; 1100 1101static struct spi_imx_devtype_data imx27_cspi_devtype_data = { 1102 /* i.mx27 cspi shares the functions with i.mx21 one */ 1103 .intctrl = mx21_intctrl, 1104 .prepare_message = mx21_prepare_message, 1105 .prepare_transfer = mx21_prepare_transfer, 1106 .trigger = mx21_trigger, 1107 .rx_available = mx21_rx_available, 1108 .reset = mx21_reset, 1109 .fifo_size = 8, 1110 .has_dmamode = false, 1111 .dynamic_burst = false, 1112 .has_targetmode = false, 1113 .devtype = IMX27_CSPI, 1114}; 1115 1116static struct spi_imx_devtype_data imx31_cspi_devtype_data = { 1117 .intctrl = mx31_intctrl, 1118 .prepare_message = mx31_prepare_message, 1119 .prepare_transfer = mx31_prepare_transfer, 1120 .trigger = mx31_trigger, 1121 .rx_available = mx31_rx_available, 1122 .reset = mx31_reset, 1123 .fifo_size = 8, 1124 .has_dmamode = false, 1125 .dynamic_burst = false, 1126 .has_targetmode = false, 1127 .devtype = IMX31_CSPI, 1128}; 1129 1130static struct spi_imx_devtype_data imx35_cspi_devtype_data = { 1131 /* i.mx35 and later cspi shares the functions with i.mx31 one */ 1132 .intctrl = mx31_intctrl, 1133 .prepare_message = mx31_prepare_message, 1134 .prepare_transfer = mx31_prepare_transfer, 1135 .trigger = mx31_trigger, 1136 .rx_available = mx31_rx_available, 1137 .reset = mx31_reset, 1138 .fifo_size = 8, 1139 .has_dmamode = false, 1140 .dynamic_burst = false, 1141 .has_targetmode = false, 1142 .devtype = IMX35_CSPI, 1143}; 1144 1145static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { 1146 .intctrl = mx51_ecspi_intctrl, 1147 .prepare_message = mx51_ecspi_prepare_message, 1148 .prepare_transfer = mx51_ecspi_prepare_transfer, 1149 .trigger = mx51_ecspi_trigger, 1150 .rx_available = mx51_ecspi_rx_available, 1151 .reset = mx51_ecspi_reset, 1152 .setup_wml = mx51_setup_wml, 1153 .fifo_size = 64, 1154 .has_dmamode = true, 1155 .dynamic_burst = true, 1156 .has_targetmode = true, 1157 .disable = mx51_ecspi_disable, 1158 .devtype = IMX51_ECSPI, 1159}; 1160 1161static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { 1162 .intctrl = mx51_ecspi_intctrl, 1163 .prepare_message = mx51_ecspi_prepare_message, 1164 .prepare_transfer = mx51_ecspi_prepare_transfer, 1165 .trigger = mx51_ecspi_trigger, 1166 .rx_available = mx51_ecspi_rx_available, 1167 .reset = mx51_ecspi_reset, 1168 .fifo_size = 64, 1169 .has_dmamode = true, 1170 .has_targetmode = true, 1171 .disable = mx51_ecspi_disable, 1172 .devtype = IMX53_ECSPI, 1173}; 1174 1175static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = { 1176 .intctrl = mx51_ecspi_intctrl, 1177 .prepare_message = mx51_ecspi_prepare_message, 1178 .prepare_transfer = mx51_ecspi_prepare_transfer, 1179 .trigger = mx51_ecspi_trigger, 1180 .rx_available = mx51_ecspi_rx_available, 1181 .reset = mx51_ecspi_reset, 1182 .setup_wml = mx51_setup_wml, 1183 .fifo_size = 64, 1184 .has_dmamode = true, 1185 .dynamic_burst = true, 1186 .has_targetmode = true, 1187 .tx_glitch_fixed = true, 1188 .disable = mx51_ecspi_disable, 1189 .devtype = IMX51_ECSPI, 1190}; 1191 1192static const struct of_device_id spi_imx_dt_ids[] = { 1193 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, 1194 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, 1195 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, 1196 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 1197 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 1198 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 1199 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, 1200 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, }, 1201 { /* sentinel */ } 1202}; 1203MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 1204 1205static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits) 1206{ 1207 u32 ctrl; 1208 1209 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); 1210 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; 1211 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); 1212 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); 1213} 1214 1215static void spi_imx_push(struct spi_imx_data *spi_imx) 1216{ 1217 unsigned int burst_len; 1218 1219 /* 1220 * Reload the FIFO when the remaining bytes to be transferred in the 1221 * current burst is 0. This only applies when bits_per_word is a 1222 * multiple of 8. 1223 */ 1224 if (!spi_imx->remainder) { 1225 if (spi_imx->dynamic_burst) { 1226 1227 /* We need to deal unaligned data first */ 1228 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; 1229 1230 if (!burst_len) 1231 burst_len = MX51_ECSPI_CTRL_MAX_BURST; 1232 1233 spi_imx_set_burst_len(spi_imx, burst_len * 8); 1234 1235 spi_imx->remainder = burst_len; 1236 } else { 1237 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); 1238 } 1239 } 1240 1241 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { 1242 if (!spi_imx->count) 1243 break; 1244 if (spi_imx->dynamic_burst && 1245 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) 1246 break; 1247 spi_imx->tx(spi_imx); 1248 spi_imx->txfifo++; 1249 } 1250 1251 if (!spi_imx->target_mode) 1252 spi_imx->devtype_data->trigger(spi_imx); 1253} 1254 1255static irqreturn_t spi_imx_isr(int irq, void *dev_id) 1256{ 1257 struct spi_imx_data *spi_imx = dev_id; 1258 1259 while (spi_imx->txfifo && 1260 spi_imx->devtype_data->rx_available(spi_imx)) { 1261 spi_imx->rx(spi_imx); 1262 spi_imx->txfifo--; 1263 } 1264 1265 if (spi_imx->count) { 1266 spi_imx_push(spi_imx); 1267 return IRQ_HANDLED; 1268 } 1269 1270 if (spi_imx->txfifo) { 1271 /* No data left to push, but still waiting for rx data, 1272 * enable receive data available interrupt. 1273 */ 1274 spi_imx->devtype_data->intctrl( 1275 spi_imx, MXC_INT_RR); 1276 return IRQ_HANDLED; 1277 } 1278 1279 spi_imx->devtype_data->intctrl(spi_imx, 0); 1280 complete(&spi_imx->xfer_done); 1281 1282 return IRQ_HANDLED; 1283} 1284 1285static int spi_imx_dma_configure(struct spi_controller *controller) 1286{ 1287 int ret; 1288 enum dma_slave_buswidth buswidth; 1289 struct dma_slave_config rx = {}, tx = {}; 1290 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1291 1292 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { 1293 case 4: 1294 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1295 break; 1296 case 2: 1297 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1298 break; 1299 case 1: 1300 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1301 break; 1302 default: 1303 return -EINVAL; 1304 } 1305 1306 tx.direction = DMA_MEM_TO_DEV; 1307 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; 1308 tx.dst_addr_width = buswidth; 1309 tx.dst_maxburst = spi_imx->wml; 1310 ret = dmaengine_slave_config(controller->dma_tx, &tx); 1311 if (ret) { 1312 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); 1313 return ret; 1314 } 1315 1316 rx.direction = DMA_DEV_TO_MEM; 1317 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; 1318 rx.src_addr_width = buswidth; 1319 rx.src_maxburst = spi_imx->wml; 1320 ret = dmaengine_slave_config(controller->dma_rx, &rx); 1321 if (ret) { 1322 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); 1323 return ret; 1324 } 1325 1326 return 0; 1327} 1328 1329static int spi_imx_setupxfer(struct spi_device *spi, 1330 struct spi_transfer *t) 1331{ 1332 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1333 1334 if (!t) 1335 return 0; 1336 1337 if (!spi_imx->target_mode) { 1338 if (!t->speed_hz) { 1339 if (!spi->max_speed_hz) { 1340 dev_err(&spi->dev, "no speed_hz provided!\n"); 1341 return -EINVAL; 1342 } 1343 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); 1344 spi_imx->spi_bus_clk = spi->max_speed_hz; 1345 } else { 1346 spi_imx->spi_bus_clk = t->speed_hz; 1347 } 1348 } 1349 1350 spi_imx->bits_per_word = t->bits_per_word; 1351 spi_imx->count = t->len; 1352 1353 /* 1354 * Initialize the functions for transfer. To transfer non byte-aligned 1355 * words, we have to use multiple word-size bursts. To insert word 1356 * delay, the burst size has to equal the word size. We can't use 1357 * dynamic_burst in these cases. 1358 */ 1359 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode && 1360 !(spi->mode & SPI_CS_WORD) && 1361 !(t->word_delay.value) && 1362 (spi_imx->bits_per_word == 8 || 1363 spi_imx->bits_per_word == 16 || 1364 spi_imx->bits_per_word == 32)) { 1365 1366 spi_imx->rx = spi_imx_buf_rx_swap; 1367 spi_imx->tx = spi_imx_buf_tx_swap; 1368 spi_imx->dynamic_burst = 1; 1369 1370 } else { 1371 if (spi_imx->bits_per_word <= 8) { 1372 spi_imx->rx = spi_imx_buf_rx_u8; 1373 spi_imx->tx = spi_imx_buf_tx_u8; 1374 } else if (spi_imx->bits_per_word <= 16) { 1375 spi_imx->rx = spi_imx_buf_rx_u16; 1376 spi_imx->tx = spi_imx_buf_tx_u16; 1377 } else { 1378 spi_imx->rx = spi_imx_buf_rx_u32; 1379 spi_imx->tx = spi_imx_buf_tx_u32; 1380 } 1381 spi_imx->dynamic_burst = 0; 1382 } 1383 1384 if (spi_imx_can_dma(spi_imx->controller, spi, t)) 1385 spi_imx->usedma = true; 1386 else 1387 spi_imx->usedma = false; 1388 1389 spi_imx->rx_only = ((t->tx_buf == NULL) 1390 || (t->tx_buf == spi->controller->dummy_tx)); 1391 1392 if (spi_imx->target_mode) { 1393 spi_imx->rx = mx53_ecspi_rx_target; 1394 spi_imx->tx = mx53_ecspi_tx_target; 1395 spi_imx->target_burst = t->len; 1396 } 1397 1398 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t); 1399 1400 return 0; 1401} 1402 1403static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) 1404{ 1405 struct spi_controller *controller = spi_imx->controller; 1406 1407 if (controller->dma_rx) { 1408 dma_release_channel(controller->dma_rx); 1409 controller->dma_rx = NULL; 1410 } 1411 1412 if (controller->dma_tx) { 1413 dma_release_channel(controller->dma_tx); 1414 controller->dma_tx = NULL; 1415 } 1416} 1417 1418static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, 1419 struct spi_controller *controller) 1420{ 1421 int ret; 1422 1423 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; 1424 1425 /* Prepare for TX DMA: */ 1426 controller->dma_tx = dma_request_chan(dev, "tx"); 1427 if (IS_ERR(controller->dma_tx)) { 1428 ret = PTR_ERR(controller->dma_tx); 1429 dev_err_probe(dev, ret, "can't get the TX DMA channel!\n"); 1430 controller->dma_tx = NULL; 1431 goto err; 1432 } 1433 1434 /* Prepare for RX : */ 1435 controller->dma_rx = dma_request_chan(dev, "rx"); 1436 if (IS_ERR(controller->dma_rx)) { 1437 ret = PTR_ERR(controller->dma_rx); 1438 dev_err_probe(dev, ret, "can't get the RX DMA channel!\n"); 1439 controller->dma_rx = NULL; 1440 goto err; 1441 } 1442 1443 init_completion(&spi_imx->dma_rx_completion); 1444 init_completion(&spi_imx->dma_tx_completion); 1445 controller->can_dma = spi_imx_can_dma; 1446 controller->max_dma_len = MAX_SDMA_BD_BYTES; 1447 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX | 1448 SPI_CONTROLLER_MUST_TX; 1449 1450 return 0; 1451err: 1452 spi_imx_sdma_exit(spi_imx); 1453 return ret; 1454} 1455 1456static void spi_imx_dma_rx_callback(void *cookie) 1457{ 1458 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1459 1460 complete(&spi_imx->dma_rx_completion); 1461} 1462 1463static void spi_imx_dma_tx_callback(void *cookie) 1464{ 1465 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; 1466 1467 complete(&spi_imx->dma_tx_completion); 1468} 1469 1470static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) 1471{ 1472 unsigned long timeout = 0; 1473 1474 /* Time with actual data transfer and CS change delay related to HW */ 1475 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; 1476 1477 /* Add extra second for scheduler related activities */ 1478 timeout += 1; 1479 1480 /* Double calculated timeout */ 1481 return secs_to_jiffies(2 * timeout); 1482} 1483 1484static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, 1485 struct spi_transfer *transfer) 1486{ 1487 struct dma_async_tx_descriptor *desc_tx, *desc_rx; 1488 unsigned long transfer_timeout; 1489 unsigned long time_left; 1490 struct spi_controller *controller = spi_imx->controller; 1491 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; 1492 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); 1493 unsigned int bytes_per_word, i; 1494 int ret; 1495 1496 /* Get the right burst length from the last sg to ensure no tail data */ 1497 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); 1498 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { 1499 if (!(sg_dma_len(last_sg) % (i * bytes_per_word))) 1500 break; 1501 } 1502 /* Use 1 as wml in case no available burst length got */ 1503 if (i == 0) 1504 i = 1; 1505 1506 spi_imx->wml = i; 1507 1508 ret = spi_imx_dma_configure(controller); 1509 if (ret) 1510 goto dma_failure_no_start; 1511 1512 if (!spi_imx->devtype_data->setup_wml) { 1513 dev_err(spi_imx->dev, "No setup_wml()?\n"); 1514 ret = -EINVAL; 1515 goto dma_failure_no_start; 1516 } 1517 spi_imx->devtype_data->setup_wml(spi_imx); 1518 1519 /* 1520 * The TX DMA setup starts the transfer, so make sure RX is configured 1521 * before TX. 1522 */ 1523 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, 1524 rx->sgl, rx->nents, DMA_DEV_TO_MEM, 1525 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1526 if (!desc_rx) { 1527 ret = -EINVAL; 1528 goto dma_failure_no_start; 1529 } 1530 1531 desc_rx->callback = spi_imx_dma_rx_callback; 1532 desc_rx->callback_param = (void *)spi_imx; 1533 dmaengine_submit(desc_rx); 1534 reinit_completion(&spi_imx->dma_rx_completion); 1535 dma_async_issue_pending(controller->dma_rx); 1536 1537 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, 1538 tx->sgl, tx->nents, DMA_MEM_TO_DEV, 1539 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1540 if (!desc_tx) { 1541 dmaengine_terminate_all(controller->dma_tx); 1542 dmaengine_terminate_all(controller->dma_rx); 1543 return -EINVAL; 1544 } 1545 1546 desc_tx->callback = spi_imx_dma_tx_callback; 1547 desc_tx->callback_param = (void *)spi_imx; 1548 dmaengine_submit(desc_tx); 1549 reinit_completion(&spi_imx->dma_tx_completion); 1550 dma_async_issue_pending(controller->dma_tx); 1551 1552 spi_imx->devtype_data->trigger(spi_imx); 1553 1554 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1555 1556 /* Wait SDMA to finish the data transfer.*/ 1557 time_left = wait_for_completion_timeout(&spi_imx->dma_tx_completion, 1558 transfer_timeout); 1559 if (!time_left) { 1560 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); 1561 dmaengine_terminate_all(controller->dma_tx); 1562 dmaengine_terminate_all(controller->dma_rx); 1563 return -ETIMEDOUT; 1564 } 1565 1566 time_left = wait_for_completion_timeout(&spi_imx->dma_rx_completion, 1567 transfer_timeout); 1568 if (!time_left) { 1569 dev_err(&controller->dev, "I/O Error in DMA RX\n"); 1570 spi_imx->devtype_data->reset(spi_imx); 1571 dmaengine_terminate_all(controller->dma_rx); 1572 return -ETIMEDOUT; 1573 } 1574 1575 return 0; 1576/* fallback to pio */ 1577dma_failure_no_start: 1578 transfer->error |= SPI_TRANS_FAIL_NO_START; 1579 return ret; 1580} 1581 1582static int spi_imx_pio_transfer(struct spi_device *spi, 1583 struct spi_transfer *transfer) 1584{ 1585 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1586 unsigned long transfer_timeout; 1587 unsigned long time_left; 1588 1589 spi_imx->tx_buf = transfer->tx_buf; 1590 spi_imx->rx_buf = transfer->rx_buf; 1591 spi_imx->count = transfer->len; 1592 spi_imx->txfifo = 0; 1593 spi_imx->remainder = 0; 1594 1595 reinit_completion(&spi_imx->xfer_done); 1596 1597 spi_imx_push(spi_imx); 1598 1599 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); 1600 1601 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); 1602 1603 time_left = wait_for_completion_timeout(&spi_imx->xfer_done, 1604 transfer_timeout); 1605 if (!time_left) { 1606 dev_err(&spi->dev, "I/O Error in PIO\n"); 1607 spi_imx->devtype_data->reset(spi_imx); 1608 return -ETIMEDOUT; 1609 } 1610 1611 return 0; 1612} 1613 1614static int spi_imx_poll_transfer(struct spi_device *spi, 1615 struct spi_transfer *transfer) 1616{ 1617 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1618 unsigned long timeout; 1619 1620 spi_imx->tx_buf = transfer->tx_buf; 1621 spi_imx->rx_buf = transfer->rx_buf; 1622 spi_imx->count = transfer->len; 1623 spi_imx->txfifo = 0; 1624 spi_imx->remainder = 0; 1625 1626 /* fill in the fifo before timeout calculations if we are 1627 * interrupted here, then the data is getting transferred by 1628 * the HW while we are interrupted 1629 */ 1630 spi_imx_push(spi_imx); 1631 1632 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies; 1633 while (spi_imx->txfifo) { 1634 /* RX */ 1635 while (spi_imx->txfifo && 1636 spi_imx->devtype_data->rx_available(spi_imx)) { 1637 spi_imx->rx(spi_imx); 1638 spi_imx->txfifo--; 1639 } 1640 1641 /* TX */ 1642 if (spi_imx->count) { 1643 spi_imx_push(spi_imx); 1644 continue; 1645 } 1646 1647 if (spi_imx->txfifo && 1648 time_after(jiffies, timeout)) { 1649 1650 dev_err_ratelimited(&spi->dev, 1651 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n", 1652 jiffies - timeout); 1653 1654 /* fall back to interrupt mode */ 1655 return spi_imx_pio_transfer(spi, transfer); 1656 } 1657 } 1658 1659 return 0; 1660} 1661 1662static int spi_imx_pio_transfer_target(struct spi_device *spi, 1663 struct spi_transfer *transfer) 1664{ 1665 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1666 int ret = 0; 1667 1668 if (transfer->len > MX53_MAX_TRANSFER_BYTES) { 1669 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", 1670 MX53_MAX_TRANSFER_BYTES); 1671 return -EMSGSIZE; 1672 } 1673 1674 spi_imx->tx_buf = transfer->tx_buf; 1675 spi_imx->rx_buf = transfer->rx_buf; 1676 spi_imx->count = transfer->len; 1677 spi_imx->txfifo = 0; 1678 spi_imx->remainder = 0; 1679 1680 reinit_completion(&spi_imx->xfer_done); 1681 spi_imx->target_aborted = false; 1682 1683 spi_imx_push(spi_imx); 1684 1685 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); 1686 1687 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || 1688 spi_imx->target_aborted) { 1689 dev_dbg(&spi->dev, "interrupted\n"); 1690 ret = -EINTR; 1691 } 1692 1693 /* ecspi has a HW issue when works in Target mode, 1694 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty, 1695 * ECSPI_TXDATA keeps shift out the last word data, 1696 * so we have to disable ECSPI when in target mode after the 1697 * transfer completes 1698 */ 1699 if (spi_imx->devtype_data->disable) 1700 spi_imx->devtype_data->disable(spi_imx); 1701 1702 return ret; 1703} 1704 1705static unsigned int spi_imx_transfer_estimate_time_us(struct spi_transfer *transfer) 1706{ 1707 u64 result; 1708 1709 result = DIV_U64_ROUND_CLOSEST((u64)USEC_PER_SEC * transfer->len * BITS_PER_BYTE, 1710 transfer->effective_speed_hz); 1711 if (transfer->word_delay.value) { 1712 unsigned int word_delay_us; 1713 unsigned int words; 1714 1715 words = DIV_ROUND_UP(transfer->len * BITS_PER_BYTE, transfer->bits_per_word); 1716 word_delay_us = DIV_ROUND_CLOSEST(spi_delay_to_ns(&transfer->word_delay, transfer), 1717 NSEC_PER_USEC); 1718 result += (u64)words * word_delay_us; 1719 } 1720 1721 return min(result, U32_MAX); 1722} 1723 1724static int spi_imx_transfer_one(struct spi_controller *controller, 1725 struct spi_device *spi, 1726 struct spi_transfer *transfer) 1727{ 1728 int ret; 1729 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); 1730 1731 ret = spi_imx_setupxfer(spi, transfer); 1732 if (ret < 0) 1733 return ret; 1734 transfer->effective_speed_hz = spi_imx->spi_bus_clk; 1735 1736 /* flush rxfifo before transfer */ 1737 while (spi_imx->devtype_data->rx_available(spi_imx)) 1738 readl(spi_imx->base + MXC_CSPIRXDATA); 1739 1740 if (spi_imx->target_mode) 1741 return spi_imx_pio_transfer_target(spi, transfer); 1742 1743 /* 1744 * If we decided in spi_imx_can_dma() that we want to do a DMA 1745 * transfer, the SPI transfer has already been mapped, so we 1746 * have to do the DMA transfer here. 1747 */ 1748 if (spi_imx->usedma) 1749 return spi_imx_dma_transfer(spi_imx, transfer); 1750 1751 /* run in polling mode for short transfers */ 1752 if (transfer->len == 1 || (polling_limit_us && 1753 spi_imx_transfer_estimate_time_us(transfer) < polling_limit_us)) 1754 return spi_imx_poll_transfer(spi, transfer); 1755 1756 return spi_imx_pio_transfer(spi, transfer); 1757} 1758 1759static int spi_imx_setup(struct spi_device *spi) 1760{ 1761 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1762 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1763 1764 return 0; 1765} 1766 1767static int 1768spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg) 1769{ 1770 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1771 int ret; 1772 1773 ret = pm_runtime_resume_and_get(spi_imx->dev); 1774 if (ret < 0) { 1775 dev_err(spi_imx->dev, "failed to enable clock\n"); 1776 return ret; 1777 } 1778 1779 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); 1780 if (ret) { 1781 pm_runtime_put_autosuspend(spi_imx->dev); 1782 } 1783 1784 return ret; 1785} 1786 1787static int 1788spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg) 1789{ 1790 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1791 1792 pm_runtime_put_autosuspend(spi_imx->dev); 1793 return 0; 1794} 1795 1796static int spi_imx_target_abort(struct spi_controller *controller) 1797{ 1798 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1799 1800 spi_imx->target_aborted = true; 1801 complete(&spi_imx->xfer_done); 1802 1803 return 0; 1804} 1805 1806static int spi_imx_probe(struct platform_device *pdev) 1807{ 1808 struct device_node *np = pdev->dev.of_node; 1809 struct spi_controller *controller; 1810 struct spi_imx_data *spi_imx; 1811 struct resource *res; 1812 int ret, irq, spi_drctl; 1813 const struct spi_imx_devtype_data *devtype_data = 1814 of_device_get_match_data(&pdev->dev); 1815 bool target_mode; 1816 u32 val; 1817 1818 target_mode = devtype_data->has_targetmode && 1819 of_property_read_bool(np, "spi-slave"); 1820 if (target_mode) 1821 controller = spi_alloc_target(&pdev->dev, 1822 sizeof(struct spi_imx_data)); 1823 else 1824 controller = spi_alloc_host(&pdev->dev, 1825 sizeof(struct spi_imx_data)); 1826 if (!controller) 1827 return -ENOMEM; 1828 1829 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); 1830 if ((ret < 0) || (spi_drctl >= 0x3)) { 1831 /* '11' is reserved */ 1832 spi_drctl = 0; 1833 } 1834 1835 platform_set_drvdata(pdev, controller); 1836 1837 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 1838 controller->bus_num = np ? -1 : pdev->id; 1839 controller->use_gpio_descriptors = true; 1840 1841 spi_imx = spi_controller_get_devdata(controller); 1842 spi_imx->controller = controller; 1843 spi_imx->dev = &pdev->dev; 1844 spi_imx->target_mode = target_mode; 1845 1846 spi_imx->devtype_data = devtype_data; 1847 1848 /* 1849 * Get number of chip selects from device properties. This can be 1850 * coming from device tree or boardfiles, if it is not defined, 1851 * a default value of 3 chip selects will be used, as all the legacy 1852 * board files have <= 3 chip selects. 1853 */ 1854 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) 1855 controller->num_chipselect = val; 1856 else 1857 controller->num_chipselect = 3; 1858 1859 controller->transfer_one = spi_imx_transfer_one; 1860 controller->setup = spi_imx_setup; 1861 controller->prepare_message = spi_imx_prepare_message; 1862 controller->unprepare_message = spi_imx_unprepare_message; 1863 controller->target_abort = spi_imx_target_abort; 1864 spi_imx->spi_bus_clk = MXC_SPI_DEFAULT_SPEED; 1865 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS | 1866 SPI_MOSI_IDLE_LOW; 1867 1868 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || 1869 is_imx53_ecspi(spi_imx)) 1870 controller->mode_bits |= SPI_LOOP | SPI_READY; 1871 1872 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) 1873 controller->mode_bits |= SPI_RX_CPHA_FLIP; 1874 1875 if (is_imx51_ecspi(spi_imx) && 1876 device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) 1877 /* 1878 * When using HW-CS implementing SPI_CS_WORD can be done by just 1879 * setting the burst length to the word size. This is 1880 * considerably faster than manually controlling the CS. 1881 */ 1882 controller->mode_bits |= SPI_CS_WORD; 1883 1884 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) { 1885 controller->max_native_cs = 4; 1886 controller->flags |= SPI_CONTROLLER_GPIO_SS; 1887 } 1888 1889 spi_imx->spi_drctl = spi_drctl; 1890 1891 init_completion(&spi_imx->xfer_done); 1892 1893 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1894 if (IS_ERR(spi_imx->base)) { 1895 ret = PTR_ERR(spi_imx->base); 1896 goto out_controller_put; 1897 } 1898 spi_imx->base_phys = res->start; 1899 1900 irq = platform_get_irq(pdev, 0); 1901 if (irq < 0) { 1902 ret = irq; 1903 goto out_controller_put; 1904 } 1905 1906 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, 1907 dev_name(&pdev->dev), spi_imx); 1908 if (ret) { 1909 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); 1910 goto out_controller_put; 1911 } 1912 1913 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1914 if (IS_ERR(spi_imx->clk_ipg)) { 1915 ret = PTR_ERR(spi_imx->clk_ipg); 1916 goto out_controller_put; 1917 } 1918 1919 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); 1920 if (IS_ERR(spi_imx->clk_per)) { 1921 ret = PTR_ERR(spi_imx->clk_per); 1922 goto out_controller_put; 1923 } 1924 1925 ret = clk_prepare_enable(spi_imx->clk_per); 1926 if (ret) 1927 goto out_controller_put; 1928 1929 ret = clk_prepare_enable(spi_imx->clk_ipg); 1930 if (ret) 1931 goto out_put_per; 1932 1933 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); 1934 pm_runtime_use_autosuspend(spi_imx->dev); 1935 pm_runtime_get_noresume(spi_imx->dev); 1936 pm_runtime_set_active(spi_imx->dev); 1937 pm_runtime_enable(spi_imx->dev); 1938 1939 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); 1940 /* 1941 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1942 * if validated on other chips. 1943 */ 1944 if (spi_imx->devtype_data->has_dmamode) { 1945 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller); 1946 if (ret == -EPROBE_DEFER) 1947 goto out_runtime_pm_put; 1948 1949 if (ret < 0) 1950 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", 1951 ret); 1952 } 1953 1954 spi_imx->devtype_data->reset(spi_imx); 1955 1956 spi_imx->devtype_data->intctrl(spi_imx, 0); 1957 1958 controller->dev.of_node = pdev->dev.of_node; 1959 ret = spi_register_controller(controller); 1960 if (ret) { 1961 dev_err_probe(&pdev->dev, ret, "register controller failed\n"); 1962 goto out_register_controller; 1963 } 1964 1965 pm_runtime_put_autosuspend(spi_imx->dev); 1966 1967 return ret; 1968 1969out_register_controller: 1970 if (spi_imx->devtype_data->has_dmamode) 1971 spi_imx_sdma_exit(spi_imx); 1972out_runtime_pm_put: 1973 pm_runtime_dont_use_autosuspend(spi_imx->dev); 1974 pm_runtime_disable(spi_imx->dev); 1975 pm_runtime_set_suspended(&pdev->dev); 1976 1977 clk_disable_unprepare(spi_imx->clk_ipg); 1978out_put_per: 1979 clk_disable_unprepare(spi_imx->clk_per); 1980out_controller_put: 1981 spi_controller_put(controller); 1982 1983 return ret; 1984} 1985 1986static void spi_imx_remove(struct platform_device *pdev) 1987{ 1988 struct spi_controller *controller = platform_get_drvdata(pdev); 1989 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller); 1990 int ret; 1991 1992 spi_unregister_controller(controller); 1993 1994 ret = pm_runtime_get_sync(spi_imx->dev); 1995 if (ret >= 0) 1996 writel(0, spi_imx->base + MXC_CSPICTRL); 1997 else 1998 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n"); 1999 2000 pm_runtime_dont_use_autosuspend(spi_imx->dev); 2001 pm_runtime_put_sync(spi_imx->dev); 2002 pm_runtime_disable(spi_imx->dev); 2003 2004 spi_imx_sdma_exit(spi_imx); 2005} 2006 2007static int spi_imx_runtime_resume(struct device *dev) 2008{ 2009 struct spi_controller *controller = dev_get_drvdata(dev); 2010 struct spi_imx_data *spi_imx; 2011 int ret; 2012 2013 spi_imx = spi_controller_get_devdata(controller); 2014 2015 ret = clk_prepare_enable(spi_imx->clk_per); 2016 if (ret) 2017 return ret; 2018 2019 ret = clk_prepare_enable(spi_imx->clk_ipg); 2020 if (ret) { 2021 clk_disable_unprepare(spi_imx->clk_per); 2022 return ret; 2023 } 2024 2025 return 0; 2026} 2027 2028static int spi_imx_runtime_suspend(struct device *dev) 2029{ 2030 struct spi_controller *controller = dev_get_drvdata(dev); 2031 struct spi_imx_data *spi_imx; 2032 2033 spi_imx = spi_controller_get_devdata(controller); 2034 2035 clk_disable_unprepare(spi_imx->clk_per); 2036 clk_disable_unprepare(spi_imx->clk_ipg); 2037 2038 return 0; 2039} 2040 2041static int spi_imx_suspend(struct device *dev) 2042{ 2043 pinctrl_pm_select_sleep_state(dev); 2044 return 0; 2045} 2046 2047static int spi_imx_resume(struct device *dev) 2048{ 2049 pinctrl_pm_select_default_state(dev); 2050 return 0; 2051} 2052 2053static const struct dev_pm_ops imx_spi_pm = { 2054 RUNTIME_PM_OPS(spi_imx_runtime_suspend, spi_imx_runtime_resume, NULL) 2055 SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume) 2056}; 2057 2058static struct platform_driver spi_imx_driver = { 2059 .driver = { 2060 .name = DRIVER_NAME, 2061 .of_match_table = spi_imx_dt_ids, 2062 .pm = pm_ptr(&imx_spi_pm), 2063 }, 2064 .probe = spi_imx_probe, 2065 .remove = spi_imx_remove, 2066}; 2067module_platform_driver(spi_imx_driver); 2068 2069MODULE_DESCRIPTION("i.MX SPI Controller driver"); 2070MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 2071MODULE_LICENSE("GPL"); 2072MODULE_ALIAS("platform:" DRIVER_NAME);
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