spi-hisi-kunpeng.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2//
  3// HiSilicon SPI Controller Driver for Kunpeng SoCs
  4//
  5// Copyright (c) 2021 HiSilicon Technologies Co., Ltd.
  6// Author: Jay Fang <f.fangjian@huawei.com>
  7//
  8// This code is based on spi-dw-core.c.
  9
 10#include <linux/acpi.h>
 11#include <linux/bitfield.h>
 12#include <linux/debugfs.h>
 13#include <linux/delay.h>
 14#include <linux/err.h>
 15#include <linux/interrupt.h>
 16#include <linux/module.h>
 17#include <linux/property.h>
 18#include <linux/platform_device.h>
 19#include <linux/slab.h>
 20#include <linux/spi/spi.h>
 21
 22/* Register offsets */
 23#define HISI_SPI_CSCR		0x00	/* cs control register */
 24#define HISI_SPI_CR		0x04	/* spi common control register */
 25#define HISI_SPI_ENR		0x08	/* spi enable register */
 26#define HISI_SPI_FIFOC		0x0c	/* fifo level control register */
 27#define HISI_SPI_IMR		0x10	/* interrupt mask register */
 28#define HISI_SPI_DIN		0x14	/* data in register */
 29#define HISI_SPI_DOUT		0x18	/* data out register */
 30#define HISI_SPI_SR		0x1c	/* status register */
 31#define HISI_SPI_RISR		0x20	/* raw interrupt status register */
 32#define HISI_SPI_ISR		0x24	/* interrupt status register */
 33#define HISI_SPI_ICR		0x28	/* interrupt clear register */
 34#define HISI_SPI_VERSION	0xe0	/* version register */
 35
 36/* Bit fields in HISI_SPI_CR */
 37#define CR_LOOP_MASK		GENMASK(1, 1)
 38#define CR_CPOL_MASK		GENMASK(2, 2)
 39#define CR_CPHA_MASK		GENMASK(3, 3)
 40#define CR_DIV_PRE_MASK		GENMASK(11, 4)
 41#define CR_DIV_POST_MASK	GENMASK(19, 12)
 42#define CR_BPW_MASK		GENMASK(24, 20)
 43#define CR_SPD_MODE_MASK	GENMASK(25, 25)
 44
 45/* Bit fields in HISI_SPI_FIFOC */
 46#define FIFOC_TX_MASK		GENMASK(5, 3)
 47#define FIFOC_RX_MASK		GENMASK(11, 9)
 48
 49/* Bit fields in HISI_SPI_IMR, 4 bits */
 50#define IMR_RXOF		BIT(0)		/* Receive Overflow */
 51#define IMR_RXTO		BIT(1)		/* Receive Timeout */
 52#define IMR_RX			BIT(2)		/* Receive */
 53#define IMR_TX			BIT(3)		/* Transmit */
 54#define IMR_MASK		(IMR_RXOF | IMR_RXTO | IMR_RX | IMR_TX)
 55
 56/* Bit fields in HISI_SPI_SR, 5 bits */
 57#define SR_TXE			BIT(0)		/* Transmit FIFO empty */
 58#define SR_TXNF			BIT(1)		/* Transmit FIFO not full */
 59#define SR_RXNE			BIT(2)		/* Receive FIFO not empty */
 60#define SR_RXF			BIT(3)		/* Receive FIFO full */
 61#define SR_BUSY			BIT(4)		/* Busy Flag */
 62
 63/* Bit fields in HISI_SPI_ISR, 4 bits */
 64#define ISR_RXOF		BIT(0)		/* Receive Overflow */
 65#define ISR_RXTO		BIT(1)		/* Receive Timeout */
 66#define ISR_RX			BIT(2)		/* Receive */
 67#define ISR_TX			BIT(3)		/* Transmit */
 68#define ISR_MASK		(ISR_RXOF | ISR_RXTO | ISR_RX | ISR_TX)
 69
 70/* Bit fields in HISI_SPI_ICR, 2 bits */
 71#define ICR_RXOF		BIT(0)		/* Receive Overflow */
 72#define ICR_RXTO		BIT(1)		/* Receive Timeout */
 73#define ICR_MASK		(ICR_RXOF | ICR_RXTO)
 74
 75#define DIV_POST_MAX		0xFF
 76#define DIV_POST_MIN		0x00
 77#define DIV_PRE_MAX		0xFE
 78#define DIV_PRE_MIN		0x02
 79#define CLK_DIV_MAX		((1 + DIV_POST_MAX) * DIV_PRE_MAX)
 80#define CLK_DIV_MIN		((1 + DIV_POST_MIN) * DIV_PRE_MIN)
 81
 82#define DEFAULT_NUM_CS		1
 83
 84#define HISI_SPI_WAIT_TIMEOUT_MS	10UL
 85
 86enum hisi_spi_rx_level_trig {
 87	HISI_SPI_RX_1,
 88	HISI_SPI_RX_4,
 89	HISI_SPI_RX_8,
 90	HISI_SPI_RX_16,
 91	HISI_SPI_RX_32,
 92	HISI_SPI_RX_64,
 93	HISI_SPI_RX_128
 94};
 95
 96enum hisi_spi_tx_level_trig {
 97	HISI_SPI_TX_1_OR_LESS,
 98	HISI_SPI_TX_4_OR_LESS,
 99	HISI_SPI_TX_8_OR_LESS,
100	HISI_SPI_TX_16_OR_LESS,
101	HISI_SPI_TX_32_OR_LESS,
102	HISI_SPI_TX_64_OR_LESS,
103	HISI_SPI_TX_128_OR_LESS
104};
105
106enum hisi_spi_frame_n_bytes {
107	HISI_SPI_N_BYTES_NULL,
108	HISI_SPI_N_BYTES_U8,
109	HISI_SPI_N_BYTES_U16,
110	HISI_SPI_N_BYTES_U32 = 4
111};
112
113/* Slave spi_dev related */
114struct hisi_chip_data {
115	u32 cr;
116	u32 speed_hz;	/* baud rate */
117	u16 clk_div;	/* baud rate divider */
118
119	/* clk_div = (1 + div_post) * div_pre */
120	u8 div_post;	/* value from 0 to 255 */
121	u8 div_pre;	/* value from 2 to 254 (even only!) */
122};
123
124struct hisi_spi {
125	struct device		*dev;
126
127	void __iomem		*regs;
128	int			irq;
129	u32			fifo_len; /* depth of the FIFO buffer */
130
131	/* Current message transfer state info */
132	const void		*tx;
133	unsigned int		tx_len;
134	void			*rx;
135	unsigned int		rx_len;
136	u8			n_bytes; /* current is a 1/2/4 bytes op */
137
138	struct dentry *debugfs;
139	struct debugfs_regset32 regset;
140};
141
142#define HISI_SPI_DBGFS_REG(_name, _off)	\
143{					\
144	.name = _name,			\
145	.offset = _off,			\
146}
147
148static const struct debugfs_reg32 hisi_spi_regs[] = {
149	HISI_SPI_DBGFS_REG("CSCR", HISI_SPI_CSCR),
150	HISI_SPI_DBGFS_REG("CR", HISI_SPI_CR),
151	HISI_SPI_DBGFS_REG("ENR", HISI_SPI_ENR),
152	HISI_SPI_DBGFS_REG("FIFOC", HISI_SPI_FIFOC),
153	HISI_SPI_DBGFS_REG("IMR", HISI_SPI_IMR),
154	HISI_SPI_DBGFS_REG("SR", HISI_SPI_SR),
155	HISI_SPI_DBGFS_REG("RISR", HISI_SPI_RISR),
156	HISI_SPI_DBGFS_REG("ISR", HISI_SPI_ISR),
157	HISI_SPI_DBGFS_REG("ICR", HISI_SPI_ICR),
158	HISI_SPI_DBGFS_REG("VERSION", HISI_SPI_VERSION),
159};
160
161static int hisi_spi_debugfs_init(struct hisi_spi *hs)
162{
163	char name[32];
164	struct spi_controller *host = dev_get_drvdata(hs->dev);
165
166	snprintf(name, 32, "hisi_spi%d", host->bus_num);
167	hs->debugfs = debugfs_create_dir(name, NULL);
168	if (IS_ERR(hs->debugfs))
169		return -ENOMEM;
170
171	hs->regset.regs = hisi_spi_regs;
172	hs->regset.nregs = ARRAY_SIZE(hisi_spi_regs);
173	hs->regset.base = hs->regs;
174	debugfs_create_regset32("registers", 0400, hs->debugfs, &hs->regset);
175
176	return 0;
177}
178
179static u32 hisi_spi_busy(struct hisi_spi *hs)
180{
181	return readl(hs->regs + HISI_SPI_SR) & SR_BUSY;
182}
183
184static u32 hisi_spi_rx_not_empty(struct hisi_spi *hs)
185{
186	return readl(hs->regs + HISI_SPI_SR) & SR_RXNE;
187}
188
189static u32 hisi_spi_tx_not_full(struct hisi_spi *hs)
190{
191	return readl(hs->regs + HISI_SPI_SR) & SR_TXNF;
192}
193
194static void hisi_spi_flush_fifo(struct hisi_spi *hs)
195{
196	unsigned long limit = loops_per_jiffy << 1;
197
198	do {
199		while (hisi_spi_rx_not_empty(hs))
200			readl(hs->regs + HISI_SPI_DOUT);
201	} while (hisi_spi_busy(hs) && limit--);
202}
203
204/* Disable the controller and all interrupts */
205static void hisi_spi_disable(struct hisi_spi *hs)
206{
207	writel(0, hs->regs + HISI_SPI_ENR);
208	writel(IMR_MASK, hs->regs + HISI_SPI_IMR);
209	writel(ICR_MASK, hs->regs + HISI_SPI_ICR);
210}
211
212static u8 hisi_spi_n_bytes(struct spi_transfer *transfer)
213{
214	if (transfer->bits_per_word <= 8)
215		return HISI_SPI_N_BYTES_U8;
216	else if (transfer->bits_per_word <= 16)
217		return HISI_SPI_N_BYTES_U16;
218	else
219		return HISI_SPI_N_BYTES_U32;
220}
221
222static void hisi_spi_reader(struct hisi_spi *hs)
223{
224	u32 max = min_t(u32, hs->rx_len, hs->fifo_len);
225	u32 rxw;
226
227	while (hisi_spi_rx_not_empty(hs) && max--) {
228		rxw = readl(hs->regs + HISI_SPI_DOUT);
229		/* Check the transfer's original "rx" is not null */
230		if (hs->rx) {
231			switch (hs->n_bytes) {
232			case HISI_SPI_N_BYTES_U8:
233				*(u8 *)(hs->rx) = rxw;
234				break;
235			case HISI_SPI_N_BYTES_U16:
236				*(u16 *)(hs->rx) = rxw;
237				break;
238			case HISI_SPI_N_BYTES_U32:
239				*(u32 *)(hs->rx) = rxw;
240				break;
241			}
242			hs->rx += hs->n_bytes;
243		}
244		--hs->rx_len;
245	}
246}
247
248static void hisi_spi_writer(struct hisi_spi *hs)
249{
250	u32 max = min_t(u32, hs->tx_len, hs->fifo_len);
251	u32 txw = 0;
252
253	while (hisi_spi_tx_not_full(hs) && max--) {
254		/* Check the transfer's original "tx" is not null */
255		if (hs->tx) {
256			switch (hs->n_bytes) {
257			case HISI_SPI_N_BYTES_U8:
258				txw = *(u8 *)(hs->tx);
259				break;
260			case HISI_SPI_N_BYTES_U16:
261				txw = *(u16 *)(hs->tx);
262				break;
263			case HISI_SPI_N_BYTES_U32:
264				txw = *(u32 *)(hs->tx);
265				break;
266			}
267			hs->tx += hs->n_bytes;
268		}
269		writel(txw, hs->regs + HISI_SPI_DIN);
270		--hs->tx_len;
271	}
272}
273
274static void __hisi_calc_div_reg(struct hisi_chip_data *chip)
275{
276	chip->div_pre = DIV_PRE_MAX;
277	while (chip->div_pre >= DIV_PRE_MIN) {
278		if (chip->clk_div % chip->div_pre == 0)
279			break;
280
281		chip->div_pre -= 2;
282	}
283
284	if (chip->div_pre > chip->clk_div)
285		chip->div_pre = chip->clk_div;
286
287	chip->div_post = (chip->clk_div / chip->div_pre) - 1;
288}
289
290static u32 hisi_calc_effective_speed(struct spi_controller *host,
291			struct hisi_chip_data *chip, u32 speed_hz)
292{
293	u32 effective_speed;
294
295	/* Note clock divider doesn't support odd numbers */
296	chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1;
297	chip->clk_div &= 0xfffe;
298	if (chip->clk_div > CLK_DIV_MAX)
299		chip->clk_div = CLK_DIV_MAX;
300
301	effective_speed = host->max_speed_hz / chip->clk_div;
302	if (chip->speed_hz != effective_speed) {
303		__hisi_calc_div_reg(chip);
304		chip->speed_hz = effective_speed;
305	}
306
307	return effective_speed;
308}
309
310static u32 hisi_spi_prepare_cr(struct spi_device *spi)
311{
312	u32 cr = FIELD_PREP(CR_SPD_MODE_MASK, 1);
313
314	cr |= FIELD_PREP(CR_CPHA_MASK, (spi->mode & SPI_CPHA) ? 1 : 0);
315	cr |= FIELD_PREP(CR_CPOL_MASK, (spi->mode & SPI_CPOL) ? 1 : 0);
316	cr |= FIELD_PREP(CR_LOOP_MASK, (spi->mode & SPI_LOOP) ? 1 : 0);
317
318	return cr;
319}
320
321static void hisi_spi_hw_init(struct hisi_spi *hs)
322{
323	hisi_spi_disable(hs);
324
325	/* FIFO default config */
326	writel(FIELD_PREP(FIFOC_TX_MASK, HISI_SPI_TX_64_OR_LESS) |
327		FIELD_PREP(FIFOC_RX_MASK, HISI_SPI_RX_16),
328		hs->regs + HISI_SPI_FIFOC);
329
330	hs->fifo_len = 256;
331}
332
333static irqreturn_t hisi_spi_irq(int irq, void *dev_id)
334{
335	struct spi_controller *host = dev_id;
336	struct hisi_spi *hs = spi_controller_get_devdata(host);
337	u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK;
338
339	if (!irq_status)
340		return IRQ_NONE;
341
342	if (!host->cur_msg)
343		return IRQ_HANDLED;
344
345	/* Error handling */
346	if (irq_status & ISR_RXOF) {
347		dev_err(hs->dev, "interrupt_transfer: fifo overflow\n");
348		host->cur_msg->status = -EIO;
349		goto finalize_transfer;
350	}
351
352	/*
353	 * Read data from the Rx FIFO every time. If there is
354	 * nothing left to receive, finalize the transfer.
355	 */
356	hisi_spi_reader(hs);
357	if (!hs->rx_len)
358		goto finalize_transfer;
359
360	/* Send data out when Tx FIFO IRQ triggered */
361	if (irq_status & ISR_TX)
362		hisi_spi_writer(hs);
363
364	return IRQ_HANDLED;
365
366finalize_transfer:
367	hisi_spi_disable(hs);
368	spi_finalize_current_transfer(host);
369	return IRQ_HANDLED;
370}
371
372static int hisi_spi_transfer_one(struct spi_controller *host,
373		struct spi_device *spi, struct spi_transfer *transfer)
374{
375	struct hisi_spi *hs = spi_controller_get_devdata(host);
376	struct hisi_chip_data *chip = spi_get_ctldata(spi);
377	u32 cr = chip->cr;
378
379	/* Update per transfer options for speed and bpw */
380	transfer->effective_speed_hz =
381		hisi_calc_effective_speed(host, chip, transfer->speed_hz);
382	cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre);
383	cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post);
384	cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1);
385	writel(cr, hs->regs + HISI_SPI_CR);
386
387	hisi_spi_flush_fifo(hs);
388
389	hs->n_bytes = hisi_spi_n_bytes(transfer);
390	hs->tx = transfer->tx_buf;
391	hs->tx_len = transfer->len / hs->n_bytes;
392	hs->rx = transfer->rx_buf;
393	hs->rx_len = hs->tx_len;
394
395	/*
396	 * Ensure that the transfer data above has been updated
397	 * before the interrupt to start.
398	 */
399	smp_mb();
400
401	/* Enable all interrupts and the controller */
402	writel(~(u32)IMR_MASK, hs->regs + HISI_SPI_IMR);
403	writel(1, hs->regs + HISI_SPI_ENR);
404
405	return 1;
406}
407
408static void hisi_spi_handle_err(struct spi_controller *host,
409		struct spi_message *msg)
410{
411	struct hisi_spi *hs = spi_controller_get_devdata(host);
412
413	hisi_spi_disable(hs);
414
415	/*
416	 * Wait for interrupt handler that is
417	 * already in timeout to complete.
418	 */
419	msleep(HISI_SPI_WAIT_TIMEOUT_MS);
420}
421
422static int hisi_spi_setup(struct spi_device *spi)
423{
424	struct hisi_chip_data *chip;
425
426	/* Only alloc on first setup */
427	chip = spi_get_ctldata(spi);
428	if (!chip) {
429		chip = kzalloc(sizeof(*chip), GFP_KERNEL);
430		if (!chip)
431			return -ENOMEM;
432		spi_set_ctldata(spi, chip);
433	}
434
435	chip->cr = hisi_spi_prepare_cr(spi);
436
437	return 0;
438}
439
440static void hisi_spi_cleanup(struct spi_device *spi)
441{
442	struct hisi_chip_data *chip = spi_get_ctldata(spi);
443
444	kfree(chip);
445	spi_set_ctldata(spi, NULL);
446}
447
448static int hisi_spi_probe(struct platform_device *pdev)
449{
450	struct device *dev = &pdev->dev;
451	struct spi_controller *host;
452	struct hisi_spi *hs;
453	int ret, irq;
454
455	irq = platform_get_irq(pdev, 0);
456	if (irq < 0)
457		return irq;
458
459	host = devm_spi_alloc_host(dev, sizeof(*hs));
460	if (!host)
461		return -ENOMEM;
462
463	platform_set_drvdata(pdev, host);
464
465	hs = spi_controller_get_devdata(host);
466	hs->dev = dev;
467	hs->irq = irq;
468
469	hs->regs = devm_platform_ioremap_resource(pdev, 0);
470	if (IS_ERR(hs->regs))
471		return PTR_ERR(hs->regs);
472
473	/* Specify maximum SPI clocking speed (host only) by firmware */
474	ret = device_property_read_u32(dev, "spi-max-frequency",
475					&host->max_speed_hz);
476	if (ret) {
477		dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n",
478			ret);
479		return -EINVAL;
480	}
481
482	if (host->max_speed_hz == 0)
483		return dev_err_probe(dev, -EINVAL, "spi-max-frequency can't be 0\n");
484
485	ret = device_property_read_u16(dev, "num-cs",
486					&host->num_chipselect);
487	if (ret)
488		host->num_chipselect = DEFAULT_NUM_CS;
489
490	host->use_gpio_descriptors = true;
491	host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
492	host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
493	host->bus_num = pdev->id;
494	host->setup = hisi_spi_setup;
495	host->cleanup = hisi_spi_cleanup;
496	host->transfer_one = hisi_spi_transfer_one;
497	host->handle_err = hisi_spi_handle_err;
498	host->dev.fwnode = dev->fwnode;
499	host->min_speed_hz = DIV_ROUND_UP(host->max_speed_hz, CLK_DIV_MAX);
500
501	hisi_spi_hw_init(hs);
502
503	ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev),
504			       host);
505	if (ret < 0) {
506		dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret);
507		return ret;
508	}
509
510	ret = spi_register_controller(host);
511	if (ret) {
512		dev_err(dev, "failed to register spi host, ret=%d\n", ret);
513		return ret;
514	}
515
516	if (hisi_spi_debugfs_init(hs))
517		dev_info(dev, "failed to create debugfs dir\n");
518
519	dev_info(dev, "hw version:0x%x max-freq:%u kHz\n",
520		readl(hs->regs + HISI_SPI_VERSION),
521		host->max_speed_hz / 1000);
522
523	return 0;
524}
525
526static void hisi_spi_remove(struct platform_device *pdev)
527{
528	struct spi_controller *host = platform_get_drvdata(pdev);
529	struct hisi_spi *hs = spi_controller_get_devdata(host);
530
531	debugfs_remove_recursive(hs->debugfs);
532	spi_unregister_controller(host);
533}
534
535static const struct acpi_device_id hisi_spi_acpi_match[] = {
536	{"HISI03E1", 0},
537	{}
538};
539MODULE_DEVICE_TABLE(acpi, hisi_spi_acpi_match);
540
541static struct platform_driver hisi_spi_driver = {
542	.probe		= hisi_spi_probe,
543	.remove		= hisi_spi_remove,
544	.driver		= {
545		.name	= "hisi-kunpeng-spi",
546		.acpi_match_table = hisi_spi_acpi_match,
547	},
548};
549module_platform_driver(hisi_spi_driver);
550
551MODULE_AUTHOR("Jay Fang <f.fangjian@huawei.com>");
552MODULE_DESCRIPTION("HiSilicon SPI Controller Driver for Kunpeng SoCs");
553MODULE_LICENSE("GPL v2");