spi-geni-qcom.c

   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4#include <linux/clk.h>
   5#include <linux/dmaengine.h>
   6#include <linux/dma-mapping.h>
   7#include <linux/dma/qcom-gpi-dma.h>
   8#include <linux/interrupt.h>
   9#include <linux/io.h>
  10#include <linux/log2.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13#include <linux/pm_opp.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/property.h>
  16#include <linux/soc/qcom/geni-se.h>
  17#include <linux/spi/spi.h>
  18#include <linux/spinlock.h>
  19
  20/* SPI SE specific registers and respective register fields */
  21#define SE_SPI_CPHA		0x224
  22#define CPHA			BIT(0)
  23
  24#define SE_SPI_LOOPBACK		0x22c
  25#define LOOPBACK_ENABLE		0x1
  26#define NORMAL_MODE		0x0
  27#define LOOPBACK_MSK		GENMASK(1, 0)
  28
  29#define SE_SPI_CPOL		0x230
  30#define CPOL			BIT(2)
  31
  32#define SE_SPI_DEMUX_OUTPUT_INV	0x24c
  33#define CS_DEMUX_OUTPUT_INV_MSK	GENMASK(3, 0)
  34
  35#define SE_SPI_DEMUX_SEL	0x250
  36#define CS_DEMUX_OUTPUT_SEL	GENMASK(3, 0)
  37
  38#define SE_SPI_TRANS_CFG	0x25c
  39#define CS_TOGGLE		BIT(1)
  40
  41#define SE_SPI_WORD_LEN		0x268
  42#define WORD_LEN_MSK		GENMASK(9, 0)
  43#define MIN_WORD_LEN		4
  44
  45#define SE_SPI_TX_TRANS_LEN	0x26c
  46#define SE_SPI_RX_TRANS_LEN	0x270
  47#define TRANS_LEN_MSK		GENMASK(23, 0)
  48
  49#define SE_SPI_PRE_POST_CMD_DLY	0x274
  50
  51#define SE_SPI_DELAY_COUNTERS	0x278
  52#define SPI_INTER_WORDS_DELAY_MSK	GENMASK(9, 0)
  53#define SPI_CS_CLK_DELAY_MSK		GENMASK(19, 10)
  54#define SPI_CS_CLK_DELAY_SHFT		10
  55
  56#define SE_SPI_SLAVE_EN				(0x2BC)
  57#define SPI_SLAVE_EN				BIT(0)
  58
  59/* M_CMD OP codes for SPI */
  60#define SPI_TX_ONLY		1
  61#define SPI_RX_ONLY		2
  62#define SPI_TX_RX		7
  63#define SPI_CS_ASSERT		8
  64#define SPI_CS_DEASSERT		9
  65#define SPI_SCK_ONLY		10
  66/* M_CMD params for SPI */
  67#define SPI_PRE_CMD_DELAY	BIT(0)
  68#define TIMESTAMP_BEFORE	BIT(1)
  69#define FRAGMENTATION		BIT(2)
  70#define TIMESTAMP_AFTER		BIT(3)
  71#define POST_CMD_DELAY		BIT(4)
  72
  73#define GSI_LOOPBACK_EN		BIT(0)
  74#define GSI_CS_TOGGLE		BIT(3)
  75#define GSI_CPHA		BIT(4)
  76#define GSI_CPOL		BIT(5)
  77
  78struct spi_geni_master {
  79	struct geni_se se;
  80	struct device *dev;
  81	u32 tx_fifo_depth;
  82	u32 fifo_width_bits;
  83	u32 tx_wm;
  84	u32 last_mode;
  85	unsigned long cur_speed_hz;
  86	unsigned long cur_sclk_hz;
  87	unsigned int cur_bits_per_word;
  88	unsigned int tx_rem_bytes;
  89	unsigned int rx_rem_bytes;
  90	const struct spi_transfer *cur_xfer;
  91	struct completion cs_done;
  92	struct completion cancel_done;
  93	struct completion abort_done;
  94	struct completion tx_reset_done;
  95	struct completion rx_reset_done;
  96	unsigned int oversampling;
  97	spinlock_t lock;
  98	int irq;
  99	bool cs_flag;
 100	bool abort_failed;
 101	struct dma_chan *tx;
 102	struct dma_chan *rx;
 103	int cur_xfer_mode;
 104};
 105
 106static void spi_slv_setup(struct spi_geni_master *mas)
 107{
 108	struct geni_se *se = &mas->se;
 109
 110	writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
 111	writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
 112	writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
 113	dev_dbg(mas->dev, "spi slave setup done\n");
 114}
 115
 116static int get_spi_clk_cfg(unsigned int speed_hz,
 117			struct spi_geni_master *mas,
 118			unsigned int *clk_idx,
 119			unsigned int *clk_div)
 120{
 121	unsigned long sclk_freq;
 122	unsigned int actual_hz;
 123	int ret;
 124
 125	ret = geni_se_clk_freq_match(&mas->se,
 126				speed_hz * mas->oversampling,
 127				clk_idx, &sclk_freq, false);
 128	if (ret) {
 129		dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
 130							ret, speed_hz);
 131		return ret;
 132	}
 133
 134	*clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
 135	actual_hz = sclk_freq / (mas->oversampling * *clk_div);
 136
 137	dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
 138				actual_hz, sclk_freq, *clk_idx, *clk_div);
 139	ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
 140	if (ret)
 141		dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
 142	else
 143		mas->cur_sclk_hz = sclk_freq;
 144
 145	return ret;
 146}
 147
 148static void handle_se_timeout(struct spi_controller *spi,
 149			      struct spi_message *msg)
 150{
 151	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
 152	unsigned long time_left;
 153	struct geni_se *se = &mas->se;
 154	const struct spi_transfer *xfer;
 155
 156	spin_lock_irq(&mas->lock);
 157	if (mas->cur_xfer_mode == GENI_SE_FIFO)
 158		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
 159
 160	xfer = mas->cur_xfer;
 161	mas->cur_xfer = NULL;
 162
 163	/* The controller doesn't support the Cancel commnand in target mode */
 164	if (!spi->target) {
 165		reinit_completion(&mas->cancel_done);
 166		geni_se_cancel_m_cmd(se);
 167
 168		spin_unlock_irq(&mas->lock);
 169
 170		time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
 171		if (time_left)
 172			goto reset_if_dma;
 173
 174		spin_lock_irq(&mas->lock);
 175	}
 176
 177	reinit_completion(&mas->abort_done);
 178	geni_se_abort_m_cmd(se);
 179	spin_unlock_irq(&mas->lock);
 180
 181	time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
 182	if (!time_left) {
 183		dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
 184
 185		/*
 186		 * No need for a lock since SPI core has a lock and we never
 187		 * access this from an interrupt.
 188		 */
 189		mas->abort_failed = true;
 190	}
 191
 192reset_if_dma:
 193	if (mas->cur_xfer_mode == GENI_SE_DMA) {
 194		if (xfer) {
 195			if (xfer->tx_buf) {
 196				spin_lock_irq(&mas->lock);
 197				reinit_completion(&mas->tx_reset_done);
 198				writel(1, se->base + SE_DMA_TX_FSM_RST);
 199				spin_unlock_irq(&mas->lock);
 200				time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ);
 201				if (!time_left)
 202					dev_err(mas->dev, "DMA TX RESET failed\n");
 203			}
 204			if (xfer->rx_buf) {
 205				spin_lock_irq(&mas->lock);
 206				reinit_completion(&mas->rx_reset_done);
 207				writel(1, se->base + SE_DMA_RX_FSM_RST);
 208				spin_unlock_irq(&mas->lock);
 209				time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ);
 210				if (!time_left)
 211					dev_err(mas->dev, "DMA RX RESET failed\n");
 212			}
 213		} else {
 214			/*
 215			 * This can happen if a timeout happened and we had to wait
 216			 * for lock in this function because isr was holding the lock
 217			 * and handling transfer completion at that time.
 218			 */
 219			dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n");
 220		}
 221	}
 222}
 223
 224static void handle_gpi_timeout(struct spi_controller *spi, struct spi_message *msg)
 225{
 226	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
 227
 228	dmaengine_terminate_sync(mas->tx);
 229	dmaengine_terminate_sync(mas->rx);
 230}
 231
 232static void spi_geni_handle_err(struct spi_controller *spi, struct spi_message *msg)
 233{
 234	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
 235
 236	switch (mas->cur_xfer_mode) {
 237	case GENI_SE_FIFO:
 238	case GENI_SE_DMA:
 239		handle_se_timeout(spi, msg);
 240		break;
 241	case GENI_GPI_DMA:
 242		handle_gpi_timeout(spi, msg);
 243		break;
 244	default:
 245		dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode);
 246	}
 247}
 248
 249static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
 250{
 251	struct geni_se *se = &mas->se;
 252	u32 m_irq, m_irq_en;
 253
 254	if (!mas->abort_failed)
 255		return false;
 256
 257	/*
 258	 * The only known case where a transfer times out and then a cancel
 259	 * times out then an abort times out is if something is blocking our
 260	 * interrupt handler from running.  Avoid starting any new transfers
 261	 * until that sorts itself out.
 262	 */
 263	spin_lock_irq(&mas->lock);
 264	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
 265	m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
 266	spin_unlock_irq(&mas->lock);
 267
 268	if (m_irq & m_irq_en) {
 269		dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
 270			m_irq & m_irq_en);
 271		return true;
 272	}
 273
 274	/*
 275	 * If we're here the problem resolved itself so no need to check more
 276	 * on future transfers.
 277	 */
 278	mas->abort_failed = false;
 279
 280	return false;
 281}
 282
 283static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
 284{
 285	struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller);
 286	struct spi_controller *spi = dev_get_drvdata(mas->dev);
 287	struct geni_se *se = &mas->se;
 288	unsigned long time_left;
 289
 290	if (!(slv->mode & SPI_CS_HIGH))
 291		set_flag = !set_flag;
 292
 293	if (set_flag == mas->cs_flag)
 294		return;
 295
 296	pm_runtime_get_sync(mas->dev);
 297
 298	if (spi_geni_is_abort_still_pending(mas)) {
 299		dev_err(mas->dev, "Can't set chip select\n");
 300		goto exit;
 301	}
 302
 303	spin_lock_irq(&mas->lock);
 304	if (mas->cur_xfer) {
 305		dev_err(mas->dev, "Can't set CS when prev xfer running\n");
 306		spin_unlock_irq(&mas->lock);
 307		goto exit;
 308	}
 309
 310	mas->cs_flag = set_flag;
 311	/* set xfer_mode to FIFO to complete cs_done in isr */
 312	mas->cur_xfer_mode = GENI_SE_FIFO;
 313	geni_se_select_mode(se, mas->cur_xfer_mode);
 314
 315	reinit_completion(&mas->cs_done);
 316	if (set_flag)
 317		geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
 318	else
 319		geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
 320	spin_unlock_irq(&mas->lock);
 321
 322	time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
 323	if (!time_left) {
 324		dev_warn(mas->dev, "Timeout setting chip select\n");
 325		handle_se_timeout(spi, NULL);
 326	}
 327
 328exit:
 329	pm_runtime_put(mas->dev);
 330}
 331
 332static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
 333					unsigned int bits_per_word)
 334{
 335	unsigned int pack_words;
 336	bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
 337	struct geni_se *se = &mas->se;
 338	u32 word_len;
 339
 340	/*
 341	 * If bits_per_word isn't a byte aligned value, set the packing to be
 342	 * 1 SPI word per FIFO word.
 343	 */
 344	if (!(mas->fifo_width_bits % bits_per_word))
 345		pack_words = mas->fifo_width_bits / bits_per_word;
 346	else
 347		pack_words = 1;
 348	geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
 349								true, true);
 350	word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
 351	writel(word_len, se->base + SE_SPI_WORD_LEN);
 352}
 353
 354static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
 355					unsigned long clk_hz)
 356{
 357	u32 clk_sel, m_clk_cfg, idx, div;
 358	struct geni_se *se = &mas->se;
 359	int ret;
 360
 361	if (clk_hz == mas->cur_speed_hz)
 362		return 0;
 363
 364	ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
 365	if (ret) {
 366		dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
 367		return ret;
 368	}
 369
 370	/*
 371	 * SPI core clock gets configured with the requested frequency
 372	 * or the frequency closer to the requested frequency.
 373	 * For that reason requested frequency is stored in the
 374	 * cur_speed_hz and referred in the consecutive transfer instead
 375	 * of calling clk_get_rate() API.
 376	 */
 377	mas->cur_speed_hz = clk_hz;
 378
 379	clk_sel = idx & CLK_SEL_MSK;
 380	m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
 381	writel(clk_sel, se->base + SE_GENI_CLK_SEL);
 382	writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
 383
 384	/* Set BW quota for CPU as driver supports FIFO mode only. */
 385	se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
 386	ret = geni_icc_set_bw(se);
 387	if (ret)
 388		return ret;
 389
 390	return 0;
 391}
 392
 393static int setup_fifo_params(struct spi_device *spi_slv,
 394					struct spi_controller *spi)
 395{
 396	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
 397	struct geni_se *se = &mas->se;
 398	u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
 399	u32 demux_sel;
 400
 401	if (mas->last_mode != spi_slv->mode) {
 402		if (spi_slv->mode & SPI_LOOP)
 403			loopback_cfg = LOOPBACK_ENABLE;
 404
 405		if (spi_slv->mode & SPI_CPOL)
 406			cpol = CPOL;
 407
 408		if (spi_slv->mode & SPI_CPHA)
 409			cpha = CPHA;
 410
 411		if (spi_slv->mode & SPI_CS_HIGH)
 412			demux_output_inv = BIT(spi_get_chipselect(spi_slv, 0));
 413
 414		demux_sel = spi_get_chipselect(spi_slv, 0);
 415		mas->cur_bits_per_word = spi_slv->bits_per_word;
 416
 417		spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
 418		writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
 419		writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
 420		writel(cpha, se->base + SE_SPI_CPHA);
 421		writel(cpol, se->base + SE_SPI_CPOL);
 422		writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
 423
 424		mas->last_mode = spi_slv->mode;
 425	}
 426
 427	return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
 428}
 429
 430static void
 431spi_gsi_callback_result(void *cb, const struct dmaengine_result *result)
 432{
 433	struct spi_controller *spi = cb;
 434
 435	spi->cur_msg->status = -EIO;
 436	if (result->result != DMA_TRANS_NOERROR) {
 437		dev_err(&spi->dev, "DMA txn failed: %d\n", result->result);
 438		spi_finalize_current_transfer(spi);
 439		return;
 440	}
 441
 442	if (!result->residue) {
 443		spi->cur_msg->status = 0;
 444		dev_dbg(&spi->dev, "DMA txn completed\n");
 445	} else {
 446		dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue);
 447	}
 448
 449	spi_finalize_current_transfer(spi);
 450}
 451
 452static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
 453			  struct spi_device *spi_slv, struct spi_controller *spi)
 454{
 455	unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
 456	struct dma_slave_config config = {};
 457	struct gpi_spi_config peripheral = {};
 458	struct dma_async_tx_descriptor *tx_desc, *rx_desc;
 459	int ret;
 460
 461	config.peripheral_config = &peripheral;
 462	config.peripheral_size = sizeof(peripheral);
 463	peripheral.set_config = true;
 464
 465	if (xfer->bits_per_word != mas->cur_bits_per_word ||
 466	    xfer->speed_hz != mas->cur_speed_hz) {
 467		mas->cur_bits_per_word = xfer->bits_per_word;
 468		mas->cur_speed_hz = xfer->speed_hz;
 469	}
 470
 471	if (xfer->tx_buf && xfer->rx_buf) {
 472		peripheral.cmd = SPI_DUPLEX;
 473	} else if (xfer->tx_buf) {
 474		peripheral.cmd = SPI_TX;
 475		peripheral.rx_len = 0;
 476	} else if (xfer->rx_buf) {
 477		peripheral.cmd = SPI_RX;
 478		if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
 479			peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
 480		} else {
 481			int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
 482
 483			peripheral.rx_len = (xfer->len / bytes_per_word);
 484		}
 485	}
 486
 487	peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
 488	peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
 489	peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
 490	peripheral.cs = spi_get_chipselect(spi_slv, 0);
 491	peripheral.pack_en = true;
 492	peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
 493
 494	ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
 495			      &peripheral.clk_src, &peripheral.clk_div);
 496	if (ret) {
 497		dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
 498		return ret;
 499	}
 500
 501	if (!xfer->cs_change) {
 502		if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers))
 503			peripheral.fragmentation = FRAGMENTATION;
 504	}
 505
 506	if (peripheral.cmd & SPI_RX) {
 507		dmaengine_slave_config(mas->rx, &config);
 508		rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
 509						  DMA_DEV_TO_MEM, flags);
 510		if (!rx_desc) {
 511			dev_err(mas->dev, "Err setting up rx desc\n");
 512			return -EIO;
 513		}
 514	}
 515
 516	/*
 517	 * Prepare the TX always, even for RX or tx_buf being null, we would
 518	 * need TX to be prepared per GSI spec
 519	 */
 520	dmaengine_slave_config(mas->tx, &config);
 521	tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
 522					  DMA_MEM_TO_DEV, flags);
 523	if (!tx_desc) {
 524		dev_err(mas->dev, "Err setting up tx desc\n");
 525		return -EIO;
 526	}
 527
 528	tx_desc->callback_result = spi_gsi_callback_result;
 529	tx_desc->callback_param = spi;
 530
 531	if (peripheral.cmd & SPI_RX)
 532		dmaengine_submit(rx_desc);
 533	dmaengine_submit(tx_desc);
 534
 535	if (peripheral.cmd & SPI_RX)
 536		dma_async_issue_pending(mas->rx);
 537
 538	dma_async_issue_pending(mas->tx);
 539	return 1;
 540}
 541
 542static u32 get_xfer_len_in_words(struct spi_transfer *xfer,
 543				struct spi_geni_master *mas)
 544{
 545	u32 len;
 546
 547	if (!(xfer->bits_per_word % MIN_WORD_LEN))
 548		len = xfer->len * BITS_PER_BYTE / xfer->bits_per_word;
 549	else
 550		len = xfer->len / (xfer->bits_per_word / BITS_PER_BYTE + 1);
 551	len &= TRANS_LEN_MSK;
 552
 553	return len;
 554}
 555
 556static bool geni_can_dma(struct spi_controller *ctlr,
 557			 struct spi_device *slv, struct spi_transfer *xfer)
 558{
 559	struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller);
 560	u32 len, fifo_size;
 561
 562	if (mas->cur_xfer_mode == GENI_GPI_DMA)
 563		return true;
 564
 565	/* Set SE DMA mode for SPI target. */
 566	if (ctlr->target)
 567		return true;
 568
 569	len = get_xfer_len_in_words(xfer, mas);
 570	fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / xfer->bits_per_word;
 571
 572	if (len > fifo_size)
 573		return true;
 574	else
 575		return false;
 576}
 577
 578static int spi_geni_prepare_message(struct spi_controller *spi,
 579				    struct spi_message *spi_msg)
 580{
 581	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
 582	int ret;
 583
 584	switch (mas->cur_xfer_mode) {
 585	case GENI_SE_FIFO:
 586	case GENI_SE_DMA:
 587		if (spi_geni_is_abort_still_pending(mas))
 588			return -EBUSY;
 589		ret = setup_fifo_params(spi_msg->spi, spi);
 590		if (ret)
 591			dev_err(mas->dev, "Couldn't select mode %d\n", ret);
 592		return ret;
 593
 594	case GENI_GPI_DMA:
 595		/* nothing to do for GPI DMA */
 596		return 0;
 597	}
 598
 599	dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
 600	return -EINVAL;
 601}
 602
 603static void spi_geni_release_dma_chan(void *data)
 604{
 605	struct spi_geni_master *mas = data;
 606
 607	if (mas->rx) {
 608		dma_release_channel(mas->rx);
 609		mas->rx = NULL;
 610	}
 611
 612	if (mas->tx) {
 613		dma_release_channel(mas->tx);
 614		mas->tx = NULL;
 615	}
 616}
 617
 618static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
 619{
 620	int ret;
 621
 622	mas->tx = dma_request_chan(mas->dev, "tx");
 623	if (IS_ERR(mas->tx)) {
 624		ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx),
 625				    "Failed to get tx DMA ch\n");
 626		goto err_tx;
 627	}
 628
 629	mas->rx = dma_request_chan(mas->dev, "rx");
 630	if (IS_ERR(mas->rx)) {
 631		ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx),
 632				    "Failed to get rx DMA ch\n");
 633		goto err_rx;
 634	}
 635
 636	ret = devm_add_action_or_reset(mas->dev, spi_geni_release_dma_chan, mas);
 637	if (ret) {
 638		dev_err(mas->dev, "Unable to add action.\n");
 639		return ret;
 640	}
 641
 642	return 0;
 643
 644err_rx:
 645	mas->rx = NULL;
 646	dma_release_channel(mas->tx);
 647err_tx:
 648	mas->tx = NULL;
 649	return ret;
 650}
 651
 652static int spi_geni_init(struct spi_geni_master *mas)
 653{
 654	struct spi_controller *spi = dev_get_drvdata(mas->dev);
 655	struct geni_se *se = &mas->se;
 656	unsigned int proto, major, minor, ver;
 657	u32 spi_tx_cfg, fifo_disable;
 658	int ret = -ENXIO;
 659
 660	pm_runtime_get_sync(mas->dev);
 661
 662	proto = geni_se_read_proto(se);
 663
 664	if (spi->target) {
 665		if (proto != GENI_SE_SPI_SLAVE) {
 666			dev_err(mas->dev, "Invalid proto %d\n", proto);
 667			goto out_pm;
 668		}
 669		spi_slv_setup(mas);
 670	} else if (proto == GENI_SE_INVALID_PROTO) {
 671		ret = geni_load_se_firmware(se, GENI_SE_SPI);
 672		if (ret) {
 673			dev_err(mas->dev, "spi master firmware load failed ret: %d\n", ret);
 674			goto out_pm;
 675		}
 676	} else if (proto != GENI_SE_SPI) {
 677		dev_err(mas->dev, "Invalid proto %d\n", proto);
 678		goto out_pm;
 679	}
 680	mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
 681
 682	/* Width of Tx and Rx FIFO is same */
 683	mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
 684
 685	/*
 686	 * Hardware programming guide suggests to configure
 687	 * RX FIFO RFR level to fifo_depth-2.
 688	 */
 689	geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
 690	/* Transmit an entire FIFO worth of data per IRQ */
 691	mas->tx_wm = 1;
 692	ver = geni_se_get_qup_hw_version(se);
 693	major = GENI_SE_VERSION_MAJOR(ver);
 694	minor = GENI_SE_VERSION_MINOR(ver);
 695
 696	if (major == 1 && minor == 0)
 697		mas->oversampling = 2;
 698	else
 699		mas->oversampling = 1;
 700
 701	fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
 702	switch (fifo_disable) {
 703	case 1:
 704		ret = spi_geni_grab_gpi_chan(mas);
 705		if (!ret) { /* success case */
 706			mas->cur_xfer_mode = GENI_GPI_DMA;
 707			geni_se_select_mode(se, GENI_GPI_DMA);
 708			dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
 709			break;
 710		} else if (ret == -EPROBE_DEFER) {
 711			goto out_pm;
 712		}
 713		/*
 714		 * in case of failure to get gpi dma channel, we can still do the
 715		 * FIFO mode, so fallthrough
 716		 */
 717		dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
 718		fallthrough;
 719
 720	case 0:
 721		mas->cur_xfer_mode = GENI_SE_FIFO;
 722		geni_se_select_mode(se, GENI_SE_FIFO);
 723		/* setup_fifo_params assumes that these registers start with a zero value */
 724		writel(0, se->base + SE_SPI_LOOPBACK);
 725		writel(0, se->base + SE_SPI_DEMUX_SEL);
 726		writel(0, se->base + SE_SPI_CPHA);
 727		writel(0, se->base + SE_SPI_CPOL);
 728		writel(0, se->base + SE_SPI_DEMUX_OUTPUT_INV);
 729		ret = 0;
 730		break;
 731	}
 732
 733	/* We always control CS manually */
 734	if (!spi->target) {
 735		spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
 736		spi_tx_cfg &= ~CS_TOGGLE;
 737		writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
 738	}
 739
 740out_pm:
 741	pm_runtime_put(mas->dev);
 742	return ret;
 743}
 744
 745static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
 746{
 747	/*
 748	 * Calculate how many bytes we'll put in each FIFO word.  If the
 749	 * transfer words don't pack cleanly into a FIFO word we'll just put
 750	 * one transfer word in each FIFO word.  If they do pack we'll pack 'em.
 751	 */
 752	if (mas->fifo_width_bits % mas->cur_bits_per_word)
 753		return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
 754						       BITS_PER_BYTE));
 755
 756	return mas->fifo_width_bits / BITS_PER_BYTE;
 757}
 758
 759static bool geni_spi_handle_tx(struct spi_geni_master *mas)
 760{
 761	struct geni_se *se = &mas->se;
 762	unsigned int max_bytes;
 763	const u8 *tx_buf;
 764	unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
 765	unsigned int i = 0;
 766
 767	/* Stop the watermark IRQ if nothing to send */
 768	if (!mas->cur_xfer) {
 769		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
 770		return false;
 771	}
 772
 773	max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
 774	if (mas->tx_rem_bytes < max_bytes)
 775		max_bytes = mas->tx_rem_bytes;
 776
 777	tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
 778	while (i < max_bytes) {
 779		unsigned int j;
 780		unsigned int bytes_to_write;
 781		u32 fifo_word = 0;
 782		u8 *fifo_byte = (u8 *)&fifo_word;
 783
 784		bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
 785		for (j = 0; j < bytes_to_write; j++)
 786			fifo_byte[j] = tx_buf[i++];
 787		iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
 788	}
 789	mas->tx_rem_bytes -= max_bytes;
 790	if (!mas->tx_rem_bytes) {
 791		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
 792		return false;
 793	}
 794	return true;
 795}
 796
 797static void geni_spi_handle_rx(struct spi_geni_master *mas)
 798{
 799	struct geni_se *se = &mas->se;
 800	u32 rx_fifo_status;
 801	unsigned int rx_bytes;
 802	unsigned int rx_last_byte_valid;
 803	u8 *rx_buf;
 804	unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
 805	unsigned int i = 0;
 806
 807	rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
 808	rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
 809	if (rx_fifo_status & RX_LAST) {
 810		rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
 811		rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
 812		if (rx_last_byte_valid && rx_last_byte_valid < 4)
 813			rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
 814	}
 815
 816	/* Clear out the FIFO and bail if nowhere to put it */
 817	if (!mas->cur_xfer) {
 818		for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
 819			readl(se->base + SE_GENI_RX_FIFOn);
 820		return;
 821	}
 822
 823	if (mas->rx_rem_bytes < rx_bytes)
 824		rx_bytes = mas->rx_rem_bytes;
 825
 826	rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
 827	while (i < rx_bytes) {
 828		u32 fifo_word = 0;
 829		u8 *fifo_byte = (u8 *)&fifo_word;
 830		unsigned int bytes_to_read;
 831		unsigned int j;
 832
 833		bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
 834		ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
 835		for (j = 0; j < bytes_to_read; j++)
 836			rx_buf[i++] = fifo_byte[j];
 837	}
 838	mas->rx_rem_bytes -= rx_bytes;
 839}
 840
 841static int setup_se_xfer(struct spi_transfer *xfer,
 842				struct spi_geni_master *mas,
 843				u16 mode, struct spi_controller *spi)
 844{
 845	u32 m_cmd = 0;
 846	u32 len;
 847	struct geni_se *se = &mas->se;
 848	int ret;
 849
 850	/*
 851	 * Ensure that our interrupt handler isn't still running from some
 852	 * prior command before we start messing with the hardware behind
 853	 * its back.  We don't need to _keep_ the lock here since we're only
 854	 * worried about racing with out interrupt handler.  The SPI core
 855	 * already handles making sure that we're not trying to do two
 856	 * transfers at once or setting a chip select and doing a transfer
 857	 * concurrently.
 858	 *
 859	 * NOTE: we actually _can't_ hold the lock here because possibly we
 860	 * might call clk_set_rate() which needs to be able to sleep.
 861	 */
 862	spin_lock_irq(&mas->lock);
 863	spin_unlock_irq(&mas->lock);
 864
 865	if (xfer->bits_per_word != mas->cur_bits_per_word) {
 866		spi_setup_word_len(mas, mode, xfer->bits_per_word);
 867		mas->cur_bits_per_word = xfer->bits_per_word;
 868	}
 869
 870	/* Speed and bits per word can be overridden per transfer */
 871	ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
 872	if (ret)
 873		return ret;
 874
 875	mas->tx_rem_bytes = 0;
 876	mas->rx_rem_bytes = 0;
 877
 878	len = get_xfer_len_in_words(xfer, mas);
 879
 880	mas->cur_xfer = xfer;
 881	if (xfer->tx_buf) {
 882		m_cmd |= SPI_TX_ONLY;
 883		mas->tx_rem_bytes = xfer->len;
 884		writel(len, se->base + SE_SPI_TX_TRANS_LEN);
 885	}
 886
 887	if (xfer->rx_buf) {
 888		m_cmd |= SPI_RX_ONLY;
 889		writel(len, se->base + SE_SPI_RX_TRANS_LEN);
 890		mas->rx_rem_bytes = xfer->len;
 891	}
 892
 893	/*
 894	 * Select DMA mode if sgt are present; and with only 1 entry
 895	 * This is not a serious limitation because the xfer buffers are
 896	 * expected to fit into in 1 entry almost always, and if any
 897	 * doesn't for any reason we fall back to FIFO mode anyway
 898	 */
 899	if (!xfer->tx_sg.nents && !xfer->rx_sg.nents)
 900		mas->cur_xfer_mode = GENI_SE_FIFO;
 901	else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) {
 902		dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n",
 903			xfer->tx_sg.nents, xfer->rx_sg.nents);
 904		mas->cur_xfer_mode = GENI_SE_FIFO;
 905	} else
 906		mas->cur_xfer_mode = GENI_SE_DMA;
 907	geni_se_select_mode(se, mas->cur_xfer_mode);
 908
 909	/*
 910	 * Lock around right before we start the transfer since our
 911	 * interrupt could come in at any time now.
 912	 */
 913	spin_lock_irq(&mas->lock);
 914	geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
 915
 916	if (mas->cur_xfer_mode == GENI_SE_DMA) {
 917		if (m_cmd & SPI_RX_ONLY)
 918			geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),
 919				sg_dma_len(xfer->rx_sg.sgl));
 920		if (m_cmd & SPI_TX_ONLY)
 921			geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl),
 922				sg_dma_len(xfer->tx_sg.sgl));
 923	} else if (m_cmd & SPI_TX_ONLY) {
 924		if (geni_spi_handle_tx(mas))
 925			writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
 926	}
 927
 928	spin_unlock_irq(&mas->lock);
 929	return ret;
 930}
 931
 932static int spi_geni_transfer_one(struct spi_controller *spi,
 933				 struct spi_device *slv,
 934				 struct spi_transfer *xfer)
 935{
 936	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
 937	int ret;
 938
 939	if (spi_geni_is_abort_still_pending(mas))
 940		return -EBUSY;
 941
 942	/* Terminate and return success for 0 byte length transfer */
 943	if (!xfer->len)
 944		return 0;
 945
 946	if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) {
 947		ret = setup_se_xfer(xfer, mas, slv->mode, spi);
 948		/* SPI framework expects +ve ret code to wait for transfer complete */
 949		if (!ret)
 950			ret = 1;
 951		return ret;
 952	}
 953	return setup_gsi_xfer(xfer, mas, slv, spi);
 954}
 955
 956static irqreturn_t geni_spi_isr(int irq, void *data)
 957{
 958	struct spi_controller *spi = data;
 959	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
 960	struct geni_se *se = &mas->se;
 961	u32 m_irq, dma_tx_status, dma_rx_status;
 962
 963	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
 964	dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
 965	dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
 966
 967	if (!m_irq && !dma_tx_status && !dma_rx_status)
 968		return IRQ_NONE;
 969
 970	if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
 971		     M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
 972		     M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
 973		dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
 974
 975	spin_lock(&mas->lock);
 976
 977	if (mas->cur_xfer_mode == GENI_SE_FIFO) {
 978		if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
 979			geni_spi_handle_rx(mas);
 980
 981		if (m_irq & M_TX_FIFO_WATERMARK_EN)
 982			geni_spi_handle_tx(mas);
 983
 984		if (m_irq & M_CMD_DONE_EN) {
 985			if (mas->cur_xfer) {
 986				spi_finalize_current_transfer(spi);
 987				mas->cur_xfer = NULL;
 988				/*
 989				 * If this happens, then a CMD_DONE came before all the
 990				 * Tx buffer bytes were sent out. This is unusual, log
 991				 * this condition and disable the WM interrupt to
 992				 * prevent the system from stalling due an interrupt
 993				 * storm.
 994				 *
 995				 * If this happens when all Rx bytes haven't been
 996				 * received, log the condition. The only known time
 997				 * this can happen is if bits_per_word != 8 and some
 998				 * registers that expect xfer lengths in num spi_words
 999				 * weren't written correctly.
1000				 */
1001				if (mas->tx_rem_bytes) {
1002					writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
1003					dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
1004						mas->tx_rem_bytes, mas->cur_bits_per_word);
1005				}
1006				if (mas->rx_rem_bytes)
1007					dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
1008						mas->rx_rem_bytes, mas->cur_bits_per_word);
1009			} else {
1010				complete(&mas->cs_done);
1011			}
1012		}
1013	} else if (mas->cur_xfer_mode == GENI_SE_DMA) {
1014		const struct spi_transfer *xfer = mas->cur_xfer;
1015
1016		if (dma_tx_status)
1017			writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);
1018		if (dma_rx_status)
1019			writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);
1020		if (dma_tx_status & TX_DMA_DONE)
1021			mas->tx_rem_bytes = 0;
1022		if (dma_rx_status & RX_DMA_DONE)
1023			mas->rx_rem_bytes = 0;
1024		if (dma_tx_status & TX_RESET_DONE)
1025			complete(&mas->tx_reset_done);
1026		if (dma_rx_status & RX_RESET_DONE)
1027			complete(&mas->rx_reset_done);
1028		if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) {
1029			spi_finalize_current_transfer(spi);
1030			mas->cur_xfer = NULL;
1031		}
1032	}
1033
1034	if (m_irq & M_CMD_CANCEL_EN)
1035		complete(&mas->cancel_done);
1036	if (m_irq & M_CMD_ABORT_EN)
1037		complete(&mas->abort_done);
1038
1039	/*
1040	 * It's safe or a good idea to Ack all of our interrupts at the end
1041	 * of the function. Specifically:
1042	 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
1043	 *   clearing Acks. Clearing at the end relies on nobody else having
1044	 *   started a new transfer yet or else we could be clearing _their_
1045	 *   done bit, but everyone grabs the spinlock before starting a new
1046	 *   transfer.
1047	 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
1048	 *   to be "latched level" interrupts so it's important to clear them
1049	 *   _after_ you've handled the condition and always safe to do so
1050	 *   since they'll re-assert if they're still happening.
1051	 */
1052	writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
1053
1054	spin_unlock(&mas->lock);
1055
1056	return IRQ_HANDLED;
1057}
1058
1059static int spi_geni_probe(struct platform_device *pdev)
1060{
1061	int ret, irq;
1062	struct spi_controller *spi;
1063	struct spi_geni_master *mas;
1064	void __iomem *base;
1065	struct clk *clk;
1066	struct device *dev = &pdev->dev;
1067
1068	irq = platform_get_irq(pdev, 0);
1069	if (irq < 0)
1070		return irq;
1071
1072	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
1073	if (ret)
1074		return dev_err_probe(dev, ret, "could not set DMA mask\n");
1075
1076	base = devm_platform_ioremap_resource(pdev, 0);
1077	if (IS_ERR(base))
1078		return PTR_ERR(base);
1079
1080	clk = devm_clk_get(dev, "se");
1081	if (IS_ERR(clk))
1082		return PTR_ERR(clk);
1083
1084	spi = devm_spi_alloc_host(dev, sizeof(*mas));
1085	if (!spi)
1086		return -ENOMEM;
1087
1088	platform_set_drvdata(pdev, spi);
1089	mas = spi_controller_get_devdata(spi);
1090	mas->irq = irq;
1091	mas->dev = dev;
1092	mas->se.dev = dev;
1093	mas->se.wrapper = dev_get_drvdata(dev->parent);
1094	mas->se.base = base;
1095	mas->se.clk = clk;
1096
1097	ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1098	if (ret)
1099		return ret;
1100	/* OPP table is optional */
1101	ret = devm_pm_opp_of_add_table(&pdev->dev);
1102	if (ret && ret != -ENODEV) {
1103		dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1104		return ret;
1105	}
1106
1107	spi->bus_num = -1;
1108	spi->dev.of_node = dev->of_node;
1109	spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
1110	spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1111	spi->num_chipselect = 4;
1112	spi->max_speed_hz = 50000000;
1113	spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */
1114	spi->prepare_message = spi_geni_prepare_message;
1115	spi->transfer_one = spi_geni_transfer_one;
1116	spi->can_dma = geni_can_dma;
1117	spi->dma_map_dev = dev->parent;
1118	spi->auto_runtime_pm = true;
1119	spi->handle_err = spi_geni_handle_err;
1120	spi->use_gpio_descriptors = true;
1121
1122	init_completion(&mas->cs_done);
1123	init_completion(&mas->cancel_done);
1124	init_completion(&mas->abort_done);
1125	init_completion(&mas->tx_reset_done);
1126	init_completion(&mas->rx_reset_done);
1127	spin_lock_init(&mas->lock);
1128
1129	ret = geni_icc_get(&mas->se, NULL);
1130	if (ret)
1131		return ret;
1132
1133	pm_runtime_use_autosuspend(&pdev->dev);
1134	pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
1135	ret = devm_pm_runtime_enable(dev);
1136	if (ret)
1137		return ret;
1138
1139	if (device_property_read_bool(&pdev->dev, "spi-slave"))
1140		spi->target = true;
1141
1142	/* Set the bus quota to a reasonable value for register access */
1143	mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
1144	mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1145
1146	ret = geni_icc_set_bw(&mas->se);
1147	if (ret)
1148		return ret;
1149
1150	ret = spi_geni_init(mas);
1151	if (ret)
1152		return ret;
1153
1154	/*
1155	 * check the mode supported and set_cs for fifo mode only
1156	 * for dma (gsi) mode, the gsi will set cs based on params passed in
1157	 * TRE
1158	 */
1159	if (!spi->target && mas->cur_xfer_mode == GENI_SE_FIFO)
1160		spi->set_cs = spi_geni_set_cs;
1161
1162	/*
1163	 * TX is required per GSI spec, see setup_gsi_xfer().
1164	 */
1165	if (mas->cur_xfer_mode == GENI_GPI_DMA)
1166		spi->flags = SPI_CONTROLLER_MUST_TX;
1167
1168	ret = devm_request_irq(dev, mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
1169	if (ret)
1170		return ret;
1171
1172	return devm_spi_register_controller(dev, spi);
1173}
1174
1175static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
1176{
1177	struct spi_controller *spi = dev_get_drvdata(dev);
1178	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1179	int ret;
1180
1181	/* Drop the performance state vote */
1182	dev_pm_opp_set_rate(dev, 0);
1183
1184	ret = geni_se_resources_off(&mas->se);
1185	if (ret)
1186		return ret;
1187
1188	return geni_icc_disable(&mas->se);
1189}
1190
1191static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
1192{
1193	struct spi_controller *spi = dev_get_drvdata(dev);
1194	struct spi_geni_master *mas = spi_controller_get_devdata(spi);
1195	int ret;
1196
1197	ret = geni_icc_enable(&mas->se);
1198	if (ret)
1199		return ret;
1200
1201	ret = geni_se_resources_on(&mas->se);
1202	if (ret)
1203		return ret;
1204
1205	return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
1206}
1207
1208static int __maybe_unused spi_geni_suspend(struct device *dev)
1209{
1210	struct spi_controller *spi = dev_get_drvdata(dev);
1211	int ret;
1212
1213	ret = spi_controller_suspend(spi);
1214	if (ret)
1215		return ret;
1216
1217	ret = pm_runtime_force_suspend(dev);
1218	if (ret)
1219		spi_controller_resume(spi);
1220
1221	return ret;
1222}
1223
1224static int __maybe_unused spi_geni_resume(struct device *dev)
1225{
1226	struct spi_controller *spi = dev_get_drvdata(dev);
1227	int ret;
1228
1229	ret = pm_runtime_force_resume(dev);
1230	if (ret)
1231		return ret;
1232
1233	ret = spi_controller_resume(spi);
1234	if (ret)
1235		pm_runtime_force_suspend(dev);
1236
1237	return ret;
1238}
1239
1240static const struct dev_pm_ops spi_geni_pm_ops = {
1241	SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
1242					spi_geni_runtime_resume, NULL)
1243	SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
1244};
1245
1246static const struct of_device_id spi_geni_dt_match[] = {
1247	{ .compatible = "qcom,geni-spi" },
1248	{}
1249};
1250MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
1251
1252static struct platform_driver spi_geni_driver = {
1253	.probe  = spi_geni_probe,
1254	.driver = {
1255		.name = "geni_spi",
1256		.pm = &spi_geni_pm_ops,
1257		.of_match_table = spi_geni_dt_match,
1258	},
1259};
1260module_platform_driver(spi_geni_driver);
1261
1262MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
1263MODULE_LICENSE("GPL v2");