spi-cadence.c

  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Cadence SPI controller driver (host and target mode)
  4 *
  5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
  6 *
  7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
  8 */
  9
 10#include <linux/clk.h>
 11#include <linux/delay.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/interrupt.h>
 14#include <linux/io.h>
 15#include <linux/kernel.h>
 16#include <linux/module.h>
 17#include <linux/of_irq.h>
 18#include <linux/of_address.h>
 19#include <linux/platform_device.h>
 20#include <linux/pm_runtime.h>
 21#include <linux/reset.h>
 22#include <linux/spi/spi.h>
 23
 24/* Name of this driver */
 25#define CDNS_SPI_NAME		"cdns-spi"
 26
 27/* Register offset definitions */
 28#define CDNS_SPI_CR	0x00 /* Configuration  Register, RW */
 29#define CDNS_SPI_ISR	0x04 /* Interrupt Status Register, RO */
 30#define CDNS_SPI_IER	0x08 /* Interrupt Enable Register, WO */
 31#define CDNS_SPI_IDR	0x0c /* Interrupt Disable Register, WO */
 32#define CDNS_SPI_IMR	0x10 /* Interrupt Enabled Mask Register, RO */
 33#define CDNS_SPI_ER	0x14 /* Enable/Disable Register, RW */
 34#define CDNS_SPI_DR	0x18 /* Delay Register, RW */
 35#define CDNS_SPI_TXD	0x1C /* Data Transmit Register, WO */
 36#define CDNS_SPI_RXD	0x20 /* Data Receive Register, RO */
 37#define CDNS_SPI_SICR	0x24 /* Slave Idle Count Register, RW */
 38#define CDNS_SPI_THLD	0x28 /* Transmit FIFO Watermark Register,RW */
 39
 40#define SPI_AUTOSUSPEND_TIMEOUT		3000
 41/*
 42 * SPI Configuration Register bit Masks
 43 *
 44 * This register contains various control bits that affect the operation
 45 * of the SPI controller
 46 */
 47#define CDNS_SPI_CR_MANSTRT	0x00010000 /* Manual TX Start */
 48#define CDNS_SPI_CR_CPHA		0x00000004 /* Clock Phase Control */
 49#define CDNS_SPI_CR_CPOL		0x00000002 /* Clock Polarity Control */
 50#define CDNS_SPI_CR_SSCTRL		0x00003C00 /* Slave Select Mask */
 51#define CDNS_SPI_CR_PERI_SEL	0x00000200 /* Peripheral Select Decode */
 52#define CDNS_SPI_CR_BAUD_DIV	0x00000038 /* Baud Rate Divisor Mask */
 53#define CDNS_SPI_CR_MSTREN		0x00000001 /* Master Enable Mask */
 54#define CDNS_SPI_CR_MANSTRTEN	0x00008000 /* Manual TX Enable Mask */
 55#define CDNS_SPI_CR_SSFORCE	0x00004000 /* Manual SS Enable Mask */
 56#define CDNS_SPI_CR_BAUD_DIV_4	0x00000008 /* Default Baud Div Mask */
 57#define CDNS_SPI_CR_DEFAULT	(CDNS_SPI_CR_MSTREN | \
 58					CDNS_SPI_CR_SSCTRL | \
 59					CDNS_SPI_CR_SSFORCE | \
 60					CDNS_SPI_CR_BAUD_DIV_4)
 61
 62/*
 63 * SPI Configuration Register - Baud rate and target select
 64 *
 65 * These are the values used in the calculation of baud rate divisor and
 66 * setting the target select.
 67 */
 68
 69#define CDNS_SPI_BAUD_DIV_MAX		7 /* Baud rate divisor maximum */
 70#define CDNS_SPI_BAUD_DIV_MIN		1 /* Baud rate divisor minimum */
 71#define CDNS_SPI_BAUD_DIV_SHIFT		3 /* Baud rate divisor shift in CR */
 72#define CDNS_SPI_SS_SHIFT		10 /* Slave Select field shift in CR */
 73#define CDNS_SPI_SS0			0x1 /* Slave Select zero */
 74#define CDNS_SPI_NOSS			0xF /* No Slave select */
 75
 76/*
 77 * SPI Interrupt Registers bit Masks
 78 *
 79 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
 80 * bit definitions.
 81 */
 82#define CDNS_SPI_IXR_TXOW	0x00000004 /* SPI TX FIFO Overwater */
 83#define CDNS_SPI_IXR_MODF	0x00000002 /* SPI Mode Fault */
 84#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
 85#define CDNS_SPI_IXR_DEFAULT	(CDNS_SPI_IXR_TXOW | \
 86					CDNS_SPI_IXR_MODF)
 87#define CDNS_SPI_IXR_TXFULL	0x00000008 /* SPI TX Full */
 88#define CDNS_SPI_IXR_ALL	0x0000007F /* SPI all interrupts */
 89
 90/*
 91 * SPI Enable Register bit Masks
 92 *
 93 * This register is used to enable or disable the SPI controller
 94 */
 95#define CDNS_SPI_ER_ENABLE	0x00000001 /* SPI Enable Bit Mask */
 96#define CDNS_SPI_ER_DISABLE	0x0 /* SPI Disable Bit Mask */
 97
 98/* Default number of chip select lines */
 99#define CDNS_SPI_DEFAULT_NUM_CS		4
100
101/**
102 * struct cdns_spi - This definition defines spi driver instance
103 * @regs:		Virtual address of the SPI controller registers
104 * @ref_clk:		Pointer to the peripheral clock
105 * @pclk:		Pointer to the APB clock
106 * @clk_rate:		Reference clock frequency, taken from @ref_clk
107 * @speed_hz:		Current SPI bus clock speed in Hz
108 * @txbuf:		Pointer	to the TX buffer
109 * @rxbuf:		Pointer to the RX buffer
110 * @tx_bytes:		Number of bytes left to transfer
111 * @rx_bytes:		Number of bytes requested
112 * @n_bytes:		Number of bytes per word
113 * @dev_busy:		Device busy flag
114 * @is_decoded_cs:	Flag for decoder property set or not
115 * @tx_fifo_depth:	Depth of the TX FIFO
116 * @rstc:		Optional reset control for SPI controller
117 */
118struct cdns_spi {
119	void __iomem *regs;
120	struct clk *ref_clk;
121	struct clk *pclk;
122	unsigned int clk_rate;
123	u32 speed_hz;
124	const void *txbuf;
125	void *rxbuf;
126	int tx_bytes;
127	int rx_bytes;
128	u8 n_bytes;
129	u8 dev_busy;
130	u32 is_decoded_cs;
131	unsigned int tx_fifo_depth;
132	struct reset_control *rstc;
133};
134
135enum cdns_spi_frame_n_bytes {
136	CDNS_SPI_N_BYTES_NULL = 0,
137	CDNS_SPI_N_BYTES_U8 = 1,
138	CDNS_SPI_N_BYTES_U16 = 2,
139	CDNS_SPI_N_BYTES_U32 = 4
140};
141
142/* Macros for the SPI controller read/write */
143static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
144{
145	return readl_relaxed(xspi->regs + offset);
146}
147
148static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
149{
150	writel_relaxed(val, xspi->regs + offset);
151}
152
153/**
154 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
155 * @xspi:	Pointer to the cdns_spi structure
156 * @is_target:	Flag to indicate target or host mode
157 * * On reset the SPI controller is configured to target or host mode.
158 * In host mode baud rate divisor is set to 4, threshold value for TX FIFO
159 * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
160 *
161 * This function initializes the SPI controller to disable and clear all the
162 * interrupts, enable manual target select and manual start, deselect all the
163 * chip select lines, and enable the SPI controller.
164 */
165static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
166{
167	u32 ctrl_reg = 0;
168
169	if (!is_target)
170		ctrl_reg |= CDNS_SPI_CR_DEFAULT;
171
172	if (xspi->is_decoded_cs)
173		ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
174
175	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
176	cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
177
178	/* Clear the RX FIFO */
179	while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
180		cdns_spi_read(xspi, CDNS_SPI_RXD);
181
182	cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
183	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
184	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
185}
186
187/**
188 * cdns_spi_chipselect - Select or deselect the chip select line
189 * @spi:	Pointer to the spi_device structure
190 * @is_high:	Select(0) or deselect (1) the chip select line
191 */
192static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
193{
194	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
195	u32 ctrl_reg;
196
197	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
198
199	if (is_high) {
200		/* Deselect the target */
201		ctrl_reg |= CDNS_SPI_CR_SSCTRL;
202	} else {
203		/* Select the target */
204		ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
205		if (!(xspi->is_decoded_cs))
206			ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
207				     CDNS_SPI_SS_SHIFT) &
208				     CDNS_SPI_CR_SSCTRL;
209		else
210			ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
211				     CDNS_SPI_CR_SSCTRL;
212	}
213
214	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
215}
216
217/**
218 * cdns_spi_config_clock_mode - Sets clock polarity and phase
219 * @spi:	Pointer to the spi_device structure
220 *
221 * Sets the requested clock polarity and phase.
222 */
223static void cdns_spi_config_clock_mode(struct spi_device *spi)
224{
225	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
226	u32 ctrl_reg, new_ctrl_reg;
227
228	new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
229	ctrl_reg = new_ctrl_reg;
230
231	/* Set the SPI clock phase and clock polarity */
232	new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
233	if (spi->mode & SPI_CPHA)
234		new_ctrl_reg |= CDNS_SPI_CR_CPHA;
235	if (spi->mode & SPI_CPOL)
236		new_ctrl_reg |= CDNS_SPI_CR_CPOL;
237
238	if (new_ctrl_reg != ctrl_reg) {
239		/*
240		 * Just writing the CR register does not seem to apply the clock
241		 * setting changes. This is problematic when changing the clock
242		 * polarity as it will cause the SPI target to see spurious clock
243		 * transitions. To workaround the issue toggle the ER register.
244		 */
245		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
246		cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
247		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
248	}
249}
250
251/**
252 * cdns_spi_config_clock_freq - Sets clock frequency
253 * @spi:	Pointer to the spi_device structure
254 * @transfer:	Pointer to the spi_transfer structure which provides
255 *		information about next transfer setup parameters
256 *
257 * Sets the requested clock frequency.
258 * Note: If the requested frequency is not an exact match with what can be
259 * obtained using the prescalar value the driver sets the clock frequency which
260 * is lower than the requested frequency (maximum lower) for the transfer. If
261 * the requested frequency is higher or lower than that is supported by the SPI
262 * controller the driver will set the highest or lowest frequency supported by
263 * controller.
264 */
265static void cdns_spi_config_clock_freq(struct spi_device *spi,
266				       struct spi_transfer *transfer)
267{
268	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
269	u32 ctrl_reg, baud_rate_val;
270	unsigned long frequency;
271
272	frequency = xspi->clk_rate;
273
274	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
275
276	/* Set the clock frequency */
277	if (xspi->speed_hz != transfer->speed_hz) {
278		/* first valid value is 1 */
279		baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
280		while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
281		       (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
282			baud_rate_val++;
283
284		ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
285		ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
286
287		xspi->speed_hz = frequency / (2 << baud_rate_val);
288	}
289	cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
290}
291
292/**
293 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
294 * @spi:	Pointer to the spi_device structure
295 * @transfer:	Pointer to the spi_transfer structure which provides
296 *		information about next transfer setup parameters
297 *
298 * Sets the operational mode of SPI controller for the next SPI transfer and
299 * sets the requested clock frequency.
300 *
301 * Return:	Always 0
302 */
303static int cdns_spi_setup_transfer(struct spi_device *spi,
304				   struct spi_transfer *transfer)
305{
306	struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
307
308	cdns_spi_config_clock_freq(spi, transfer);
309
310	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
311		__func__, spi->mode, spi->bits_per_word,
312		xspi->speed_hz);
313
314	return 0;
315}
316
317static u8 cdns_spi_n_bytes(struct spi_transfer *transfer)
318{
319	if (transfer->bits_per_word <= 8)
320		return CDNS_SPI_N_BYTES_U8;
321	else if (transfer->bits_per_word <= 16)
322		return CDNS_SPI_N_BYTES_U16;
323	else
324		return CDNS_SPI_N_BYTES_U32;
325}
326
327static inline void cdns_spi_reader(struct cdns_spi *xspi)
328{
329	u32 rxw = 0;
330
331	if (xspi->rxbuf && !IS_ALIGNED((uintptr_t)xspi->rxbuf, xspi->n_bytes)) {
332		pr_err("%s: rxbuf address is not aligned for %d bytes\n",
333		       __func__, xspi->n_bytes);
334		return;
335	}
336
337	rxw = cdns_spi_read(xspi, CDNS_SPI_RXD);
338	if (xspi->rxbuf) {
339		switch (xspi->n_bytes) {
340		case CDNS_SPI_N_BYTES_U8:
341			*(u8 *)xspi->rxbuf = rxw;
342			break;
343		case CDNS_SPI_N_BYTES_U16:
344			*(u16 *)xspi->rxbuf = rxw;
345			break;
346		case CDNS_SPI_N_BYTES_U32:
347			*(u32 *)xspi->rxbuf = rxw;
348			break;
349		default:
350			pr_err("%s invalid n_bytes %d\n", __func__,
351			       xspi->n_bytes);
352			return;
353		}
354		xspi->rxbuf = (u8 *)xspi->rxbuf + xspi->n_bytes;
355	}
356}
357
358static inline void cdns_spi_writer(struct cdns_spi *xspi)
359{
360	u32 txw = 0;
361
362	if (xspi->txbuf && !IS_ALIGNED((uintptr_t)xspi->txbuf, xspi->n_bytes)) {
363		pr_err("%s: txbuf address is not aligned for %d bytes\n",
364		       __func__, xspi->n_bytes);
365		return;
366	}
367
368	if (xspi->txbuf) {
369		switch (xspi->n_bytes) {
370		case CDNS_SPI_N_BYTES_U8:
371			txw = *(u8 *)xspi->txbuf;
372			break;
373		case CDNS_SPI_N_BYTES_U16:
374			txw = *(u16 *)xspi->txbuf;
375			break;
376		case CDNS_SPI_N_BYTES_U32:
377			txw = *(u32 *)xspi->txbuf;
378			break;
379		default:
380			pr_err("%s invalid n_bytes %d\n", __func__,
381			       xspi->n_bytes);
382			return;
383		}
384		cdns_spi_write(xspi, CDNS_SPI_TXD, txw);
385		xspi->txbuf = (u8 *)xspi->txbuf + xspi->n_bytes;
386	}
387}
388
389/**
390 * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
391 * @xspi:	Pointer to the cdns_spi structure
392 * @ntx:	Number of bytes to pack into the TX FIFO
393 * @nrx:	Number of bytes to drain from the RX FIFO
394 */
395static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
396{
397	ntx = clamp(ntx, 0, xspi->tx_bytes);
398	nrx = clamp(nrx, 0, xspi->rx_bytes);
399
400	xspi->tx_bytes -= ntx;
401	xspi->rx_bytes -= nrx;
402
403	while (ntx || nrx) {
404		if (nrx) {
405			cdns_spi_reader(xspi);
406			nrx--;
407		}
408
409		if (ntx) {
410			cdns_spi_writer(xspi);
411			ntx--;
412		}
413	}
414}
415
416/**
417 * cdns_spi_irq - Interrupt service routine of the SPI controller
418 * @irq:	IRQ number
419 * @dev_id:	Pointer to the xspi structure
420 *
421 * This function handles TX empty and Mode Fault interrupts only.
422 * On TX empty interrupt this function reads the received data from RX FIFO and
423 * fills the TX FIFO if there is any data remaining to be transferred.
424 * On Mode Fault interrupt this function indicates that transfer is completed,
425 * the SPI subsystem will identify the error as the remaining bytes to be
426 * transferred is non-zero.
427 *
428 * Return:	IRQ_HANDLED when handled; IRQ_NONE otherwise.
429 */
430static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
431{
432	struct spi_controller *ctlr = dev_id;
433	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
434	irqreturn_t status;
435	u32 intr_status;
436
437	status = IRQ_NONE;
438	intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
439	cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
440
441	if (intr_status & CDNS_SPI_IXR_MODF) {
442		/* Indicate that transfer is completed, the SPI subsystem will
443		 * identify the error as the remaining bytes to be
444		 * transferred is non-zero
445		 */
446		cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
447		spi_finalize_current_transfer(ctlr);
448		status = IRQ_HANDLED;
449	} else if (intr_status & CDNS_SPI_IXR_TXOW) {
450		int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
451		int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
452
453		if (threshold > 1)
454			trans_cnt -= threshold;
455
456		/* Set threshold to one if number of pending are
457		 * less than half fifo
458		 */
459		if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
460			cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
461
462		if (xspi->tx_bytes) {
463			cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
464		} else {
465			/* Fixed delay due to controller limitation with
466			 * RX_NEMPTY incorrect status
467			 * Xilinx AR:65885 contains more details
468			 */
469			udelay(10);
470			cdns_spi_process_fifo(xspi, 0, trans_cnt);
471			cdns_spi_write(xspi, CDNS_SPI_IDR,
472				       CDNS_SPI_IXR_DEFAULT);
473			spi_finalize_current_transfer(ctlr);
474		}
475		status = IRQ_HANDLED;
476	}
477
478	return status;
479}
480
481static int cdns_prepare_message(struct spi_controller *ctlr,
482				struct spi_message *msg)
483{
484	if (!spi_controller_is_target(ctlr))
485		cdns_spi_config_clock_mode(msg->spi);
486	return 0;
487}
488
489/**
490 * cdns_transfer_one - Initiates the SPI transfer
491 * @ctlr:	Pointer to spi_controller structure
492 * @spi:	Pointer to the spi_device structure
493 * @transfer:	Pointer to the spi_transfer structure which provides
494 *		information about next transfer parameters
495 *
496 * This function in host mode fills the TX FIFO, starts the SPI transfer and
497 * returns a positive transfer count so that core will wait for completion.
498 * This function in target mode fills the TX FIFO and wait for transfer trigger.
499 *
500 * Return:	Number of bytes transferred in the last transfer
501 */
502static int cdns_transfer_one(struct spi_controller *ctlr,
503			     struct spi_device *spi,
504			     struct spi_transfer *transfer)
505{
506	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
507
508	xspi->txbuf = transfer->tx_buf;
509	xspi->rxbuf = transfer->rx_buf;
510	xspi->tx_bytes = transfer->len;
511	xspi->rx_bytes = transfer->len;
512
513	if (!spi_controller_is_target(ctlr)) {
514		cdns_spi_setup_transfer(spi, transfer);
515	} else {
516		/* Set TX empty threshold to half of FIFO depth
517		 * only if TX bytes are more than FIFO depth.
518		 */
519		if (xspi->tx_bytes > xspi->tx_fifo_depth)
520			cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
521	}
522
523	/* When xspi in busy condition, bytes may send failed,
524	 * then spi control didn't work thoroughly, add one byte delay
525	 */
526	if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
527		udelay(10);
528
529	xspi->n_bytes = cdns_spi_n_bytes(transfer);
530	xspi->tx_bytes = DIV_ROUND_UP(xspi->tx_bytes, xspi->n_bytes);
531	xspi->rx_bytes = DIV_ROUND_UP(xspi->rx_bytes, xspi->n_bytes);
532
533	cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
534
535	cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
536	return transfer->len;
537}
538
539/**
540 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
541 * @ctlr:	Pointer to the spi_controller structure which provides
542 *		information about the controller.
543 *
544 * This function enables SPI host controller.
545 *
546 * Return:	0 always
547 */
548static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
549{
550	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
551
552	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
553
554	return 0;
555}
556
557/**
558 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
559 * @ctlr:	Pointer to the spi_controller structure which provides
560 *		information about the controller.
561 *
562 * This function disables the SPI host controller when no target selected.
563 * This function flush out if any pending data in FIFO.
564 *
565 * Return:	0 always
566 */
567static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
568{
569	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
570	u32 ctrl_reg;
571	unsigned int cnt = xspi->tx_fifo_depth;
572
573	if (spi_controller_is_target(ctlr)) {
574		while (cnt--)
575			cdns_spi_read(xspi, CDNS_SPI_RXD);
576	}
577
578	/* Disable the SPI if target is deselected */
579	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
580	ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >>  CDNS_SPI_SS_SHIFT;
581	if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
582		cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
583
584	/* Reset to default */
585	cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
586	return 0;
587}
588
589/**
590 * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
591 * @xspi:	Pointer to the cdns_spi structure
592 *
593 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
594 * IP. The FIFO threshold register is sized so that its maximum value can be the
595 * FIFO size - 1. This is used to detect the size of the FIFO.
596 */
597static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
598{
599	/* The MSBs will get truncated giving us the size of the FIFO */
600	cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
601	xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
602
603	/* Reset to default */
604	cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
605}
606
607/**
608 * cdns_target_abort - Abort target transfer
609 * @ctlr:	Pointer to the spi_controller structure
610 *
611 * This function abort target transfer if there any transfer timeout.
612 *
613 * Return:      0 always
614 */
615static int cdns_target_abort(struct spi_controller *ctlr)
616{
617	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
618	u32 intr_status;
619
620	intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
621	cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
622	cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
623	spi_finalize_current_transfer(ctlr);
624
625	return 0;
626}
627
628/**
629 * cdns_spi_probe - Probe method for the SPI driver
630 * @pdev:	Pointer to the platform_device structure
631 *
632 * This function initializes the driver data structures and the hardware.
633 *
634 * Return:	0 on success and error value on error
635 */
636static int cdns_spi_probe(struct platform_device *pdev)
637{
638	int ret = 0, irq;
639	struct spi_controller *ctlr;
640	struct cdns_spi *xspi;
641	u32 num_cs;
642	bool target;
643
644	target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
645	if (target)
646		ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
647	else
648		ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
649
650	if (!ctlr)
651		return -ENOMEM;
652
653	xspi = spi_controller_get_devdata(ctlr);
654	ctlr->dev.of_node = pdev->dev.of_node;
655	platform_set_drvdata(pdev, ctlr);
656
657	xspi->regs = devm_platform_ioremap_resource(pdev, 0);
658	if (IS_ERR(xspi->regs)) {
659		ret = PTR_ERR(xspi->regs);
660		goto remove_ctlr;
661	}
662
663	xspi->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
664	if (IS_ERR(xspi->pclk)) {
665		dev_err(&pdev->dev, "pclk clock not found.\n");
666		ret = PTR_ERR(xspi->pclk);
667		goto remove_ctlr;
668	}
669
670	xspi->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
671	if (IS_ERR(xspi->rstc)) {
672		ret = dev_err_probe(&pdev->dev, PTR_ERR(xspi->rstc),
673				    "Cannot get SPI reset.\n");
674		goto remove_ctlr;
675	}
676
677	reset_control_assert(xspi->rstc);
678	reset_control_deassert(xspi->rstc);
679
680	xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk");
681	if (IS_ERR(xspi->ref_clk)) {
682		dev_err(&pdev->dev, "ref_clk clock not found.\n");
683		ret = PTR_ERR(xspi->ref_clk);
684		goto remove_ctlr;
685	}
686
687	if (!spi_controller_is_target(ctlr)) {
688		pm_runtime_use_autosuspend(&pdev->dev);
689		pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
690		pm_runtime_get_noresume(&pdev->dev);
691		pm_runtime_set_active(&pdev->dev);
692		pm_runtime_enable(&pdev->dev);
693
694		ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
695		if (ret < 0)
696			ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
697		else
698			ctlr->num_chipselect = num_cs;
699
700		ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
701					   &xspi->is_decoded_cs);
702		if (ret < 0)
703			xspi->is_decoded_cs = 0;
704	}
705
706	cdns_spi_detect_fifo_depth(xspi);
707
708	/* SPI controller initializations */
709	cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
710
711	irq = platform_get_irq(pdev, 0);
712	if (irq < 0) {
713		ret = irq;
714		goto clk_dis_all;
715	}
716
717	ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
718			       0, pdev->name, ctlr);
719	if (ret != 0) {
720		ret = -ENXIO;
721		dev_err(&pdev->dev, "request_irq failed\n");
722		goto clk_dis_all;
723	}
724
725	ctlr->use_gpio_descriptors = true;
726	ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
727	ctlr->prepare_message = cdns_prepare_message;
728	ctlr->transfer_one = cdns_transfer_one;
729	ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
730	ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
731	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
732	ctlr->flags = SPI_CONTROLLER_MUST_TX;
733
734	if (of_device_is_compatible(pdev->dev.of_node, "cix,sky1-spi-r1p6"))
735		ctlr->bits_per_word_mask |= SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
736
737	if (!spi_controller_is_target(ctlr)) {
738		ctlr->mode_bits |=  SPI_CS_HIGH;
739		ctlr->set_cs = cdns_spi_chipselect;
740		ctlr->auto_runtime_pm = true;
741		xspi->clk_rate = clk_get_rate(xspi->ref_clk);
742		/* Set to default valid value */
743		ctlr->max_speed_hz = xspi->clk_rate / 4;
744		xspi->speed_hz = ctlr->max_speed_hz;
745		pm_runtime_put_autosuspend(&pdev->dev);
746	} else {
747		ctlr->mode_bits |= SPI_NO_CS;
748		ctlr->target_abort = cdns_target_abort;
749	}
750	ret = spi_register_controller(ctlr);
751	if (ret) {
752		dev_err(&pdev->dev, "spi_register_controller failed\n");
753		goto clk_dis_all;
754	}
755
756	return ret;
757
758clk_dis_all:
759	if (!spi_controller_is_target(ctlr)) {
760		pm_runtime_disable(&pdev->dev);
761		pm_runtime_set_suspended(&pdev->dev);
762	}
763remove_ctlr:
764	spi_controller_put(ctlr);
765	return ret;
766}
767
768/**
769 * cdns_spi_remove - Remove method for the SPI driver
770 * @pdev:	Pointer to the platform_device structure
771 *
772 * This function is called if a device is physically removed from the system or
773 * if the driver module is being unloaded. It frees all resources allocated to
774 * the device.
775 */
776static void cdns_spi_remove(struct platform_device *pdev)
777{
778	struct spi_controller *ctlr = platform_get_drvdata(pdev);
779	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
780
781	cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
782
783	if (!spi_controller_is_target(ctlr)) {
784		pm_runtime_disable(&pdev->dev);
785		pm_runtime_set_suspended(&pdev->dev);
786	}
787
788	spi_unregister_controller(ctlr);
789}
790
791/**
792 * cdns_spi_suspend - Suspend method for the SPI driver
793 * @dev:	Address of the platform_device structure
794 *
795 * This function disables the SPI controller and
796 * changes the driver state to "suspend"
797 *
798 * Return:	0 on success and error value on error
799 */
800static int __maybe_unused cdns_spi_suspend(struct device *dev)
801{
802	struct spi_controller *ctlr = dev_get_drvdata(dev);
803
804	return spi_controller_suspend(ctlr);
805}
806
807/**
808 * cdns_spi_resume - Resume method for the SPI driver
809 * @dev:	Address of the platform_device structure
810 *
811 * This function changes the driver state to "ready"
812 *
813 * Return:	0 on success and error value on error
814 */
815static int __maybe_unused cdns_spi_resume(struct device *dev)
816{
817	struct spi_controller *ctlr = dev_get_drvdata(dev);
818	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
819
820	cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
821	return spi_controller_resume(ctlr);
822}
823
824/**
825 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
826 * @dev:	Address of the platform_device structure
827 *
828 * This function enables the clocks
829 *
830 * Return:	0 on success and error value on error
831 */
832static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
833{
834	struct spi_controller *ctlr = dev_get_drvdata(dev);
835	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
836	int ret;
837
838	ret = clk_prepare_enable(xspi->pclk);
839	if (ret) {
840		dev_err(dev, "Cannot enable APB clock.\n");
841		return ret;
842	}
843
844	ret = clk_prepare_enable(xspi->ref_clk);
845	if (ret) {
846		dev_err(dev, "Cannot enable device clock.\n");
847		clk_disable_unprepare(xspi->pclk);
848		return ret;
849	}
850	return 0;
851}
852
853/**
854 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
855 * @dev:	Address of the platform_device structure
856 *
857 * This function disables the clocks
858 *
859 * Return:	Always 0
860 */
861static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
862{
863	struct spi_controller *ctlr = dev_get_drvdata(dev);
864	struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
865
866	clk_disable_unprepare(xspi->ref_clk);
867	clk_disable_unprepare(xspi->pclk);
868
869	return 0;
870}
871
872static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
873	SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
874			   cdns_spi_runtime_resume, NULL)
875	SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
876};
877
878static const struct of_device_id cdns_spi_of_match[] = {
879	{ .compatible = "xlnx,zynq-spi-r1p6" },
880	{ .compatible = "cix,sky1-spi-r1p6" },
881	{ .compatible = "cdns,spi-r1p6" },
882	{ /* end of table */ }
883};
884MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
885
886/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
887static struct platform_driver cdns_spi_driver = {
888	.probe	= cdns_spi_probe,
889	.remove = cdns_spi_remove,
890	.driver = {
891		.name = CDNS_SPI_NAME,
892		.of_match_table = cdns_spi_of_match,
893		.pm = &cdns_spi_dev_pm_ops,
894	},
895};
896
897module_platform_driver(cdns_spi_driver);
898
899MODULE_AUTHOR("Xilinx, Inc.");
900MODULE_DESCRIPTION("Cadence SPI driver");
901MODULE_LICENSE("GPL");