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spi-aspeed-smc.c
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linux-6.19.14/drivers/spi/spi-aspeed-smc.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * ASPEED FMC/SPI Memory Controller Driver 4 * 5 * Copyright (c) 2015-2022, IBM Corporation. 6 * Copyright (c) 2020, ASPEED Corporation. 7 */ 8 9#include <linux/clk.h> 10#include <linux/io.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/of_platform.h> 14#include <linux/platform_device.h> 15#include <linux/spi/spi.h> 16#include <linux/spi/spi-mem.h> 17 18#define DEVICE_NAME "spi-aspeed-smc" 19 20/* Type setting Register */ 21#define CONFIG_REG 0x0 22#define CONFIG_TYPE_SPI 0x2 23 24/* CE Control Register */ 25#define CE_CTRL_REG 0x4 26 27/* CEx Control Register */ 28#define CE0_CTRL_REG 0x10 29#define CTRL_IO_MODE_MASK GENMASK(30, 28) 30#define CTRL_IO_SINGLE_DATA 0x0 31#define CTRL_IO_DUAL_DATA BIT(29) 32#define CTRL_IO_QUAD_DATA BIT(30) 33#define CTRL_COMMAND_SHIFT 16 34#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */ 35#define CTRL_IO_DUMMY_SET(dummy) \ 36 (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6)) 37#define CTRL_FREQ_SEL_SHIFT 8 38#define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT) 39#define CTRL_CE_STOP_ACTIVE BIT(2) 40#define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0) 41#define CTRL_IO_MODE_NORMAL 0x0 42#define CTRL_IO_MODE_READ 0x1 43#define CTRL_IO_MODE_WRITE 0x2 44#define CTRL_IO_MODE_USER 0x3 45 46#define CTRL_IO_CMD_MASK 0xf0ff40c3 47 48/* CEx Address Decoding Range Register */ 49#define CE0_SEGMENT_ADDR_REG 0x30 50 51/* CEx Read timing compensation register */ 52#define CE0_TIMING_COMPENSATION_REG 0x94 53 54enum aspeed_spi_ctl_reg_value { 55 ASPEED_SPI_BASE, 56 ASPEED_SPI_READ, 57 ASPEED_SPI_WRITE, 58 ASPEED_SPI_MAX, 59}; 60 61struct aspeed_spi; 62 63struct aspeed_spi_chip { 64 struct aspeed_spi *aspi; 65 u32 cs; 66 void __iomem *ctl; 67 void __iomem *ahb_base; 68 u32 ahb_window_size; 69 u32 ctl_val[ASPEED_SPI_MAX]; 70 u32 clk_freq; 71 bool force_user_mode; 72}; 73 74struct aspeed_spi_data { 75 u32 ctl0; 76 u32 max_cs; 77 bool hastype; 78 u32 mode_bits; 79 u32 we0; 80 u32 timing; 81 u32 hclk_mask; 82 u32 hdiv_max; 83 u32 min_window_size; 84 85 phys_addr_t (*segment_start)(struct aspeed_spi *aspi, u32 reg); 86 phys_addr_t (*segment_end)(struct aspeed_spi *aspi, u32 reg); 87 u32 (*segment_reg)(struct aspeed_spi *aspi, phys_addr_t start, 88 phys_addr_t end); 89 int (*adjust_window)(struct aspeed_spi *aspi); 90 u32 (*get_clk_div)(struct aspeed_spi_chip *chip, u32 hz); 91 int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv, 92 const u8 *golden_buf, u8 *test_buf); 93}; 94 95#define ASPEED_SPI_MAX_NUM_CS 5 96 97struct aspeed_spi { 98 const struct aspeed_spi_data *data; 99 100 void __iomem *regs; 101 phys_addr_t ahb_base_phy; 102 u32 ahb_window_size; 103 u32 num_cs; 104 struct device *dev; 105 106 struct clk *clk; 107 u32 clk_freq; 108 109 struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS]; 110}; 111 112static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op) 113{ 114 switch (op->data.buswidth) { 115 case 1: 116 return CTRL_IO_SINGLE_DATA; 117 case 2: 118 return CTRL_IO_DUAL_DATA; 119 case 4: 120 return CTRL_IO_QUAD_DATA; 121 default: 122 return CTRL_IO_SINGLE_DATA; 123 } 124} 125 126static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode) 127{ 128 u32 ctl; 129 130 if (io_mode > 0) { 131 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK; 132 ctl |= io_mode; 133 writel(ctl, chip->ctl); 134 } 135} 136 137static void aspeed_spi_start_user(struct aspeed_spi_chip *chip) 138{ 139 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE]; 140 141 ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE; 142 writel(ctl, chip->ctl); 143 144 ctl &= ~CTRL_CE_STOP_ACTIVE; 145 writel(ctl, chip->ctl); 146} 147 148static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip) 149{ 150 u32 ctl = chip->ctl_val[ASPEED_SPI_READ] | 151 CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE; 152 153 writel(ctl, chip->ctl); 154 155 /* Restore defaults */ 156 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 157} 158 159static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len) 160{ 161 size_t offset = 0; 162 163 if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) && 164 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 165 ioread32_rep(src, buf, len >> 2); 166 offset = len & ~0x3; 167 len -= offset; 168 } 169 ioread8_rep(src, (u8 *)buf + offset, len); 170 return 0; 171} 172 173static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len) 174{ 175 size_t offset = 0; 176 177 if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) && 178 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { 179 iowrite32_rep(dst, buf, len >> 2); 180 offset = len & ~0x3; 181 len -= offset; 182 } 183 iowrite8_rep(dst, (const u8 *)buf + offset, len); 184 return 0; 185} 186 187static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes, 188 u64 offset, u32 opcode) 189{ 190 __be32 temp; 191 u32 cmdaddr; 192 193 switch (addr_nbytes) { 194 case 3: 195 cmdaddr = offset & 0xFFFFFF; 196 cmdaddr |= opcode << 24; 197 198 temp = cpu_to_be32(cmdaddr); 199 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4); 200 break; 201 case 4: 202 temp = cpu_to_be32(offset); 203 aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1); 204 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4); 205 break; 206 default: 207 WARN_ONCE(1, "Unexpected address width %u", addr_nbytes); 208 return -EOPNOTSUPP; 209 } 210 return 0; 211} 212 213static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip, 214 const struct spi_mem_op *op) 215{ 216 aspeed_spi_start_user(chip); 217 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1); 218 aspeed_spi_read_from_ahb(op->data.buf.in, 219 chip->ahb_base, op->data.nbytes); 220 aspeed_spi_stop_user(chip); 221 return 0; 222} 223 224static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip, 225 const struct spi_mem_op *op) 226{ 227 aspeed_spi_start_user(chip); 228 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1); 229 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, 230 op->data.nbytes); 231 aspeed_spi_stop_user(chip); 232 return 0; 233} 234 235static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip, 236 const struct spi_mem_op *op, 237 u64 offset, size_t len, void *buf) 238{ 239 int io_mode = aspeed_spi_get_io_mode(op); 240 u8 dummy = 0xFF; 241 int i; 242 int ret; 243 244 aspeed_spi_start_user(chip); 245 246 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode); 247 if (ret < 0) 248 goto stop_user; 249 250 if (op->dummy.buswidth && op->dummy.nbytes) { 251 for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++) 252 aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy)); 253 } 254 255 aspeed_spi_set_io_mode(chip, io_mode); 256 257 aspeed_spi_read_from_ahb(buf, chip->ahb_base, len); 258stop_user: 259 aspeed_spi_stop_user(chip); 260 return ret; 261} 262 263static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip, 264 const struct spi_mem_op *op) 265{ 266 int ret; 267 int io_mode = aspeed_spi_get_io_mode(op); 268 269 aspeed_spi_start_user(chip); 270 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode); 271 if (ret < 0) 272 goto stop_user; 273 274 aspeed_spi_set_io_mode(chip, io_mode); 275 276 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes); 277stop_user: 278 aspeed_spi_stop_user(chip); 279 return ret; 280} 281 282/* support for 1-1-1, 1-1-2 or 1-1-4 */ 283static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) 284{ 285 if (op->cmd.buswidth > 1) 286 return false; 287 288 if (op->addr.nbytes != 0) { 289 if (op->addr.buswidth > 1) 290 return false; 291 if (op->addr.nbytes < 3 || op->addr.nbytes > 4) 292 return false; 293 } 294 295 if (op->dummy.nbytes != 0) { 296 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7) 297 return false; 298 } 299 300 if (op->data.nbytes != 0 && op->data.buswidth > 4) 301 return false; 302 303 return spi_mem_default_supports_op(mem, op); 304} 305 306static const struct aspeed_spi_data ast2400_spi_data; 307 308static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 309{ 310 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller); 311 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)]; 312 u32 addr_mode, addr_mode_backup; 313 u32 ctl_val; 314 int ret = 0; 315 316 addr_mode = readl(aspi->regs + CE_CTRL_REG); 317 addr_mode_backup = addr_mode; 318 319 ctl_val = chip->ctl_val[ASPEED_SPI_BASE]; 320 ctl_val &= ~CTRL_IO_CMD_MASK; 321 322 ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT; 323 324 /* 4BYTE address mode */ 325 if (op->addr.nbytes) { 326 if (op->addr.nbytes == 4) 327 addr_mode |= (0x11 << chip->cs); 328 else 329 addr_mode &= ~(0x11 << chip->cs); 330 331 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data) 332 ctl_val |= CTRL_IO_ADDRESS_4B; 333 } 334 335 if (op->dummy.nbytes) 336 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth); 337 338 if (op->data.nbytes) 339 ctl_val |= aspeed_spi_get_io_mode(op); 340 341 if (op->data.dir == SPI_MEM_DATA_OUT) 342 ctl_val |= CTRL_IO_MODE_WRITE; 343 else 344 ctl_val |= CTRL_IO_MODE_READ; 345 346 if (addr_mode != addr_mode_backup) 347 writel(addr_mode, aspi->regs + CE_CTRL_REG); 348 writel(ctl_val, chip->ctl); 349 350 if (op->data.dir == SPI_MEM_DATA_IN) { 351 if (!op->addr.nbytes) 352 ret = aspeed_spi_read_reg(chip, op); 353 else 354 ret = aspeed_spi_read_user(chip, op, op->addr.val, 355 op->data.nbytes, op->data.buf.in); 356 } else { 357 if (!op->addr.nbytes) 358 ret = aspeed_spi_write_reg(chip, op); 359 else 360 ret = aspeed_spi_write_user(chip, op); 361 } 362 363 /* Restore defaults */ 364 if (addr_mode != addr_mode_backup) 365 writel(addr_mode_backup, aspi->regs + CE_CTRL_REG); 366 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 367 return ret; 368} 369 370static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 371{ 372 int ret; 373 374 ret = do_aspeed_spi_exec_op(mem, op); 375 if (ret) 376 dev_err(&mem->spi->dev, "operation failed: %d\n", ret); 377 return ret; 378} 379 380static const char *aspeed_spi_get_name(struct spi_mem *mem) 381{ 382 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller); 383 struct device *dev = aspi->dev; 384 385 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), 386 spi_get_chipselect(mem->spi, 0)); 387} 388 389static int aspeed_spi_set_window(struct aspeed_spi *aspi) 390{ 391 struct device *dev = aspi->dev; 392 off_t offset = 0; 393 phys_addr_t start; 394 phys_addr_t end; 395 void __iomem *seg_reg_base = aspi->regs + CE0_SEGMENT_ADDR_REG; 396 void __iomem *seg_reg; 397 u32 seg_val_backup; 398 u32 seg_val; 399 u32 cs; 400 size_t window_size; 401 402 for (cs = 0; cs < aspi->data->max_cs; cs++) { 403 if (aspi->chips[cs].ahb_base) { 404 devm_iounmap(dev, aspi->chips[cs].ahb_base); 405 aspi->chips[cs].ahb_base = NULL; 406 } 407 } 408 409 for (cs = 0; cs < aspi->data->max_cs; cs++) { 410 seg_reg = seg_reg_base + cs * 4; 411 seg_val_backup = readl(seg_reg); 412 413 start = aspi->ahb_base_phy + offset; 414 window_size = aspi->chips[cs].ahb_window_size; 415 end = start + window_size; 416 417 seg_val = aspi->data->segment_reg(aspi, start, end); 418 writel(seg_val, seg_reg); 419 420 /* 421 * Restore initial value if something goes wrong or the segment 422 * register is written protected. 423 */ 424 if (seg_val != readl(seg_reg)) { 425 dev_warn(dev, "CE%d expected window [ 0x%.9llx - 0x%.9llx ] %zdMB\n", 426 cs, (u64)start, (u64)end - 1, window_size >> 20); 427 writel(seg_val_backup, seg_reg); 428 window_size = aspi->data->segment_end(aspi, seg_val_backup) - 429 aspi->data->segment_start(aspi, seg_val_backup); 430 aspi->chips[cs].ahb_window_size = window_size; 431 end = start + window_size; 432 } 433 434 if (window_size != 0) 435 dev_dbg(dev, "CE%d window [ 0x%.9llx - 0x%.9llx ] %zdMB\n", 436 cs, (u64)start, (u64)end - 1, window_size >> 20); 437 else 438 dev_dbg(dev, "CE%d window closed\n", cs); 439 440 offset += window_size; 441 if (offset > aspi->ahb_window_size) { 442 dev_err(dev, "CE%d offset value 0x%llx is too large.\n", 443 cs, (u64)offset); 444 return -ENOSPC; 445 } 446 447 /* 448 * No need to map the address deocding range when 449 * - window size is 0. 450 * - the CS is unused. 451 */ 452 if (window_size == 0 || cs >= aspi->num_cs) 453 continue; 454 455 aspi->chips[cs].ahb_base = 456 devm_ioremap(aspi->dev, start, window_size); 457 if (!aspi->chips[cs].ahb_base) { 458 dev_err(aspi->dev, 459 "Fail to remap window [0x%.9llx - 0x%.9llx]\n", 460 (u64)start, (u64)end - 1); 461 return -ENOMEM; 462 } 463 } 464 465 return 0; 466} 467 468static const struct aspeed_spi_data ast2500_spi_data; 469static const struct aspeed_spi_data ast2600_spi_data; 470static const struct aspeed_spi_data ast2600_fmc_data; 471 472static int aspeed_spi_chip_set_default_window(struct aspeed_spi *aspi) 473{ 474 u32 cs; 475 476 /* No segment registers for the AST2400 SPI controller */ 477 if (aspi->data == &ast2400_spi_data) { 478 aspi->chips[0].ahb_base = devm_ioremap(aspi->dev, 479 aspi->ahb_base_phy, 480 aspi->ahb_window_size); 481 aspi->chips[0].ahb_window_size = aspi->ahb_window_size; 482 return 0; 483 } 484 485 /* Assign the minimum window size to each CS */ 486 for (cs = 0; cs < aspi->num_cs; cs++) { 487 aspi->chips[cs].ahb_window_size = aspi->data->min_window_size; 488 dev_dbg(aspi->dev, "CE%d default window [ 0x%.9llx - 0x%.9llx ]", 489 cs, (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs), 490 (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1)); 491 } 492 493 /* Close unused CS */ 494 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) 495 aspi->chips[cs].ahb_window_size = 0; 496 497 if (aspi->data->adjust_window) 498 aspi->data->adjust_window(aspi); 499 500 return aspeed_spi_set_window(aspi); 501} 502 503/* 504 * As the flash size grows up, we need to trim some decoding 505 * size if needed for the sake of conforming the maximum 506 * decoding size. We trim the decoding size from the rear CS 507 * to avoid affecting the default boot up sequence, usually, 508 * from CS0. Notice, if a CS decoding size is trimmed, 509 * command mode may not work perfectly on that CS, but it only 510 * affect performance and the debug function. 511 */ 512static int aspeed_spi_trim_window_size(struct aspeed_spi *aspi) 513{ 514 struct aspeed_spi_chip *chips = aspi->chips; 515 size_t total_sz; 516 int cs = aspi->data->max_cs - 1; 517 u32 i; 518 bool trimmed = false; 519 520 do { 521 total_sz = 0; 522 for (i = 0; i < aspi->data->max_cs; i++) 523 total_sz += chips[i].ahb_window_size; 524 525 if (cs < 0) 526 return -ENOMEM; 527 528 if (chips[cs].ahb_window_size <= aspi->data->min_window_size) { 529 cs--; 530 continue; 531 } 532 533 if (total_sz > aspi->ahb_window_size) { 534 chips[cs].ahb_window_size -= 535 aspi->data->min_window_size; 536 total_sz -= aspi->data->min_window_size; 537 /* 538 * If the ahb window size is ever trimmed, only user 539 * mode can be adopted to access the whole flash. 540 */ 541 chips[cs].force_user_mode = true; 542 trimmed = true; 543 } 544 } while (total_sz > aspi->ahb_window_size); 545 546 if (trimmed) { 547 dev_warn(aspi->dev, "Window size after trimming:\n"); 548 for (cs = 0; cs < aspi->data->max_cs; cs++) { 549 dev_warn(aspi->dev, "CE%d: 0x%08x\n", 550 cs, chips[cs].ahb_window_size); 551 } 552 } 553 554 return 0; 555} 556 557static int aspeed_adjust_window_ast2400(struct aspeed_spi *aspi) 558{ 559 int ret; 560 int cs; 561 struct aspeed_spi_chip *chips = aspi->chips; 562 563 /* Close unused CS. */ 564 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) 565 chips[cs].ahb_window_size = 0; 566 567 ret = aspeed_spi_trim_window_size(aspi); 568 if (ret != 0) 569 return ret; 570 571 return 0; 572} 573 574/* 575 * For AST2500, the minimum address decoding size for each CS 576 * is 8MB. This address decoding size is mandatory for each 577 * CS no matter whether it will be used. This is a HW limitation. 578 */ 579static int aspeed_adjust_window_ast2500(struct aspeed_spi *aspi) 580{ 581 int ret; 582 int cs, i; 583 u32 cum_size, rem_size; 584 struct aspeed_spi_chip *chips = aspi->chips; 585 586 /* Assign min_window_sz to unused CS. */ 587 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) { 588 if (chips[cs].ahb_window_size < aspi->data->min_window_size) 589 chips[cs].ahb_window_size = 590 aspi->data->min_window_size; 591 } 592 593 /* 594 * If command mode or normal mode is used by dirmap read, the start 595 * address of a window should be multiple of its related flash size. 596 * Namely, the total windows size from flash 0 to flash N should 597 * be multiple of the size of flash (N + 1). 598 */ 599 for (cs = aspi->num_cs - 1; cs >= 0; cs--) { 600 cum_size = 0; 601 for (i = 0; i < cs; i++) 602 cum_size += chips[i].ahb_window_size; 603 604 rem_size = cum_size % chips[cs].ahb_window_size; 605 if (chips[cs].ahb_window_size != 0 && rem_size != 0) 606 chips[0].ahb_window_size += 607 chips[cs].ahb_window_size - rem_size; 608 } 609 610 ret = aspeed_spi_trim_window_size(aspi); 611 if (ret != 0) 612 return ret; 613 614 /* The total window size of AST2500 SPI1 CS0 and CS1 must be 128MB */ 615 if (aspi->data == &ast2500_spi_data) 616 chips[1].ahb_window_size = 617 0x08000000 - chips[0].ahb_window_size; 618 619 return 0; 620} 621 622static int aspeed_adjust_window_ast2600(struct aspeed_spi *aspi) 623{ 624 int ret; 625 int cs, i; 626 u32 cum_size, rem_size; 627 struct aspeed_spi_chip *chips = aspi->chips; 628 629 /* Close unused CS. */ 630 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) 631 chips[cs].ahb_window_size = 0; 632 633 /* 634 * If command mode or normal mode is used by dirmap read, the start 635 * address of a window should be multiple of its related flash size. 636 * Namely, the total windows size from flash 0 to flash N should 637 * be multiple of the size of flash (N + 1). 638 */ 639 for (cs = aspi->num_cs - 1; cs >= 0; cs--) { 640 cum_size = 0; 641 for (i = 0; i < cs; i++) 642 cum_size += chips[i].ahb_window_size; 643 644 rem_size = cum_size % chips[cs].ahb_window_size; 645 if (chips[cs].ahb_window_size != 0 && rem_size != 0) 646 chips[0].ahb_window_size += 647 chips[cs].ahb_window_size - rem_size; 648 } 649 650 ret = aspeed_spi_trim_window_size(aspi); 651 if (ret != 0) 652 return ret; 653 654 return 0; 655} 656 657/* 658 * Yet to be done when possible : 659 * - Align mappings on flash size (we don't have the info) 660 * - ioremap each window, not strictly necessary since the overall window 661 * is correct. 662 */ 663static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip, 664 u32 local_offset, u32 size) 665{ 666 struct aspeed_spi *aspi = chip->aspi; 667 int ret; 668 669 /* No segment registers for the AST2400 SPI controller */ 670 if (aspi->data == &ast2400_spi_data) 671 return 0; 672 673 /* Adjust this chip window */ 674 aspi->chips[chip->cs].ahb_window_size = size; 675 676 /* Adjust the overall windows size regarding each platform */ 677 if (aspi->data->adjust_window) 678 aspi->data->adjust_window(aspi); 679 680 ret = aspeed_spi_set_window(aspi); 681 if (ret) 682 return ret; 683 684 return 0; 685} 686 687static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip); 688 689static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) 690{ 691 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller); 692 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)]; 693 struct spi_mem_op *op = &desc->info.op_tmpl; 694 u32 ctl_val; 695 int ret = 0; 696 697 dev_dbg(aspi->dev, 698 "CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n", 699 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write", 700 desc->info.offset, desc->info.offset + desc->info.length, 701 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 702 op->dummy.buswidth, op->data.buswidth, 703 op->addr.nbytes, op->dummy.nbytes); 704 705 chip->clk_freq = desc->mem->spi->max_speed_hz; 706 707 /* Only for reads */ 708 if (op->data.dir != SPI_MEM_DATA_IN) 709 return -EOPNOTSUPP; 710 711 aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length); 712 713 if (desc->info.length > chip->ahb_window_size) 714 dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping", 715 chip->cs, chip->ahb_window_size >> 20); 716 717 /* Define the default IO read settings */ 718 ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK; 719 ctl_val |= aspeed_spi_get_io_mode(op) | 720 op->cmd.opcode << CTRL_COMMAND_SHIFT | 721 CTRL_IO_MODE_READ; 722 723 if (op->dummy.nbytes) 724 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth); 725 726 /* Tune 4BYTE address mode */ 727 if (op->addr.nbytes) { 728 u32 addr_mode = readl(aspi->regs + CE_CTRL_REG); 729 730 if (op->addr.nbytes == 4) 731 addr_mode |= (0x11 << chip->cs); 732 else 733 addr_mode &= ~(0x11 << chip->cs); 734 writel(addr_mode, aspi->regs + CE_CTRL_REG); 735 736 /* AST2400 SPI controller sets 4BYTE address mode in 737 * CE0 Control Register 738 */ 739 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data) 740 ctl_val |= CTRL_IO_ADDRESS_4B; 741 } 742 743 /* READ mode is the controller default setting */ 744 chip->ctl_val[ASPEED_SPI_READ] = ctl_val; 745 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 746 747 ret = aspeed_spi_do_calibration(chip); 748 749 dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n", 750 chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]); 751 752 return ret; 753} 754 755static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, 756 u64 offset, size_t len, void *buf) 757{ 758 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller); 759 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)]; 760 761 /* Switch to USER command mode if mapping window is too small */ 762 if (chip->ahb_window_size < offset + len || chip->force_user_mode) { 763 int ret; 764 765 ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf); 766 if (ret < 0) 767 return ret; 768 } else { 769 memcpy_fromio(buf, chip->ahb_base + offset, len); 770 } 771 772 return len; 773} 774 775static const struct spi_controller_mem_ops aspeed_spi_mem_ops = { 776 .supports_op = aspeed_spi_supports_op, 777 .exec_op = aspeed_spi_exec_op, 778 .get_name = aspeed_spi_get_name, 779 .dirmap_create = aspeed_spi_dirmap_create, 780 .dirmap_read = aspeed_spi_dirmap_read, 781}; 782 783static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type) 784{ 785 u32 reg; 786 787 reg = readl(aspi->regs + CONFIG_REG); 788 reg &= ~(0x3 << (cs * 2)); 789 reg |= type << (cs * 2); 790 writel(reg, aspi->regs + CONFIG_REG); 791} 792 793static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable) 794{ 795 u32 we_bit = BIT(aspi->data->we0 + cs); 796 u32 reg = readl(aspi->regs + CONFIG_REG); 797 798 if (enable) 799 reg |= we_bit; 800 else 801 reg &= ~we_bit; 802 writel(reg, aspi->regs + CONFIG_REG); 803} 804 805static int aspeed_spi_setup(struct spi_device *spi) 806{ 807 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller); 808 const struct aspeed_spi_data *data = aspi->data; 809 unsigned int cs = spi_get_chipselect(spi, 0); 810 struct aspeed_spi_chip *chip = &aspi->chips[cs]; 811 812 chip->aspi = aspi; 813 chip->cs = cs; 814 chip->ctl = aspi->regs + data->ctl0 + cs * 4; 815 816 /* The driver only supports SPI type flash */ 817 if (data->hastype) 818 aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI); 819 820 aspeed_spi_chip_enable(aspi, cs, true); 821 822 chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER; 823 824 dev_dbg(aspi->dev, "CE%d setup done\n", cs); 825 return 0; 826} 827 828static void aspeed_spi_cleanup(struct spi_device *spi) 829{ 830 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller); 831 unsigned int cs = spi_get_chipselect(spi, 0); 832 833 aspeed_spi_chip_enable(aspi, cs, false); 834 835 dev_dbg(aspi->dev, "CE%d cleanup done\n", cs); 836} 837 838static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable) 839{ 840 int cs; 841 842 for (cs = 0; cs < aspi->data->max_cs; cs++) 843 aspeed_spi_chip_enable(aspi, cs, enable); 844} 845 846static int aspeed_spi_probe(struct platform_device *pdev) 847{ 848 struct device *dev = &pdev->dev; 849 const struct aspeed_spi_data *data; 850 struct spi_controller *ctlr; 851 struct aspeed_spi *aspi; 852 struct resource *res; 853 int ret; 854 855 data = of_device_get_match_data(&pdev->dev); 856 if (!data) 857 return -ENODEV; 858 859 ctlr = devm_spi_alloc_host(dev, sizeof(*aspi)); 860 if (!ctlr) 861 return -ENOMEM; 862 863 aspi = spi_controller_get_devdata(ctlr); 864 platform_set_drvdata(pdev, aspi); 865 aspi->data = data; 866 aspi->dev = dev; 867 868 aspi->regs = devm_platform_ioremap_resource(pdev, 0); 869 if (IS_ERR(aspi->regs)) 870 return PTR_ERR(aspi->regs); 871 872 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 873 if (!res) { 874 dev_err(dev, "missing AHB memory\n"); 875 return -EINVAL; 876 } 877 878 aspi->ahb_window_size = resource_size(res); 879 aspi->ahb_base_phy = res->start; 880 881 aspi->clk = devm_clk_get_enabled(&pdev->dev, NULL); 882 if (IS_ERR(aspi->clk)) { 883 dev_err(dev, "missing clock\n"); 884 return PTR_ERR(aspi->clk); 885 } 886 887 aspi->clk_freq = clk_get_rate(aspi->clk); 888 if (!aspi->clk_freq) { 889 dev_err(dev, "invalid clock\n"); 890 return -EINVAL; 891 } 892 893 /* IRQ is for DMA, which the driver doesn't support yet */ 894 895 ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits; 896 ctlr->bus_num = pdev->id; 897 ctlr->mem_ops = &aspeed_spi_mem_ops; 898 ctlr->setup = aspeed_spi_setup; 899 ctlr->cleanup = aspeed_spi_cleanup; 900 ctlr->num_chipselect = of_get_available_child_count(dev->of_node); 901 ctlr->dev.of_node = dev->of_node; 902 903 aspi->num_cs = ctlr->num_chipselect; 904 905 ret = aspeed_spi_chip_set_default_window(aspi); 906 if (ret) { 907 dev_err(&pdev->dev, "fail to set default window\n"); 908 return ret; 909 } 910 911 ret = devm_spi_register_controller(dev, ctlr); 912 if (ret) 913 dev_err(&pdev->dev, "spi_register_controller failed\n"); 914 915 return ret; 916} 917 918static void aspeed_spi_remove(struct platform_device *pdev) 919{ 920 struct aspeed_spi *aspi = platform_get_drvdata(pdev); 921 922 aspeed_spi_enable(aspi, false); 923} 924 925/* 926 * AHB mappings 927 */ 928 929/* 930 * The Segment Registers of the AST2400 and AST2500 use a 8MB unit. 931 * The address range is encoded with absolute addresses in the overall 932 * mapping window. 933 */ 934static phys_addr_t aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg) 935{ 936 return ((reg >> 16) & 0xFF) << 23; 937} 938 939static phys_addr_t aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg) 940{ 941 return ((reg >> 24) & 0xFF) << 23; 942} 943 944static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, 945 phys_addr_t start, phys_addr_t end) 946{ 947 return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24); 948} 949 950/* 951 * The Segment Registers of the AST2600 use a 1MB unit. The address 952 * range is encoded with offsets in the overall mapping window. 953 */ 954 955#define AST2600_SEG_ADDR_MASK 0x0ff00000 956 957static phys_addr_t aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi, 958 u32 reg) 959{ 960 u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; 961 962 return aspi->ahb_base_phy + start_offset; 963} 964 965static phys_addr_t aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi, 966 u32 reg) 967{ 968 u32 end_offset = reg & AST2600_SEG_ADDR_MASK; 969 970 /* segment is disabled */ 971 if (!end_offset) 972 return aspi->ahb_base_phy; 973 974 return aspi->ahb_base_phy + end_offset + 0x100000; 975} 976 977static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi, 978 phys_addr_t start, phys_addr_t end) 979{ 980 /* disable zero size segments */ 981 if (start == end) 982 return 0; 983 984 return ((start & AST2600_SEG_ADDR_MASK) >> 16) | 985 ((end - 1) & AST2600_SEG_ADDR_MASK); 986} 987 988/* The Segment Registers of the AST2700 use a 64KB unit. */ 989#define AST2700_SEG_ADDR_MASK 0x7fff0000 990 991static phys_addr_t aspeed_spi_segment_ast2700_start(struct aspeed_spi *aspi, 992 u32 reg) 993{ 994 u64 start_offset = (reg << 16) & AST2700_SEG_ADDR_MASK; 995 996 if (!start_offset) 997 return aspi->ahb_base_phy; 998 999 return aspi->ahb_base_phy + start_offset; 1000} 1001 1002static phys_addr_t aspeed_spi_segment_ast2700_end(struct aspeed_spi *aspi, 1003 u32 reg) 1004{ 1005 u64 end_offset = reg & AST2700_SEG_ADDR_MASK; 1006 1007 if (!end_offset) 1008 return aspi->ahb_base_phy; 1009 1010 return aspi->ahb_base_phy + end_offset; 1011} 1012 1013static u32 aspeed_spi_segment_ast2700_reg(struct aspeed_spi *aspi, 1014 phys_addr_t start, phys_addr_t end) 1015{ 1016 if (start == end) 1017 return 0; 1018 1019 return (u32)(((start & AST2700_SEG_ADDR_MASK) >> 16) | 1020 (end & AST2700_SEG_ADDR_MASK)); 1021} 1022 1023/* 1024 * Read timing compensation sequences 1025 */ 1026 1027#define CALIBRATE_BUF_SIZE SZ_16K 1028 1029static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip, 1030 const u8 *golden_buf, u8 *test_buf) 1031{ 1032 int i; 1033 1034 for (i = 0; i < 10; i++) { 1035 memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); 1036 if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) { 1037#if defined(VERBOSE_DEBUG) 1038 print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE, 1039 test_buf, 0x100); 1040#endif 1041 return false; 1042 } 1043 } 1044 return true; 1045} 1046 1047#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8)) 1048 1049/* 1050 * The timing register is shared by all devices. Only update for CE0. 1051 */ 1052static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv, 1053 const u8 *golden_buf, u8 *test_buf) 1054{ 1055 struct aspeed_spi *aspi = chip->aspi; 1056 const struct aspeed_spi_data *data = aspi->data; 1057 int i; 1058 int good_pass = -1, pass_count = 0; 1059 u32 shift = (hdiv - 1) << 2; 1060 u32 mask = ~(0xfu << shift); 1061 u32 fread_timing_val = 0; 1062 1063 /* Try HCLK delay 0..5, each one with/without delay and look for a 1064 * good pair. 1065 */ 1066 for (i = 0; i < 12; i++) { 1067 bool pass; 1068 1069 if (chip->cs == 0) { 1070 fread_timing_val &= mask; 1071 fread_timing_val |= FREAD_TPASS(i) << shift; 1072 writel(fread_timing_val, aspi->regs + data->timing); 1073 } 1074 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf); 1075 dev_dbg(aspi->dev, 1076 " * [%08x] %d HCLK delay, %dns DI delay : %s", 1077 fread_timing_val, i / 2, (i & 1) ? 0 : 4, 1078 pass ? "PASS" : "FAIL"); 1079 if (pass) { 1080 pass_count++; 1081 if (pass_count == 3) { 1082 good_pass = i - 1; 1083 break; 1084 } 1085 } else { 1086 pass_count = 0; 1087 } 1088 } 1089 1090 /* No good setting for this frequency */ 1091 if (good_pass < 0) 1092 return -1; 1093 1094 /* We have at least one pass of margin, let's use first pass */ 1095 if (chip->cs == 0) { 1096 fread_timing_val &= mask; 1097 fread_timing_val |= FREAD_TPASS(good_pass) << shift; 1098 writel(fread_timing_val, aspi->regs + data->timing); 1099 } 1100 dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]", 1101 good_pass, fread_timing_val); 1102 return 0; 1103} 1104 1105static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size) 1106{ 1107 const u32 *tb32 = (const u32 *)test_buf; 1108 u32 i, cnt = 0; 1109 1110 /* We check if we have enough words that are neither all 0 1111 * nor all 1's so the calibration can be considered valid. 1112 * 1113 * I use an arbitrary threshold for now of 64 1114 */ 1115 size >>= 2; 1116 for (i = 0; i < size; i++) { 1117 if (tb32[i] != 0 && tb32[i] != 0xffffffff) 1118 cnt++; 1119 } 1120 return cnt >= 64; 1121} 1122 1123static const u32 aspeed_spi_hclk_divs[] = { 1124 /* HCLK, HCLK/2, HCLK/3, HCLK/4, HCLK/5, ..., HCLK/16 */ 1125 0xf, 0x7, 0xe, 0x6, 0xd, 1126 0x5, 0xc, 0x4, 0xb, 0x3, 1127 0xa, 0x2, 0x9, 0x1, 0x8, 1128 0x0 1129}; 1130 1131#define ASPEED_SPI_HCLK_DIV(i) \ 1132 (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT) 1133 1134/* Transfer maximum clock frequency to register setting */ 1135static u32 aspeed_get_clk_div_ast2400(struct aspeed_spi_chip *chip, 1136 u32 max_hz) 1137{ 1138 struct device *dev = chip->aspi->dev; 1139 u32 hclk_clk = chip->aspi->clk_freq; 1140 u32 div_ctl = 0; 1141 u32 i; 1142 bool found = false; 1143 1144 /* FMC/SPIR10[11:8] */ 1145 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1146 if (hclk_clk / i <= max_hz) { 1147 found = true; 1148 break; 1149 } 1150 } 1151 1152 if (found) { 1153 div_ctl = ASPEED_SPI_HCLK_DIV(i); 1154 chip->clk_freq = hclk_clk / i; 1155 } 1156 1157 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", 1158 found ? "yes" : "no", hclk_clk, max_hz); 1159 1160 if (found) { 1161 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n", 1162 div_ctl, chip->clk_freq); 1163 } 1164 1165 return div_ctl; 1166} 1167 1168static u32 aspeed_get_clk_div_ast2500(struct aspeed_spi_chip *chip, 1169 u32 max_hz) 1170{ 1171 struct device *dev = chip->aspi->dev; 1172 u32 hclk_clk = chip->aspi->clk_freq; 1173 u32 div_ctl = 0; 1174 u32 i; 1175 bool found = false; 1176 1177 /* FMC/SPIR10[11:8] */ 1178 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1179 if (hclk_clk / i <= max_hz) { 1180 found = true; 1181 chip->clk_freq = hclk_clk / i; 1182 break; 1183 } 1184 } 1185 1186 if (found) { 1187 div_ctl = ASPEED_SPI_HCLK_DIV(i); 1188 goto end; 1189 } 1190 1191 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1192 if (hclk_clk / (i * 4) <= max_hz) { 1193 found = true; 1194 chip->clk_freq = hclk_clk / (i * 4); 1195 break; 1196 } 1197 } 1198 1199 if (found) 1200 div_ctl = BIT(13) | ASPEED_SPI_HCLK_DIV(i); 1201 1202end: 1203 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", 1204 found ? "yes" : "no", hclk_clk, max_hz); 1205 1206 if (found) { 1207 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n", 1208 div_ctl, chip->clk_freq); 1209 } 1210 1211 return div_ctl; 1212} 1213 1214static u32 aspeed_get_clk_div_ast2600(struct aspeed_spi_chip *chip, 1215 u32 max_hz) 1216{ 1217 struct device *dev = chip->aspi->dev; 1218 u32 hclk_clk = chip->aspi->clk_freq; 1219 u32 div_ctl = 0; 1220 u32 i, j; 1221 bool found = false; 1222 1223 /* FMC/SPIR10[27:24] */ 1224 for (j = 0; j < 16; j++) { 1225 /* FMC/SPIR10[11:8] */ 1226 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) { 1227 if (j == 0 && i == 1) 1228 continue; 1229 1230 if (hclk_clk / (j * 16 + i) <= max_hz) { 1231 found = true; 1232 break; 1233 } 1234 } 1235 1236 if (found) { 1237 div_ctl = ((j << 24) | ASPEED_SPI_HCLK_DIV(i)); 1238 chip->clk_freq = hclk_clk / (j * 16 + i); 1239 break; 1240 } 1241 } 1242 1243 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", 1244 found ? "yes" : "no", hclk_clk, max_hz); 1245 1246 if (found) { 1247 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n", 1248 div_ctl, chip->clk_freq); 1249 } 1250 1251 return div_ctl; 1252} 1253 1254static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip) 1255{ 1256 struct aspeed_spi *aspi = chip->aspi; 1257 const struct aspeed_spi_data *data = aspi->data; 1258 u32 ahb_freq = aspi->clk_freq; 1259 u32 max_freq = chip->clk_freq; 1260 bool exec_calib = false; 1261 u32 best_freq = 0; 1262 u32 ctl_val; 1263 u8 *golden_buf = NULL; 1264 u8 *test_buf = NULL; 1265 int i, rc; 1266 u32 div_ctl; 1267 1268 dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz", 1269 ahb_freq / 1000000); 1270 1271 /* 1272 * use the related low frequency to get check calibration data 1273 * and get golden data. 1274 */ 1275 ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask; 1276 writel(ctl_val, chip->ctl); 1277 1278 test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL); 1279 if (!test_buf) 1280 return -ENOMEM; 1281 1282 golden_buf = test_buf + CALIBRATE_BUF_SIZE; 1283 1284 memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); 1285 if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) { 1286 dev_info(aspi->dev, "Calibration area too uniform, using low speed"); 1287 goto end_calib; 1288 } 1289 1290#if defined(VERBOSE_DEBUG) 1291 print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE, 1292 golden_buf, 0x100); 1293#endif 1294 1295 /* Now we iterate the HCLK dividers until we find our breaking point */ 1296 for (i = 5; i > data->hdiv_max - 1; i--) { 1297 u32 tv, freq; 1298 1299 freq = ahb_freq / i; 1300 if (freq > max_freq) 1301 continue; 1302 1303 /* Set the timing */ 1304 tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i); 1305 writel(tv, chip->ctl); 1306 dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv); 1307 rc = data->calibrate(chip, i, golden_buf, test_buf); 1308 if (rc == 0) 1309 best_freq = freq; 1310 1311 exec_calib = true; 1312 } 1313 1314end_calib: 1315 if (!exec_calib) { 1316 /* calibration process is not executed */ 1317 dev_warn(aspi->dev, "Force to dts configuration %dkHz.\n", 1318 max_freq / 1000); 1319 div_ctl = data->get_clk_div(chip, max_freq); 1320 } else if (best_freq == 0) { 1321 /* calibration process is executed, but no good frequency */ 1322 dev_warn(aspi->dev, "No good frequency, using dumb slow\n"); 1323 div_ctl = 0; 1324 } else { 1325 dev_dbg(aspi->dev, "Found good read timings at %dMHz.\n", 1326 best_freq / 1000000); 1327 div_ctl = data->get_clk_div(chip, best_freq); 1328 } 1329 1330 /* Record the freq */ 1331 for (i = 0; i < ASPEED_SPI_MAX; i++) { 1332 chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) | 1333 div_ctl; 1334 } 1335 1336 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl); 1337 kfree(test_buf); 1338 return 0; 1339} 1340 1341#define TIMING_DELAY_DI BIT(3) 1342#define TIMING_DELAY_HCYCLE_MAX 5 1343#define TIMING_DELAY_INPUT_MAX 16 1344#define TIMING_REG_AST2600(chip) \ 1345 ((chip)->aspi->regs + (chip)->aspi->data->timing + \ 1346 (chip)->cs * 4) 1347 1348/* 1349 * This function returns the center point of the longest 1350 * continuous "pass" interval within the buffer. The interval 1351 * must contains the highest number of consecutive "pass" 1352 * results and not span across multiple rows. 1353 */ 1354static u32 aspeed_spi_ast2600_optimized_timing(u32 rows, u32 cols, 1355 u8 buf[rows][cols]) 1356{ 1357 int r = 0, c = 0; 1358 int max = 0; 1359 int i, j; 1360 1361 for (i = 0; i < rows; i++) { 1362 for (j = 0; j < cols;) { 1363 int k = j; 1364 1365 while (k < cols && buf[i][k]) 1366 k++; 1367 1368 if (k - j > max) { 1369 max = k - j; 1370 r = i; 1371 c = j + (k - j) / 2; 1372 } 1373 1374 j = k + 1; 1375 } 1376 } 1377 1378 return max > 4 ? r * cols + c : 0; 1379} 1380 1381static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv, 1382 const u8 *golden_buf, u8 *test_buf) 1383{ 1384 struct aspeed_spi *aspi = chip->aspi; 1385 int hcycle; 1386 int delay_ns; 1387 u32 shift = (hdiv - 2) << 3; 1388 u32 mask = ~(0xffu << shift); 1389 u32 fread_timing_val = 0; 1390 u8 calib_res[6][17] = {0}; 1391 u32 calib_point; 1392 1393 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 1394 bool pass = false; 1395 1396 fread_timing_val &= mask; 1397 fread_timing_val |= hcycle << shift; 1398 1399 /* no DI input delay first */ 1400 writel(fread_timing_val, TIMING_REG_AST2600(chip)); 1401 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf); 1402 dev_dbg(aspi->dev, 1403 " * [%08x] %d HCLK delay, DI delay none : %s", 1404 fread_timing_val, hcycle, pass ? "PASS" : "FAIL"); 1405 if (pass) 1406 calib_res[hcycle][0] = 1; 1407 1408 /* Add DI input delays */ 1409 fread_timing_val &= mask; 1410 fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift; 1411 1412 for (delay_ns = 0; delay_ns < TIMING_DELAY_INPUT_MAX; delay_ns++) { 1413 fread_timing_val &= ~(0xfu << (4 + shift)); 1414 fread_timing_val |= delay_ns << (4 + shift); 1415 1416 writel(fread_timing_val, TIMING_REG_AST2600(chip)); 1417 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf); 1418 dev_dbg(aspi->dev, 1419 " * [%08x] %d HCLK delay, DI delay %d.%dns : %s", 1420 fread_timing_val, hcycle, (delay_ns + 1) / 2, 1421 (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL"); 1422 1423 if (pass) 1424 calib_res[hcycle][delay_ns + 1] = 1; 1425 } 1426 } 1427 1428 calib_point = aspeed_spi_ast2600_optimized_timing(6, 17, calib_res); 1429 /* No good setting for this frequency */ 1430 if (calib_point == 0) 1431 return -1; 1432 1433 hcycle = calib_point / 17; 1434 delay_ns = calib_point % 17; 1435 1436 fread_timing_val = (TIMING_DELAY_DI | hcycle | (delay_ns << 4)) << shift; 1437 1438 dev_dbg(aspi->dev, "timing val: %08x, final hcycle: %d, delay_ns: %d\n", 1439 fread_timing_val, hcycle, delay_ns); 1440 1441 writel(fread_timing_val, TIMING_REG_AST2600(chip)); 1442 1443 return 0; 1444} 1445 1446/* 1447 * Platform definitions 1448 */ 1449static const struct aspeed_spi_data ast2400_fmc_data = { 1450 .max_cs = 5, 1451 .hastype = true, 1452 .we0 = 16, 1453 .ctl0 = CE0_CTRL_REG, 1454 .timing = CE0_TIMING_COMPENSATION_REG, 1455 .hclk_mask = 0xfffff0ff, 1456 .hdiv_max = 1, 1457 .min_window_size = 0x800000, 1458 .calibrate = aspeed_spi_calibrate, 1459 .get_clk_div = aspeed_get_clk_div_ast2400, 1460 .segment_start = aspeed_spi_segment_start, 1461 .segment_end = aspeed_spi_segment_end, 1462 .segment_reg = aspeed_spi_segment_reg, 1463 .adjust_window = aspeed_adjust_window_ast2400, 1464}; 1465 1466static const struct aspeed_spi_data ast2400_spi_data = { 1467 .max_cs = 1, 1468 .hastype = false, 1469 .we0 = 0, 1470 .ctl0 = 0x04, 1471 .timing = 0x14, 1472 .hclk_mask = 0xfffff0ff, 1473 .hdiv_max = 1, 1474 .get_clk_div = aspeed_get_clk_div_ast2400, 1475 .calibrate = aspeed_spi_calibrate, 1476 /* No segment registers */ 1477}; 1478 1479static const struct aspeed_spi_data ast2500_fmc_data = { 1480 .max_cs = 3, 1481 .hastype = true, 1482 .we0 = 16, 1483 .ctl0 = CE0_CTRL_REG, 1484 .timing = CE0_TIMING_COMPENSATION_REG, 1485 .hclk_mask = 0xffffd0ff, 1486 .hdiv_max = 1, 1487 .min_window_size = 0x800000, 1488 .get_clk_div = aspeed_get_clk_div_ast2500, 1489 .calibrate = aspeed_spi_calibrate, 1490 .segment_start = aspeed_spi_segment_start, 1491 .segment_end = aspeed_spi_segment_end, 1492 .segment_reg = aspeed_spi_segment_reg, 1493 .adjust_window = aspeed_adjust_window_ast2500, 1494}; 1495 1496static const struct aspeed_spi_data ast2500_spi_data = { 1497 .max_cs = 2, 1498 .hastype = false, 1499 .we0 = 16, 1500 .ctl0 = CE0_CTRL_REG, 1501 .timing = CE0_TIMING_COMPENSATION_REG, 1502 .hclk_mask = 0xffffd0ff, 1503 .hdiv_max = 1, 1504 .min_window_size = 0x800000, 1505 .get_clk_div = aspeed_get_clk_div_ast2500, 1506 .calibrate = aspeed_spi_calibrate, 1507 .segment_start = aspeed_spi_segment_start, 1508 .segment_end = aspeed_spi_segment_end, 1509 .segment_reg = aspeed_spi_segment_reg, 1510 .adjust_window = aspeed_adjust_window_ast2500, 1511}; 1512 1513static const struct aspeed_spi_data ast2600_fmc_data = { 1514 .max_cs = 3, 1515 .hastype = false, 1516 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1517 .we0 = 16, 1518 .ctl0 = CE0_CTRL_REG, 1519 .timing = CE0_TIMING_COMPENSATION_REG, 1520 .hclk_mask = 0xf0fff0ff, 1521 .hdiv_max = 2, 1522 .min_window_size = 0x200000, 1523 .get_clk_div = aspeed_get_clk_div_ast2600, 1524 .calibrate = aspeed_spi_ast2600_calibrate, 1525 .segment_start = aspeed_spi_segment_ast2600_start, 1526 .segment_end = aspeed_spi_segment_ast2600_end, 1527 .segment_reg = aspeed_spi_segment_ast2600_reg, 1528 .adjust_window = aspeed_adjust_window_ast2600, 1529}; 1530 1531static const struct aspeed_spi_data ast2600_spi_data = { 1532 .max_cs = 2, 1533 .hastype = false, 1534 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1535 .we0 = 16, 1536 .ctl0 = CE0_CTRL_REG, 1537 .timing = CE0_TIMING_COMPENSATION_REG, 1538 .hclk_mask = 0xf0fff0ff, 1539 .hdiv_max = 2, 1540 .min_window_size = 0x200000, 1541 .get_clk_div = aspeed_get_clk_div_ast2600, 1542 .calibrate = aspeed_spi_ast2600_calibrate, 1543 .segment_start = aspeed_spi_segment_ast2600_start, 1544 .segment_end = aspeed_spi_segment_ast2600_end, 1545 .segment_reg = aspeed_spi_segment_ast2600_reg, 1546 .adjust_window = aspeed_adjust_window_ast2600, 1547}; 1548 1549static const struct aspeed_spi_data ast2700_fmc_data = { 1550 .max_cs = 3, 1551 .hastype = false, 1552 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1553 .we0 = 16, 1554 .ctl0 = CE0_CTRL_REG, 1555 .timing = CE0_TIMING_COMPENSATION_REG, 1556 .hclk_mask = 0xf0fff0ff, 1557 .hdiv_max = 2, 1558 .min_window_size = 0x10000, 1559 .get_clk_div = aspeed_get_clk_div_ast2600, 1560 .calibrate = aspeed_spi_ast2600_calibrate, 1561 .segment_start = aspeed_spi_segment_ast2700_start, 1562 .segment_end = aspeed_spi_segment_ast2700_end, 1563 .segment_reg = aspeed_spi_segment_ast2700_reg, 1564}; 1565 1566static const struct aspeed_spi_data ast2700_spi_data = { 1567 .max_cs = 2, 1568 .hastype = false, 1569 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD, 1570 .we0 = 16, 1571 .ctl0 = CE0_CTRL_REG, 1572 .timing = CE0_TIMING_COMPENSATION_REG, 1573 .hclk_mask = 0xf0fff0ff, 1574 .hdiv_max = 2, 1575 .min_window_size = 0x10000, 1576 .get_clk_div = aspeed_get_clk_div_ast2600, 1577 .calibrate = aspeed_spi_ast2600_calibrate, 1578 .segment_start = aspeed_spi_segment_ast2700_start, 1579 .segment_end = aspeed_spi_segment_ast2700_end, 1580 .segment_reg = aspeed_spi_segment_ast2700_reg, 1581}; 1582 1583static const struct of_device_id aspeed_spi_matches[] = { 1584 { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data }, 1585 { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data }, 1586 { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data }, 1587 { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data }, 1588 { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data }, 1589 { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data }, 1590 { .compatible = "aspeed,ast2700-fmc", .data = &ast2700_fmc_data }, 1591 { .compatible = "aspeed,ast2700-spi", .data = &ast2700_spi_data }, 1592 { } 1593}; 1594MODULE_DEVICE_TABLE(of, aspeed_spi_matches); 1595 1596static struct platform_driver aspeed_spi_driver = { 1597 .probe = aspeed_spi_probe, 1598 .remove = aspeed_spi_remove, 1599 .driver = { 1600 .name = DEVICE_NAME, 1601 .of_match_table = aspeed_spi_matches, 1602 } 1603}; 1604 1605module_platform_driver(aspeed_spi_driver); 1606 1607MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver"); 1608MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>"); 1609MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>"); 1610MODULE_LICENSE("GPL v2");
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