qcom.c

   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (c) 2019, Linaro Limited
   3
   4#include <linux/clk.h>
   5#include <linux/completion.h>
   6#include <linux/interrupt.h>
   7#include <linux/io.h>
   8#include <linux/kernel.h>
   9#include <linux/module.h>
  10#include <linux/debugfs.h>
  11#include <linux/of.h>
  12#include <linux/of_irq.h>
  13#include <linux/pm_runtime.h>
  14#include <linux/regmap.h>
  15#include <linux/reset.h>
  16#include <linux/slab.h>
  17#include <linux/pm_wakeirq.h>
  18#include <linux/slimbus.h>
  19#include <linux/soundwire/sdw.h>
  20#include <linux/soundwire/sdw_registers.h>
  21#include <sound/pcm_params.h>
  22#include <sound/soc.h>
  23#include "bus.h"
  24
  25#define SWRM_COMP_SW_RESET					0x008
  26#define SWRM_COMP_STATUS					0x014
  27#define SWRM_LINK_MANAGER_EE					0x018
  28#define SWRM_EE_CPU						1
  29#define SWRM_FRM_GEN_ENABLED					BIT(0)
  30#define SWRM_VERSION_1_3_0					0x01030000
  31#define SWRM_VERSION_1_5_1					0x01050001
  32#define SWRM_VERSION_1_7_0					0x01070000
  33#define SWRM_VERSION_2_0_0					0x02000000
  34#define SWRM_VERSION_3_1_0					0x03010000
  35#define SWRM_COMP_HW_VERSION					0x00
  36#define SWRM_COMP_CFG_ADDR					0x04
  37#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK			BIT(1)
  38#define SWRM_COMP_CFG_ENABLE_MSK				BIT(0)
  39#define SWRM_COMP_PARAMS					0x100
  40#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH				GENMASK(14, 10)
  41#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH				GENMASK(19, 15)
  42#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK			GENMASK(4, 0)
  43#define SWRM_COMP_PARAMS_DIN_PORTS_MASK				GENMASK(9, 5)
  44#define SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH			GENMASK(17, 10)
  45#define SWRM_V3_COMP_PARAMS_RD_FIFO_DEPTH			GENMASK(23, 18)
  46
  47#define SWRM_COMP_MASTER_ID					0x104
  48#define SWRM_V1_3_INTERRUPT_STATUS				0x200
  49#define SWRM_V2_0_INTERRUPT_STATUS				0x5000
  50#define SWRM_INTERRUPT_STATUS_RMSK				GENMASK(16, 0)
  51#define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ			BIT(0)
  52#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED		BIT(1)
  53#define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS		BIT(2)
  54#define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET			BIT(3)
  55#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW			BIT(4)
  56#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW			BIT(5)
  57#define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW		BIT(6)
  58#define SWRM_INTERRUPT_STATUS_CMD_ERROR				BIT(7)
  59#define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION		BIT(8)
  60#define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH		BIT(9)
  61#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED		BIT(10)
  62#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED			BIT(11)
  63#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL		BIT(12)
  64#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2		BIT(13)
  65#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2		BIT(14)
  66#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP		BIT(16)
  67#define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED	BIT(19)
  68#define SWRM_INTERRUPT_MAX					17
  69#define SWRM_V1_3_INTERRUPT_MASK_ADDR				0x204
  70#define SWRM_V1_3_INTERRUPT_CLEAR				0x208
  71#define SWRM_V2_0_INTERRUPT_CLEAR				0x5008
  72#define SWRM_V1_3_INTERRUPT_CPU_EN				0x210
  73#define SWRM_V2_0_INTERRUPT_CPU_EN				0x5004
  74#define SWRM_V1_3_CMD_FIFO_WR_CMD				0x300
  75#define SWRM_V2_0_CMD_FIFO_WR_CMD				0x5020
  76#define SWRM_V1_3_CMD_FIFO_RD_CMD				0x304
  77#define SWRM_V2_0_CMD_FIFO_RD_CMD				0x5024
  78#define SWRM_CMD_FIFO_CMD					0x308
  79#define SWRM_CMD_FIFO_FLUSH					0x1
  80#define SWRM_V1_3_CMD_FIFO_STATUS				0x30C
  81#define SWRM_V2_0_CMD_FIFO_STATUS				0x5050
  82#define SWRM_RD_CMD_FIFO_CNT_MASK				GENMASK(20, 16)
  83#define SWRM_WR_CMD_FIFO_CNT_MASK				GENMASK(12, 8)
  84#define SWRM_CMD_FIFO_CFG_ADDR					0x314
  85#define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE			BIT(31)
  86#define SWRM_RD_WR_CMD_RETRIES					0x7
  87#define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR				0x318
  88#define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR				0x5040
  89#define SWRM_RD_FIFO_CMD_ID_MASK				GENMASK(11, 8)
  90#define SWRM_ENUMERATOR_CFG_ADDR				0x500
  91#define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)		(0x530 + 0x8 * (m))
  92#define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)		(0x534 + 0x8 * (m))
  93#define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)		(0x101C + 0x40 * (m))
  94#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK			GENMASK(2, 0)
  95#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK			GENMASK(7, 3)
  96#define SWRM_MCP_BUS_CTRL					0x1044
  97#define SWRM_MCP_BUS_CLK_START					BIT(1)
  98#define SWRM_MCP_CFG_ADDR					0x1048
  99#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK		GENMASK(21, 17)
 100#define SWRM_DEF_CMD_NO_PINGS					0x1f
 101#define SWRM_MCP_STATUS						0x104C
 102#define SWRM_MCP_STATUS_BANK_NUM_MASK				BIT(0)
 103#define SWRM_MCP_SLV_STATUS					0x1090
 104#define SWRM_MCP_SLV_STATUS_MASK				GENMASK(1, 0)
 105#define SWRM_MCP_SLV_STATUS_SZ					2
 106
 107#define SWRM_DPn_PORT_CTRL_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)
 108#define SWRM_DPn_PORT_CTRL_2_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)
 109#define SWRM_DPn_BLOCK_CTRL_1(offset, n)	(offset + 0x100 * (n - 1))
 110#define SWRM_DPn_BLOCK_CTRL2_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)
 111#define SWRM_DPn_PORT_HCTRL_BANK(offset,  n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)
 112#define SWRM_DPn_BLOCK_CTRL3_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)
 113#define SWRM_DPn_SAMPLECTRL2_BANK(offset, n, m)	(offset + 0x100 * (n - 1) + 0x40 * m)
 114
 115#define SWR_V1_3_MSTR_MAX_REG_ADDR				0x1740
 116#define SWR_V2_0_MSTR_MAX_REG_ADDR				0x50ac
 117
 118#define SWRM_V2_0_CLK_CTRL					0x5060
 119#define SWRM_V2_0_CLK_CTRL_CLK_START				BIT(0)
 120#define SWRM_V2_0_LINK_STATUS					0x5064
 121
 122#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT				0x18
 123#define SWRM_DP_PORT_CTRL_OFFSET2_SHFT				0x10
 124#define SWRM_DP_PORT_CTRL_OFFSET1_SHFT				0x08
 125#define SWRM_AHB_BRIDGE_WR_DATA_0				0xc85
 126#define SWRM_AHB_BRIDGE_WR_ADDR_0				0xc89
 127#define SWRM_AHB_BRIDGE_RD_ADDR_0				0xc8d
 128#define SWRM_AHB_BRIDGE_RD_DATA_0				0xc91
 129
 130#define SWRM_REG_VAL_PACK(data, dev, id, reg)	\
 131			((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 132
 133#define MAX_FREQ_NUM						1
 134#define TIMEOUT_MS						100
 135#define QCOM_SWRM_MAX_RD_LEN					0x1
 136#define DEFAULT_CLK_FREQ					9600000
 137#define SWRM_MAX_DAIS						0xF
 138#define SWR_INVALID_PARAM					0xFF
 139#define SWR_HSTOP_MAX_VAL					0xF
 140#define SWR_HSTART_MIN_VAL					0x0
 141#define SWR_BROADCAST_CMD_ID					0x0F
 142#define SWR_MAX_CMD_ID						14
 143#define MAX_FIFO_RD_RETRY					3
 144#define SWR_OVERFLOW_RETRY_COUNT				30
 145#define SWRM_LINK_STATUS_RETRY_CNT				100
 146
 147enum {
 148	MASTER_ID_WSA = 1,
 149	MASTER_ID_RX,
 150	MASTER_ID_TX
 151};
 152
 153struct qcom_swrm_port_config {
 154	u16 si;
 155	u8 off1;
 156	u8 off2;
 157	u8 bp_mode;
 158	u8 hstart;
 159	u8 hstop;
 160	u8 word_length;
 161	u8 blk_group_count;
 162	u8 lane_control;
 163};
 164
 165/*
 166 * Internal IDs for different register layouts.  Only few registers differ per
 167 * each variant, so the list of IDs below does not include all of registers.
 168 */
 169enum {
 170	SWRM_REG_FRAME_GEN_ENABLED,
 171	SWRM_REG_INTERRUPT_STATUS,
 172	SWRM_REG_INTERRUPT_MASK_ADDR,
 173	SWRM_REG_INTERRUPT_CLEAR,
 174	SWRM_REG_INTERRUPT_CPU_EN,
 175	SWRM_REG_CMD_FIFO_WR_CMD,
 176	SWRM_REG_CMD_FIFO_RD_CMD,
 177	SWRM_REG_CMD_FIFO_STATUS,
 178	SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
 179	SWRM_OFFSET_DP_PORT_CTRL_BANK,
 180	SWRM_OFFSET_DP_PORT_CTRL_2_BANK,
 181	SWRM_OFFSET_DP_BLOCK_CTRL_1,
 182	SWRM_OFFSET_DP_BLOCK_CTRL2_BANK,
 183	SWRM_OFFSET_DP_PORT_HCTRL_BANK,
 184	SWRM_OFFSET_DP_BLOCK_CTRL3_BANK,
 185	SWRM_OFFSET_DP_SAMPLECTRL2_BANK,
 186};
 187
 188struct qcom_swrm_ctrl {
 189	struct sdw_bus bus;
 190	struct device *dev;
 191	struct regmap *regmap;
 192	u32 max_reg;
 193	const unsigned int *reg_layout;
 194	void __iomem *mmio;
 195	struct reset_control *audio_cgcr;
 196#ifdef CONFIG_DEBUG_FS
 197	struct dentry *debugfs;
 198#endif
 199	struct completion broadcast;
 200	struct completion enumeration;
 201	/* Port alloc/free lock */
 202	struct mutex port_lock;
 203	struct clk *hclk;
 204	int irq;
 205	unsigned int version;
 206	int wake_irq;
 207	int num_din_ports;
 208	int num_dout_ports;
 209	int nports;
 210	int cols_index;
 211	int rows_index;
 212	unsigned long port_mask;
 213	u32 intr_mask;
 214	u8 rcmd_id;
 215	u8 wcmd_id;
 216	/* Port numbers are 1 - 14 */
 217	struct qcom_swrm_port_config *pconfig;
 218	struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 219	enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 220	int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 221	int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 222	u32 slave_status;
 223	u32 wr_fifo_depth;
 224	bool clock_stop_not_supported;
 225};
 226
 227struct qcom_swrm_data {
 228	u32 default_cols;
 229	u32 default_rows;
 230	bool sw_clk_gate_required;
 231	u32 max_reg;
 232	const unsigned int *reg_layout;
 233};
 234
 235static const unsigned int swrm_v1_3_reg_layout[] = {
 236	[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
 237	[SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
 238	[SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
 239	[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
 240	[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
 241	[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
 242	[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
 243	[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
 244	[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
 245	[SWRM_OFFSET_DP_PORT_CTRL_BANK]		= 0x1124,
 246	[SWRM_OFFSET_DP_PORT_CTRL_2_BANK]	= 0x1128,
 247	[SWRM_OFFSET_DP_BLOCK_CTRL_1]		= 0x112c,
 248	[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK]	= 0x1130,
 249	[SWRM_OFFSET_DP_PORT_HCTRL_BANK]	= 0x1134,
 250	[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK]	= 0x1138,
 251	[SWRM_OFFSET_DP_SAMPLECTRL2_BANK]	= 0x113c,
 252};
 253
 254static const struct qcom_swrm_data swrm_v1_3_data = {
 255	.default_rows = 48,
 256	.default_cols = 16,
 257	.max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 258	.reg_layout = swrm_v1_3_reg_layout,
 259};
 260
 261static const struct qcom_swrm_data swrm_v1_5_data = {
 262	.default_rows = 50,
 263	.default_cols = 16,
 264	.max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 265	.reg_layout = swrm_v1_3_reg_layout,
 266};
 267
 268static const struct qcom_swrm_data swrm_v1_6_data = {
 269	.default_rows = 50,
 270	.default_cols = 16,
 271	.sw_clk_gate_required = true,
 272	.max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
 273	.reg_layout = swrm_v1_3_reg_layout,
 274};
 275
 276static const unsigned int swrm_v2_0_reg_layout[] = {
 277	[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
 278	[SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
 279	[SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
 280	[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
 281	[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
 282	[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
 283	[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
 284	[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
 285	[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
 286	[SWRM_OFFSET_DP_PORT_CTRL_BANK]		= 0x1124,
 287	[SWRM_OFFSET_DP_PORT_CTRL_2_BANK]	= 0x1128,
 288	[SWRM_OFFSET_DP_BLOCK_CTRL_1]		= 0x112c,
 289	[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK]	= 0x1130,
 290	[SWRM_OFFSET_DP_PORT_HCTRL_BANK]	= 0x1134,
 291	[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK]	= 0x1138,
 292	[SWRM_OFFSET_DP_SAMPLECTRL2_BANK]	= 0x113c,
 293};
 294
 295static const struct qcom_swrm_data swrm_v2_0_data = {
 296	.default_rows = 50,
 297	.default_cols = 16,
 298	.sw_clk_gate_required = true,
 299	.max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
 300	.reg_layout = swrm_v2_0_reg_layout,
 301};
 302
 303static const unsigned int swrm_v3_0_reg_layout[] = {
 304	[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
 305	[SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
 306	[SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
 307	[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
 308	[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
 309	[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
 310	[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
 311	[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
 312	[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
 313	[SWRM_OFFSET_DP_PORT_CTRL_BANK]		= 0x1224,
 314	[SWRM_OFFSET_DP_PORT_CTRL_2_BANK]	= 0x1228,
 315	[SWRM_OFFSET_DP_BLOCK_CTRL_1]		= 0x122c,
 316	[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK]	= 0x1230,
 317	[SWRM_OFFSET_DP_PORT_HCTRL_BANK]	= 0x1234,
 318	[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK]	= 0x1238,
 319	[SWRM_OFFSET_DP_SAMPLECTRL2_BANK]	= 0x123c,
 320};
 321
 322static const struct qcom_swrm_data swrm_v3_0_data = {
 323	.default_rows = 50,
 324	.default_cols = 16,
 325	.sw_clk_gate_required = true,
 326	.max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
 327	.reg_layout = swrm_v3_0_reg_layout,
 328};
 329#define to_qcom_sdw(b)	container_of(b, struct qcom_swrm_ctrl, bus)
 330
 331static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 332				  u32 *val)
 333{
 334	struct regmap *wcd_regmap = ctrl->regmap;
 335	int ret;
 336
 337	/* pg register + offset */
 338	ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 339			  (u8 *)&reg, 4);
 340	if (ret < 0)
 341		return SDW_CMD_FAIL;
 342
 343	ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 344			       val, 4);
 345	if (ret < 0)
 346		return SDW_CMD_FAIL;
 347
 348	return SDW_CMD_OK;
 349}
 350
 351static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 352				   int reg, int val)
 353{
 354	struct regmap *wcd_regmap = ctrl->regmap;
 355	int ret;
 356	/* pg register + offset */
 357	ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 358			  (u8 *)&val, 4);
 359	if (ret)
 360		return SDW_CMD_FAIL;
 361
 362	/* write address register */
 363	ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 364			  (u8 *)&reg, 4);
 365	if (ret)
 366		return SDW_CMD_FAIL;
 367
 368	return SDW_CMD_OK;
 369}
 370
 371static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 372				  u32 *val)
 373{
 374	*val = readl(ctrl->mmio + reg);
 375	return SDW_CMD_OK;
 376}
 377
 378static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 379				   int val)
 380{
 381	writel(val, ctrl->mmio + reg);
 382	return SDW_CMD_OK;
 383}
 384
 385static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 386				   u8 dev_addr, u16 reg_addr)
 387{
 388	u32 val;
 389	u8 id = *cmd_id;
 390
 391	if (id != SWR_BROADCAST_CMD_ID) {
 392		if (id < SWR_MAX_CMD_ID)
 393			id += 1;
 394		else
 395			id = 0;
 396		*cmd_id = id;
 397	}
 398	val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 399
 400	return val;
 401}
 402
 403static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 404{
 405	u32 fifo_outstanding_data, value;
 406	int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 407
 408	do {
 409		/* Check for fifo underflow during read */
 410		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 411			       &value);
 412		fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 413
 414		/* Check if read data is available in read fifo */
 415		if (fifo_outstanding_data > 0)
 416			return 0;
 417
 418		usleep_range(500, 510);
 419	} while (fifo_retry_count--);
 420
 421	if (fifo_outstanding_data == 0) {
 422		dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
 423		return -EIO;
 424	}
 425
 426	return 0;
 427}
 428
 429static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
 430{
 431	u32 fifo_outstanding_cmds, value;
 432	int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 433
 434	do {
 435		/* Check for fifo overflow during write */
 436		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 437			       &value);
 438		fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 439
 440		/* Check for space in write fifo before writing */
 441		if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
 442			return 0;
 443
 444		usleep_range(500, 510);
 445	} while (fifo_retry_count--);
 446
 447	if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
 448		dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
 449		return -EIO;
 450	}
 451
 452	return 0;
 453}
 454
 455static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
 456{
 457	u32 fifo_outstanding_cmds, value;
 458	int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 459
 460	/* Check for fifo overflow during write */
 461	ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
 462	fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 463
 464	if (fifo_outstanding_cmds) {
 465		while (fifo_retry_count) {
 466			usleep_range(500, 510);
 467			ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
 468			fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 469			fifo_retry_count--;
 470			if (fifo_outstanding_cmds == 0)
 471				return true;
 472		}
 473	} else {
 474		return true;
 475	}
 476
 477
 478	return false;
 479}
 480
 481static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
 482				     u8 dev_addr, u16 reg_addr)
 483{
 484
 485	u32 val;
 486	int ret = 0;
 487	u8 cmd_id = 0x0;
 488
 489	if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 490		cmd_id = SWR_BROADCAST_CMD_ID;
 491		val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 492					      dev_addr, reg_addr);
 493	} else {
 494		val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
 495					      dev_addr, reg_addr);
 496	}
 497
 498	if (swrm_wait_for_wr_fifo_avail(ctrl))
 499		return SDW_CMD_FAIL_OTHER;
 500
 501	if (cmd_id == SWR_BROADCAST_CMD_ID)
 502		reinit_completion(&ctrl->broadcast);
 503
 504	/* Its assumed that write is okay as we do not get any status back */
 505	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
 506
 507	if (ctrl->version <= SWRM_VERSION_1_3_0)
 508		usleep_range(150, 155);
 509
 510	if (cmd_id == SWR_BROADCAST_CMD_ID) {
 511		swrm_wait_for_wr_fifo_done(ctrl);
 512		/*
 513		 * sleep for 10ms for MSM soundwire variant to allow broadcast
 514		 * command to complete.
 515		 */
 516		ret = wait_for_completion_timeout(&ctrl->broadcast,
 517						  msecs_to_jiffies(TIMEOUT_MS));
 518		if (!ret)
 519			ret = SDW_CMD_IGNORED;
 520		else
 521			ret = SDW_CMD_OK;
 522
 523	} else {
 524		ret = SDW_CMD_OK;
 525	}
 526	return ret;
 527}
 528
 529static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
 530				     u8 dev_addr, u16 reg_addr,
 531				     u32 len, u8 *rval)
 532{
 533	u32 cmd_data, cmd_id, val, retry_attempt = 0;
 534
 535	val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
 536
 537	/*
 538	 * Check for outstanding cmd wrt. write fifo depth to avoid
 539	 * overflow as read will also increase write fifo cnt.
 540	 */
 541	swrm_wait_for_wr_fifo_avail(ctrl);
 542
 543	/* wait for FIFO RD to complete to avoid overflow */
 544	usleep_range(100, 105);
 545	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
 546	/* wait for FIFO RD CMD complete to avoid overflow */
 547	usleep_range(250, 255);
 548
 549	if (swrm_wait_for_rd_fifo_avail(ctrl))
 550		return SDW_CMD_FAIL_OTHER;
 551
 552	do {
 553		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
 554			       &cmd_data);
 555		rval[0] = cmd_data & 0xFF;
 556		cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 557
 558		if (cmd_id != ctrl->rcmd_id) {
 559			if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 560				/* wait 500 us before retry on fifo read failure */
 561				usleep_range(500, 505);
 562				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
 563						SWRM_CMD_FIFO_FLUSH);
 564				ctrl->reg_write(ctrl,
 565						ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
 566						val);
 567			}
 568			retry_attempt++;
 569		} else {
 570			return SDW_CMD_OK;
 571		}
 572
 573	} while (retry_attempt < MAX_FIFO_RD_RETRY);
 574
 575	dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 576		dev_num: 0x%x, cmd_data: 0x%x\n",
 577		reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
 578
 579	return SDW_CMD_IGNORED;
 580}
 581
 582static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 583{
 584	u32 val, status;
 585	int dev_num;
 586
 587	ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 588
 589	for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 590		status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 591
 592		if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 593			ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
 594			return dev_num;
 595		}
 596	}
 597
 598	return -EINVAL;
 599}
 600
 601static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 602{
 603	u32 val;
 604	int i;
 605
 606	ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 607	ctrl->slave_status = val;
 608
 609	for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 610		u32 s;
 611
 612		s = (val >> (i * 2));
 613		s &= SWRM_MCP_SLV_STATUS_MASK;
 614		ctrl->status[i] = s;
 615	}
 616}
 617
 618static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 619					struct sdw_slave *slave, int devnum)
 620{
 621	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 622	u32 status;
 623
 624	ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 625	status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 626	status &= SWRM_MCP_SLV_STATUS_MASK;
 627
 628	if (status == SDW_SLAVE_ATTACHED) {
 629		if (slave)
 630			slave->dev_num = devnum;
 631		mutex_lock(&bus->bus_lock);
 632		set_bit(devnum, bus->assigned);
 633		mutex_unlock(&bus->bus_lock);
 634	}
 635}
 636
 637static int qcom_swrm_enumerate(struct sdw_bus *bus)
 638{
 639	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 640	struct sdw_slave *slave, *_s;
 641	struct sdw_slave_id id;
 642	u32 val1, val2;
 643	bool found;
 644	u64 addr;
 645	int i;
 646	char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 647
 648	for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 649		/* do not continue if the status is Not Present  */
 650		if (!ctrl->status[i])
 651			continue;
 652
 653		/*SCP_Devid5 - Devid 4*/
 654		ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 655
 656		/*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 657		ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 658
 659		if (!val1 && !val2)
 660			break;
 661
 662		addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 663			((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 664			((u64)buf1[0] << 40);
 665
 666		sdw_extract_slave_id(bus, addr, &id);
 667		found = false;
 668		ctrl->clock_stop_not_supported = false;
 669		/* Now compare with entries */
 670		list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 671			if (sdw_compare_devid(slave, id) == 0) {
 672				qcom_swrm_set_slave_dev_num(bus, slave, i);
 673				if (slave->prop.clk_stop_mode1)
 674					ctrl->clock_stop_not_supported = true;
 675
 676				found = true;
 677				break;
 678			}
 679		}
 680
 681		if (!found) {
 682			qcom_swrm_set_slave_dev_num(bus, NULL, i);
 683			sdw_slave_add(bus, &id, NULL);
 684		}
 685	}
 686
 687	complete(&ctrl->enumeration);
 688	return 0;
 689}
 690
 691static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 692{
 693	struct qcom_swrm_ctrl *ctrl = dev_id;
 694	int ret;
 695
 696	ret = pm_runtime_get_sync(ctrl->dev);
 697	if (ret < 0 && ret != -EACCES) {
 698		dev_err_ratelimited(ctrl->dev,
 699				    "pm_runtime_get_sync failed in %s, ret %d\n",
 700				    __func__, ret);
 701		pm_runtime_put_noidle(ctrl->dev);
 702		return ret;
 703	}
 704
 705	if (ctrl->wake_irq > 0) {
 706		if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
 707			disable_irq_nosync(ctrl->wake_irq);
 708	}
 709
 710	pm_runtime_mark_last_busy(ctrl->dev);
 711	pm_runtime_put_autosuspend(ctrl->dev);
 712
 713	return IRQ_HANDLED;
 714}
 715
 716static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 717{
 718	struct qcom_swrm_ctrl *ctrl = dev_id;
 719	u32 value, intr_sts, intr_sts_masked, slave_status;
 720	u32 i;
 721	int devnum;
 722	int ret = IRQ_HANDLED;
 723	clk_prepare_enable(ctrl->hclk);
 724
 725	ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 726		       &intr_sts);
 727	intr_sts_masked = intr_sts & ctrl->intr_mask;
 728
 729	do {
 730		for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 731			value = intr_sts_masked & BIT(i);
 732			if (!value)
 733				continue;
 734
 735			switch (value) {
 736			case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 737				devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
 738				if (devnum < 0) {
 739					dev_err_ratelimited(ctrl->dev,
 740					    "no slave alert found.spurious interrupt\n");
 741				} else {
 742					sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 743				}
 744
 745				break;
 746			case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 747			case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 748				dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
 749				ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
 750				if (ctrl->slave_status == slave_status) {
 751					dev_dbg(ctrl->dev, "Slave status not changed %x\n",
 752						slave_status);
 753				} else {
 754					qcom_swrm_get_device_status(ctrl);
 755					qcom_swrm_enumerate(&ctrl->bus);
 756					sdw_handle_slave_status(&ctrl->bus, ctrl->status);
 757				}
 758				break;
 759			case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 760				dev_err_ratelimited(ctrl->dev,
 761						"%s: SWR bus clsh detected\n",
 762						__func__);
 763				ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 764				ctrl->reg_write(ctrl,
 765						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 766						ctrl->intr_mask);
 767				break;
 768			case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 769				ctrl->reg_read(ctrl,
 770					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 771					       &value);
 772				dev_err_ratelimited(ctrl->dev,
 773					"%s: SWR read FIFO overflow fifo status 0x%x\n",
 774					__func__, value);
 775				break;
 776			case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 777				ctrl->reg_read(ctrl,
 778					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 779					       &value);
 780				dev_err_ratelimited(ctrl->dev,
 781					"%s: SWR read FIFO underflow fifo status 0x%x\n",
 782					__func__, value);
 783				break;
 784			case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 785				ctrl->reg_read(ctrl,
 786					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 787					       &value);
 788				dev_err(ctrl->dev,
 789					"%s: SWR write FIFO overflow fifo status %x\n",
 790					__func__, value);
 791				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 792				break;
 793			case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 794				ctrl->reg_read(ctrl,
 795					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 796					       &value);
 797				dev_err_ratelimited(ctrl->dev,
 798					"%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 799					__func__, value);
 800				ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
 801				break;
 802			case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 803				dev_err_ratelimited(ctrl->dev,
 804						"%s: SWR Port collision detected\n",
 805						__func__);
 806				ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 807				ctrl->reg_write(ctrl,
 808						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 809						ctrl->intr_mask);
 810				break;
 811			case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 812				dev_err_ratelimited(ctrl->dev,
 813					"%s: SWR read enable valid mismatch\n",
 814					__func__);
 815				ctrl->intr_mask &=
 816					~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 817				ctrl->reg_write(ctrl,
 818						ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 819						ctrl->intr_mask);
 820				break;
 821			case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 822				complete(&ctrl->broadcast);
 823				break;
 824			case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 825				break;
 826			case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 827				break;
 828			case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 829				break;
 830			case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED:
 831				ctrl->reg_read(ctrl,
 832					       ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
 833					       &value);
 834				dev_err(ctrl->dev,
 835					"%s: SWR CMD ignored, fifo status %x\n",
 836					__func__, value);
 837
 838				/* Wait 3.5ms to clear */
 839				usleep_range(3500, 3505);
 840				break;
 841			default:
 842				dev_err_ratelimited(ctrl->dev,
 843						"%s: SWR unknown interrupt value: %d\n",
 844						__func__, value);
 845				ret = IRQ_NONE;
 846				break;
 847			}
 848		}
 849		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
 850				intr_sts);
 851		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
 852			       &intr_sts);
 853		intr_sts_masked = intr_sts & ctrl->intr_mask;
 854	} while (intr_sts_masked);
 855
 856	clk_disable_unprepare(ctrl->hclk);
 857	return ret;
 858}
 859
 860static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
 861{
 862	int retry = SWRM_LINK_STATUS_RETRY_CNT;
 863	int comp_sts;
 864
 865	do {
 866		ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],
 867			       &comp_sts);
 868		if (comp_sts & SWRM_FRM_GEN_ENABLED)
 869			return true;
 870
 871		usleep_range(500, 510);
 872	} while (retry--);
 873
 874	dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
 875		comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
 876
 877	return false;
 878}
 879
 880static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 881{
 882	u32 val;
 883
 884	/* Clear Rows and Cols */
 885	val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 886	val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 887
 888	reset_control_reset(ctrl->audio_cgcr);
 889
 890	ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 891
 892	/* Enable Auto enumeration */
 893	ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 894
 895	ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 896	/* Mask soundwire interrupts */
 897	if (ctrl->version < SWRM_VERSION_2_0_0)
 898		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
 899				SWRM_INTERRUPT_STATUS_RMSK);
 900
 901	/* Configure No pings */
 902	ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 903	u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 904	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 905
 906	if (ctrl->version == SWRM_VERSION_1_7_0) {
 907		ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 908		ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
 909				SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
 910	} else if (ctrl->version >= SWRM_VERSION_2_0_0) {
 911		ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
 912		ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
 913				SWRM_V2_0_CLK_CTRL_CLK_START);
 914	} else {
 915		ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 916	}
 917
 918	/* Configure number of retries of a read/write cmd */
 919	if (ctrl->version >= SWRM_VERSION_1_5_1) {
 920		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 921				SWRM_RD_WR_CMD_RETRIES |
 922				SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 923	} else {
 924		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 925				SWRM_RD_WR_CMD_RETRIES);
 926	}
 927
 928	/* COMP Enable */
 929	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
 930
 931	/* Set IRQ to PULSE */
 932	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 933			SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK);
 934
 935	ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
 936			0xFFFFFFFF);
 937
 938	/* enable CPU IRQs */
 939	if (ctrl->mmio) {
 940		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
 941				SWRM_INTERRUPT_STATUS_RMSK);
 942	}
 943
 944	/* Set IRQ to PULSE */
 945	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 946			SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 947			SWRM_COMP_CFG_ENABLE_MSK);
 948
 949	swrm_wait_for_frame_gen_enabled(ctrl);
 950	ctrl->slave_status = 0;
 951	ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 952
 953	if (ctrl->version >= SWRM_VERSION_3_1_0)
 954		ctrl->wr_fifo_depth = FIELD_GET(SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH, val);
 955	else
 956		ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 957
 958	return 0;
 959}
 960
 961static int qcom_swrm_read_prop(struct sdw_bus *bus)
 962{
 963	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 964
 965	if (ctrl->version >= SWRM_VERSION_2_0_0) {
 966		bus->multi_link = true;
 967		bus->hw_sync_min_links = 3;
 968	}
 969
 970	return 0;
 971}
 972
 973static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 974						    struct sdw_msg *msg)
 975{
 976	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 977	int ret, i, len;
 978
 979	if (msg->flags == SDW_MSG_FLAG_READ) {
 980		for (i = 0; i < msg->len;) {
 981			len = min(msg->len - i, QCOM_SWRM_MAX_RD_LEN);
 982
 983			ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 984							msg->addr + i, len,
 985						       &msg->buf[i]);
 986			if (ret)
 987				return ret;
 988
 989			i = i + len;
 990		}
 991	} else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 992		for (i = 0; i < msg->len; i++) {
 993			ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 994							msg->dev_num,
 995						       msg->addr + i);
 996			if (ret)
 997				return SDW_CMD_IGNORED;
 998		}
 999	}
1000
1001	return SDW_CMD_OK;
1002}
1003
1004static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
1005{
1006	u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
1007	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1008	u32 val;
1009
1010	ctrl->reg_read(ctrl, reg, &val);
1011
1012	u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
1013	u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
1014
1015	return ctrl->reg_write(ctrl, reg, val);
1016}
1017
1018static int qcom_swrm_port_params(struct sdw_bus *bus,
1019				 struct sdw_port_params *p_params,
1020				 unsigned int bank)
1021{
1022	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1023	u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL_1];
1024
1025	return ctrl->reg_write(ctrl, SWRM_DPn_BLOCK_CTRL_1(offset, p_params->num),
1026				p_params->bps - 1);
1027}
1028
1029static int qcom_swrm_transport_params(struct sdw_bus *bus,
1030				      struct sdw_transport_params *params,
1031				      enum sdw_reg_bank bank)
1032{
1033	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1034	struct qcom_swrm_port_config *pcfg;
1035	u32 value;
1036	int reg, offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
1037	int ret;
1038
1039	reg = SWRM_DPn_PORT_CTRL_BANK(offset, params->port_num, bank);
1040
1041	pcfg = &ctrl->pconfig[params->port_num];
1042
1043	value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
1044	value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
1045	value |= pcfg->si & 0xff;
1046
1047	ret = ctrl->reg_write(ctrl, reg, value);
1048	if (ret)
1049		goto err;
1050
1051	if (pcfg->si > 0xff) {
1052		offset = ctrl->reg_layout[SWRM_OFFSET_DP_SAMPLECTRL2_BANK];
1053		value = (pcfg->si >> 8) & 0xff;
1054		reg = SWRM_DPn_SAMPLECTRL2_BANK(offset, params->port_num, bank);
1055
1056		ret = ctrl->reg_write(ctrl, reg, value);
1057		if (ret)
1058			goto err;
1059	}
1060
1061	if (pcfg->lane_control != SWR_INVALID_PARAM) {
1062		offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_2_BANK];
1063		reg = SWRM_DPn_PORT_CTRL_2_BANK(offset, params->port_num, bank);
1064
1065		value = pcfg->lane_control;
1066		ret = ctrl->reg_write(ctrl, reg, value);
1067		if (ret)
1068			goto err;
1069	}
1070
1071	if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
1072		offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK];
1073
1074		reg = SWRM_DPn_BLOCK_CTRL2_BANK(offset, params->port_num, bank);
1075
1076		value = pcfg->blk_group_count;
1077		ret = ctrl->reg_write(ctrl, reg, value);
1078		if (ret)
1079			goto err;
1080	}
1081
1082	offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_HCTRL_BANK];
1083	reg = SWRM_DPn_PORT_HCTRL_BANK(offset, params->port_num, bank);
1084
1085	if (pcfg->hstart != SWR_INVALID_PARAM && pcfg->hstop != SWR_INVALID_PARAM) {
1086		value = (pcfg->hstop << 4) | pcfg->hstart;
1087		ret = ctrl->reg_write(ctrl, reg, value);
1088	} else {
1089		value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
1090		ret = ctrl->reg_write(ctrl, reg, value);
1091	}
1092
1093	if (ret)
1094		goto err;
1095
1096	if (pcfg->bp_mode != SWR_INVALID_PARAM) {
1097		offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK];
1098		reg = SWRM_DPn_BLOCK_CTRL3_BANK(offset, params->port_num, bank);
1099		ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1100	}
1101
1102err:
1103	return ret;
1104}
1105
1106static int qcom_swrm_port_enable(struct sdw_bus *bus,
1107				 struct sdw_enable_ch *enable_ch,
1108				 unsigned int bank)
1109{
1110	u32 reg;
1111	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1112	u32 val;
1113	u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
1114
1115	reg = SWRM_DPn_PORT_CTRL_BANK(offset, enable_ch->port_num, bank);
1116
1117	ctrl->reg_read(ctrl, reg, &val);
1118
1119	if (enable_ch->enable)
1120		val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1121	else
1122		val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1123
1124	return ctrl->reg_write(ctrl, reg, val);
1125}
1126
1127static const struct sdw_master_port_ops qcom_swrm_port_ops = {
1128	.dpn_set_port_params = qcom_swrm_port_params,
1129	.dpn_set_port_transport_params = qcom_swrm_transport_params,
1130	.dpn_port_enable_ch = qcom_swrm_port_enable,
1131};
1132
1133static const struct sdw_master_ops qcom_swrm_ops = {
1134	.read_prop = qcom_swrm_read_prop,
1135	.xfer_msg = qcom_swrm_xfer_msg,
1136	.pre_bank_switch = qcom_swrm_pre_bank_switch,
1137};
1138
1139static int qcom_swrm_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
1140{
1141	struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1142	struct sdw_master_runtime *m_rt;
1143	struct sdw_slave_runtime *s_rt;
1144	struct sdw_port_runtime *p_rt;
1145	struct qcom_swrm_port_config *pcfg;
1146	struct sdw_slave *slave;
1147	unsigned int m_port;
1148	int i = 1;
1149
1150	list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
1151		list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1152			pcfg = &ctrl->pconfig[p_rt->num];
1153			p_rt->transport_params.port_num = p_rt->num;
1154			if (pcfg->word_length != SWR_INVALID_PARAM) {
1155				sdw_fill_port_params(&p_rt->port_params,
1156					     p_rt->num,  pcfg->word_length + 1,
1157					     SDW_PORT_FLOW_MODE_ISOCH,
1158					     SDW_PORT_DATA_MODE_NORMAL);
1159			}
1160
1161		}
1162
1163		list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1164			slave = s_rt->slave;
1165			list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1166				m_port = slave->m_port_map[p_rt->num];
1167				/* port config starts at offset 0 so -1 from actual port number */
1168				if (m_port)
1169					pcfg = &ctrl->pconfig[m_port];
1170				else
1171					pcfg = &ctrl->pconfig[i];
1172				p_rt->transport_params.port_num = p_rt->num;
1173				p_rt->transport_params.sample_interval =
1174					pcfg->si + 1;
1175				p_rt->transport_params.offset1 = pcfg->off1;
1176				p_rt->transport_params.offset2 = pcfg->off2;
1177				p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
1178				p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
1179
1180				p_rt->transport_params.hstart = pcfg->hstart;
1181				p_rt->transport_params.hstop = pcfg->hstop;
1182				p_rt->transport_params.lane_ctrl = pcfg->lane_control;
1183				if (pcfg->word_length != SWR_INVALID_PARAM) {
1184					sdw_fill_port_params(&p_rt->port_params,
1185						     p_rt->num,
1186						     pcfg->word_length + 1,
1187						     SDW_PORT_FLOW_MODE_ISOCH,
1188						     SDW_PORT_DATA_MODE_NORMAL);
1189				}
1190				i++;
1191			}
1192		}
1193	}
1194
1195	return 0;
1196}
1197
1198static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1199	DEFAULT_CLK_FREQ,
1200};
1201
1202static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1203					struct sdw_stream_runtime *stream)
1204{
1205	struct sdw_master_runtime *m_rt;
1206	struct sdw_port_runtime *p_rt;
1207	unsigned long *port_mask;
1208
1209	mutex_lock(&ctrl->port_lock);
1210
1211	list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1212		port_mask = &ctrl->port_mask;
1213		list_for_each_entry(p_rt, &m_rt->port_list, port_node)
1214			clear_bit(p_rt->num, port_mask);
1215	}
1216
1217	mutex_unlock(&ctrl->port_lock);
1218}
1219
1220static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1221					struct sdw_stream_runtime *stream,
1222				       struct snd_pcm_hw_params *params,
1223				       int direction)
1224{
1225	struct sdw_stream_config sconfig;
1226	struct sdw_master_runtime *m_rt;
1227	struct sdw_slave_runtime *s_rt;
1228	struct sdw_port_runtime *p_rt;
1229	struct sdw_slave *slave;
1230	unsigned long *port_mask;
1231	int maxport, pn, nports = 0, ret = 0;
1232	unsigned int m_port;
1233	struct sdw_port_config *pconfig __free(kfree) = kcalloc(ctrl->nports,
1234								sizeof(*pconfig), GFP_KERNEL);
1235	if (!pconfig)
1236		return -ENOMEM;
1237
1238	if (direction == SNDRV_PCM_STREAM_CAPTURE)
1239		sconfig.direction = SDW_DATA_DIR_TX;
1240	else
1241		sconfig.direction = SDW_DATA_DIR_RX;
1242
1243	/* hw parameters will be ignored as we only support PDM */
1244	sconfig.ch_count = 1;
1245	sconfig.frame_rate = params_rate(params);
1246	sconfig.type = stream->type;
1247	sconfig.bps = 1;
1248
1249	mutex_lock(&ctrl->port_lock);
1250	list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1251		/*
1252		 * For streams with multiple masters:
1253		 * Allocate ports only for devices connected to this master.
1254		 * Such devices will have ports allocated by their own master
1255		 * and its qcom_swrm_stream_alloc_ports() call.
1256		 */
1257		if (ctrl->bus.id != m_rt->bus->id)
1258			continue;
1259
1260		port_mask = &ctrl->port_mask;
1261		maxport = ctrl->nports;
1262
1263		list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1264			slave = s_rt->slave;
1265			list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1266				m_port = slave->m_port_map[p_rt->num];
1267				/* Port numbers start from 1 - 14*/
1268				if (m_port)
1269					pn = m_port;
1270				else
1271					pn = find_first_zero_bit(port_mask, maxport);
1272
1273				if (pn > maxport) {
1274					dev_err(ctrl->dev, "All ports busy\n");
1275					ret = -EBUSY;
1276					goto out;
1277				}
1278				set_bit(pn, port_mask);
1279				pconfig[nports].num = pn;
1280				pconfig[nports].ch_mask = p_rt->ch_mask;
1281				nports++;
1282			}
1283		}
1284	}
1285
1286	sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1287			      nports, stream);
1288out:
1289	mutex_unlock(&ctrl->port_lock);
1290
1291	return ret;
1292}
1293
1294static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1295			       struct snd_pcm_hw_params *params,
1296			      struct snd_soc_dai *dai)
1297{
1298	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1299	struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1300	int ret;
1301
1302	ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1303					   substream->stream);
1304	if (ret)
1305		qcom_swrm_stream_free_ports(ctrl, sruntime);
1306
1307	return ret;
1308}
1309
1310static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1311			     struct snd_soc_dai *dai)
1312{
1313	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1314	struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1315
1316	qcom_swrm_stream_free_ports(ctrl, sruntime);
1317	sdw_stream_remove_master(&ctrl->bus, sruntime);
1318
1319	return 0;
1320}
1321
1322static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1323				    void *stream, int direction)
1324{
1325	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1326
1327	ctrl->sruntime[dai->id] = stream;
1328
1329	return 0;
1330}
1331
1332static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1333{
1334	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1335
1336	return ctrl->sruntime[dai->id];
1337}
1338
1339static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1340			     struct snd_soc_dai *dai)
1341{
1342	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1343	int ret;
1344
1345	ret = pm_runtime_get_sync(ctrl->dev);
1346	if (ret < 0 && ret != -EACCES) {
1347		dev_err_ratelimited(ctrl->dev,
1348				    "pm_runtime_get_sync failed in %s, ret %d\n",
1349				    __func__, ret);
1350		pm_runtime_put_noidle(ctrl->dev);
1351		return ret;
1352	}
1353
1354	return 0;
1355}
1356
1357static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1358			       struct snd_soc_dai *dai)
1359{
1360	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1361
1362	swrm_wait_for_wr_fifo_done(ctrl);
1363	pm_runtime_mark_last_busy(ctrl->dev);
1364	pm_runtime_put_autosuspend(ctrl->dev);
1365
1366}
1367
1368static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1369	.hw_params = qcom_swrm_hw_params,
1370	.hw_free = qcom_swrm_hw_free,
1371	.startup = qcom_swrm_startup,
1372	.shutdown = qcom_swrm_shutdown,
1373	.set_stream = qcom_swrm_set_sdw_stream,
1374	.get_stream = qcom_swrm_get_sdw_stream,
1375};
1376
1377static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1378	.name = "soundwire",
1379};
1380
1381static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1382{
1383	int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1384	struct snd_soc_dai_driver *dais;
1385	struct snd_soc_pcm_stream *stream;
1386	struct device *dev = ctrl->dev;
1387	int i;
1388
1389	/* PDM dais are only tested for now */
1390	dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1391	if (!dais)
1392		return -ENOMEM;
1393
1394	for (i = 0; i < num_dais; i++) {
1395		dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1396		if (!dais[i].name)
1397			return -ENOMEM;
1398
1399		if (i < ctrl->num_dout_ports)
1400			stream = &dais[i].playback;
1401		else
1402			stream = &dais[i].capture;
1403
1404		stream->channels_min = 1;
1405		stream->channels_max = 1;
1406		stream->rates = SNDRV_PCM_RATE_48000;
1407		stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1408
1409		dais[i].ops = &qcom_swrm_pdm_dai_ops;
1410		dais[i].id = i;
1411	}
1412
1413	return devm_snd_soc_register_component(ctrl->dev,
1414						&qcom_swrm_dai_component,
1415						dais, num_dais);
1416}
1417
1418static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1419{
1420	struct device_node *np = ctrl->dev->of_node;
1421	struct qcom_swrm_port_config *pcfg;
1422	int i, ret, val;
1423
1424	ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1425
1426	ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1427	ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1428
1429	ret = of_property_read_u32(np, "qcom,din-ports", &val);
1430	if (!ret) { /* only if present */
1431		if (val != ctrl->num_din_ports) {
1432			dev_err(ctrl->dev, "din-ports (%d) mismatch with controller (%d)",
1433				val, ctrl->num_din_ports);
1434		}
1435
1436		ctrl->num_din_ports = val;
1437	}
1438
1439	ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1440	if (!ret) { /* only if present */
1441		if (val != ctrl->num_dout_ports) {
1442			dev_err(ctrl->dev, "dout-ports (%d) mismatch with controller (%d)",
1443				val, ctrl->num_dout_ports);
1444		}
1445
1446		ctrl->num_dout_ports = val;
1447	}
1448
1449	ctrl->nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1450
1451	ctrl->pconfig = devm_kcalloc(ctrl->dev, ctrl->nports + 1,
1452					sizeof(*ctrl->pconfig), GFP_KERNEL);
1453	if (!ctrl->pconfig)
1454		return -ENOMEM;
1455
1456	set_bit(0, &ctrl->port_mask);
1457	/* Valid port numbers are from 1, so mask out port 0 explicitly */
1458	for (i = 0; i < ctrl->nports; i++) {
1459		pcfg = &ctrl->pconfig[i + 1];
1460
1461		ret = of_property_read_u8_index(np, "qcom,ports-offset1", i, &pcfg->off1);
1462		if (ret)
1463			return ret;
1464
1465		ret = of_property_read_u8_index(np, "qcom,ports-offset2", i, &pcfg->off2);
1466		if (ret)
1467			return ret;
1468
1469		ret = of_property_read_u8_index(np, "qcom,ports-sinterval-low", i, (u8 *)&pcfg->si);
1470		if (ret) {
1471			ret = of_property_read_u16_index(np, "qcom,ports-sinterval", i, &pcfg->si);
1472			if (ret)
1473				return ret;
1474		}
1475
1476		ret = of_property_read_u8_index(np, "qcom,ports-block-pack-mode",
1477						i, &pcfg->bp_mode);
1478		if (ret) {
1479			if (ctrl->version <= SWRM_VERSION_1_3_0)
1480				pcfg->bp_mode = SWR_INVALID_PARAM;
1481			else
1482				return ret;
1483		}
1484
1485		/* Optional properties */
1486		pcfg->hstart = SWR_INVALID_PARAM;
1487		pcfg->hstop = SWR_INVALID_PARAM;
1488		pcfg->word_length = SWR_INVALID_PARAM;
1489		pcfg->blk_group_count = SWR_INVALID_PARAM;
1490		pcfg->lane_control = SWR_INVALID_PARAM;
1491
1492		of_property_read_u8_index(np, "qcom,ports-hstart", i, &pcfg->hstart);
1493
1494		of_property_read_u8_index(np, "qcom,ports-hstop", i, &pcfg->hstop);
1495
1496		of_property_read_u8_index(np, "qcom,ports-word-length", i, &pcfg->word_length);
1497
1498		of_property_read_u8_index(np, "qcom,ports-block-group-count",
1499					i, &pcfg->blk_group_count);
1500
1501		of_property_read_u8_index(np, "qcom,ports-lane-control", i, &pcfg->lane_control);
1502	}
1503
1504	return 0;
1505}
1506
1507#ifdef CONFIG_DEBUG_FS
1508static int swrm_reg_show(struct seq_file *s_file, void *data)
1509{
1510	struct qcom_swrm_ctrl *ctrl = s_file->private;
1511	int reg, reg_val, ret;
1512
1513	ret = pm_runtime_get_sync(ctrl->dev);
1514	if (ret < 0 && ret != -EACCES) {
1515		dev_err_ratelimited(ctrl->dev,
1516				    "pm_runtime_get_sync failed in %s, ret %d\n",
1517				    __func__, ret);
1518		pm_runtime_put_noidle(ctrl->dev);
1519		return ret;
1520	}
1521
1522	for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1523		ctrl->reg_read(ctrl, reg, &reg_val);
1524		seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1525	}
1526	pm_runtime_mark_last_busy(ctrl->dev);
1527	pm_runtime_put_autosuspend(ctrl->dev);
1528
1529
1530	return 0;
1531}
1532DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1533#endif
1534
1535static int qcom_swrm_probe(struct platform_device *pdev)
1536{
1537	struct device *dev = &pdev->dev;
1538	struct sdw_master_prop *prop;
1539	struct sdw_bus_params *params;
1540	struct qcom_swrm_ctrl *ctrl;
1541	const struct qcom_swrm_data *data;
1542	int ret;
1543	u32 val;
1544
1545	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1546	if (!ctrl)
1547		return -ENOMEM;
1548
1549	data = of_device_get_match_data(dev);
1550	ctrl->max_reg = data->max_reg;
1551	ctrl->reg_layout = data->reg_layout;
1552	ctrl->rows_index = sdw_find_row_index(data->default_rows);
1553	ctrl->cols_index = sdw_find_col_index(data->default_cols);
1554#if IS_REACHABLE(CONFIG_SLIMBUS)
1555	if (dev->parent->bus == &slimbus_bus) {
1556#else
1557	if (false) {
1558#endif
1559		ctrl->reg_read = qcom_swrm_ahb_reg_read;
1560		ctrl->reg_write = qcom_swrm_ahb_reg_write;
1561		ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1562		if (!ctrl->regmap)
1563			return -EINVAL;
1564	} else {
1565		ctrl->reg_read = qcom_swrm_cpu_reg_read;
1566		ctrl->reg_write = qcom_swrm_cpu_reg_write;
1567		ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1568		if (IS_ERR(ctrl->mmio))
1569			return PTR_ERR(ctrl->mmio);
1570	}
1571
1572	if (data->sw_clk_gate_required) {
1573		ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1574		if (IS_ERR(ctrl->audio_cgcr)) {
1575			dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1576			ret = PTR_ERR(ctrl->audio_cgcr);
1577			goto err_init;
1578		}
1579	}
1580
1581	ctrl->irq = of_irq_get(dev->of_node, 0);
1582	if (ctrl->irq < 0) {
1583		ret = ctrl->irq;
1584		goto err_init;
1585	}
1586
1587	ctrl->hclk = devm_clk_get(dev, "iface");
1588	if (IS_ERR(ctrl->hclk)) {
1589		ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1590		goto err_init;
1591	}
1592
1593	clk_prepare_enable(ctrl->hclk);
1594
1595	ctrl->dev = dev;
1596	dev_set_drvdata(&pdev->dev, ctrl);
1597	mutex_init(&ctrl->port_lock);
1598	init_completion(&ctrl->broadcast);
1599	init_completion(&ctrl->enumeration);
1600
1601	ctrl->bus.ops = &qcom_swrm_ops;
1602	ctrl->bus.port_ops = &qcom_swrm_port_ops;
1603	ctrl->bus.compute_params = &qcom_swrm_compute_params;
1604	ctrl->bus.clk_stop_timeout = 300;
1605
1606	ret = qcom_swrm_get_port_config(ctrl);
1607	if (ret)
1608		goto err_clk;
1609
1610	params = &ctrl->bus.params;
1611	params->max_dr_freq = DEFAULT_CLK_FREQ;
1612	params->curr_dr_freq = DEFAULT_CLK_FREQ;
1613	params->col = data->default_cols;
1614	params->row = data->default_rows;
1615	ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1616	params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1617	params->next_bank = !params->curr_bank;
1618
1619	prop = &ctrl->bus.prop;
1620	prop->max_clk_freq = DEFAULT_CLK_FREQ;
1621	prop->num_clk_gears = 0;
1622	prop->num_clk_freq = MAX_FREQ_NUM;
1623	prop->clk_freq = &qcom_swrm_freq_tbl[0];
1624	prop->default_col = data->default_cols;
1625	prop->default_row = data->default_rows;
1626
1627	ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1628
1629	ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1630					qcom_swrm_irq_handler,
1631					IRQF_TRIGGER_RISING |
1632					IRQF_ONESHOT,
1633					"soundwire", ctrl);
1634	if (ret) {
1635		dev_err(dev, "Failed to request soundwire irq\n");
1636		goto err_clk;
1637	}
1638
1639	ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1640	if (ctrl->wake_irq > 0) {
1641		ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1642						qcom_swrm_wake_irq_handler,
1643						IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1644						"swr_wake_irq", ctrl);
1645		if (ret) {
1646			dev_err(dev, "Failed to request soundwire wake irq\n");
1647			goto err_init;
1648		}
1649	}
1650
1651	ctrl->bus.controller_id = -1;
1652
1653	if (ctrl->version > SWRM_VERSION_1_3_0) {
1654		ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1655		ctrl->bus.controller_id = val;
1656	}
1657
1658	ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1659	if (ret) {
1660		dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1661			ret);
1662		goto err_clk;
1663	}
1664
1665	qcom_swrm_init(ctrl);
1666	wait_for_completion_timeout(&ctrl->enumeration,
1667				    msecs_to_jiffies(TIMEOUT_MS));
1668	ret = qcom_swrm_register_dais(ctrl);
1669	if (ret)
1670		goto err_master_add;
1671
1672	dev_dbg(dev, "Qualcomm Soundwire controller v%x.%x.%x registered\n",
1673		(ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1674		ctrl->version & 0xffff);
1675
1676	pm_runtime_set_autosuspend_delay(dev, 3000);
1677	pm_runtime_use_autosuspend(dev);
1678	pm_runtime_mark_last_busy(dev);
1679	pm_runtime_set_active(dev);
1680	pm_runtime_enable(dev);
1681
1682#ifdef CONFIG_DEBUG_FS
1683	ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1684	debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1685			    &swrm_reg_fops);
1686#endif
1687
1688	return 0;
1689
1690err_master_add:
1691	sdw_bus_master_delete(&ctrl->bus);
1692err_clk:
1693	clk_disable_unprepare(ctrl->hclk);
1694err_init:
1695	return ret;
1696}
1697
1698static void qcom_swrm_remove(struct platform_device *pdev)
1699{
1700	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1701
1702	sdw_bus_master_delete(&ctrl->bus);
1703	clk_disable_unprepare(ctrl->hclk);
1704}
1705
1706static int __maybe_unused swrm_runtime_resume(struct device *dev)
1707{
1708	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1709	int ret;
1710
1711	if (ctrl->wake_irq > 0) {
1712		if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1713			disable_irq_nosync(ctrl->wake_irq);
1714	}
1715
1716	clk_prepare_enable(ctrl->hclk);
1717
1718	if (ctrl->clock_stop_not_supported) {
1719		reinit_completion(&ctrl->enumeration);
1720		ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1721		usleep_range(100, 105);
1722
1723		qcom_swrm_init(ctrl);
1724
1725		usleep_range(100, 105);
1726		if (!swrm_wait_for_frame_gen_enabled(ctrl))
1727			dev_err(ctrl->dev, "link failed to connect\n");
1728
1729		/* wait for hw enumeration to complete */
1730		wait_for_completion_timeout(&ctrl->enumeration,
1731					    msecs_to_jiffies(TIMEOUT_MS));
1732		qcom_swrm_get_device_status(ctrl);
1733		sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1734	} else {
1735		reset_control_reset(ctrl->audio_cgcr);
1736
1737		if (ctrl->version == SWRM_VERSION_1_7_0) {
1738			ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1739			ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1740					SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1741		} else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1742			ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1743			ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1744					SWRM_V2_0_CLK_CTRL_CLK_START);
1745		} else {
1746			ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1747		}
1748		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1749			SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1750
1751		ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1752		if (ctrl->version < SWRM_VERSION_2_0_0)
1753			ctrl->reg_write(ctrl,
1754					ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1755					ctrl->intr_mask);
1756		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1757				ctrl->intr_mask);
1758
1759		usleep_range(100, 105);
1760		if (!swrm_wait_for_frame_gen_enabled(ctrl))
1761			dev_err(ctrl->dev, "link failed to connect\n");
1762
1763		ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1764		if (ret < 0)
1765			dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1766	}
1767
1768	return 0;
1769}
1770
1771static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1772{
1773	struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1774	int ret;
1775
1776	swrm_wait_for_wr_fifo_done(ctrl);
1777	if (!ctrl->clock_stop_not_supported) {
1778		/* Mask bus clash interrupt */
1779		ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1780		if (ctrl->version < SWRM_VERSION_2_0_0)
1781			ctrl->reg_write(ctrl,
1782					ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1783					ctrl->intr_mask);
1784		ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1785				ctrl->intr_mask);
1786		/* Prepare slaves for clock stop */
1787		ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1788		if (ret < 0 && ret != -ENODATA) {
1789			dev_err(dev, "prepare clock stop failed %d", ret);
1790			return ret;
1791		}
1792
1793		ret = sdw_bus_clk_stop(&ctrl->bus);
1794		if (ret < 0 && ret != -ENODATA) {
1795			dev_err(dev, "bus clock stop failed %d", ret);
1796			return ret;
1797		}
1798	}
1799
1800	clk_disable_unprepare(ctrl->hclk);
1801
1802	usleep_range(300, 305);
1803
1804	if (ctrl->wake_irq > 0) {
1805		if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1806			enable_irq(ctrl->wake_irq);
1807	}
1808
1809	return 0;
1810}
1811
1812static const struct dev_pm_ops swrm_dev_pm_ops = {
1813	SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1814};
1815
1816static const struct of_device_id qcom_swrm_of_match[] = {
1817	{ .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1818	{ .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1819	{ .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1820	{ .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1821	{ .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1822	{ .compatible = "qcom,soundwire-v3.1.0", .data = &swrm_v3_0_data },
1823	{/* sentinel */},
1824};
1825
1826MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1827
1828static struct platform_driver qcom_swrm_driver = {
1829	.probe	= &qcom_swrm_probe,
1830	.remove = qcom_swrm_remove,
1831	.driver = {
1832		.name	= "qcom-soundwire",
1833		.of_match_table = qcom_swrm_of_match,
1834		.pm = &swrm_dev_pm_ops,
1835	}
1836};
1837module_platform_driver(qcom_swrm_driver);
1838
1839MODULE_DESCRIPTION("Qualcomm soundwire driver");
1840MODULE_LICENSE("GPL v2");