amd_manager.h

  1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
  2/*
  3 * Copyright (C) 2023-24 Advanced Micro Devices, Inc. All rights reserved.
  4 */
  5
  6#ifndef __AMD_MANAGER_H
  7#define __AMD_MANAGER_H
  8
  9#include <linux/soundwire/sdw_amd.h>
 10
 11#define SDW_MANAGER_REG_OFFSET				0xc00
 12#define AMD_SDW_DEFAULT_ROWS				50
 13#define AMD_SDW_DEFAULT_COLUMNS				10
 14#define ACP_PAD_PULLDOWN_CTRL				0x0001448
 15#define ACP_SW_PAD_KEEPER_EN				0x0001454
 16#define ACP_SW0_WAKE_EN					0x0001458
 17#define ACP_EXTERNAL_INTR_CNTL0				0x0001a04
 18#define ACP_EXTERNAL_INTR_STAT0				0x0001a0c
 19#define ACP_EXTERNAL_INTR_CNTL(i)			(ACP_EXTERNAL_INTR_CNTL0 + ((i) * 4))
 20#define ACP_EXTERNAL_INTR_STAT(i)			(ACP_EXTERNAL_INTR_STAT0 + ((i) * 4))
 21#define ACP_SW_WAKE_EN(i)				(ACP_SW0_WAKE_EN + ((i) * 8))
 22
 23#define ACP_SW_EN					0x0003000
 24#define ACP_SW_EN_STATUS				0x0003004
 25#define ACP_SW_FRAMESIZE				0x0003008
 26#define ACP_SW_SSP_COUNTER				0x000300c
 27#define ACP_SW_AUDIO0_TX_EN				0x0003010
 28#define ACP_SW_AUDIO0_TX_EN_STATUS			0x0003014
 29#define ACP_SW_AUDIO0_TX_FRAME_FORMAT			0x0003018
 30#define ACP_SW_AUDIO0_TX_SAMPLEINTERVAL			0x000301c
 31#define ACP_SW_AUDIO0_TX_HCTRL_DP0			0x0003020
 32#define ACP_SW_AUDIO0_TX_HCTRL_DP1			0x0003024
 33#define ACP_SW_AUDIO0_TX_HCTRL_DP2			0x0003028
 34#define ACP_SW_AUDIO0_TX_HCTRL_DP3			0x000302c
 35#define ACP_SW_AUDIO0_TX_OFFSET_DP0			0x0003030
 36#define ACP_SW_AUDIO0_TX_OFFSET_DP1			0x0003034
 37#define ACP_SW_AUDIO0_TX_OFFSET_DP2			0x0003038
 38#define ACP_SW_AUDIO0_TX_OFFSET_DP3			0x000303c
 39#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0		0x0003040
 40#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP1		0x0003044
 41#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP2		0x0003048
 42#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP3		0x000304c
 43#define ACP_SW_AUDIO1_TX_EN				0x0003050
 44#define ACP_SW_AUDIO1_TX_EN_STATUS			0x0003054
 45#define ACP_SW_AUDIO1_TX_FRAME_FORMAT			0x0003058
 46#define ACP_SW_AUDIO1_TX_SAMPLEINTERVAL			0x000305c
 47#define ACP_SW_AUDIO1_TX_HCTRL				0x0003060
 48#define ACP_SW_AUDIO1_TX_OFFSET				0x0003064
 49#define ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0		0x0003068
 50#define ACP_SW_AUDIO2_TX_EN				0x000306c
 51#define ACP_SW_AUDIO2_TX_EN_STATUS			0x0003070
 52#define ACP_SW_AUDIO2_TX_FRAME_FORMAT			0x0003074
 53#define ACP_SW_AUDIO2_TX_SAMPLEINTERVAL			0x0003078
 54#define ACP_SW_AUDIO2_TX_HCTRL				0x000307c
 55#define ACP_SW_AUDIO2_TX_OFFSET				0x0003080
 56#define ACP_SW_AUDIO2_TX_CHANNEL_ENABLE_DP0		0x0003084
 57#define ACP_SW_AUDIO0_RX_EN				0x0003088
 58#define ACP_SW_AUDIO0_RX_EN_STATUS			0x000308c
 59#define ACP_SW_AUDIO0_RX_FRAME_FORMAT			0x0003090
 60#define ACP_SW_AUDIO0_RX_SAMPLEINTERVAL			0x0003094
 61#define ACP_SW_AUDIO0_RX_HCTRL_DP0			0x0003098
 62#define ACP_SW_AUDIO0_RX_HCTRL_DP1			0x000309c
 63#define ACP_SW_AUDIO0_RX_HCTRL_DP2			0x0003100
 64#define ACP_SW_AUDIO0_RX_HCTRL_DP3			0x0003104
 65#define ACP_SW_AUDIO0_RX_OFFSET_DP0			0x0003108
 66#define ACP_SW_AUDIO0_RX_OFFSET_DP1			0x000310c
 67#define ACP_SW_AUDIO0_RX_OFFSET_DP2			0x0003110
 68#define ACP_SW_AUDIO0_RX_OFFSET_DP3			0x0003114
 69#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP0		0x0003118
 70#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP1		0x000311c
 71#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP2		0x0003120
 72#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP3		0x0003124
 73#define ACP_SW_AUDIO1_RX_EN				0x0003128
 74#define ACP_SW_AUDIO1_RX_EN_STATUS			0x000312c
 75#define ACP_SW_AUDIO1_RX_FRAME_FORMAT			0x0003130
 76#define ACP_SW_AUDIO1_RX_SAMPLEINTERVAL			0x0003134
 77#define ACP_SW_AUDIO1_RX_HCTRL				0x0003138
 78#define ACP_SW_AUDIO1_RX_OFFSET				0x000313c
 79#define ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0		0x0003140
 80#define ACP_SW_AUDIO2_RX_EN				0x0003144
 81#define ACP_SW_AUDIO2_RX_EN_STATUS			0x0003148
 82#define ACP_SW_AUDIO2_RX_FRAME_FORMAT			0x000314c
 83#define ACP_SW_AUDIO2_RX_SAMPLEINTERVAL			0x0003150
 84#define ACP_SW_AUDIO2_RX_HCTRL				0x0003154
 85#define ACP_SW_AUDIO2_RX_OFFSET				0x0003158
 86#define ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0		0x000315c
 87#define ACP_SW_BPT_PORT_EN				0x0003160
 88#define ACP_SW_BPT_PORT_EN_STATUS			0x0003164
 89#define ACP_SW_BPT_PORT_FRAME_FORMAT			0x0003168
 90#define ACP_SW_BPT_PORT_SAMPLEINTERVAL			0x000316c
 91#define ACP_SW_BPT_PORT_HCTRL				0x0003170
 92#define ACP_SW_BPT_PORT_OFFSET				0x0003174
 93#define ACP_SW_BPT_PORT_CHANNEL_ENABLE			0x0003178
 94#define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR			0x000317c
 95#define ACP_SW_CLK_RESUME_CTRL				0x0003180
 96#define ACP_SW_CLK_RESUME_DELAY_CNTR			0x0003184
 97#define ACP_SW_BUS_RESET_CTRL				0x0003188
 98#define ACP_SW_PRBS_ERR_STATUS				0x000318c
 99#define ACP_SW_IMM_CMD_UPPER_WORD			0x0003230
100#define ACP_SW_IMM_CMD_LOWER_QWORD			0x0003234
101#define ACP_SW_IMM_RESP_UPPER_WORD			0x0003238
102#define ACP_SW_IMM_RESP_LOWER_QWORD			0x000323c
103#define ACP_SW_IMM_CMD_STS				0x0003240
104#define ACP_SW_BRA_BASE_ADDRESS				0x0003244
105#define ACP_SW_BRA_TRANSFER_SIZE			0x0003248
106#define ACP_SW_BRA_DMA_BUSY				0x000324c
107#define ACP_SW_BRA_RESP					0x0003250
108#define ACP_SW_BRA_RESP_FRAME_ADDR			0x0003254
109#define ACP_SW_BRA_CURRENT_TRANSFER_SIZE		0x0003258
110#define ACP_SW_STATE_CHANGE_STATUS_0TO7			0x000325c
111#define ACP_SW_STATE_CHANGE_STATUS_8TO11		0x0003260
112#define ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7		0x0003264
113#define ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11		0x0003268
114#define ACP_SW_CLK_FREQUENCY_CTRL			0x000326c
115#define ACP_SW_ERROR_INTR_MASK				0x0003270
116#define ACP_SW_PHY_TEST_MODE_DATA_OFF			0x0003274
117
118#define ACP_DELAY_US					10
119#define AMD_SDW_TIMEOUT					1000
120#define AMD_SDW_DEFAULT_CLK_FREQ			12000000
121
122#define AMD_SDW_MCP_RESP_ACK				BIT(0)
123#define AMD_SDW_MCP_RESP_NACK				BIT(1)
124#define AMD_SDW_MCP_RESP_RDATA				GENMASK(14, 7)
125
126#define AMD_SDW_MCP_CMD_SSP_TAG				BIT(31)
127#define AMD_SDW_MCP_CMD_COMMAND				GENMASK(14, 12)
128#define AMD_SDW_MCP_CMD_DEV_ADDR			GENMASK(11, 8)
129#define AMD_SDW_MCP_CMD_REG_ADDR_HIGH			GENMASK(7, 0)
130#define AMD_SDW_MCP_CMD_REG_ADDR_LOW			GENMASK(31, 24)
131#define AMD_SDW_MCP_CMD_REG_DATA			GENMASK(14, 7)
132#define AMD_SDW_MCP_SLAVE_STAT_0_3			GENMASK(14, 7)
133#define AMD_SDW_MCP_SLAVE_STAT_4_11			GENMASK_ULL(39, 24)
134#define AMD_SDW_MCP_SLAVE_STATUS_MASK			GENMASK(1, 0)
135#define AMD_SDW_MCP_SLAVE_STATUS_BITS			GENMASK(3, 2)
136#define AMD_SDW_MCP_SLAVE_STATUS_8TO_11			GENMASK_ULL(15, 0)
137#define AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(x)		BIT(((x) * 4))
138#define AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(x)		(((x) * 4) + 1)
139
140#define AMD_SDW_MASTER_SUSPEND_DELAY_MS			2000
141#define AMD_SDW_QUIRK_MASK_BUS_ENABLE			BIT(0)
142
143#define AMD_SDW_IMM_RES_VALID		1
144#define AMD_SDW_IMM_CMD_BUSY		2
145#define AMD_SDW_ENABLE			1
146#define AMD_SDW_DISABLE			0
147#define AMD_SDW_BUS_RESET_CLEAR_REQ	0
148#define AMD_SDW_BUS_RESET_REQ		1
149#define AMD_SDW_BUS_RESET_DONE		2
150#define AMD_SDW_BUS_BASE_FREQ		24000000
151
152#define AMD_SDW0_EXT_INTR_MASK		0x200000
153#define AMD_SDW1_EXT_INTR_MASK		4
154#define AMD_SDW_IRQ_MASK_0TO7		0x77777777
155#define AMD_SDW_IRQ_MASK_8TO11		0x000c7777
156#define AMD_SDW_IRQ_ERROR_MASK		0xff
157#define AMD_SDW_MAX_FREQ_NUM		1
158#define AMD_ACP63_SDW0_MAX_TX_PORTS		3
159#define AMD_ACP63_SDW0_MAX_RX_PORTS		3
160#define AMD_ACP63_SDW1_MAX_TX_PORTS		1
161#define AMD_ACP63_SDW1_MAX_RX_PORTS		1
162#define AMD_ACP70_SDW_MAX_TX_PORTS		3
163#define AMD_ACP70_SDW_MAX_RX_PORTS		3
164#define AMD_ACP63_SDW0_MAX_DAI		6
165#define AMD_ACP63_SDW1_MAX_DAI		2
166#define AMD_ACP70_SDW_MAX_DAI		6
167#define AMD_SDW_SLAVE_0_ATTACHED	5
168#define AMD_SDW_SSP_COUNTER_VAL		3
169
170#define AMD_DPN_FRAME_FMT_PFM				GENMASK(1, 0)
171#define AMD_DPN_FRAME_FMT_PDM				GENMASK(3, 2)
172#define AMD_DPN_FRAME_FMT_BLK_PKG_MODE			BIT(4)
173#define AMD_DPN_FRAME_FMT_BLK_GRP_CTRL			GENMASK(6, 5)
174#define AMD_DPN_FRAME_FMT_WORD_LEN			GENMASK(12, 7)
175#define AMD_DPN_FRAME_FMT_PCM_OR_PDM			BIT(13)
176#define AMD_DPN_HCTRL_HSTOP				GENMASK(3, 0)
177#define AMD_DPN_HCTRL_HSTART				GENMASK(7, 4)
178#define AMD_DPN_OFFSET_CTRL_1				GENMASK(7, 0)
179#define AMD_DPN_OFFSET_CTRL_2				GENMASK(15, 8)
180#define AMD_DPN_CH_EN_LCTRL				GENMASK(2, 0)
181#define AMD_DPN_CH_EN_CHMASK				GENMASK(10, 3)
182#define AMD_SDW_STAT_MAX_RETRY_COUNT			100
183#define AMD_SDW0_PAD_PULLDOWN_CTRL_ENABLE_MASK		0x7f9f
184#define AMD_SDW1_PAD_PULLDOWN_CTRL_ENABLE_MASK		0x7ffa
185#define AMD_SDW0_PAD_PULLDOWN_CTRL_DISABLE_MASK		0x60
186#define AMD_SDW1_PAD_PULLDOWN_CTRL_DISABLE_MASK		5
187#define AMD_SDW0_PAD_KEEPER_EN_MASK			1
188#define AMD_SDW1_PAD_KEEPER_EN_MASK			0x10
189#define AMD_SDW0_PAD_KEEPER_DISABLE_MASK		0x1e
190#define AMD_SDW1_PAD_KEEPER_DISABLE_MASK		0xf
191#define AMD_SDW_PREQ_INTR_STAT				BIT(19)
192#define AMD_SDW_CLK_STOP_DONE				1
193#define AMD_SDW_CLK_RESUME_REQ				2
194#define AMD_SDW_CLK_RESUME_DONE				3
195#define AMD_SDW_WAKE_STAT_MASK				BIT(16)
196#define AMD_SDW_WAKE_INTR_MASK				BIT(16)
197#define AMD_SDW0_HOST_WAKE_INTR_MASK			BIT(22)
198#define AMD_SDW1_HOST_WAKE_INTR_MASK			BIT(23)
199#define AMD_SDW_DEVICE_STATE				0x1430
200#define AMD_SDW0_DEVICE_STATE_MASK			GENMASK(1, 0)
201#define AMD_SDW1_DEVICE_STATE_MASK			GENMASK(3, 2)
202#define AMD_SDW_DEVICE_STATE_D0				0
203#define AMD_SDW_DEVICE_STATE_D3				3
204#define ACP_PME_EN					0x0001400
205
206static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
207	AMD_SDW_DEFAULT_CLK_FREQ,
208};
209
210struct sdw_manager_dp_reg {
211	u32 frame_fmt_reg;
212	u32 sample_int_reg;
213	u32 hctrl_dp0_reg;
214	u32 offset_reg;
215	u32 lane_ctrl_ch_en_reg;
216};
217
218/*
219 * SDW0 Manager instance registers  6 CPU DAI (3 TX & 3 RX Ports)
220 * whereas SDW1  Manager Instance registers 2 CPU DAI (one TX & one RX port)
221 * Below is the CPU DAI <->Manager port number mapping
222 * i.e SDW0 Pin0 -> port number 0 -> AUDIO0 TX
223 *     SDW0 Pin1 -> Port number 1 -> AUDIO1 TX
224 *     SDW0 Pin2 -> Port number 2 -> AUDIO2 TX
225 *     SDW0 Pin3 -> port number 3 -> AUDIO0 RX
226 *     SDW0 Pin4 -> Port number 4 -> AUDIO1 RX
227 *     SDW0 Pin5 -> Port number 5 -> AUDIO2 RX
228 *  Whereas for SDW1 instance
229 *  SDW1 Pin0 -> port number 0 -> AUDIO1 TX
230 *  SDW1 Pin1 -> Port number 1 -> AUDIO1 RX
231 *  Same mapping should be used for programming DMA controller registers in SoundWire DMA driver.
232 * i.e if AUDIO0 TX channel is selected then we need to use AUDIO0 TX registers for DMA programming
233 * in SoundWire DMA driver.
234 */
235
236static struct sdw_manager_dp_reg acp63_sdw0_dp_reg[AMD_ACP63_SDW0_MAX_DAI] =  {
237	{ACP_SW_AUDIO0_TX_FRAME_FORMAT, ACP_SW_AUDIO0_TX_SAMPLEINTERVAL, ACP_SW_AUDIO0_TX_HCTRL_DP0,
238	 ACP_SW_AUDIO0_TX_OFFSET_DP0, ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0},
239	{ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,
240	 ACP_SW_AUDIO1_TX_OFFSET, ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0},
241	{ACP_SW_AUDIO2_TX_FRAME_FORMAT, ACP_SW_AUDIO2_TX_SAMPLEINTERVAL, ACP_SW_AUDIO2_TX_HCTRL,
242	 ACP_SW_AUDIO2_TX_OFFSET, ACP_SW_AUDIO2_TX_CHANNEL_ENABLE_DP0},
243	{ACP_SW_AUDIO0_RX_FRAME_FORMAT, ACP_SW_AUDIO0_RX_SAMPLEINTERVAL, ACP_SW_AUDIO0_RX_HCTRL_DP0,
244	 ACP_SW_AUDIO0_RX_OFFSET_DP0, ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP0},
245	{ACP_SW_AUDIO1_RX_FRAME_FORMAT, ACP_SW_AUDIO1_RX_SAMPLEINTERVAL, ACP_SW_AUDIO1_RX_HCTRL,
246	 ACP_SW_AUDIO1_RX_OFFSET, ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0},
247	{ACP_SW_AUDIO2_RX_FRAME_FORMAT, ACP_SW_AUDIO2_RX_SAMPLEINTERVAL, ACP_SW_AUDIO2_RX_HCTRL,
248	 ACP_SW_AUDIO2_RX_OFFSET, ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0},
249};
250
251static struct sdw_manager_dp_reg acp63_sdw1_dp_reg[AMD_ACP63_SDW1_MAX_DAI] =  {
252	{ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,
253	 ACP_SW_AUDIO1_TX_OFFSET, ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0},
254	{ACP_SW_AUDIO1_RX_FRAME_FORMAT, ACP_SW_AUDIO1_RX_SAMPLEINTERVAL, ACP_SW_AUDIO1_RX_HCTRL,
255	 ACP_SW_AUDIO1_RX_OFFSET, ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0}
256};
257
258static struct sdw_manager_dp_reg acp70_sdw_dp_reg[AMD_ACP70_SDW_MAX_DAI] =  {
259	{ACP_SW_AUDIO0_TX_FRAME_FORMAT, ACP_SW_AUDIO0_TX_SAMPLEINTERVAL, ACP_SW_AUDIO0_TX_HCTRL_DP0,
260	 ACP_SW_AUDIO0_TX_OFFSET_DP0, ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0},
261	{ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,
262	 ACP_SW_AUDIO1_TX_OFFSET, ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0},
263	{ACP_SW_AUDIO2_TX_FRAME_FORMAT, ACP_SW_AUDIO2_TX_SAMPLEINTERVAL, ACP_SW_AUDIO2_TX_HCTRL,
264	 ACP_SW_AUDIO2_TX_OFFSET, ACP_SW_AUDIO2_TX_CHANNEL_ENABLE_DP0},
265	{ACP_SW_AUDIO0_RX_FRAME_FORMAT, ACP_SW_AUDIO0_RX_SAMPLEINTERVAL, ACP_SW_AUDIO0_RX_HCTRL_DP0,
266	 ACP_SW_AUDIO0_RX_OFFSET_DP0, ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP0},
267	{ACP_SW_AUDIO1_RX_FRAME_FORMAT, ACP_SW_AUDIO1_RX_SAMPLEINTERVAL, ACP_SW_AUDIO1_RX_HCTRL,
268	 ACP_SW_AUDIO1_RX_OFFSET, ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0},
269	{ACP_SW_AUDIO2_RX_FRAME_FORMAT, ACP_SW_AUDIO2_RX_SAMPLEINTERVAL, ACP_SW_AUDIO2_RX_HCTRL,
270	 ACP_SW_AUDIO2_RX_OFFSET, ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0},
271};
272
273static u32 sdw_manager_reg_mask_array[AMD_SDW_MAX_MANAGER_COUNT] =  {
274		AMD_SDW0_EXT_INTR_MASK,
275		AMD_SDW1_EXT_INTR_MASK
276};
277#endif