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pmc.c
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linux-6.19.14/drivers/soc/tegra/pmc.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12#define pr_fmt(fmt) "tegra-pmc: " fmt 13 14#include <linux/arm-smccc.h> 15#include <linux/clk.h> 16#include <linux/clk-provider.h> 17#include <linux/clkdev.h> 18#include <linux/clk/clk-conf.h> 19#include <linux/clk/tegra.h> 20#include <linux/debugfs.h> 21#include <linux/delay.h> 22#include <linux/device.h> 23#include <linux/err.h> 24#include <linux/export.h> 25#include <linux/init.h> 26#include <linux/interrupt.h> 27#include <linux/io.h> 28#include <linux/iopoll.h> 29#include <linux/irqdomain.h> 30#include <linux/irq.h> 31#include <linux/irq_work.h> 32#include <linux/kernel.h> 33#include <linux/of_address.h> 34#include <linux/of_clk.h> 35#include <linux/of.h> 36#include <linux/of_irq.h> 37#include <linux/of_platform.h> 38#include <linux/pinctrl/pinconf-generic.h> 39#include <linux/pinctrl/pinconf.h> 40#include <linux/pinctrl/pinctrl.h> 41#include <linux/platform_device.h> 42#include <linux/pm_domain.h> 43#include <linux/pm_opp.h> 44#include <linux/power_supply.h> 45#include <linux/reboot.h> 46#include <linux/regmap.h> 47#include <linux/reset.h> 48#include <linux/seq_file.h> 49#include <linux/slab.h> 50#include <linux/spinlock.h> 51#include <linux/string_choices.h> 52#include <linux/syscore_ops.h> 53 54#include <soc/tegra/common.h> 55#include <soc/tegra/fuse.h> 56#include <soc/tegra/pmc.h> 57 58#include <dt-bindings/interrupt-controller/arm-gic.h> 59#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 60#include <dt-bindings/gpio/tegra186-gpio.h> 61#include <dt-bindings/gpio/tegra194-gpio.h> 62#include <dt-bindings/gpio/tegra234-gpio.h> 63#include <dt-bindings/soc/tegra-pmc.h> 64 65#define PMC_CNTRL 0x0 66#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 67#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 68#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 69#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 70#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 71#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 72#define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 73#define PMC_CNTRL_BLINK_EN 7 74#define PMC_CNTRL_MAIN_RST BIT(4) 75 76#define PMC_WAKE_MASK 0x0c 77#define PMC_WAKE_LEVEL 0x10 78#define PMC_WAKE_STATUS 0x14 79#define PMC_SW_WAKE_STATUS 0x18 80#define PMC_DPD_PADS_ORIDE 0x1c 81#define PMC_DPD_PADS_ORIDE_BLINK 20 82 83#define DPD_SAMPLE 0x020 84#define DPD_SAMPLE_ENABLE BIT(0) 85#define DPD_SAMPLE_DISABLE (0 << 0) 86 87#define PWRGATE_TOGGLE 0x30 88#define PWRGATE_TOGGLE_START BIT(8) 89 90#define REMOVE_CLAMPING 0x34 91 92#define PWRGATE_STATUS 0x38 93 94#define PMC_BLINK_TIMER 0x40 95#define PMC_IMPL_E_33V_PWR 0x40 96 97#define PMC_PWR_DET 0x48 98 99#define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 100#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 101#define PMC_SCRATCH0_MODE_RCM BIT(1) 102#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 103 PMC_SCRATCH0_MODE_BOOTLOADER | \ 104 PMC_SCRATCH0_MODE_RCM) 105 106#define PMC_CPUPWRGOOD_TIMER 0xc8 107#define PMC_CPUPWROFF_TIMER 0xcc 108#define PMC_COREPWRGOOD_TIMER 0x3c 109#define PMC_COREPWROFF_TIMER 0xe0 110 111#define PMC_PWR_DET_VALUE 0xe4 112 113#define PMC_USB_DEBOUNCE_DEL 0xec 114#define PMC_USB_AO 0xf0 115 116#define PMC_SCRATCH37 0x130 117#define PMC_SCRATCH41 0x140 118 119#define PMC_WAKE2_MASK 0x160 120#define PMC_WAKE2_LEVEL 0x164 121#define PMC_WAKE2_STATUS 0x168 122#define PMC_SW_WAKE2_STATUS 0x16c 123 124#define PMC_CLK_OUT_CNTRL 0x1a8 125#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 126#define PMC_SENSOR_CTRL 0x1b0 127#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 128#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 129 130#define PMC_RST_STATUS_POR 0 131#define PMC_RST_STATUS_WATCHDOG 1 132#define PMC_RST_STATUS_SENSOR 2 133#define PMC_RST_STATUS_SW_MAIN 3 134#define PMC_RST_STATUS_LP0 4 135#define PMC_RST_STATUS_AOTAG 5 136 137#define IO_DPD_REQ 0x1b8 138#define IO_DPD_REQ_CODE_IDLE (0U << 30) 139#define IO_DPD_REQ_CODE_OFF (1U << 30) 140#define IO_DPD_REQ_CODE_ON (2U << 30) 141#define IO_DPD_REQ_CODE_MASK (3U << 30) 142 143#define IO_DPD_STATUS 0x1bc 144#define IO_DPD2_REQ 0x1c0 145#define IO_DPD2_STATUS 0x1c4 146#define SEL_DPD_TIM 0x1c8 147 148#define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 149#define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 150 151#define PMC_UTMIP_TERM_PAD_CFG 0x1f8 152#define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 153#define PMC_UTMIP_UHSIC_FAKE 0x218 154 155#define PMC_SCRATCH54 0x258 156#define PMC_SCRATCH54_DATA_SHIFT 8 157#define PMC_SCRATCH54_ADDR_SHIFT 0 158 159#define PMC_SCRATCH55 0x25c 160#define PMC_SCRATCH55_RESET_TEGRA BIT(31) 161#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 162#define PMC_SCRATCH55_PINMUX_SHIFT 24 163#define PMC_SCRATCH55_16BITOP BIT(15) 164#define PMC_SCRATCH55_CHECKSUM_SHIFT 16 165#define PMC_SCRATCH55_I2CSLV1_SHIFT 0 166 167#define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 168 169#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 170#define PMC_UTMIP_MASTER_CONFIG 0x274 171#define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 172#define PMC_UTMIP_MASTER2_CONFIG 0x29c 173 174#define GPU_RG_CNTRL 0x2d4 175 176#define PMC_UTMIP_PAD_CFG0 0x4c0 177#define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 178#define PMC_UTMIP_SLEEPWALK_P3 0x4e0 179/* Tegra186 and later */ 180#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 181#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 182#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) 183#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 184#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 185#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 186#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 187#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 188#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 189#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 190#define WAKE_AOWAKE_SW_STATUS_W_0 0x49c 191#define WAKE_AOWAKE_SW_STATUS(x) (0x4a0 + ((x) << 2)) 192#define WAKE_LATCH_SW 0x498 193 194#define WAKE_AOWAKE_CTRL 0x4f4 195#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 196 197#define SW_WAKE_ID 83 /* wake83 */ 198 199/* for secure PMC */ 200#define TEGRA_SMC_PMC 0xc2fffe00 201#define TEGRA_SMC_PMC_READ 0xaa 202#define TEGRA_SMC_PMC_WRITE 0xbb 203 204struct pmc_clk { 205 struct clk_hw hw; 206 unsigned long offs; 207 u32 mux_shift; 208 u32 force_en_shift; 209}; 210 211#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 212 213struct pmc_clk_gate { 214 struct clk_hw hw; 215 unsigned long offs; 216 u32 shift; 217}; 218 219#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 220 221struct pmc_clk_init_data { 222 char *name; 223 const char *const *parents; 224 int num_parents; 225 int clk_id; 226 u8 mux_shift; 227 u8 force_en_shift; 228}; 229 230static const char * const clk_out1_parents[] = { "osc", "osc_div2", 231 "osc_div4", "extern1", 232}; 233 234static const char * const clk_out2_parents[] = { "osc", "osc_div2", 235 "osc_div4", "extern2", 236}; 237 238static const char * const clk_out3_parents[] = { "osc", "osc_div2", 239 "osc_div4", "extern3", 240}; 241 242static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 243 { 244 .name = "pmc_clk_out_1", 245 .parents = clk_out1_parents, 246 .num_parents = ARRAY_SIZE(clk_out1_parents), 247 .clk_id = TEGRA_PMC_CLK_OUT_1, 248 .mux_shift = 6, 249 .force_en_shift = 2, 250 }, 251 { 252 .name = "pmc_clk_out_2", 253 .parents = clk_out2_parents, 254 .num_parents = ARRAY_SIZE(clk_out2_parents), 255 .clk_id = TEGRA_PMC_CLK_OUT_2, 256 .mux_shift = 14, 257 .force_en_shift = 10, 258 }, 259 { 260 .name = "pmc_clk_out_3", 261 .parents = clk_out3_parents, 262 .num_parents = ARRAY_SIZE(clk_out3_parents), 263 .clk_id = TEGRA_PMC_CLK_OUT_3, 264 .mux_shift = 22, 265 .force_en_shift = 18, 266 }, 267}; 268 269struct tegra_powergate { 270 struct generic_pm_domain genpd; 271 struct tegra_pmc *pmc; 272 unsigned int id; 273 struct clk **clks; 274 unsigned int num_clks; 275 unsigned long *clk_rates; 276 struct reset_control *reset; 277}; 278 279struct tegra_io_pad_soc { 280 enum tegra_io_pad id; 281 unsigned int dpd; 282 unsigned int request; 283 unsigned int status; 284 unsigned int voltage; 285 const char *name; 286}; 287 288struct tegra_pmc_regs { 289 unsigned int scratch0; 290 unsigned int rst_status; 291 unsigned int rst_source_shift; 292 unsigned int rst_source_mask; 293 unsigned int rst_level_shift; 294 unsigned int rst_level_mask; 295}; 296 297struct tegra_wake_event { 298 const char *name; 299 unsigned int id; 300 unsigned int irq; 301 struct { 302 unsigned int instance; 303 unsigned int pin; 304 } gpio; 305}; 306 307#define TEGRA_WAKE_SIMPLE(_name, _id) \ 308 { \ 309 .name = _name, \ 310 .id = _id, \ 311 .irq = 0, \ 312 .gpio = { \ 313 .instance = UINT_MAX, \ 314 .pin = UINT_MAX, \ 315 }, \ 316 } 317 318#define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 319 { \ 320 .name = _name, \ 321 .id = _id, \ 322 .irq = _irq, \ 323 .gpio = { \ 324 .instance = UINT_MAX, \ 325 .pin = UINT_MAX, \ 326 }, \ 327 } 328 329#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 330 { \ 331 .name = _name, \ 332 .id = _id, \ 333 .irq = 0, \ 334 .gpio = { \ 335 .instance = _instance, \ 336 .pin = _pin, \ 337 }, \ 338 } 339 340struct tegra_pmc_soc { 341 unsigned int num_powergates; 342 const char *const *powergates; 343 unsigned int num_cpu_powergates; 344 const u8 *cpu_powergates; 345 346 bool has_tsense_reset; 347 bool has_gpu_clamps; 348 bool needs_mbist_war; 349 bool has_impl_33v_pwr; 350 bool maybe_tz_only; 351 352 const struct tegra_io_pad_soc *io_pads; 353 unsigned int num_io_pads; 354 355 const struct pinctrl_pin_desc *pin_descs; 356 unsigned int num_pin_descs; 357 358 const struct tegra_pmc_regs *regs; 359 void (*init)(struct tegra_pmc *pmc); 360 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 361 struct device_node *np, 362 bool invert); 363 void (*set_wake_filters)(struct tegra_pmc *pmc); 364 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 365 int (*irq_set_type)(struct irq_data *data, unsigned int type); 366 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 367 bool new_state); 368 369 const char * const *reset_sources; 370 unsigned int num_reset_sources; 371 const char * const *reset_levels; 372 unsigned int num_reset_levels; 373 374 /* 375 * These describe events that can wake the system from sleep (i.e. 376 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 377 * are dealt with in the LIC. 378 */ 379 const struct tegra_wake_event *wake_events; 380 unsigned int num_wake_events; 381 unsigned int max_wake_events; 382 unsigned int max_wake_vectors; 383 384 const struct pmc_clk_init_data *pmc_clks_data; 385 unsigned int num_pmc_clks; 386 bool has_blink_output; 387 bool has_usb_sleepwalk; 388 bool supports_core_domain; 389 bool has_single_mmio_aperture; 390}; 391 392/** 393 * struct tegra_pmc - NVIDIA Tegra PMC 394 * @dev: pointer to PMC device structure 395 * @base: pointer to I/O remapped register region 396 * @wake: pointer to I/O remapped region for WAKE registers 397 * @aotag: pointer to I/O remapped region for AOTAG registers 398 * @scratch: pointer to I/O remapped region for scratch registers 399 * @clk: pointer to pclk clock 400 * @soc: pointer to SoC data structure 401 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 402 * @rate: currently configured rate of pclk 403 * @suspend_mode: lowest suspend mode available 404 * @cpu_good_time: CPU power good time (in microseconds) 405 * @cpu_off_time: CPU power off time (in microsecends) 406 * @core_osc_time: core power good OSC time (in microseconds) 407 * @core_pmu_time: core power good PMU time (in microseconds) 408 * @core_off_time: core power off time (in microseconds) 409 * @corereq_high: core power request is active-high 410 * @sysclkreq_high: system clock request is active-high 411 * @combined_req: combined power request for CPU & core 412 * @cpu_pwr_good_en: CPU power good signal is enabled 413 * @lp0_vec_phys: physical base address of the LP0 warm boot code 414 * @lp0_vec_size: size of the LP0 warm boot code 415 * @powergates_available: Bitmap of available power gates 416 * @powergates_lock: mutex for power gate register access 417 * @pctl_dev: pin controller exposed by the PMC 418 * @domain: IRQ domain provided by the PMC 419 * @irq: chip implementation for the IRQ domain 420 * @clk_nb: pclk clock changes handler 421 * @core_domain_state_synced: flag marking the core domain's state as synced 422 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes 423 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not 424 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask 425 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in 426 * cntrl register associated with each wake during system suspend. 427 * @syscore: syscore suspend/resume callbacks 428 */ 429struct tegra_pmc { 430 struct device *dev; 431 void __iomem *base; 432 void __iomem *wake; 433 void __iomem *aotag; 434 void __iomem *scratch; 435 struct clk *clk; 436 437 const struct tegra_pmc_soc *soc; 438 bool tz_only; 439 440 unsigned long rate; 441 442 enum tegra_suspend_mode suspend_mode; 443 u32 cpu_good_time; 444 u32 cpu_off_time; 445 u32 core_osc_time; 446 u32 core_pmu_time; 447 u32 core_off_time; 448 bool corereq_high; 449 bool sysclkreq_high; 450 bool combined_req; 451 bool cpu_pwr_good_en; 452 u32 lp0_vec_phys; 453 u32 lp0_vec_size; 454 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 455 456 struct mutex powergates_lock; 457 458 struct pinctrl_dev *pctl_dev; 459 460 struct irq_domain *domain; 461 struct irq_chip irq; 462 463 struct notifier_block clk_nb; 464 465 bool core_domain_state_synced; 466 467 unsigned long *wake_type_level_map; 468 unsigned long *wake_type_dual_edge_map; 469 unsigned long *wake_sw_status_map; 470 unsigned long *wake_cntrl_level_map; 471 struct syscore syscore; 472 473 /* Pending wake IRQ processing */ 474 struct irq_work wake_work; 475 u32 *wake_status; 476}; 477 478static struct tegra_pmc *pmc = &(struct tegra_pmc) { 479 .base = NULL, 480 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 481}; 482 483static inline struct tegra_powergate * 484to_powergate(struct generic_pm_domain *domain) 485{ 486 return container_of(domain, struct tegra_powergate, genpd); 487} 488 489static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 490{ 491 struct arm_smccc_res res; 492 493 if (pmc->tz_only) { 494 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 495 0, 0, 0, &res); 496 if (res.a0) { 497 if (pmc->dev) 498 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 499 __func__, res.a0); 500 else 501 pr_warn("%s(): SMC failed: %lu\n", __func__, 502 res.a0); 503 } 504 505 return res.a1; 506 } 507 508 return readl(pmc->base + offset); 509} 510 511static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 512 unsigned long offset) 513{ 514 struct arm_smccc_res res; 515 516 if (pmc->tz_only) { 517 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 518 value, 0, 0, 0, 0, &res); 519 if (res.a0) { 520 if (pmc->dev) 521 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 522 __func__, res.a0); 523 else 524 pr_warn("%s(): SMC failed: %lu\n", __func__, 525 res.a0); 526 } 527 } else { 528 writel(value, pmc->base + offset); 529 } 530} 531 532static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 533{ 534 if (pmc->tz_only) 535 return tegra_pmc_readl(pmc, offset); 536 537 return readl(pmc->scratch + offset); 538} 539 540static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 541 unsigned long offset) 542{ 543 if (pmc->tz_only) 544 tegra_pmc_writel(pmc, value, offset); 545 else 546 writel(value, pmc->scratch + offset); 547} 548 549/* 550 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 551 * This currently doesn't work because readx_poll_timeout() can only operate 552 * on functions that take a single argument. 553 */ 554static inline bool tegra_powergate_state(int id) 555{ 556 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 557 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 558 else 559 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 560} 561 562static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 563{ 564 return (pmc->soc && pmc->soc->powergates[id]); 565} 566 567static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 568{ 569 return test_bit(id, pmc->powergates_available); 570} 571 572static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 573{ 574 unsigned int i; 575 576 if (!pmc || !pmc->soc || !name) 577 return -EINVAL; 578 579 for (i = 0; i < pmc->soc->num_powergates; i++) { 580 if (!tegra_powergate_is_valid(pmc, i)) 581 continue; 582 583 if (!strcmp(name, pmc->soc->powergates[i])) 584 return i; 585 } 586 587 return -ENODEV; 588} 589 590static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 591 bool new_state) 592{ 593 unsigned int retries = 100; 594 bool status; 595 int ret; 596 597 /* 598 * As per TRM documentation, the toggle command will be dropped by PMC 599 * if there is contention with a HW-initiated toggling (i.e. CPU core 600 * power-gated), the command should be retried in that case. 601 */ 602 do { 603 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 604 605 /* wait for PMC to execute the command */ 606 ret = readx_poll_timeout(tegra_powergate_state, id, status, 607 status == new_state, 1, 10); 608 } while (ret == -ETIMEDOUT && retries--); 609 610 return ret; 611} 612 613static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 614{ 615 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 616} 617 618static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 619 bool new_state) 620{ 621 bool status; 622 int err; 623 624 /* wait while PMC power gating is contended */ 625 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 626 status == true, 1, 100); 627 if (err) 628 return err; 629 630 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 631 632 /* wait for PMC to accept the command */ 633 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 634 status == true, 1, 100); 635 if (err) 636 return err; 637 638 /* wait for PMC to execute the command */ 639 err = readx_poll_timeout(tegra_powergate_state, id, status, 640 status == new_state, 10, 100000); 641 if (err) 642 return err; 643 644 return 0; 645} 646 647/** 648 * tegra_powergate_set() - set the state of a partition 649 * @pmc: power management controller 650 * @id: partition ID 651 * @new_state: new state of the partition 652 */ 653static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 654 bool new_state) 655{ 656 int err; 657 658 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 659 return -EINVAL; 660 661 mutex_lock(&pmc->powergates_lock); 662 663 if (tegra_powergate_state(id) == new_state) { 664 mutex_unlock(&pmc->powergates_lock); 665 return 0; 666 } 667 668 err = pmc->soc->powergate_set(pmc, id, new_state); 669 670 mutex_unlock(&pmc->powergates_lock); 671 672 return err; 673} 674 675static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 676 unsigned int id) 677{ 678 u32 mask; 679 680 mutex_lock(&pmc->powergates_lock); 681 682 /* 683 * On Tegra124 and later, the clamps for the GPU are controlled by a 684 * separate register (with different semantics). 685 */ 686 if (id == TEGRA_POWERGATE_3D) { 687 if (pmc->soc->has_gpu_clamps) { 688 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 689 goto out; 690 } 691 } 692 693 /* 694 * Tegra 2 has a bug where PCIE and VDE clamping masks are 695 * swapped relatively to the partition ids 696 */ 697 if (id == TEGRA_POWERGATE_VDEC) 698 mask = (1 << TEGRA_POWERGATE_PCIE); 699 else if (id == TEGRA_POWERGATE_PCIE) 700 mask = (1 << TEGRA_POWERGATE_VDEC); 701 else 702 mask = (1 << id); 703 704 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 705 706out: 707 mutex_unlock(&pmc->powergates_lock); 708 709 return 0; 710} 711 712static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 713{ 714 unsigned long safe_rate = 100 * 1000 * 1000; 715 unsigned int i; 716 int err; 717 718 for (i = 0; i < pg->num_clks; i++) { 719 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 720 721 if (!pg->clk_rates[i]) { 722 err = -EINVAL; 723 goto out; 724 } 725 726 if (pg->clk_rates[i] <= safe_rate) 727 continue; 728 729 /* 730 * We don't know whether voltage state is okay for the 731 * current clock rate, hence it's better to temporally 732 * switch clock to a safe rate which is suitable for 733 * all voltages, before enabling the clock. 734 */ 735 err = clk_set_rate(pg->clks[i], safe_rate); 736 if (err) 737 goto out; 738 } 739 740 return 0; 741 742out: 743 while (i--) 744 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 745 746 return err; 747} 748 749static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 750{ 751 unsigned int i; 752 int err; 753 754 for (i = 0; i < pg->num_clks; i++) { 755 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 756 if (err) 757 return err; 758 } 759 760 return 0; 761} 762 763static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 764{ 765 unsigned int i; 766 767 for (i = 0; i < pg->num_clks; i++) 768 clk_disable_unprepare(pg->clks[i]); 769} 770 771static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 772{ 773 unsigned int i; 774 int err; 775 776 for (i = 0; i < pg->num_clks; i++) { 777 err = clk_prepare_enable(pg->clks[i]); 778 if (err) 779 goto out; 780 } 781 782 return 0; 783 784out: 785 while (i--) 786 clk_disable_unprepare(pg->clks[i]); 787 788 return err; 789} 790 791static int tegra_powergate_power_up(struct tegra_powergate *pg, 792 bool disable_clocks) 793{ 794 int err; 795 796 err = reset_control_assert(pg->reset); 797 if (err) 798 return err; 799 800 usleep_range(10, 20); 801 802 err = tegra_powergate_set(pg->pmc, pg->id, true); 803 if (err < 0) 804 return err; 805 806 usleep_range(10, 20); 807 808 err = tegra_powergate_prepare_clocks(pg); 809 if (err) 810 goto powergate_off; 811 812 err = tegra_powergate_enable_clocks(pg); 813 if (err) 814 goto unprepare_clks; 815 816 usleep_range(10, 20); 817 818 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 819 if (err) 820 goto disable_clks; 821 822 usleep_range(10, 20); 823 824 err = reset_control_deassert(pg->reset); 825 if (err) 826 goto disable_clks; 827 828 usleep_range(10, 20); 829 830 if (pg->pmc->soc->needs_mbist_war) 831 err = tegra210_clk_handle_mbist_war(pg->id); 832 if (err) 833 goto disable_clks; 834 835 if (disable_clocks) 836 tegra_powergate_disable_clocks(pg); 837 838 err = tegra_powergate_unprepare_clocks(pg); 839 if (err) 840 return err; 841 842 return 0; 843 844disable_clks: 845 tegra_powergate_disable_clocks(pg); 846 usleep_range(10, 20); 847 848unprepare_clks: 849 tegra_powergate_unprepare_clocks(pg); 850 851powergate_off: 852 tegra_powergate_set(pg->pmc, pg->id, false); 853 854 return err; 855} 856 857static int tegra_powergate_power_down(struct tegra_powergate *pg) 858{ 859 int err; 860 861 err = tegra_powergate_prepare_clocks(pg); 862 if (err) 863 return err; 864 865 err = tegra_powergate_enable_clocks(pg); 866 if (err) 867 goto unprepare_clks; 868 869 usleep_range(10, 20); 870 871 err = reset_control_assert(pg->reset); 872 if (err) 873 goto disable_clks; 874 875 usleep_range(10, 20); 876 877 tegra_powergate_disable_clocks(pg); 878 879 usleep_range(10, 20); 880 881 err = tegra_powergate_set(pg->pmc, pg->id, false); 882 if (err) 883 goto assert_resets; 884 885 err = tegra_powergate_unprepare_clocks(pg); 886 if (err) 887 return err; 888 889 return 0; 890 891assert_resets: 892 tegra_powergate_enable_clocks(pg); 893 usleep_range(10, 20); 894 reset_control_deassert(pg->reset); 895 usleep_range(10, 20); 896 897disable_clks: 898 tegra_powergate_disable_clocks(pg); 899 900unprepare_clks: 901 tegra_powergate_unprepare_clocks(pg); 902 903 return err; 904} 905 906static int tegra_genpd_power_on(struct generic_pm_domain *domain) 907{ 908 struct tegra_powergate *pg = to_powergate(domain); 909 struct device *dev = pg->pmc->dev; 910 int err; 911 912 err = tegra_powergate_power_up(pg, true); 913 if (err) { 914 dev_err(dev, "failed to turn on PM domain %s: %d\n", 915 pg->genpd.name, err); 916 goto out; 917 } 918 919 reset_control_release(pg->reset); 920 921out: 922 return err; 923} 924 925static int tegra_genpd_power_off(struct generic_pm_domain *domain) 926{ 927 struct tegra_powergate *pg = to_powergate(domain); 928 struct device *dev = pg->pmc->dev; 929 int err; 930 931 err = reset_control_acquire(pg->reset); 932 if (err < 0) { 933 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 934 pg->genpd.name, err); 935 return err; 936 } 937 938 err = tegra_powergate_power_down(pg); 939 if (err) { 940 dev_err(dev, "failed to turn off PM domain %s: %d\n", 941 pg->genpd.name, err); 942 reset_control_release(pg->reset); 943 } 944 945 return err; 946} 947 948/** 949 * tegra_powergate_power_on() - power on partition 950 * @id: partition ID 951 */ 952int tegra_powergate_power_on(unsigned int id) 953{ 954 if (!tegra_powergate_is_available(pmc, id)) 955 return -EINVAL; 956 957 return tegra_powergate_set(pmc, id, true); 958} 959EXPORT_SYMBOL(tegra_powergate_power_on); 960 961/** 962 * tegra_powergate_power_off() - power off partition 963 * @id: partition ID 964 */ 965int tegra_powergate_power_off(unsigned int id) 966{ 967 if (!tegra_powergate_is_available(pmc, id)) 968 return -EINVAL; 969 970 return tegra_powergate_set(pmc, id, false); 971} 972EXPORT_SYMBOL(tegra_powergate_power_off); 973 974/** 975 * tegra_powergate_is_powered() - check if partition is powered 976 * @pmc: power management controller 977 * @id: partition ID 978 */ 979static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 980{ 981 if (!tegra_powergate_is_valid(pmc, id)) 982 return -EINVAL; 983 984 return tegra_powergate_state(id); 985} 986 987/** 988 * tegra_powergate_remove_clamping() - remove power clamps for partition 989 * @id: partition ID 990 */ 991int tegra_powergate_remove_clamping(unsigned int id) 992{ 993 if (!tegra_powergate_is_available(pmc, id)) 994 return -EINVAL; 995 996 return __tegra_powergate_remove_clamping(pmc, id); 997} 998EXPORT_SYMBOL(tegra_powergate_remove_clamping); 999 1000/** 1001 * tegra_powergate_sequence_power_up() - power up partition 1002 * @id: partition ID 1003 * @clk: clock for partition 1004 * @rst: reset for partition 1005 * 1006 * Must be called with clk disabled, and returns with clk enabled. 1007 */ 1008int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 1009 struct reset_control *rst) 1010{ 1011 struct tegra_powergate *pg; 1012 int err; 1013 1014 if (!tegra_powergate_is_available(pmc, id)) 1015 return -EINVAL; 1016 1017 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1018 if (!pg) 1019 return -ENOMEM; 1020 1021 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 1022 if (!pg->clk_rates) { 1023 kfree(pg->clks); 1024 return -ENOMEM; 1025 } 1026 1027 pg->id = id; 1028 pg->clks = &clk; 1029 pg->num_clks = 1; 1030 pg->reset = rst; 1031 pg->pmc = pmc; 1032 1033 err = tegra_powergate_power_up(pg, false); 1034 if (err) 1035 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1036 err); 1037 1038 kfree(pg->clk_rates); 1039 kfree(pg); 1040 1041 return err; 1042} 1043EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1044 1045/** 1046 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1047 * @pmc: power management controller 1048 * @cpuid: CPU partition ID 1049 * 1050 * Returns the partition ID corresponding to the CPU partition ID or a 1051 * negative error code on failure. 1052 */ 1053static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1054 unsigned int cpuid) 1055{ 1056 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1057 return pmc->soc->cpu_powergates[cpuid]; 1058 1059 return -EINVAL; 1060} 1061 1062/** 1063 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1064 * @cpuid: CPU partition ID 1065 */ 1066bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1067{ 1068 int id; 1069 1070 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1071 if (id < 0) 1072 return false; 1073 1074 return tegra_powergate_is_powered(pmc, id); 1075} 1076 1077/** 1078 * tegra_pmc_cpu_power_on() - power on CPU partition 1079 * @cpuid: CPU partition ID 1080 */ 1081int tegra_pmc_cpu_power_on(unsigned int cpuid) 1082{ 1083 int id; 1084 1085 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1086 if (id < 0) 1087 return id; 1088 1089 return tegra_powergate_set(pmc, id, true); 1090} 1091 1092/** 1093 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1094 * @cpuid: CPU partition ID 1095 */ 1096int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1097{ 1098 int id; 1099 1100 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1101 if (id < 0) 1102 return id; 1103 1104 return tegra_powergate_remove_clamping(id); 1105} 1106 1107static void tegra_pmc_program_reboot_reason(const char *cmd) 1108{ 1109 u32 value; 1110 1111 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1112 value &= ~PMC_SCRATCH0_MODE_MASK; 1113 1114 if (cmd) { 1115 if (strcmp(cmd, "recovery") == 0) 1116 value |= PMC_SCRATCH0_MODE_RECOVERY; 1117 1118 if (strcmp(cmd, "bootloader") == 0) 1119 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1120 1121 if (strcmp(cmd, "forced-recovery") == 0) 1122 value |= PMC_SCRATCH0_MODE_RCM; 1123 } 1124 1125 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1126} 1127 1128static int tegra_pmc_reboot_notify(struct notifier_block *this, 1129 unsigned long action, void *data) 1130{ 1131 if (action == SYS_RESTART) 1132 tegra_pmc_program_reboot_reason(data); 1133 1134 return NOTIFY_DONE; 1135} 1136 1137static struct notifier_block tegra_pmc_reboot_notifier = { 1138 .notifier_call = tegra_pmc_reboot_notify, 1139}; 1140 1141static void tegra_pmc_restart(void) 1142{ 1143 u32 value; 1144 1145 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1146 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1147 value |= PMC_CNTRL_MAIN_RST; 1148 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1149} 1150 1151static int tegra_pmc_restart_handler(struct sys_off_data *data) 1152{ 1153 tegra_pmc_restart(); 1154 1155 return NOTIFY_DONE; 1156} 1157 1158static int tegra_pmc_power_off_handler(struct sys_off_data *data) 1159{ 1160 /* 1161 * Reboot Nexus 7 into special bootloader mode if USB cable is 1162 * connected in order to display battery status and power off. 1163 */ 1164 if (of_machine_is_compatible("asus,grouper") && 1165 power_supply_is_system_supplied()) { 1166 const u32 go_to_charger_mode = 0xa5a55a5a; 1167 1168 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1169 tegra_pmc_restart(); 1170 } 1171 1172 return NOTIFY_DONE; 1173} 1174 1175static int powergate_show(struct seq_file *s, void *data) 1176{ 1177 unsigned int i; 1178 int status; 1179 1180 seq_printf(s, " powergate powered\n"); 1181 seq_printf(s, "------------------\n"); 1182 1183 for (i = 0; i < pmc->soc->num_powergates; i++) { 1184 status = tegra_powergate_is_powered(pmc, i); 1185 if (status < 0) 1186 continue; 1187 1188 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1189 str_yes_no(status)); 1190 } 1191 1192 return 0; 1193} 1194 1195DEFINE_SHOW_ATTRIBUTE(powergate); 1196 1197static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1198 struct device_node *np) 1199{ 1200 struct clk *clk; 1201 unsigned int i, count; 1202 int err; 1203 1204 count = of_clk_get_parent_count(np); 1205 if (count == 0) 1206 return -ENODEV; 1207 1208 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1209 if (!pg->clks) 1210 return -ENOMEM; 1211 1212 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1213 if (!pg->clk_rates) { 1214 kfree(pg->clks); 1215 return -ENOMEM; 1216 } 1217 1218 for (i = 0; i < count; i++) { 1219 pg->clks[i] = of_clk_get(np, i); 1220 if (IS_ERR(pg->clks[i])) { 1221 err = PTR_ERR(pg->clks[i]); 1222 goto err; 1223 } 1224 } 1225 1226 pg->num_clks = count; 1227 1228 return 0; 1229 1230err: 1231 while (i--) 1232 clk_put(pg->clks[i]); 1233 1234 kfree(pg->clk_rates); 1235 kfree(pg->clks); 1236 1237 return err; 1238} 1239 1240static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1241 struct device_node *np) 1242{ 1243 struct device *dev = pg->pmc->dev; 1244 int err; 1245 1246 pg->reset = of_reset_control_array_get_exclusive_released(np); 1247 if (IS_ERR(pg->reset)) { 1248 err = PTR_ERR(pg->reset); 1249 dev_err(dev, "failed to get device resets: %d\n", err); 1250 return err; 1251 } 1252 1253 err = reset_control_acquire(pg->reset); 1254 if (err < 0) { 1255 pr_err("failed to acquire resets: %d\n", err); 1256 reset_control_put(pg->reset); 1257 } 1258 1259 return err; 1260} 1261 1262static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1263{ 1264 struct device *dev = pmc->dev; 1265 struct tegra_powergate *pg; 1266 int id, err = 0; 1267 bool off; 1268 1269 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1270 if (!pg) 1271 return -ENOMEM; 1272 1273 id = tegra_powergate_lookup(pmc, np->name); 1274 if (id < 0) { 1275 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1276 err = -ENODEV; 1277 goto free_mem; 1278 } 1279 1280 /* 1281 * Clear the bit for this powergate so it cannot be managed 1282 * directly via the legacy APIs for controlling powergates. 1283 */ 1284 clear_bit(id, pmc->powergates_available); 1285 1286 pg->id = id; 1287 pg->genpd.name = np->name; 1288 pg->genpd.flags = GENPD_FLAG_NO_SYNC_STATE; 1289 pg->genpd.power_off = tegra_genpd_power_off; 1290 pg->genpd.power_on = tegra_genpd_power_on; 1291 pg->pmc = pmc; 1292 1293 off = !tegra_powergate_is_powered(pmc, pg->id); 1294 1295 err = tegra_powergate_of_get_clks(pg, np); 1296 if (err < 0) { 1297 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1298 goto set_available; 1299 } 1300 1301 err = tegra_powergate_of_get_resets(pg, np); 1302 if (err < 0) { 1303 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1304 goto remove_clks; 1305 } 1306 1307 /* 1308 * If the power-domain is off, then ensure the resets are asserted. 1309 * If the power-domain is on, then power down to ensure that when is 1310 * it turned on the power-domain, clocks and resets are all in the 1311 * expected state. 1312 */ 1313 if (off) { 1314 err = reset_control_assert(pg->reset); 1315 if (err) { 1316 pr_err("failed to assert resets: %d\n", err); 1317 goto remove_resets; 1318 } 1319 } else { 1320 err = tegra_powergate_power_down(pg); 1321 if (err) { 1322 dev_err(dev, "failed to turn off PM domain %s: %d\n", 1323 pg->genpd.name, err); 1324 goto remove_resets; 1325 } 1326 } 1327 1328 /* 1329 * If PM_GENERIC_DOMAINS is not enabled, power-on 1330 * the domain and skip the genpd registration. 1331 */ 1332 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1333 WARN_ON(tegra_powergate_power_up(pg, true)); 1334 goto remove_resets; 1335 } 1336 1337 err = pm_genpd_init(&pg->genpd, NULL, true); 1338 if (err < 0) { 1339 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1340 err); 1341 goto remove_resets; 1342 } 1343 1344 err = of_genpd_add_provider_simple(np, &pg->genpd); 1345 if (err < 0) { 1346 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1347 np, err); 1348 goto remove_genpd; 1349 } 1350 1351 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1352 1353 return 0; 1354 1355remove_genpd: 1356 pm_genpd_remove(&pg->genpd); 1357 1358remove_resets: 1359 reset_control_put(pg->reset); 1360 1361remove_clks: 1362 while (pg->num_clks--) 1363 clk_put(pg->clks[pg->num_clks]); 1364 1365 kfree(pg->clks); 1366 1367set_available: 1368 set_bit(id, pmc->powergates_available); 1369 1370free_mem: 1371 kfree(pg); 1372 1373 return err; 1374} 1375 1376bool tegra_pmc_core_domain_state_synced(void) 1377{ 1378 return pmc->core_domain_state_synced; 1379} 1380 1381static int 1382tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1383 unsigned int level) 1384{ 1385 struct dev_pm_opp *opp; 1386 int err; 1387 1388 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1389 if (IS_ERR(opp)) { 1390 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1391 level, opp); 1392 return PTR_ERR(opp); 1393 } 1394 1395 mutex_lock(&pmc->powergates_lock); 1396 err = dev_pm_opp_set_opp(pmc->dev, opp); 1397 mutex_unlock(&pmc->powergates_lock); 1398 1399 dev_pm_opp_put(opp); 1400 1401 if (err) { 1402 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1403 level, err); 1404 return err; 1405 } 1406 1407 return 0; 1408} 1409 1410static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1411{ 1412 struct generic_pm_domain *genpd; 1413 const char *rname[] = { "core", NULL}; 1414 int err; 1415 1416 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); 1417 if (!genpd) 1418 return -ENOMEM; 1419 1420 genpd->name = "core"; 1421 genpd->flags = GENPD_FLAG_NO_SYNC_STATE; 1422 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; 1423 1424 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1425 if (err) 1426 return dev_err_probe(pmc->dev, err, 1427 "failed to set core OPP regulator\n"); 1428 1429 err = pm_genpd_init(genpd, NULL, false); 1430 if (err) { 1431 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1432 return err; 1433 } 1434 1435 err = of_genpd_add_provider_simple(np, genpd); 1436 if (err) { 1437 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1438 goto remove_genpd; 1439 } 1440 1441 return 0; 1442 1443remove_genpd: 1444 pm_genpd_remove(genpd); 1445 1446 return err; 1447} 1448 1449static int tegra_powergate_init(struct tegra_pmc *pmc, 1450 struct device_node *parent) 1451{ 1452 struct of_phandle_args child_args, parent_args; 1453 struct device_node *np; 1454 int err = 0; 1455 1456 /* 1457 * Core power domain is the parent of powergate domains, hence it 1458 * should be registered first. 1459 */ 1460 np = of_get_child_by_name(parent, "core-domain"); 1461 if (np) { 1462 err = tegra_pmc_core_pd_add(pmc, np); 1463 of_node_put(np); 1464 if (err) 1465 return err; 1466 } 1467 1468 np = of_get_child_by_name(parent, "powergates"); 1469 if (!np) 1470 return 0; 1471 1472 for_each_child_of_node_scoped(np, child) { 1473 err = tegra_powergate_add(pmc, child); 1474 if (err < 0) 1475 break; 1476 1477 if (of_parse_phandle_with_args(child, "power-domains", 1478 "#power-domain-cells", 1479 0, &parent_args)) 1480 continue; 1481 1482 child_args.np = child; 1483 child_args.args_count = 0; 1484 1485 err = of_genpd_add_subdomain(&parent_args, &child_args); 1486 of_node_put(parent_args.np); 1487 if (err) 1488 break; 1489 } 1490 1491 of_node_put(np); 1492 1493 return err; 1494} 1495 1496static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1497{ 1498 struct tegra_powergate *pg = to_powergate(genpd); 1499 1500 reset_control_put(pg->reset); 1501 1502 while (pg->num_clks--) 1503 clk_put(pg->clks[pg->num_clks]); 1504 1505 kfree(pg->clks); 1506 1507 set_bit(pg->id, pmc->powergates_available); 1508 1509 kfree(pg); 1510} 1511 1512static void tegra_powergate_remove_all(struct device_node *parent) 1513{ 1514 struct generic_pm_domain *genpd; 1515 struct device_node *np, *child; 1516 1517 np = of_get_child_by_name(parent, "powergates"); 1518 if (!np) 1519 return; 1520 1521 for_each_child_of_node(np, child) { 1522 of_genpd_del_provider(child); 1523 1524 genpd = of_genpd_remove_last(child); 1525 if (IS_ERR(genpd)) 1526 continue; 1527 1528 tegra_powergate_remove(genpd); 1529 } 1530 1531 of_node_put(np); 1532 1533 np = of_get_child_by_name(parent, "core-domain"); 1534 if (np) { 1535 of_genpd_del_provider(np); 1536 of_genpd_remove_last(np); 1537 } 1538} 1539 1540static const struct tegra_io_pad_soc * 1541tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1542{ 1543 unsigned int i; 1544 1545 for (i = 0; i < pmc->soc->num_io_pads; i++) 1546 if (pmc->soc->io_pads[i].id == id) 1547 return &pmc->soc->io_pads[i]; 1548 1549 return NULL; 1550} 1551 1552static int tegra_io_pad_prepare(struct tegra_pmc *pmc, 1553 const struct tegra_io_pad_soc *pad, 1554 unsigned long *request, 1555 unsigned long *status, 1556 u32 *mask) 1557{ 1558 unsigned long rate, value; 1559 1560 if (pad->dpd == UINT_MAX) 1561 return -EINVAL; 1562 1563 *request = pad->request; 1564 *status = pad->status; 1565 *mask = BIT(pad->dpd); 1566 1567 if (pmc->clk) { 1568 rate = pmc->rate; 1569 if (!rate) { 1570 dev_err(pmc->dev, "failed to get clock rate\n"); 1571 return -ENODEV; 1572 } 1573 1574 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1575 1576 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1577 value = DIV_ROUND_UP(1000000000, rate); 1578 value = DIV_ROUND_UP(200, value); 1579 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1580 } 1581 1582 return 0; 1583} 1584 1585static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1586 u32 mask, u32 val, unsigned long timeout) 1587{ 1588 u32 value; 1589 1590 timeout = jiffies + msecs_to_jiffies(timeout); 1591 1592 while (time_after(timeout, jiffies)) { 1593 value = tegra_pmc_readl(pmc, offset); 1594 if ((value & mask) == val) 1595 return 0; 1596 1597 usleep_range(250, 1000); 1598 } 1599 1600 return -ETIMEDOUT; 1601} 1602 1603static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1604{ 1605 if (pmc->clk) 1606 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1607} 1608 1609/** 1610 * tegra_io_pad_power_enable() - enable power to I/O pad 1611 * @id: Tegra I/O pad ID for which to enable power 1612 * 1613 * Returns: 0 on success or a negative error code on failure. 1614 */ 1615int tegra_io_pad_power_enable(enum tegra_io_pad id) 1616{ 1617 const struct tegra_io_pad_soc *pad; 1618 unsigned long request, status; 1619 u32 mask; 1620 int err; 1621 1622 pad = tegra_io_pad_find(pmc, id); 1623 if (!pad) { 1624 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1625 return -ENOENT; 1626 } 1627 1628 mutex_lock(&pmc->powergates_lock); 1629 1630 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1631 if (err < 0) { 1632 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1633 goto unlock; 1634 } 1635 1636 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1637 1638 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1639 if (err < 0) { 1640 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1641 goto unlock; 1642 } 1643 1644 tegra_io_pad_unprepare(pmc); 1645 1646unlock: 1647 mutex_unlock(&pmc->powergates_lock); 1648 return err; 1649} 1650EXPORT_SYMBOL(tegra_io_pad_power_enable); 1651 1652/** 1653 * tegra_io_pad_power_disable() - disable power to I/O pad 1654 * @id: Tegra I/O pad ID for which to disable power 1655 * 1656 * Returns: 0 on success or a negative error code on failure. 1657 */ 1658int tegra_io_pad_power_disable(enum tegra_io_pad id) 1659{ 1660 const struct tegra_io_pad_soc *pad; 1661 unsigned long request, status; 1662 u32 mask; 1663 int err; 1664 1665 pad = tegra_io_pad_find(pmc, id); 1666 if (!pad) { 1667 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1668 return -ENOENT; 1669 } 1670 1671 mutex_lock(&pmc->powergates_lock); 1672 1673 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask); 1674 if (err < 0) { 1675 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1676 goto unlock; 1677 } 1678 1679 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1680 1681 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1682 if (err < 0) { 1683 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1684 goto unlock; 1685 } 1686 1687 tegra_io_pad_unprepare(pmc); 1688 1689unlock: 1690 mutex_unlock(&pmc->powergates_lock); 1691 return err; 1692} 1693EXPORT_SYMBOL(tegra_io_pad_power_disable); 1694 1695static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1696{ 1697 const struct tegra_io_pad_soc *pad; 1698 unsigned long status; 1699 u32 mask, value; 1700 1701 pad = tegra_io_pad_find(pmc, id); 1702 if (!pad) { 1703 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1704 return -ENOENT; 1705 } 1706 1707 if (pad->dpd == UINT_MAX) 1708 return -EINVAL; 1709 1710 status = pad->status; 1711 mask = BIT(pad->dpd); 1712 1713 value = tegra_pmc_readl(pmc, status); 1714 1715 return !(value & mask); 1716} 1717 1718static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1719 int voltage) 1720{ 1721 const struct tegra_io_pad_soc *pad; 1722 u32 value; 1723 1724 pad = tegra_io_pad_find(pmc, id); 1725 if (!pad) 1726 return -ENOENT; 1727 1728 if (pad->voltage == UINT_MAX) 1729 return -ENOTSUPP; 1730 1731 mutex_lock(&pmc->powergates_lock); 1732 1733 if (pmc->soc->has_impl_33v_pwr) { 1734 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1735 1736 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1737 value &= ~BIT(pad->voltage); 1738 else 1739 value |= BIT(pad->voltage); 1740 1741 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1742 } else { 1743 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1744 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1745 value |= BIT(pad->voltage); 1746 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1747 1748 /* update I/O voltage */ 1749 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1750 1751 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1752 value &= ~BIT(pad->voltage); 1753 else 1754 value |= BIT(pad->voltage); 1755 1756 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1757 } 1758 1759 mutex_unlock(&pmc->powergates_lock); 1760 1761 usleep_range(100, 250); 1762 1763 return 0; 1764} 1765 1766static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1767{ 1768 const struct tegra_io_pad_soc *pad; 1769 u32 value; 1770 1771 pad = tegra_io_pad_find(pmc, id); 1772 if (!pad) 1773 return -ENOENT; 1774 1775 if (pad->voltage == UINT_MAX) 1776 return -ENOTSUPP; 1777 1778 if (pmc->soc->has_impl_33v_pwr) 1779 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1780 else 1781 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1782 1783 if ((value & BIT(pad->voltage)) == 0) 1784 return TEGRA_IO_PAD_VOLTAGE_1V8; 1785 1786 return TEGRA_IO_PAD_VOLTAGE_3V3; 1787} 1788 1789#ifdef CONFIG_PM_SLEEP 1790enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1791{ 1792 return pmc->suspend_mode; 1793} 1794 1795void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1796{ 1797 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1798 return; 1799 1800 pmc->suspend_mode = mode; 1801} 1802 1803void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1804{ 1805 unsigned long long rate = 0; 1806 u64 ticks; 1807 u32 value; 1808 1809 switch (mode) { 1810 case TEGRA_SUSPEND_LP1: 1811 rate = 32768; 1812 break; 1813 1814 case TEGRA_SUSPEND_LP2: 1815 rate = pmc->rate; 1816 break; 1817 1818 default: 1819 break; 1820 } 1821 1822 if (WARN_ON_ONCE(rate == 0)) 1823 rate = 100000000; 1824 1825 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1826 do_div(ticks, USEC_PER_SEC); 1827 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1828 1829 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1830 do_div(ticks, USEC_PER_SEC); 1831 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1832 1833 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1834 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1835 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1836 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1837} 1838#endif 1839 1840static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1841{ 1842 u32 value, values[2]; 1843 1844 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1845 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1846 } else { 1847 switch (value) { 1848 case 0: 1849 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1850 break; 1851 1852 case 1: 1853 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1854 break; 1855 1856 case 2: 1857 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1858 break; 1859 1860 default: 1861 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1862 break; 1863 } 1864 } 1865 1866 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1867 1868 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1869 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1870 1871 pmc->cpu_good_time = value; 1872 1873 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1874 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1875 1876 pmc->cpu_off_time = value; 1877 1878 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1879 values, ARRAY_SIZE(values))) 1880 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1881 1882 pmc->core_osc_time = values[0]; 1883 pmc->core_pmu_time = values[1]; 1884 1885 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1886 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1887 1888 pmc->core_off_time = value; 1889 1890 pmc->corereq_high = of_property_read_bool(np, 1891 "nvidia,core-power-req-active-high"); 1892 1893 pmc->sysclkreq_high = of_property_read_bool(np, 1894 "nvidia,sys-clock-req-active-high"); 1895 1896 pmc->combined_req = of_property_read_bool(np, 1897 "nvidia,combined-power-req"); 1898 1899 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1900 "nvidia,cpu-pwr-good-en"); 1901 1902 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1903 ARRAY_SIZE(values))) 1904 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1905 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1906 1907 pmc->lp0_vec_phys = values[0]; 1908 pmc->lp0_vec_size = values[1]; 1909 1910 return 0; 1911} 1912 1913/* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */ 1914static void tegra186_pmc_wake_handler(struct irq_work *work) 1915{ 1916 struct tegra_pmc *pmc = container_of(work, struct tegra_pmc, wake_work); 1917 unsigned int i, wake; 1918 1919 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 1920 unsigned long status = pmc->wake_status[i]; 1921 1922 for_each_set_bit(wake, &status, 32) { 1923 irq_hw_number_t hwirq = wake + (i * 32); 1924 struct irq_desc *desc; 1925 unsigned int irq; 1926 1927 irq = irq_find_mapping(pmc->domain, hwirq); 1928 if (!irq) { 1929 dev_warn(pmc->dev, 1930 "No IRQ found for WAKE#%lu!\n", 1931 hwirq); 1932 continue; 1933 } 1934 1935 dev_dbg(pmc->dev, 1936 "Resume caused by WAKE#%lu mapped to IRQ#%u\n", 1937 hwirq, irq); 1938 1939 desc = irq_to_desc(irq); 1940 if (!desc) { 1941 dev_warn(pmc->dev, 1942 "No descriptor found for IRQ#%u\n", 1943 irq); 1944 continue; 1945 } 1946 1947 if (!desc->action || !desc->action->name) 1948 continue; 1949 1950 generic_handle_irq(irq); 1951 } 1952 1953 pmc->wake_status[i] = 0; 1954 } 1955} 1956 1957static int tegra_pmc_init(struct tegra_pmc *pmc) 1958{ 1959 if (pmc->soc->max_wake_events > 0) { 1960 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1961 if (!pmc->wake_type_level_map) 1962 return -ENOMEM; 1963 1964 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1965 if (!pmc->wake_type_dual_edge_map) 1966 return -ENOMEM; 1967 1968 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1969 if (!pmc->wake_sw_status_map) 1970 return -ENOMEM; 1971 1972 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL); 1973 if (!pmc->wake_cntrl_level_map) 1974 return -ENOMEM; 1975 1976 pmc->wake_status = kcalloc(pmc->soc->max_wake_vectors, sizeof(u32), GFP_KERNEL); 1977 if (!pmc->wake_status) 1978 return -ENOMEM; 1979 1980 /* 1981 * Initialize IRQ work for processing wake IRQs. Must use 1982 * HARD_IRQ variant to run in hard IRQ context on PREEMPT_RT 1983 * because we call generic_handle_irq() which requires hard 1984 * IRQ context. 1985 */ 1986 pmc->wake_work = IRQ_WORK_INIT_HARD(tegra186_pmc_wake_handler); 1987 } 1988 1989 if (pmc->soc->init) 1990 pmc->soc->init(pmc); 1991 1992 return 0; 1993} 1994 1995static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1996{ 1997 static const char disabled[] = "emergency thermal reset disabled"; 1998 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1999 struct device *dev = pmc->dev; 2000 struct device_node *np; 2001 u32 value, checksum; 2002 2003 if (!pmc->soc->has_tsense_reset) 2004 return; 2005 2006 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 2007 if (!np) { 2008 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 2009 return; 2010 } 2011 2012 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 2013 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 2014 goto out; 2015 } 2016 2017 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 2018 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 2019 goto out; 2020 } 2021 2022 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 2023 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 2024 goto out; 2025 } 2026 2027 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 2028 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 2029 goto out; 2030 } 2031 2032 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 2033 pinmux = 0; 2034 2035 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2036 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 2037 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2038 2039 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 2040 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 2041 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 2042 2043 value = PMC_SCRATCH55_RESET_TEGRA; 2044 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 2045 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 2046 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 2047 2048 /* 2049 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 2050 * contain the checksum and are currently zero, so they are not added. 2051 */ 2052 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 2053 + ((value >> 24) & 0xff); 2054 checksum &= 0xff; 2055 checksum = 0x100 - checksum; 2056 2057 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 2058 2059 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 2060 2061 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 2062 value |= PMC_SENSOR_CTRL_ENABLE_RST; 2063 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 2064 2065 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 2066 2067out: 2068 of_node_put(np); 2069} 2070 2071static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2072{ 2073 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2074 2075 return pmc->soc->num_io_pads; 2076} 2077 2078static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2079 unsigned int group) 2080{ 2081 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2082 2083 return pmc->soc->io_pads[group].name; 2084} 2085 2086static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2087 unsigned int group, 2088 const unsigned int **pins, 2089 unsigned int *num_pins) 2090{ 2091 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2092 2093 *pins = &pmc->soc->io_pads[group].id; 2094 *num_pins = 1; 2095 2096 return 0; 2097} 2098 2099static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2100 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2101 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2102 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2103 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2104 .dt_free_map = pinconf_generic_dt_free_map, 2105}; 2106 2107static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2108 unsigned int pin, unsigned long *config) 2109{ 2110 enum pin_config_param param = pinconf_to_config_param(*config); 2111 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2112 const struct tegra_io_pad_soc *pad; 2113 int ret; 2114 u32 arg; 2115 2116 pad = tegra_io_pad_find(pmc, pin); 2117 if (!pad) 2118 return -EINVAL; 2119 2120 switch (param) { 2121 case PIN_CONFIG_POWER_SOURCE: 2122 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2123 if (ret < 0) 2124 return ret; 2125 2126 arg = ret; 2127 break; 2128 2129 case PIN_CONFIG_MODE_LOW_POWER: 2130 ret = tegra_io_pad_is_powered(pmc, pad->id); 2131 if (ret < 0) 2132 return ret; 2133 2134 arg = !ret; 2135 break; 2136 2137 default: 2138 return -EINVAL; 2139 } 2140 2141 *config = pinconf_to_config_packed(param, arg); 2142 2143 return 0; 2144} 2145 2146static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2147 unsigned int pin, unsigned long *configs, 2148 unsigned int num_configs) 2149{ 2150 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2151 const struct tegra_io_pad_soc *pad; 2152 enum pin_config_param param; 2153 unsigned int i; 2154 int err; 2155 u32 arg; 2156 2157 pad = tegra_io_pad_find(pmc, pin); 2158 if (!pad) 2159 return -EINVAL; 2160 2161 for (i = 0; i < num_configs; ++i) { 2162 param = pinconf_to_config_param(configs[i]); 2163 arg = pinconf_to_config_argument(configs[i]); 2164 2165 switch (param) { 2166 case PIN_CONFIG_MODE_LOW_POWER: 2167 if (arg) 2168 err = tegra_io_pad_power_disable(pad->id); 2169 else 2170 err = tegra_io_pad_power_enable(pad->id); 2171 if (err) 2172 return err; 2173 break; 2174 case PIN_CONFIG_POWER_SOURCE: 2175 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2176 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2177 return -EINVAL; 2178 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2179 if (err) 2180 return err; 2181 break; 2182 default: 2183 return -EINVAL; 2184 } 2185 } 2186 2187 return 0; 2188} 2189 2190static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2191 .pin_config_get = tegra_io_pad_pinconf_get, 2192 .pin_config_set = tegra_io_pad_pinconf_set, 2193 .is_generic = true, 2194}; 2195 2196static struct pinctrl_desc tegra_pmc_pctl_desc = { 2197 .pctlops = &tegra_io_pad_pinctrl_ops, 2198 .confops = &tegra_io_pad_pinconf_ops, 2199}; 2200 2201static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2202{ 2203 int err; 2204 2205 if (!pmc->soc->num_pin_descs) 2206 return 0; 2207 2208 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2209 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2210 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2211 2212 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2213 pmc); 2214 if (IS_ERR(pmc->pctl_dev)) { 2215 err = PTR_ERR(pmc->pctl_dev); 2216 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2217 err); 2218 return err; 2219 } 2220 2221 return 0; 2222} 2223 2224static ssize_t reset_reason_show(struct device *dev, 2225 struct device_attribute *attr, char *buf) 2226{ 2227 u32 value; 2228 2229 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2230 value &= pmc->soc->regs->rst_source_mask; 2231 value >>= pmc->soc->regs->rst_source_shift; 2232 2233 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2234 return sprintf(buf, "%s\n", "UNKNOWN"); 2235 2236 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2237} 2238 2239static DEVICE_ATTR_RO(reset_reason); 2240 2241static ssize_t reset_level_show(struct device *dev, 2242 struct device_attribute *attr, char *buf) 2243{ 2244 u32 value; 2245 2246 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2247 value &= pmc->soc->regs->rst_level_mask; 2248 value >>= pmc->soc->regs->rst_level_shift; 2249 2250 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2251 return sprintf(buf, "%s\n", "UNKNOWN"); 2252 2253 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2254} 2255 2256static DEVICE_ATTR_RO(reset_level); 2257 2258static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2259{ 2260 struct device *dev = pmc->dev; 2261 int err = 0; 2262 2263 if (pmc->soc->reset_sources) { 2264 err = device_create_file(dev, &dev_attr_reset_reason); 2265 if (err < 0) 2266 dev_warn(dev, 2267 "failed to create attr \"reset_reason\": %d\n", 2268 err); 2269 } 2270 2271 if (pmc->soc->reset_levels) { 2272 err = device_create_file(dev, &dev_attr_reset_level); 2273 if (err < 0) 2274 dev_warn(dev, 2275 "failed to create attr \"reset_level\": %d\n", 2276 err); 2277 } 2278} 2279 2280static int tegra_pmc_irq_translate(struct irq_domain *domain, 2281 struct irq_fwspec *fwspec, 2282 unsigned long *hwirq, 2283 unsigned int *type) 2284{ 2285 if (WARN_ON(fwspec->param_count < 2)) 2286 return -EINVAL; 2287 2288 *hwirq = fwspec->param[0]; 2289 *type = fwspec->param[1]; 2290 2291 return 0; 2292} 2293 2294static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2295 unsigned int num_irqs, void *data) 2296{ 2297 struct tegra_pmc *pmc = domain->host_data; 2298 const struct tegra_pmc_soc *soc = pmc->soc; 2299 struct irq_fwspec *fwspec = data; 2300 unsigned int i; 2301 int err = 0; 2302 2303 if (WARN_ON(num_irqs > 1)) 2304 return -EINVAL; 2305 2306 for (i = 0; i < soc->num_wake_events; i++) { 2307 const struct tegra_wake_event *event = &soc->wake_events[i]; 2308 2309 /* IRQ and simple wake events */ 2310 if (fwspec->param_count == 2) { 2311 struct irq_fwspec spec; 2312 2313 if (event->id != fwspec->param[0]) 2314 continue; 2315 2316 err = irq_domain_set_hwirq_and_chip(domain, virq, 2317 event->id, 2318 &pmc->irq, pmc); 2319 if (err < 0) 2320 break; 2321 2322 /* simple hierarchies stop at the PMC level */ 2323 if (event->irq == 0) { 2324 err = irq_domain_disconnect_hierarchy(domain->parent, virq); 2325 break; 2326 } 2327 2328 spec.fwnode = &pmc->dev->of_node->fwnode; 2329 spec.param_count = 3; 2330 spec.param[0] = GIC_SPI; 2331 spec.param[1] = event->irq; 2332 spec.param[2] = fwspec->param[1]; 2333 2334 err = irq_domain_alloc_irqs_parent(domain, virq, 2335 num_irqs, &spec); 2336 2337 break; 2338 } 2339 2340 /* GPIO wake events */ 2341 if (fwspec->param_count == 3) { 2342 if (event->gpio.instance != fwspec->param[0] || 2343 event->gpio.pin != fwspec->param[1]) 2344 continue; 2345 2346 err = irq_domain_set_hwirq_and_chip(domain, virq, 2347 event->id, 2348 &pmc->irq, pmc); 2349 2350 /* GPIO hierarchies stop at the PMC level */ 2351 if (!err && domain->parent) 2352 err = irq_domain_disconnect_hierarchy(domain->parent, 2353 virq); 2354 break; 2355 } 2356 } 2357 2358 /* If there is no wake-up event, there is no PMC mapping */ 2359 if (i == soc->num_wake_events) 2360 err = irq_domain_disconnect_hierarchy(domain, virq); 2361 2362 return err; 2363} 2364 2365static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2366 .translate = tegra_pmc_irq_translate, 2367 .alloc = tegra_pmc_irq_alloc, 2368}; 2369 2370static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2371{ 2372 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2373 unsigned int offset, bit; 2374 u32 value; 2375 2376 offset = data->hwirq / 32; 2377 bit = data->hwirq % 32; 2378 2379 /* clear wake status */ 2380 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2381 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2382 2383 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2384 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2385 2386 /* enable PMC wake */ 2387 if (data->hwirq >= 32) 2388 offset = PMC_WAKE2_MASK; 2389 else 2390 offset = PMC_WAKE_MASK; 2391 2392 value = tegra_pmc_readl(pmc, offset); 2393 2394 if (on) 2395 value |= BIT(bit); 2396 else 2397 value &= ~BIT(bit); 2398 2399 tegra_pmc_writel(pmc, value, offset); 2400 2401 return 0; 2402} 2403 2404static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2405{ 2406 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2407 unsigned int offset, bit; 2408 u32 value; 2409 2410 offset = data->hwirq / 32; 2411 bit = data->hwirq % 32; 2412 2413 if (data->hwirq >= 32) 2414 offset = PMC_WAKE2_LEVEL; 2415 else 2416 offset = PMC_WAKE_LEVEL; 2417 2418 value = tegra_pmc_readl(pmc, offset); 2419 2420 switch (type) { 2421 case IRQ_TYPE_EDGE_RISING: 2422 case IRQ_TYPE_LEVEL_HIGH: 2423 value |= BIT(bit); 2424 break; 2425 2426 case IRQ_TYPE_EDGE_FALLING: 2427 case IRQ_TYPE_LEVEL_LOW: 2428 value &= ~BIT(bit); 2429 break; 2430 2431 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2432 value ^= BIT(bit); 2433 break; 2434 2435 default: 2436 return -EINVAL; 2437 } 2438 2439 tegra_pmc_writel(pmc, value, offset); 2440 2441 return 0; 2442} 2443 2444static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) 2445{ 2446 u32 value; 2447 2448 /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ 2449 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2450 value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; 2451 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); 2452 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); 2453} 2454 2455static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2456{ 2457 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2458 unsigned int offset, bit; 2459 u32 value; 2460 2461 offset = data->hwirq / 32; 2462 bit = data->hwirq % 32; 2463 2464 /* clear wake status */ 2465 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2466 2467 /* route wake to tier 2 */ 2468 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2469 2470 if (!on) 2471 value &= ~(1 << bit); 2472 else 2473 value |= 1 << bit; 2474 2475 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2476 2477 /* enable wakeup event */ 2478 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2479 2480 return 0; 2481} 2482 2483static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2484{ 2485 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2486 u32 value; 2487 2488 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2489 2490 switch (type) { 2491 case IRQ_TYPE_EDGE_RISING: 2492 case IRQ_TYPE_LEVEL_HIGH: 2493 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2494 set_bit(data->hwirq, pmc->wake_type_level_map); 2495 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2496 break; 2497 2498 case IRQ_TYPE_EDGE_FALLING: 2499 case IRQ_TYPE_LEVEL_LOW: 2500 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2501 clear_bit(data->hwirq, pmc->wake_type_level_map); 2502 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2503 break; 2504 2505 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2506 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2507 clear_bit(data->hwirq, pmc->wake_type_level_map); 2508 set_bit(data->hwirq, pmc->wake_type_dual_edge_map); 2509 break; 2510 2511 default: 2512 return -EINVAL; 2513 } 2514 2515 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2516 2517 return 0; 2518} 2519 2520static void tegra_irq_mask_parent(struct irq_data *data) 2521{ 2522 if (data->parent_data) 2523 irq_chip_mask_parent(data); 2524} 2525 2526static void tegra_irq_unmask_parent(struct irq_data *data) 2527{ 2528 if (data->parent_data) 2529 irq_chip_unmask_parent(data); 2530} 2531 2532static void tegra_irq_eoi_parent(struct irq_data *data) 2533{ 2534 if (data->parent_data) 2535 irq_chip_eoi_parent(data); 2536} 2537 2538static int tegra_irq_set_affinity_parent(struct irq_data *data, 2539 const struct cpumask *dest, 2540 bool force) 2541{ 2542 if (data->parent_data) 2543 return irq_chip_set_affinity_parent(data, dest, force); 2544 2545 return -EINVAL; 2546} 2547 2548static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2549{ 2550 struct irq_domain *parent = NULL; 2551 struct device_node *np; 2552 2553 np = of_irq_find_parent(pmc->dev->of_node); 2554 if (np) { 2555 parent = irq_find_host(np); 2556 of_node_put(np); 2557 } 2558 2559 if (!parent) 2560 return 0; 2561 2562 pmc->irq.name = dev_name(pmc->dev); 2563 pmc->irq.irq_mask = tegra_irq_mask_parent; 2564 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2565 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2566 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2567 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2568 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2569 2570 pmc->domain = irq_domain_create_hierarchy(parent, 0, 96, dev_fwnode(pmc->dev), 2571 &tegra_pmc_irq_domain_ops, pmc); 2572 if (!pmc->domain) { 2573 dev_err(pmc->dev, "failed to allocate domain\n"); 2574 return -ENOMEM; 2575 } 2576 2577 return 0; 2578} 2579 2580static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2581 unsigned long action, void *ptr) 2582{ 2583 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2584 struct clk_notifier_data *data = ptr; 2585 2586 switch (action) { 2587 case PRE_RATE_CHANGE: 2588 mutex_lock(&pmc->powergates_lock); 2589 break; 2590 2591 case POST_RATE_CHANGE: 2592 pmc->rate = data->new_rate; 2593 fallthrough; 2594 2595 case ABORT_RATE_CHANGE: 2596 mutex_unlock(&pmc->powergates_lock); 2597 break; 2598 2599 default: 2600 WARN_ON_ONCE(1); 2601 return notifier_from_errno(-EINVAL); 2602 } 2603 2604 return NOTIFY_OK; 2605} 2606 2607static void pmc_clk_fence_udelay(u32 offset) 2608{ 2609 tegra_pmc_readl(pmc, offset); 2610 /* pmc clk propagation delay 2 us */ 2611 udelay(2); 2612} 2613 2614static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2615{ 2616 struct pmc_clk *clk = to_pmc_clk(hw); 2617 u32 val; 2618 2619 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2620 val &= PMC_CLK_OUT_MUX_MASK; 2621 2622 return val; 2623} 2624 2625static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2626{ 2627 struct pmc_clk *clk = to_pmc_clk(hw); 2628 u32 val; 2629 2630 val = tegra_pmc_readl(pmc, clk->offs); 2631 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2632 val |= index << clk->mux_shift; 2633 tegra_pmc_writel(pmc, val, clk->offs); 2634 pmc_clk_fence_udelay(clk->offs); 2635 2636 return 0; 2637} 2638 2639static int pmc_clk_is_enabled(struct clk_hw *hw) 2640{ 2641 struct pmc_clk *clk = to_pmc_clk(hw); 2642 u32 val; 2643 2644 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2645 2646 return val ? 1 : 0; 2647} 2648 2649static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2650{ 2651 u32 val; 2652 2653 val = tegra_pmc_readl(pmc, offs); 2654 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2655 tegra_pmc_writel(pmc, val, offs); 2656 pmc_clk_fence_udelay(offs); 2657} 2658 2659static int pmc_clk_enable(struct clk_hw *hw) 2660{ 2661 struct pmc_clk *clk = to_pmc_clk(hw); 2662 2663 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2664 2665 return 0; 2666} 2667 2668static void pmc_clk_disable(struct clk_hw *hw) 2669{ 2670 struct pmc_clk *clk = to_pmc_clk(hw); 2671 2672 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2673} 2674 2675static const struct clk_ops pmc_clk_ops = { 2676 .get_parent = pmc_clk_mux_get_parent, 2677 .set_parent = pmc_clk_mux_set_parent, 2678 .determine_rate = __clk_mux_determine_rate, 2679 .is_enabled = pmc_clk_is_enabled, 2680 .enable = pmc_clk_enable, 2681 .disable = pmc_clk_disable, 2682}; 2683 2684static struct clk * 2685tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2686 const struct pmc_clk_init_data *data, 2687 unsigned long offset) 2688{ 2689 struct clk_init_data init; 2690 struct pmc_clk *pmc_clk; 2691 2692 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2693 if (!pmc_clk) 2694 return ERR_PTR(-ENOMEM); 2695 2696 init.name = data->name; 2697 init.ops = &pmc_clk_ops; 2698 init.parent_names = data->parents; 2699 init.num_parents = data->num_parents; 2700 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2701 CLK_SET_PARENT_GATE; 2702 2703 pmc_clk->hw.init = &init; 2704 pmc_clk->offs = offset; 2705 pmc_clk->mux_shift = data->mux_shift; 2706 pmc_clk->force_en_shift = data->force_en_shift; 2707 2708 return clk_register(NULL, &pmc_clk->hw); 2709} 2710 2711static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2712{ 2713 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2714 2715 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2716} 2717 2718static int pmc_clk_gate_enable(struct clk_hw *hw) 2719{ 2720 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2721 2722 pmc_clk_set_state(gate->offs, gate->shift, 1); 2723 2724 return 0; 2725} 2726 2727static void pmc_clk_gate_disable(struct clk_hw *hw) 2728{ 2729 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2730 2731 pmc_clk_set_state(gate->offs, gate->shift, 0); 2732} 2733 2734static const struct clk_ops pmc_clk_gate_ops = { 2735 .is_enabled = pmc_clk_gate_is_enabled, 2736 .enable = pmc_clk_gate_enable, 2737 .disable = pmc_clk_gate_disable, 2738}; 2739 2740static struct clk * 2741tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2742 const char *parent_name, unsigned long offset, 2743 u32 shift) 2744{ 2745 struct clk_init_data init; 2746 struct pmc_clk_gate *gate; 2747 2748 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2749 if (!gate) 2750 return ERR_PTR(-ENOMEM); 2751 2752 init.name = name; 2753 init.ops = &pmc_clk_gate_ops; 2754 init.parent_names = &parent_name; 2755 init.num_parents = 1; 2756 init.flags = 0; 2757 2758 gate->hw.init = &init; 2759 gate->offs = offset; 2760 gate->shift = shift; 2761 2762 return clk_register(NULL, &gate->hw); 2763} 2764 2765static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2766 struct device_node *np) 2767{ 2768 struct clk *clk; 2769 struct clk_onecell_data *clk_data; 2770 unsigned int num_clks; 2771 int i, err; 2772 2773 num_clks = pmc->soc->num_pmc_clks; 2774 if (pmc->soc->has_blink_output) 2775 num_clks += 1; 2776 2777 if (!num_clks) 2778 return; 2779 2780 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2781 if (!clk_data) 2782 return; 2783 2784 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2785 sizeof(*clk_data->clks), GFP_KERNEL); 2786 if (!clk_data->clks) 2787 return; 2788 2789 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2790 2791 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2792 clk_data->clks[i] = ERR_PTR(-ENOENT); 2793 2794 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2795 const struct pmc_clk_init_data *data; 2796 2797 data = pmc->soc->pmc_clks_data + i; 2798 2799 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2800 if (IS_ERR(clk)) { 2801 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2802 data->name, PTR_ERR_OR_ZERO(clk)); 2803 return; 2804 } 2805 2806 err = clk_register_clkdev(clk, data->name, NULL); 2807 if (err) { 2808 dev_warn(pmc->dev, 2809 "unable to register %s clock lookup: %d\n", 2810 data->name, err); 2811 return; 2812 } 2813 2814 clk_data->clks[data->clk_id] = clk; 2815 } 2816 2817 if (pmc->soc->has_blink_output) { 2818 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2819 clk = tegra_pmc_clk_gate_register(pmc, 2820 "pmc_blink_override", 2821 "clk_32k", 2822 PMC_DPD_PADS_ORIDE, 2823 PMC_DPD_PADS_ORIDE_BLINK); 2824 if (IS_ERR(clk)) { 2825 dev_warn(pmc->dev, 2826 "unable to register pmc_blink_override: %d\n", 2827 PTR_ERR_OR_ZERO(clk)); 2828 return; 2829 } 2830 2831 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2832 "pmc_blink_override", 2833 PMC_CNTRL, 2834 PMC_CNTRL_BLINK_EN); 2835 if (IS_ERR(clk)) { 2836 dev_warn(pmc->dev, 2837 "unable to register pmc_blink: %d\n", 2838 PTR_ERR_OR_ZERO(clk)); 2839 return; 2840 } 2841 2842 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2843 if (err) { 2844 dev_warn(pmc->dev, 2845 "unable to register pmc_blink lookup: %d\n", 2846 err); 2847 return; 2848 } 2849 2850 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2851 } 2852 2853 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2854 if (err) 2855 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2856 err); 2857} 2858 2859static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2860 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2861 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2862 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2863 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2864 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2865 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2866 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2867 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2868}; 2869 2870static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2871 .yes_ranges = pmc_usb_sleepwalk_ranges, 2872 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2873}; 2874 2875static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2876{ 2877 struct tegra_pmc *pmc = context; 2878 2879 *value = tegra_pmc_readl(pmc, offset); 2880 return 0; 2881} 2882 2883static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2884{ 2885 struct tegra_pmc *pmc = context; 2886 2887 tegra_pmc_writel(pmc, value, offset); 2888 return 0; 2889} 2890 2891static const struct regmap_config usb_sleepwalk_regmap_config = { 2892 .name = "usb_sleepwalk", 2893 .reg_bits = 32, 2894 .val_bits = 32, 2895 .reg_stride = 4, 2896 .fast_io = true, 2897 .rd_table = &pmc_usb_sleepwalk_table, 2898 .wr_table = &pmc_usb_sleepwalk_table, 2899 .reg_read = tegra_pmc_regmap_readl, 2900 .reg_write = tegra_pmc_regmap_writel, 2901}; 2902 2903static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2904{ 2905 struct regmap *regmap; 2906 int err; 2907 2908 if (pmc->soc->has_usb_sleepwalk) { 2909 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2910 if (IS_ERR(regmap)) { 2911 err = PTR_ERR(regmap); 2912 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2913 return err; 2914 } 2915 } 2916 2917 return 0; 2918} 2919 2920static void tegra_pmc_reset_suspend_mode(void *data) 2921{ 2922 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2923} 2924 2925static int tegra_pmc_probe(struct platform_device *pdev) 2926{ 2927 void __iomem *base; 2928 struct resource *res; 2929 int err; 2930 2931 /* 2932 * Early initialisation should have configured an initial 2933 * register mapping and setup the soc data pointer. If these 2934 * are not valid then something went badly wrong! 2935 */ 2936 if (WARN_ON(!pmc->base || !pmc->soc)) 2937 return -ENODEV; 2938 2939 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2940 if (err < 0) 2941 return err; 2942 2943 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 2944 NULL); 2945 if (err) 2946 return err; 2947 2948 /* take over the memory region from the early initialization */ 2949 base = devm_platform_ioremap_resource(pdev, 0); 2950 if (IS_ERR(base)) 2951 return PTR_ERR(base); 2952 2953 if (pmc->soc->has_single_mmio_aperture) { 2954 pmc->wake = base; 2955 pmc->aotag = base; 2956 pmc->scratch = base; 2957 } else { 2958 pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake"); 2959 if (IS_ERR(pmc->wake)) 2960 return PTR_ERR(pmc->wake); 2961 2962 /* "aotag" is an optional aperture */ 2963 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2964 "aotag"); 2965 if (res) { 2966 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2967 if (IS_ERR(pmc->aotag)) 2968 return PTR_ERR(pmc->aotag); 2969 } else { 2970 pmc->aotag = NULL; 2971 } 2972 2973 /* "scratch" is an optional aperture */ 2974 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2975 "scratch"); 2976 if (res) { 2977 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2978 if (IS_ERR(pmc->scratch)) 2979 return PTR_ERR(pmc->scratch); 2980 } else { 2981 pmc->scratch = NULL; 2982 } 2983 } 2984 2985 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); 2986 if (IS_ERR(pmc->clk)) 2987 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), 2988 "failed to get pclk\n"); 2989 2990 /* 2991 * PMC should be last resort for restarting since it soft-resets 2992 * CPU without resetting everything else. 2993 */ 2994 if (pmc->scratch) { 2995 err = devm_register_reboot_notifier(&pdev->dev, 2996 &tegra_pmc_reboot_notifier); 2997 if (err) { 2998 dev_err(&pdev->dev, 2999 "unable to register reboot notifier, %d\n", 3000 err); 3001 return err; 3002 } 3003 } 3004 3005 err = devm_register_sys_off_handler(&pdev->dev, 3006 SYS_OFF_MODE_RESTART, 3007 SYS_OFF_PRIO_LOW, 3008 tegra_pmc_restart_handler, NULL); 3009 if (err) { 3010 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 3011 err); 3012 return err; 3013 } 3014 3015 /* 3016 * PMC should be primary power-off method if it soft-resets CPU, 3017 * asking bootloader to shutdown hardware. 3018 */ 3019 err = devm_register_sys_off_handler(&pdev->dev, 3020 SYS_OFF_MODE_POWER_OFF, 3021 SYS_OFF_PRIO_FIRMWARE, 3022 tegra_pmc_power_off_handler, NULL); 3023 if (err) { 3024 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 3025 err); 3026 return err; 3027 } 3028 3029 /* 3030 * PCLK clock rate can't be retrieved using CLK API because it 3031 * causes lockup if CPU enters LP2 idle state from some other 3032 * CLK notifier, hence we're caching the rate's value locally. 3033 */ 3034 if (pmc->clk) { 3035 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 3036 err = devm_clk_notifier_register(&pdev->dev, pmc->clk, 3037 &pmc->clk_nb); 3038 if (err) { 3039 dev_err(&pdev->dev, 3040 "failed to register clk notifier\n"); 3041 return err; 3042 } 3043 3044 pmc->rate = clk_get_rate(pmc->clk); 3045 } 3046 3047 pmc->dev = &pdev->dev; 3048 3049 err = tegra_pmc_init(pmc); 3050 if (err < 0) { 3051 dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err); 3052 return err; 3053 } 3054 3055 tegra_pmc_init_tsense_reset(pmc); 3056 3057 tegra_pmc_reset_sysfs_init(pmc); 3058 3059 err = tegra_pmc_pinctrl_init(pmc); 3060 if (err) 3061 goto cleanup_sysfs; 3062 3063 err = tegra_pmc_regmap_init(pmc); 3064 if (err < 0) 3065 goto cleanup_sysfs; 3066 3067 err = tegra_powergate_init(pmc, pdev->dev.of_node); 3068 if (err < 0) 3069 goto cleanup_powergates; 3070 3071 err = tegra_pmc_irq_init(pmc); 3072 if (err < 0) 3073 goto cleanup_powergates; 3074 3075 mutex_lock(&pmc->powergates_lock); 3076 iounmap(pmc->base); 3077 pmc->base = base; 3078 mutex_unlock(&pmc->powergates_lock); 3079 3080 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 3081 platform_set_drvdata(pdev, pmc); 3082 tegra_pm_init_suspend(); 3083 3084 /* Some wakes require specific filter configuration */ 3085 if (pmc->soc->set_wake_filters) 3086 pmc->soc->set_wake_filters(pmc); 3087 3088 debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops); 3089 3090 return 0; 3091 3092cleanup_powergates: 3093 tegra_powergate_remove_all(pdev->dev.of_node); 3094cleanup_sysfs: 3095 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3096 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3097 3098 return err; 3099} 3100 3101/* 3102 * Ensures that sufficient time is passed for a register write to 3103 * serialize into the 32KHz domain. 3104 */ 3105static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset) 3106{ 3107 writel(value, pmc->wake + offset); 3108 udelay(130); 3109} 3110 3111static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level) 3112{ 3113 unsigned int offset = WAKE_AOWAKE_CNTRL(wake); 3114 u32 value; 3115 3116 value = readl(pmc->wake + offset); 3117 if (level) 3118 value |= WAKE_AOWAKE_CNTRL_LEVEL; 3119 else 3120 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 3121 3122 writel(value, pmc->wake + offset); 3123} 3124 3125static void wke_write_wake_levels(struct tegra_pmc *pmc) 3126{ 3127 unsigned int i; 3128 3129 for (i = 0; i < pmc->soc->max_wake_events; i++) 3130 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map)); 3131} 3132 3133static void wke_clear_sw_wake_status(struct tegra_pmc *pmc) 3134{ 3135 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0); 3136} 3137 3138static void wke_read_sw_wake_status(struct tegra_pmc *pmc) 3139{ 3140 unsigned long status; 3141 unsigned int wake, i; 3142 3143 for (i = 0; i < pmc->soc->max_wake_events; i++) 3144 wke_write_wake_level(pmc, i, 0); 3145 3146 wke_clear_sw_wake_status(pmc); 3147 3148 wke_32kwritel(pmc, 1, WAKE_LATCH_SW); 3149 3150 /* 3151 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to 3152 * obtain the current status of the input wake signals, change 3153 * the polarity of the wake level from 0->1 while latching to force 3154 * a positive edge if the sampled signal is '1'. 3155 */ 3156 for (i = 0; i < pmc->soc->max_wake_events; i++) 3157 wke_write_wake_level(pmc, i, 1); 3158 3159 /* 3160 * Wait for the update to be synced into the 32kHz domain, 3161 * and let enough time lapse, so that the wake signals have time to 3162 * be sampled. 3163 */ 3164 udelay(300); 3165 3166 wke_32kwritel(pmc, 0, WAKE_LATCH_SW); 3167 3168 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3169 3170 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3171 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i)); 3172 3173 for_each_set_bit(wake, &status, 32) 3174 set_bit(wake + (i * 32), pmc->wake_sw_status_map); 3175 } 3176} 3177 3178static void wke_clear_wake_status(struct tegra_pmc *pmc) 3179{ 3180 unsigned long status; 3181 unsigned int i, wake; 3182 u32 mask; 3183 3184 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3185 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3186 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3187 3188 for_each_set_bit(wake, &status, 32) 3189 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake)); 3190 } 3191} 3192 3193static void tegra186_pmc_wake_syscore_resume(void *data) 3194{ 3195 unsigned int i; 3196 u32 mask; 3197 3198 for (i = 0; i < pmc->soc->max_wake_vectors; i++) { 3199 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i)); 3200 pmc->wake_status[i] = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask; 3201 } 3202 3203 /* Schedule IRQ work to process wake IRQs (if any) */ 3204 irq_work_queue(&pmc->wake_work); 3205} 3206 3207static int tegra186_pmc_wake_syscore_suspend(void *data) 3208{ 3209 unsigned int i; 3210 3211 /* Check if there are unhandled wake IRQs */ 3212 for (i = 0; i < pmc->soc->max_wake_vectors; i++) 3213 if (pmc->wake_status[i]) 3214 dev_warn(pmc->dev, 3215 "Unhandled wake IRQs pending vector[%u]: 0x%x\n", 3216 i, pmc->wake_status[i]); 3217 wke_read_sw_wake_status(pmc); 3218 3219 /* flip the wakeup trigger for dual-edge triggered pads 3220 * which are currently asserting as wakeups 3221 */ 3222 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map, 3223 pmc->wake_sw_status_map, pmc->soc->max_wake_events); 3224 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map, 3225 pmc->wake_type_level_map, pmc->soc->max_wake_events); 3226 3227 /* Clear PMC Wake Status registers while going to suspend */ 3228 wke_clear_wake_status(pmc); 3229 wke_write_wake_levels(pmc); 3230 3231 return 0; 3232} 3233 3234static const struct syscore_ops tegra186_pmc_wake_syscore_ops = { 3235 .suspend = tegra186_pmc_wake_syscore_suspend, 3236 .resume = tegra186_pmc_wake_syscore_resume, 3237}; 3238 3239#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3240static int tegra_pmc_suspend(struct device *dev) 3241{ 3242 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3243 3244 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3245 3246 return 0; 3247} 3248 3249static int tegra_pmc_resume(struct device *dev) 3250{ 3251 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3252 3253 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3254 3255 return 0; 3256} 3257 3258static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3259 3260#endif 3261 3262static const char * const tegra20_powergates[] = { 3263 [TEGRA_POWERGATE_CPU] = "cpu", 3264 [TEGRA_POWERGATE_3D] = "td", 3265 [TEGRA_POWERGATE_VENC] = "venc", 3266 [TEGRA_POWERGATE_VDEC] = "vdec", 3267 [TEGRA_POWERGATE_PCIE] = "pcie", 3268 [TEGRA_POWERGATE_L2] = "l2", 3269 [TEGRA_POWERGATE_MPE] = "mpe", 3270}; 3271 3272static const struct tegra_pmc_regs tegra20_pmc_regs = { 3273 .scratch0 = 0x50, 3274 .rst_status = 0x1b4, 3275 .rst_source_shift = 0x0, 3276 .rst_source_mask = 0x7, 3277 .rst_level_shift = 0x0, 3278 .rst_level_mask = 0x0, 3279}; 3280 3281static void tegra20_pmc_init(struct tegra_pmc *pmc) 3282{ 3283 u32 value, osc, pmu, off; 3284 3285 /* Always enable CPU power request */ 3286 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3287 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3288 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3289 3290 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3291 3292 if (pmc->sysclkreq_high) 3293 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3294 else 3295 value |= PMC_CNTRL_SYSCLK_POLARITY; 3296 3297 if (pmc->corereq_high) 3298 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3299 else 3300 value |= PMC_CNTRL_PWRREQ_POLARITY; 3301 3302 /* configure the output polarity while the request is tristated */ 3303 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3304 3305 /* now enable the request */ 3306 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3307 value |= PMC_CNTRL_SYSCLK_OE; 3308 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3309 3310 /* program core timings which are applicable only for suspend state */ 3311 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3312 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3313 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3314 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3315 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3316 PMC_COREPWRGOOD_TIMER); 3317 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3318 } 3319} 3320 3321static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3322 struct device_node *np, 3323 bool invert) 3324{ 3325 u32 value; 3326 3327 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3328 3329 if (invert) 3330 value |= PMC_CNTRL_INTR_POLARITY; 3331 else 3332 value &= ~PMC_CNTRL_INTR_POLARITY; 3333 3334 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3335} 3336 3337static const struct tegra_pmc_soc tegra20_pmc_soc = { 3338 .supports_core_domain = true, 3339 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3340 .powergates = tegra20_powergates, 3341 .num_cpu_powergates = 0, 3342 .cpu_powergates = NULL, 3343 .has_tsense_reset = false, 3344 .has_gpu_clamps = false, 3345 .needs_mbist_war = false, 3346 .has_impl_33v_pwr = false, 3347 .maybe_tz_only = false, 3348 .num_io_pads = 0, 3349 .io_pads = NULL, 3350 .num_pin_descs = 0, 3351 .pin_descs = NULL, 3352 .regs = &tegra20_pmc_regs, 3353 .init = tegra20_pmc_init, 3354 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3355 .powergate_set = tegra20_powergate_set, 3356 .reset_sources = NULL, 3357 .num_reset_sources = 0, 3358 .reset_levels = NULL, 3359 .num_reset_levels = 0, 3360 .pmc_clks_data = NULL, 3361 .num_pmc_clks = 0, 3362 .has_blink_output = true, 3363 .has_usb_sleepwalk = true, 3364 .has_single_mmio_aperture = true, 3365}; 3366 3367static const char * const tegra30_powergates[] = { 3368 [TEGRA_POWERGATE_CPU] = "cpu0", 3369 [TEGRA_POWERGATE_3D] = "td", 3370 [TEGRA_POWERGATE_VENC] = "venc", 3371 [TEGRA_POWERGATE_VDEC] = "vdec", 3372 [TEGRA_POWERGATE_PCIE] = "pcie", 3373 [TEGRA_POWERGATE_L2] = "l2", 3374 [TEGRA_POWERGATE_MPE] = "mpe", 3375 [TEGRA_POWERGATE_HEG] = "heg", 3376 [TEGRA_POWERGATE_SATA] = "sata", 3377 [TEGRA_POWERGATE_CPU1] = "cpu1", 3378 [TEGRA_POWERGATE_CPU2] = "cpu2", 3379 [TEGRA_POWERGATE_CPU3] = "cpu3", 3380 [TEGRA_POWERGATE_CELP] = "celp", 3381 [TEGRA_POWERGATE_3D1] = "td2", 3382}; 3383 3384static const u8 tegra30_cpu_powergates[] = { 3385 TEGRA_POWERGATE_CPU, 3386 TEGRA_POWERGATE_CPU1, 3387 TEGRA_POWERGATE_CPU2, 3388 TEGRA_POWERGATE_CPU3, 3389}; 3390 3391static const char * const tegra30_reset_sources[] = { 3392 "POWER_ON_RESET", 3393 "WATCHDOG", 3394 "SENSOR", 3395 "SW_MAIN", 3396 "LP0" 3397}; 3398 3399static const struct tegra_pmc_soc tegra30_pmc_soc = { 3400 .supports_core_domain = true, 3401 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3402 .powergates = tegra30_powergates, 3403 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3404 .cpu_powergates = tegra30_cpu_powergates, 3405 .has_tsense_reset = true, 3406 .has_gpu_clamps = false, 3407 .needs_mbist_war = false, 3408 .has_impl_33v_pwr = false, 3409 .maybe_tz_only = false, 3410 .num_io_pads = 0, 3411 .io_pads = NULL, 3412 .num_pin_descs = 0, 3413 .pin_descs = NULL, 3414 .regs = &tegra20_pmc_regs, 3415 .init = tegra20_pmc_init, 3416 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3417 .powergate_set = tegra20_powergate_set, 3418 .reset_sources = tegra30_reset_sources, 3419 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3420 .reset_levels = NULL, 3421 .num_reset_levels = 0, 3422 .pmc_clks_data = tegra_pmc_clks_data, 3423 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3424 .has_blink_output = true, 3425 .has_usb_sleepwalk = true, 3426 .has_single_mmio_aperture = true, 3427}; 3428 3429static const char * const tegra114_powergates[] = { 3430 [TEGRA_POWERGATE_CPU] = "crail", 3431 [TEGRA_POWERGATE_3D] = "td", 3432 [TEGRA_POWERGATE_VENC] = "venc", 3433 [TEGRA_POWERGATE_VDEC] = "vdec", 3434 [TEGRA_POWERGATE_MPE] = "mpe", 3435 [TEGRA_POWERGATE_HEG] = "heg", 3436 [TEGRA_POWERGATE_CPU1] = "cpu1", 3437 [TEGRA_POWERGATE_CPU2] = "cpu2", 3438 [TEGRA_POWERGATE_CPU3] = "cpu3", 3439 [TEGRA_POWERGATE_CELP] = "celp", 3440 [TEGRA_POWERGATE_CPU0] = "cpu0", 3441 [TEGRA_POWERGATE_C0NC] = "c0nc", 3442 [TEGRA_POWERGATE_C1NC] = "c1nc", 3443 [TEGRA_POWERGATE_DIS] = "dis", 3444 [TEGRA_POWERGATE_DISB] = "disb", 3445 [TEGRA_POWERGATE_XUSBA] = "xusba", 3446 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3447 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3448}; 3449 3450static const u8 tegra114_cpu_powergates[] = { 3451 TEGRA_POWERGATE_CPU0, 3452 TEGRA_POWERGATE_CPU1, 3453 TEGRA_POWERGATE_CPU2, 3454 TEGRA_POWERGATE_CPU3, 3455}; 3456 3457static const struct tegra_pmc_soc tegra114_pmc_soc = { 3458 .supports_core_domain = false, 3459 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3460 .powergates = tegra114_powergates, 3461 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3462 .cpu_powergates = tegra114_cpu_powergates, 3463 .has_tsense_reset = true, 3464 .has_gpu_clamps = false, 3465 .needs_mbist_war = false, 3466 .has_impl_33v_pwr = false, 3467 .maybe_tz_only = false, 3468 .num_io_pads = 0, 3469 .io_pads = NULL, 3470 .num_pin_descs = 0, 3471 .pin_descs = NULL, 3472 .regs = &tegra20_pmc_regs, 3473 .init = tegra20_pmc_init, 3474 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3475 .powergate_set = tegra114_powergate_set, 3476 .reset_sources = tegra30_reset_sources, 3477 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3478 .reset_levels = NULL, 3479 .num_reset_levels = 0, 3480 .pmc_clks_data = tegra_pmc_clks_data, 3481 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3482 .has_blink_output = true, 3483 .has_usb_sleepwalk = true, 3484 .has_single_mmio_aperture = true, 3485}; 3486 3487static const char * const tegra124_powergates[] = { 3488 [TEGRA_POWERGATE_CPU] = "crail", 3489 [TEGRA_POWERGATE_3D] = "3d", 3490 [TEGRA_POWERGATE_VENC] = "venc", 3491 [TEGRA_POWERGATE_PCIE] = "pcie", 3492 [TEGRA_POWERGATE_VDEC] = "vdec", 3493 [TEGRA_POWERGATE_MPE] = "mpe", 3494 [TEGRA_POWERGATE_HEG] = "heg", 3495 [TEGRA_POWERGATE_SATA] = "sata", 3496 [TEGRA_POWERGATE_CPU1] = "cpu1", 3497 [TEGRA_POWERGATE_CPU2] = "cpu2", 3498 [TEGRA_POWERGATE_CPU3] = "cpu3", 3499 [TEGRA_POWERGATE_CELP] = "celp", 3500 [TEGRA_POWERGATE_CPU0] = "cpu0", 3501 [TEGRA_POWERGATE_C0NC] = "c0nc", 3502 [TEGRA_POWERGATE_C1NC] = "c1nc", 3503 [TEGRA_POWERGATE_SOR] = "sor", 3504 [TEGRA_POWERGATE_DIS] = "dis", 3505 [TEGRA_POWERGATE_DISB] = "disb", 3506 [TEGRA_POWERGATE_XUSBA] = "xusba", 3507 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3508 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3509 [TEGRA_POWERGATE_VIC] = "vic", 3510 [TEGRA_POWERGATE_IRAM] = "iram", 3511}; 3512 3513static const u8 tegra124_cpu_powergates[] = { 3514 TEGRA_POWERGATE_CPU0, 3515 TEGRA_POWERGATE_CPU1, 3516 TEGRA_POWERGATE_CPU2, 3517 TEGRA_POWERGATE_CPU3, 3518}; 3519 3520#define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name) \ 3521 ((struct tegra_io_pad_soc) { \ 3522 .id = (_id), \ 3523 .dpd = (_dpd), \ 3524 .request = (_request), \ 3525 .status = (_status), \ 3526 .voltage = (_voltage), \ 3527 .name = (_name), \ 3528 }) 3529 3530#define TEGRA_IO_PIN_DESC(_id, _name) \ 3531 ((struct pinctrl_pin_desc) { \ 3532 .number = (_id), \ 3533 .name = (_name), \ 3534 }) 3535 3536static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3537 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"), 3538 TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"), 3539 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"), 3540 TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"), 3541 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3542 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3543 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3544 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3545 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3546 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3547 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3548 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3549 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3550 TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"), 3551 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3552 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3553 TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"), 3554 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3555 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3556 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3557 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"), 3558 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"), 3559 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"), 3560 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"), 3561 TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"), 3562 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"), 3563 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3564 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3565 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3566 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"), 3567}; 3568 3569static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3570 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3571 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"), 3572 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3573 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"), 3574 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3575 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3576 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3577 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3578 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3579 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3580 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3581 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3582 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3583 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"), 3584 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3585 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3586 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"), 3587 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3588 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3589 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3590 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3591 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3592 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3593 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3594 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"), 3595 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3596 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3597 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3598 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3599 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"), 3600}; 3601 3602static const struct tegra_pmc_soc tegra124_pmc_soc = { 3603 .supports_core_domain = false, 3604 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3605 .powergates = tegra124_powergates, 3606 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3607 .cpu_powergates = tegra124_cpu_powergates, 3608 .has_tsense_reset = true, 3609 .has_gpu_clamps = true, 3610 .needs_mbist_war = false, 3611 .has_impl_33v_pwr = false, 3612 .maybe_tz_only = false, 3613 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3614 .io_pads = tegra124_io_pads, 3615 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3616 .pin_descs = tegra124_pin_descs, 3617 .regs = &tegra20_pmc_regs, 3618 .init = tegra20_pmc_init, 3619 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3620 .powergate_set = tegra114_powergate_set, 3621 .reset_sources = tegra30_reset_sources, 3622 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3623 .reset_levels = NULL, 3624 .num_reset_levels = 0, 3625 .pmc_clks_data = tegra_pmc_clks_data, 3626 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3627 .has_blink_output = true, 3628 .has_usb_sleepwalk = true, 3629 .has_single_mmio_aperture = true, 3630}; 3631 3632static const char * const tegra210_powergates[] = { 3633 [TEGRA_POWERGATE_CPU] = "crail", 3634 [TEGRA_POWERGATE_3D] = "3d", 3635 [TEGRA_POWERGATE_VENC] = "venc", 3636 [TEGRA_POWERGATE_PCIE] = "pcie", 3637 [TEGRA_POWERGATE_MPE] = "mpe", 3638 [TEGRA_POWERGATE_SATA] = "sata", 3639 [TEGRA_POWERGATE_CPU1] = "cpu1", 3640 [TEGRA_POWERGATE_CPU2] = "cpu2", 3641 [TEGRA_POWERGATE_CPU3] = "cpu3", 3642 [TEGRA_POWERGATE_CPU0] = "cpu0", 3643 [TEGRA_POWERGATE_C0NC] = "c0nc", 3644 [TEGRA_POWERGATE_SOR] = "sor", 3645 [TEGRA_POWERGATE_DIS] = "dis", 3646 [TEGRA_POWERGATE_DISB] = "disb", 3647 [TEGRA_POWERGATE_XUSBA] = "xusba", 3648 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3649 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3650 [TEGRA_POWERGATE_VIC] = "vic", 3651 [TEGRA_POWERGATE_IRAM] = "iram", 3652 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3653 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3654 [TEGRA_POWERGATE_AUD] = "aud", 3655 [TEGRA_POWERGATE_DFD] = "dfd", 3656 [TEGRA_POWERGATE_VE2] = "ve2", 3657}; 3658 3659static const u8 tegra210_cpu_powergates[] = { 3660 TEGRA_POWERGATE_CPU0, 3661 TEGRA_POWERGATE_CPU1, 3662 TEGRA_POWERGATE_CPU2, 3663 TEGRA_POWERGATE_CPU3, 3664}; 3665 3666static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3667 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"), 3668 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"), 3669 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"), 3670 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"), 3671 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"), 3672 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"), 3673 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"), 3674 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"), 3675 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"), 3676 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"), 3677 TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"), 3678 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"), 3679 TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"), 3680 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"), 3681 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"), 3682 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"), 3683 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"), 3684 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"), 3685 TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"), 3686 TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"), 3687 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"), 3688 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"), 3689 TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"), 3690 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"), 3691 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"), 3692 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"), 3693 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"), 3694 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"), 3695 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"), 3696 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"), 3697 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"), 3698 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"), 3699 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"), 3700 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"), 3701 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"), 3702 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"), 3703 TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"), 3704 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"), 3705}; 3706 3707static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3708 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3709 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3710 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3711 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3712 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3713 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3714 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3715 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3716 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3717 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3718 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), 3719 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), 3720 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), 3721 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3722 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3723 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3724 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3725 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), 3726 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), 3727 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), 3728 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), 3729 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3730 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), 3731 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3732 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), 3733 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3734 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3735 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3736 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), 3737 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), 3738 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3739 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), 3740 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3741 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3742 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3743 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3744 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), 3745 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3746}; 3747 3748static const char * const tegra210_reset_sources[] = { 3749 "POWER_ON_RESET", 3750 "WATCHDOG", 3751 "SENSOR", 3752 "SW_MAIN", 3753 "LP0", 3754 "AOTAG" 3755}; 3756 3757static const struct tegra_wake_event tegra210_wake_events[] = { 3758 TEGRA_WAKE_IRQ("rtc", 16, 2), 3759 TEGRA_WAKE_IRQ("pmu", 51, 86), 3760}; 3761 3762static const struct tegra_pmc_soc tegra210_pmc_soc = { 3763 .supports_core_domain = false, 3764 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3765 .powergates = tegra210_powergates, 3766 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3767 .cpu_powergates = tegra210_cpu_powergates, 3768 .has_tsense_reset = true, 3769 .has_gpu_clamps = true, 3770 .needs_mbist_war = true, 3771 .has_impl_33v_pwr = false, 3772 .maybe_tz_only = true, 3773 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3774 .io_pads = tegra210_io_pads, 3775 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3776 .pin_descs = tegra210_pin_descs, 3777 .regs = &tegra20_pmc_regs, 3778 .init = tegra20_pmc_init, 3779 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3780 .powergate_set = tegra114_powergate_set, 3781 .irq_set_wake = tegra210_pmc_irq_set_wake, 3782 .irq_set_type = tegra210_pmc_irq_set_type, 3783 .reset_sources = tegra210_reset_sources, 3784 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3785 .reset_levels = NULL, 3786 .num_reset_levels = 0, 3787 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3788 .wake_events = tegra210_wake_events, 3789 .pmc_clks_data = tegra_pmc_clks_data, 3790 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3791 .has_blink_output = true, 3792 .has_usb_sleepwalk = true, 3793 .has_single_mmio_aperture = true, 3794}; 3795 3796static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3797 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3798 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3799 TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"), 3800 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3801 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3802 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3803 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3804 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 3805 TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"), 3806 TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"), 3807 TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"), 3808 TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"), 3809 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 3810 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 3811 TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"), 3812 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 3813 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 3814 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 3815 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 3816 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"), 3817 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 3818 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 3819 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"), 3820 TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"), 3821 TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"), 3822 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 3823 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 3824 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 3825 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 3826 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 3827 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 3828 TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"), 3829 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 3830 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 3831 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 3832 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 3833 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 3834 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 3835}; 3836 3837static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3838 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 3839 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 3840 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), 3841 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 3842 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 3843 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 3844 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 3845 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 3846 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), 3847 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), 3848 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), 3849 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), 3850 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 3851 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 3852 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), 3853 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 3854 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 3855 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 3856 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 3857 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"), 3858 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 3859 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 3860 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), 3861 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), 3862 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), 3863 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 3864 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 3865 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 3866 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 3867 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 3868 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 3869 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"), 3870 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 3871 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 3872 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 3873 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 3874 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 3875 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 3876}; 3877 3878static const struct tegra_pmc_regs tegra186_pmc_regs = { 3879 .scratch0 = 0x2000, 3880 .rst_status = 0x70, 3881 .rst_source_shift = 0x2, 3882 .rst_source_mask = 0x3c, 3883 .rst_level_shift = 0x0, 3884 .rst_level_mask = 0x3, 3885}; 3886 3887static void tegra186_pmc_init(struct tegra_pmc *pmc) 3888{ 3889 pmc->syscore.ops = &tegra186_pmc_wake_syscore_ops; 3890 register_syscore(&pmc->syscore); 3891} 3892 3893static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3894 struct device_node *np, 3895 bool invert) 3896{ 3897 struct resource regs; 3898 void __iomem *wake; 3899 u32 value; 3900 int index; 3901 3902 index = of_property_match_string(np, "reg-names", "wake"); 3903 if (index < 0) { 3904 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3905 return; 3906 } 3907 3908 of_address_to_resource(np, index, ®s); 3909 3910 wake = ioremap(regs.start, resource_size(®s)); 3911 if (!wake) { 3912 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3913 return; 3914 } 3915 3916 value = readl(wake + WAKE_AOWAKE_CTRL); 3917 3918 if (invert) 3919 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3920 else 3921 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3922 3923 writel(value, wake + WAKE_AOWAKE_CTRL); 3924 3925 iounmap(wake); 3926} 3927 3928static const char * const tegra186_reset_sources[] = { 3929 "SYS_RESET", 3930 "AOWDT", 3931 "MCCPLEXWDT", 3932 "BPMPWDT", 3933 "SCEWDT", 3934 "SPEWDT", 3935 "APEWDT", 3936 "BCCPLEXWDT", 3937 "SENSOR", 3938 "AOTAG", 3939 "VFSENSOR", 3940 "SWREST", 3941 "SC7", 3942 "HSM", 3943 "CORESIGHT" 3944}; 3945 3946static const char * const tegra186_reset_levels[] = { 3947 "L0", "L1", "L2", "WARM" 3948}; 3949 3950static const struct tegra_wake_event tegra186_wake_events[] = { 3951 TEGRA_WAKE_IRQ("pmu", 24, 209), 3952 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3953 TEGRA_WAKE_IRQ("rtc", 73, 10), 3954}; 3955 3956static const struct tegra_pmc_soc tegra186_pmc_soc = { 3957 .supports_core_domain = false, 3958 .num_powergates = 0, 3959 .powergates = NULL, 3960 .num_cpu_powergates = 0, 3961 .cpu_powergates = NULL, 3962 .has_tsense_reset = false, 3963 .has_gpu_clamps = false, 3964 .needs_mbist_war = false, 3965 .has_impl_33v_pwr = true, 3966 .maybe_tz_only = false, 3967 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3968 .io_pads = tegra186_io_pads, 3969 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3970 .pin_descs = tegra186_pin_descs, 3971 .regs = &tegra186_pmc_regs, 3972 .init = tegra186_pmc_init, 3973 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3974 .set_wake_filters = tegra186_pmc_set_wake_filters, 3975 .irq_set_wake = tegra186_pmc_irq_set_wake, 3976 .irq_set_type = tegra186_pmc_irq_set_type, 3977 .reset_sources = tegra186_reset_sources, 3978 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3979 .reset_levels = tegra186_reset_levels, 3980 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3981 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3982 .wake_events = tegra186_wake_events, 3983 .max_wake_events = 96, 3984 .max_wake_vectors = 3, 3985 .pmc_clks_data = NULL, 3986 .num_pmc_clks = 0, 3987 .has_blink_output = false, 3988 .has_usb_sleepwalk = false, 3989 .has_single_mmio_aperture = false, 3990}; 3991 3992static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3993 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"), 3994 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"), 3995 TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"), 3996 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"), 3997 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"), 3998 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"), 3999 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"), 4000 TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"), 4001 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"), 4002 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"), 4003 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"), 4004 TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"), 4005 TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"), 4006 TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"), 4007 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"), 4008 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"), 4009 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"), 4010 TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"), 4011 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"), 4012 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"), 4013 TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"), 4014 TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"), 4015 TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"), 4016 TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"), 4017 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"), 4018 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"), 4019 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"), 4020 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"), 4021 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"), 4022 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"), 4023 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"), 4024 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"), 4025 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"), 4026 TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"), 4027 TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"), 4028 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"), 4029 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"), 4030 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"), 4031 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"), 4032 TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"), 4033 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"), 4034 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"), 4035 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"), 4036 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"), 4037 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"), 4038 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"), 4039 TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"), 4040 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"), 4041 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4042}; 4043 4044static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 4045 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4046 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4047 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), 4048 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"), 4049 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"), 4050 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), 4051 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), 4052 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"), 4053 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"), 4054 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"), 4055 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"), 4056 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"), 4057 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), 4058 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"), 4059 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"), 4060 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), 4061 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"), 4062 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"), 4063 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"), 4064 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"), 4065 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"), 4066 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"), 4067 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"), 4068 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), 4069 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"), 4070 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"), 4071 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4072 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"), 4073 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), 4074 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"), 4075 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"), 4076 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"), 4077 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"), 4078 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"), 4079 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), 4080 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4081 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4082 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4083 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4084 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), 4085 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4086 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4087 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4088 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4089 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4090 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4091 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"), 4092 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4093 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4094}; 4095 4096static const struct tegra_pmc_regs tegra194_pmc_regs = { 4097 .scratch0 = 0x2000, 4098 .rst_status = 0x70, 4099 .rst_source_shift = 0x2, 4100 .rst_source_mask = 0x7c, 4101 .rst_level_shift = 0x0, 4102 .rst_level_mask = 0x3, 4103}; 4104 4105static const char * const tegra194_reset_sources[] = { 4106 "SYS_RESET_N", 4107 "AOWDT", 4108 "BCCPLEXWDT", 4109 "BPMPWDT", 4110 "SCEWDT", 4111 "SPEWDT", 4112 "APEWDT", 4113 "LCCPLEXWDT", 4114 "SENSOR", 4115 "AOTAG", 4116 "VFSENSOR", 4117 "MAINSWRST", 4118 "SC7", 4119 "HSM", 4120 "CSITE", 4121 "RCEWDT", 4122 "PVA0WDT", 4123 "PVA1WDT", 4124 "L1A_ASYNC", 4125 "BPMPBOOT", 4126 "FUSECRC", 4127}; 4128 4129static const struct tegra_wake_event tegra194_wake_events[] = { 4130 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)), 4131 TEGRA_WAKE_IRQ("pmu", 24, 209), 4132 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 4133 TEGRA_WAKE_IRQ("rtc", 73, 10), 4134 TEGRA_WAKE_SIMPLE("usb3-port-0", 76), 4135 TEGRA_WAKE_SIMPLE("usb3-port-1", 77), 4136 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78), 4137 TEGRA_WAKE_SIMPLE("usb2-port-0", 79), 4138 TEGRA_WAKE_SIMPLE("usb2-port-1", 80), 4139 TEGRA_WAKE_SIMPLE("usb2-port-2", 81), 4140 TEGRA_WAKE_SIMPLE("usb2-port-3", 82), 4141}; 4142 4143static const struct tegra_pmc_soc tegra194_pmc_soc = { 4144 .supports_core_domain = false, 4145 .num_powergates = 0, 4146 .powergates = NULL, 4147 .num_cpu_powergates = 0, 4148 .cpu_powergates = NULL, 4149 .has_tsense_reset = false, 4150 .has_gpu_clamps = false, 4151 .needs_mbist_war = false, 4152 .has_impl_33v_pwr = true, 4153 .maybe_tz_only = false, 4154 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 4155 .io_pads = tegra194_io_pads, 4156 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 4157 .pin_descs = tegra194_pin_descs, 4158 .regs = &tegra194_pmc_regs, 4159 .init = tegra186_pmc_init, 4160 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4161 .set_wake_filters = tegra186_pmc_set_wake_filters, 4162 .irq_set_wake = tegra186_pmc_irq_set_wake, 4163 .irq_set_type = tegra186_pmc_irq_set_type, 4164 .reset_sources = tegra194_reset_sources, 4165 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 4166 .reset_levels = tegra186_reset_levels, 4167 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4168 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 4169 .wake_events = tegra194_wake_events, 4170 .max_wake_events = 96, 4171 .max_wake_vectors = 3, 4172 .pmc_clks_data = NULL, 4173 .num_pmc_clks = 0, 4174 .has_blink_output = false, 4175 .has_usb_sleepwalk = false, 4176 .has_single_mmio_aperture = false, 4177}; 4178 4179static const struct tegra_io_pad_soc tegra234_io_pads[] = { 4180 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"), 4181 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"), 4182 TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"), 4183 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"), 4184 TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"), 4185 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"), 4186 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"), 4187 TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"), 4188 TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"), 4189 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"), 4190 TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"), 4191 TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"), 4192 TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"), 4193 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"), 4194 TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"), 4195}; 4196 4197static const struct pinctrl_pin_desc tegra234_pin_descs[] = { 4198 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), 4199 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), 4200 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"), 4201 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), 4202 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), 4203 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), 4204 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), 4205 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"), 4206 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"), 4207 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"), 4208 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"), 4209 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), 4210 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"), 4211 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"), 4212 TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"), 4213}; 4214 4215static const struct tegra_pmc_regs tegra234_pmc_regs = { 4216 .scratch0 = 0x2000, 4217 .rst_status = 0x70, 4218 .rst_source_shift = 0x2, 4219 .rst_source_mask = 0xfc, 4220 .rst_level_shift = 0x0, 4221 .rst_level_mask = 0x3, 4222}; 4223 4224static const char * const tegra234_reset_sources[] = { 4225 "SYS_RESET_N", /* 0x0 */ 4226 "AOWDT", 4227 "BCCPLEXWDT", 4228 "BPMPWDT", 4229 "SCEWDT", 4230 "SPEWDT", 4231 "APEWDT", 4232 "LCCPLEXWDT", 4233 "SENSOR", /* 0x8 */ 4234 NULL, 4235 NULL, 4236 "MAINSWRST", 4237 "SC7", 4238 "HSM", 4239 NULL, 4240 "RCEWDT", 4241 NULL, /* 0x10 */ 4242 NULL, 4243 NULL, 4244 "BPMPBOOT", 4245 "FUSECRC", 4246 "DCEWDT", 4247 "PSCWDT", 4248 "PSC", 4249 "CSITE_SW", /* 0x18 */ 4250 "POD", 4251 "SCPM", 4252 "VREFRO_POWERBAD", 4253 "VMON", 4254 "FMON", 4255 "FSI_R5WDT", 4256 "FSI_THERM", 4257 "FSI_R52C0WDT", /* 0x20 */ 4258 "FSI_R52C1WDT", 4259 "FSI_R52C2WDT", 4260 "FSI_R52C3WDT", 4261 "FSI_FMON", 4262 "FSI_VMON", /* 0x25 */ 4263}; 4264 4265static const struct tegra_wake_event tegra234_wake_events[] = { 4266 TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), 4267 TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)), 4268 TEGRA_WAKE_IRQ("pmu", 24, 209), 4269 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 4270 TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), 4271 TEGRA_WAKE_IRQ("rtc", 73, 10), 4272 TEGRA_WAKE_IRQ("usb3-port-0", 76, 167), 4273 TEGRA_WAKE_IRQ("usb3-port-1", 77, 167), 4274 TEGRA_WAKE_IRQ("usb3-port-2-3", 78, 167), 4275 TEGRA_WAKE_IRQ("usb2-port-0", 79, 167), 4276 TEGRA_WAKE_IRQ("usb2-port-1", 80, 167), 4277 TEGRA_WAKE_IRQ("usb2-port-2", 81, 167), 4278 TEGRA_WAKE_IRQ("usb2-port-3", 82, 167), 4279 TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179), 4280}; 4281 4282static const struct tegra_pmc_soc tegra234_pmc_soc = { 4283 .supports_core_domain = false, 4284 .num_powergates = 0, 4285 .powergates = NULL, 4286 .num_cpu_powergates = 0, 4287 .cpu_powergates = NULL, 4288 .has_tsense_reset = false, 4289 .has_gpu_clamps = false, 4290 .needs_mbist_war = false, 4291 .has_impl_33v_pwr = true, 4292 .maybe_tz_only = false, 4293 .num_io_pads = ARRAY_SIZE(tegra234_io_pads), 4294 .io_pads = tegra234_io_pads, 4295 .num_pin_descs = ARRAY_SIZE(tegra234_pin_descs), 4296 .pin_descs = tegra234_pin_descs, 4297 .regs = &tegra234_pmc_regs, 4298 .init = tegra186_pmc_init, 4299 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4300 .set_wake_filters = tegra186_pmc_set_wake_filters, 4301 .irq_set_wake = tegra186_pmc_irq_set_wake, 4302 .irq_set_type = tegra186_pmc_irq_set_type, 4303 .reset_sources = tegra234_reset_sources, 4304 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 4305 .reset_levels = tegra186_reset_levels, 4306 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4307 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 4308 .wake_events = tegra234_wake_events, 4309 .max_wake_events = 96, 4310 .max_wake_vectors = 3, 4311 .pmc_clks_data = NULL, 4312 .num_pmc_clks = 0, 4313 .has_blink_output = false, 4314 .has_single_mmio_aperture = false, 4315}; 4316 4317static const struct tegra_pmc_regs tegra264_pmc_regs = { 4318 .scratch0 = 0x684, 4319 .rst_status = 0x4, 4320 .rst_source_shift = 0x2, 4321 .rst_source_mask = 0x1fc, 4322 .rst_level_shift = 0x0, 4323 .rst_level_mask = 0x3, 4324}; 4325 4326static const char * const tegra264_reset_sources[] = { 4327 "SYS_RESET_N", /* 0x0 */ 4328 "CSDC_RTC_XTAL", 4329 "VREFRO_POWER_BAD", 4330 "SCPM_SOC_XTAL", 4331 "SCPM_RTC_XTAL", 4332 "FMON_32K", 4333 "FMON_OSC", 4334 "POD_RTC", 4335 "POD_IO", /* 0x8 */ 4336 "POD_PLUS_IO_SPLL", 4337 "POD_PLUS_SOC", 4338 "VMON_PLUS_UV", 4339 "VMON_PLUS_OV", 4340 "FUSECRC_FAULT", 4341 "OSC_FAULT", 4342 "BPMP_BOOT_FAULT", 4343 "SCPM_BPMP_CORE_CLK", /* 0x10 */ 4344 "SCPM_PSC_SE_CLK", 4345 "VMON_SOC_MIN", 4346 "VMON_SOC_MAX", 4347 "VMON_MSS_MIN", 4348 "VMON_MSS_MAX", 4349 "POD_PLUS_IO_VMON", 4350 "NVJTAG_SEL_MONITOR", 4351 "NV_THERM_FAULT", /* 0x18 */ 4352 "FSI_THERM_FAULT", 4353 "PSC_SW", 4354 "SCPM_OESP_SE_CLK", 4355 "SCPM_SB_SE_CLK", 4356 "POD_CPU", 4357 "POD_GPU", 4358 "DCLS_GPU", 4359 "POD_MSS", /* 0x20 */ 4360 "FMON_FSI", 4361 "POD_FSI", 4362 "VMON_FSI_MIN", 4363 "VMON_FSI_MAX", 4364 "VMON_CPU0_MIN", 4365 "VMON_CPU0_MAX", 4366 "BPMP_FMON", 4367 "AO_WDT_POR", /* 0x28 */ 4368 "BPMP_WDT_POR", 4369 "AO_TKE_WDT_POR", 4370 "RCE0_WDT_POR", 4371 "RCE1_WDT_POR", 4372 "DCE_WDT_POR", 4373 "FSI_R5_WDT_POR", 4374 "FSI_R52_0_WDT_POR", 4375 "FSI_R52_1_WDT_POR", /* 0x30 */ 4376 "FSI_R52_2_WDT_POR", 4377 "FSI_R52_3_WDT_POR", 4378 "TOP_0_WDT_POR", 4379 "TOP_1_WDT_POR", 4380 "TOP_2_WDT_POR", 4381 "APE_C0_WDT_POR", 4382 "APE_C1_WDT_POR", 4383 "GPU_TKE_WDT_POR", /* 0x38 */ 4384 "PSC_WDT_POR", 4385 "OESP_WDT_POR", 4386 "SB_WDT_POR", 4387 "SW_MAIN", 4388 "L0L1_RST_OUT_N", 4389 "FSI_HSM", 4390 "CSITE_SW", 4391 "AO_WDT_DBG", /* 0x40 */ 4392 "BPMP_WDT_DBG", 4393 "AO_TKE_WDT_DBG", 4394 "RCE0_WDT_DBG", 4395 "RCE1_WDT_DBG", 4396 "DCE_WDT_DBG", 4397 "FSI_R5_WDT_DBG", 4398 "FSI_R52_0_WDT_DBG", 4399 "FSI_R52_1_WDT_DBG", /* 0x48 */ 4400 "FSI_R52_2_WDT_DBG", 4401 "FSI_R52_3_WDT_DBG", 4402 "TOP_0_WDT_DBG", 4403 "TOP_1_WDT_DBG", 4404 "TOP_2_WDT_DBG", 4405 "APE_C0_WDT_DBG", 4406 "APE_C1_WDT_DBG", 4407 "PSC_WDT_DBG", /* 0x50 */ 4408 "OESP_WDT_DBG", 4409 "SB_WDT_DBG", 4410 "TSC_0_WDT_DBG", 4411 "TSC_1_WDT_DBG", 4412 "L2_RST_OUT_N", 4413 "SC7" 4414}; 4415 4416static const struct tegra_wake_event tegra264_wake_events[] = { 4417}; 4418 4419static const struct tegra_pmc_soc tegra264_pmc_soc = { 4420 .has_impl_33v_pwr = true, 4421 .regs = &tegra264_pmc_regs, 4422 .init = tegra186_pmc_init, 4423 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 4424 .set_wake_filters = tegra186_pmc_set_wake_filters, 4425 .irq_set_wake = tegra186_pmc_irq_set_wake, 4426 .irq_set_type = tegra186_pmc_irq_set_type, 4427 .reset_sources = tegra264_reset_sources, 4428 .num_reset_sources = ARRAY_SIZE(tegra264_reset_sources), 4429 .reset_levels = tegra186_reset_levels, 4430 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 4431 .wake_events = tegra264_wake_events, 4432 .num_wake_events = ARRAY_SIZE(tegra264_wake_events), 4433 .max_wake_events = 128, 4434 .max_wake_vectors = 4, 4435}; 4436 4437static const struct of_device_id tegra_pmc_match[] = { 4438 { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, 4439 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 4440 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 4441 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 4442 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 4443 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 4444 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 4445 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 4446 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 4447 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 4448 { } 4449}; 4450 4451static void tegra_pmc_sync_state(struct device *dev) 4452{ 4453 struct device_node *np, *child; 4454 int err; 4455 4456 np = of_get_child_by_name(dev->of_node, "powergates"); 4457 if (!np) 4458 return; 4459 4460 for_each_child_of_node(np, child) 4461 of_genpd_sync_state(child); 4462 4463 of_node_put(np); 4464 4465 np = of_get_child_by_name(dev->of_node, "core-domain"); 4466 if (!np) 4467 return; 4468 4469 of_genpd_sync_state(np); 4470 of_node_put(np); 4471 4472 /* 4473 * Newer device-trees have power domains, but we need to prepare all 4474 * device drivers with runtime PM and OPP support first, otherwise 4475 * state syncing is unsafe. 4476 */ 4477 if (!pmc->soc->supports_core_domain) 4478 return; 4479 4480 /* 4481 * Older device-trees don't have core PD, and thus, there are 4482 * no dependencies that will block the state syncing. We shouldn't 4483 * mark the domain as synced in this case. 4484 */ 4485 pmc->core_domain_state_synced = true; 4486 4487 /* this is a no-op if core regulator isn't used */ 4488 mutex_lock(&pmc->powergates_lock); 4489 err = dev_pm_opp_sync_regulators(dev); 4490 mutex_unlock(&pmc->powergates_lock); 4491 4492 if (err) 4493 dev_err(dev, "failed to sync regulators: %d\n", err); 4494} 4495 4496static struct platform_driver tegra_pmc_driver = { 4497 .driver = { 4498 .name = "tegra-pmc", 4499 .suppress_bind_attrs = true, 4500 .of_match_table = tegra_pmc_match, 4501#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 4502 .pm = &tegra_pmc_pm_ops, 4503#endif 4504 .sync_state = tegra_pmc_sync_state, 4505 }, 4506 .probe = tegra_pmc_probe, 4507}; 4508builtin_platform_driver(tegra_pmc_driver); 4509 4510static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 4511{ 4512 u32 value, saved; 4513 4514 saved = readl(pmc->base + pmc->soc->regs->scratch0); 4515 value = saved ^ 0xffffffff; 4516 4517 if (value == 0xffffffff) 4518 value = 0xdeadbeef; 4519 4520 /* write pattern and read it back */ 4521 writel(value, pmc->base + pmc->soc->regs->scratch0); 4522 value = readl(pmc->base + pmc->soc->regs->scratch0); 4523 4524 /* if we read all-zeroes, access is restricted to TZ only */ 4525 if (value == 0) { 4526 pr_info("access to PMC is restricted to TZ\n"); 4527 return true; 4528 } 4529 4530 /* restore original value */ 4531 writel(saved, pmc->base + pmc->soc->regs->scratch0); 4532 4533 return false; 4534} 4535 4536/* 4537 * Early initialization to allow access to registers in the very early boot 4538 * process. 4539 */ 4540static int __init tegra_pmc_early_init(void) 4541{ 4542 const struct of_device_id *match; 4543 struct device_node *np; 4544 struct resource regs; 4545 unsigned int i; 4546 bool invert; 4547 4548 mutex_init(&pmc->powergates_lock); 4549 4550 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 4551 if (!np) { 4552 /* 4553 * Fall back to legacy initialization for 32-bit ARM only. All 4554 * 64-bit ARM device tree files for Tegra are required to have 4555 * a PMC node. 4556 * 4557 * This is for backwards-compatibility with old device trees 4558 * that didn't contain a PMC node. Note that in this case the 4559 * SoC data can't be matched and therefore powergating is 4560 * disabled. 4561 */ 4562 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 4563 pr_warn("DT node not found, powergating disabled\n"); 4564 4565 regs.start = 0x7000e400; 4566 regs.end = 0x7000e7ff; 4567 regs.flags = IORESOURCE_MEM; 4568 4569 pr_warn("Using memory region %pR\n", ®s); 4570 } else { 4571 /* 4572 * At this point we're not running on Tegra, so play 4573 * nice with multi-platform kernels. 4574 */ 4575 return 0; 4576 } 4577 } else { 4578 /* 4579 * Extract information from the device tree if we've found a 4580 * matching node. 4581 */ 4582 if (of_address_to_resource(np, 0, ®s) < 0) { 4583 pr_err("failed to get PMC registers\n"); 4584 of_node_put(np); 4585 return -ENXIO; 4586 } 4587 } 4588 4589 pmc->base = ioremap(regs.start, resource_size(®s)); 4590 if (!pmc->base) { 4591 pr_err("failed to map PMC registers\n"); 4592 of_node_put(np); 4593 return -ENXIO; 4594 } 4595 4596 if (of_device_is_available(np)) { 4597 pmc->soc = match->data; 4598 4599 if (pmc->soc->maybe_tz_only) 4600 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 4601 4602 /* Create a bitmap of the available and valid partitions */ 4603 for (i = 0; i < pmc->soc->num_powergates; i++) 4604 if (pmc->soc->powergates[i]) 4605 set_bit(i, pmc->powergates_available); 4606 4607 /* 4608 * Invert the interrupt polarity if a PMC device tree node 4609 * exists and contains the nvidia,invert-interrupt property. 4610 */ 4611 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4612 4613 pmc->soc->setup_irq_polarity(pmc, np, invert); 4614 4615 of_node_put(np); 4616 } 4617 4618 return 0; 4619} 4620early_initcall(tegra_pmc_early_init);
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