fuse-tegra.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2013-2023, NVIDIA CORPORATION.  All rights reserved.
  4 */
  5
  6#include <linux/acpi.h>
  7#include <linux/clk.h>
  8#include <linux/device.h>
  9#include <linux/kobject.h>
 10#include <linux/init.h>
 11#include <linux/io.h>
 12#include <linux/mod_devicetable.h>
 13#include <linux/nvmem-consumer.h>
 14#include <linux/nvmem-provider.h>
 15#include <linux/of.h>
 16#include <linux/of_address.h>
 17#include <linux/platform_device.h>
 18#include <linux/pm_runtime.h>
 19#include <linux/reset.h>
 20#include <linux/slab.h>
 21#include <linux/sys_soc.h>
 22
 23#include <soc/tegra/common.h>
 24#include <soc/tegra/fuse.h>
 25
 26#include "fuse.h"
 27
 28struct tegra_sku_info tegra_sku_info;
 29EXPORT_SYMBOL(tegra_sku_info);
 30
 31static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
 32	[TEGRA_REVISION_UNKNOWN] = "unknown",
 33	[TEGRA_REVISION_A01]     = "A01",
 34	[TEGRA_REVISION_A02]     = "A02",
 35	[TEGRA_REVISION_A03]     = "A03",
 36	[TEGRA_REVISION_A03p]    = "A03 prime",
 37	[TEGRA_REVISION_A04]     = "A04",
 38};
 39
 40static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
 41	[TEGRA_PLATFORM_SILICON]			= "Silicon",
 42	[TEGRA_PLATFORM_QT]				= "QT",
 43	[TEGRA_PLATFORM_SYSTEM_FPGA]			= "System FPGA",
 44	[TEGRA_PLATFORM_UNIT_FPGA]			= "Unit FPGA",
 45	[TEGRA_PLATFORM_ASIM_QT]			= "Asim QT",
 46	[TEGRA_PLATFORM_ASIM_LINSIM]			= "Asim Linsim",
 47	[TEGRA_PLATFORM_DSIM_ASIM_LINSIM]		= "Dsim Asim Linsim",
 48	[TEGRA_PLATFORM_VERIFICATION_SIMULATION]	= "Verification Simulation",
 49	[TEGRA_PLATFORM_VDK]				= "VDK",
 50	[TEGRA_PLATFORM_VSP]				= "VSP",
 51};
 52
 53static const struct of_device_id car_match[] __initconst = {
 54	{ .compatible = "nvidia,tegra20-car", },
 55	{ .compatible = "nvidia,tegra30-car", },
 56	{ .compatible = "nvidia,tegra114-car", },
 57	{ .compatible = "nvidia,tegra124-car", },
 58	{ .compatible = "nvidia,tegra132-car", },
 59	{ .compatible = "nvidia,tegra210-car", },
 60	{},
 61};
 62
 63static struct tegra_fuse *fuse = &(struct tegra_fuse) {
 64	.base = NULL,
 65	.soc = NULL,
 66};
 67
 68static const struct of_device_id tegra_fuse_match[] = {
 69#ifdef CONFIG_ARCH_TEGRA_234_SOC
 70	{ .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
 71#endif
 72#ifdef CONFIG_ARCH_TEGRA_194_SOC
 73	{ .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
 74#endif
 75#ifdef CONFIG_ARCH_TEGRA_186_SOC
 76	{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
 77#endif
 78#ifdef CONFIG_ARCH_TEGRA_210_SOC
 79	{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
 80#endif
 81#ifdef CONFIG_ARCH_TEGRA_132_SOC
 82	{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
 83#endif
 84#ifdef CONFIG_ARCH_TEGRA_124_SOC
 85	{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
 86#endif
 87#ifdef CONFIG_ARCH_TEGRA_114_SOC
 88	{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
 89#endif
 90#ifdef CONFIG_ARCH_TEGRA_3x_SOC
 91	{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
 92#endif
 93#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 94	{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
 95#endif
 96	{ /* sentinel */ }
 97};
 98
 99static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
100			   size_t bytes)
101{
102	unsigned int count = bytes / 4, i;
103	struct tegra_fuse *fuse = priv;
104	u32 *buffer = value;
105
106	for (i = 0; i < count; i++)
107		buffer[i] = fuse->read(fuse, offset + i * 4);
108
109	return 0;
110}
111
112static void tegra_fuse_restore(void *base)
113{
114	fuse->base = (void __iomem *)base;
115	fuse->clk = NULL;
116}
117
118static void tegra_fuse_print_sku_info(struct tegra_sku_info *tegra_sku_info)
119{
120	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
121		tegra_revision_name[tegra_sku_info->revision],
122		tegra_sku_info->sku_id, tegra_sku_info->cpu_process_id,
123		tegra_sku_info->soc_process_id);
124	pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
125		tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id);
126}
127
128static int tegra_fuse_add_lookups(struct tegra_fuse *fuse)
129{
130	fuse->lookups = kmemdup_array(fuse->soc->lookups, fuse->soc->num_lookups,
131				      sizeof(*fuse->lookups), GFP_KERNEL);
132	if (!fuse->lookups)
133		return -ENOMEM;
134
135	nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
136
137	return 0;
138}
139
140static int tegra_fuse_probe(struct platform_device *pdev)
141{
142	void __iomem *base = fuse->base;
143	struct nvmem_config nvmem;
144	struct resource *res;
145	int err;
146
147	err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base);
148	if (err)
149		return err;
150
151	/* take over the memory region from the early initialization */
152	fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
153	if (IS_ERR(fuse->base))
154		return PTR_ERR(fuse->base);
155	fuse->phys = res->start;
156
157	/* Initialize the soc data and lookups if using ACPI boot. */
158	if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) {
159		u8 chip;
160
161		tegra_acpi_init_apbmisc();
162
163		chip = tegra_get_chip_id();
164		switch (chip) {
165#if defined(CONFIG_ARCH_TEGRA_194_SOC)
166		case TEGRA194:
167			fuse->soc = &tegra194_fuse_soc;
168			break;
169#endif
170#if defined(CONFIG_ARCH_TEGRA_234_SOC)
171		case TEGRA234:
172			fuse->soc = &tegra234_fuse_soc;
173			break;
174#endif
175#if defined(CONFIG_ARCH_TEGRA_241_SOC)
176		case TEGRA241:
177			fuse->soc = &tegra241_fuse_soc;
178			break;
179#endif
180		default:
181			return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip);
182		}
183
184		fuse->soc->init(fuse);
185
186		err = tegra_fuse_add_lookups(fuse);
187		if (err)
188			return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n");
189	}
190
191	fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse");
192	if (IS_ERR(fuse->clk))
193		return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n");
194
195	platform_set_drvdata(pdev, fuse);
196	fuse->dev = &pdev->dev;
197
198	err = devm_pm_runtime_enable(&pdev->dev);
199	if (err)
200		return err;
201
202	if (fuse->soc->probe) {
203		err = fuse->soc->probe(fuse);
204		if (err < 0)
205			return err;
206	}
207
208	memset(&nvmem, 0, sizeof(nvmem));
209	nvmem.dev = &pdev->dev;
210	nvmem.name = "fuse";
211	nvmem.id = -1;
212	nvmem.owner = THIS_MODULE;
213	nvmem.cells = fuse->soc->cells;
214	nvmem.ncells = fuse->soc->num_cells;
215	nvmem.keepout = fuse->soc->keepouts;
216	nvmem.nkeepout = fuse->soc->num_keepouts;
217	nvmem.type = NVMEM_TYPE_OTP;
218	nvmem.read_only = true;
219	nvmem.root_only = false;
220	nvmem.reg_read = tegra_fuse_read;
221	nvmem.size = fuse->soc->info->size;
222	nvmem.word_size = 4;
223	nvmem.stride = 4;
224	nvmem.priv = fuse;
225
226	fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
227	if (IS_ERR(fuse->nvmem)) {
228		err = PTR_ERR(fuse->nvmem);
229		dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
230			err);
231		return err;
232	}
233
234	fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
235	if (IS_ERR(fuse->rst))
236		return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n");
237
238	/*
239	 * FUSE clock is enabled at a boot time, hence this resume/suspend
240	 * disables the clock besides the h/w resetting.
241	 */
242	err = pm_runtime_resume_and_get(&pdev->dev);
243	if (err)
244		return err;
245
246	err = reset_control_reset(fuse->rst);
247	pm_runtime_put(&pdev->dev);
248
249	if (err < 0) {
250		dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);
251		return err;
252	}
253
254	/* release the early I/O memory mapping */
255	iounmap(base);
256
257	return 0;
258}
259
260static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev)
261{
262	int err;
263
264	err = clk_prepare_enable(fuse->clk);
265	if (err < 0) {
266		dev_err(dev, "failed to enable FUSE clock: %d\n", err);
267		return err;
268	}
269
270	return 0;
271}
272
273static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev)
274{
275	clk_disable_unprepare(fuse->clk);
276
277	return 0;
278}
279
280static int __maybe_unused tegra_fuse_suspend(struct device *dev)
281{
282	int ret;
283
284	/*
285	 * Critical for RAM re-repair operation, which must occur on resume
286	 * from LP1 system suspend and as part of CCPLEX cluster switching.
287	 */
288	if (fuse->soc->clk_suspend_on)
289		ret = pm_runtime_resume_and_get(dev);
290	else
291		ret = pm_runtime_force_suspend(dev);
292
293	return ret;
294}
295
296static int __maybe_unused tegra_fuse_resume(struct device *dev)
297{
298	int ret = 0;
299
300	if (fuse->soc->clk_suspend_on)
301		pm_runtime_put(dev);
302	else
303		ret = pm_runtime_force_resume(dev);
304
305	return ret;
306}
307
308static const struct dev_pm_ops tegra_fuse_pm = {
309	SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume,
310			   NULL)
311	SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume)
312};
313
314static const struct acpi_device_id tegra_fuse_acpi_match[] = {
315	{ "NVDA200F" },
316	{ /* sentinel */ }
317};
318MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match);
319
320static struct platform_driver tegra_fuse_driver = {
321	.driver = {
322		.name = "tegra-fuse",
323		.of_match_table = tegra_fuse_match,
324		.acpi_match_table = tegra_fuse_acpi_match,
325		.pm = &tegra_fuse_pm,
326		.suppress_bind_attrs = true,
327	},
328	.probe = tegra_fuse_probe,
329};
330builtin_platform_driver(tegra_fuse_driver);
331
332u32 __init tegra_fuse_read_spare(unsigned int spare)
333{
334	unsigned int offset = fuse->soc->info->spare + spare * 4;
335
336	return fuse->read_early(fuse, offset) & 1;
337}
338
339u32 __init tegra_fuse_read_early(unsigned int offset)
340{
341	return fuse->read_early(fuse, offset);
342}
343
344int tegra_fuse_readl(unsigned long offset, u32 *value)
345{
346	if (!fuse->dev)
347		return -EPROBE_DEFER;
348
349	/*
350	 * Wait for fuse->clk to be initialized if device-tree boot is used.
351	 */
352	if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk)
353		return -EPROBE_DEFER;
354
355	if (!fuse->read)
356		return -EPROBE_DEFER;
357
358	if (IS_ERR(fuse->clk))
359		return PTR_ERR(fuse->clk);
360
361	*value = fuse->read(fuse, offset);
362
363	return 0;
364}
365EXPORT_SYMBOL(tegra_fuse_readl);
366
367static void tegra_enable_fuse_clk(void __iomem *base)
368{
369	u32 reg;
370
371	reg = readl_relaxed(base + 0x48);
372	reg |= 1 << 28;
373	writel(reg, base + 0x48);
374
375	/*
376	 * Enable FUSE clock. This needs to be hardcoded because the clock
377	 * subsystem is not active during early boot.
378	 */
379	reg = readl(base + 0x14);
380	reg |= 1 << 7;
381	writel(reg, base + 0x14);
382}
383
384static ssize_t major_show(struct device *dev, struct device_attribute *attr,
385			     char *buf)
386{
387	return sprintf(buf, "%d\n", tegra_get_major_rev());
388}
389
390static DEVICE_ATTR_RO(major);
391
392static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
393			     char *buf)
394{
395	return sprintf(buf, "%d\n", tegra_get_minor_rev());
396}
397
398static DEVICE_ATTR_RO(minor);
399
400static struct attribute *tegra_soc_attr[] = {
401	&dev_attr_major.attr,
402	&dev_attr_minor.attr,
403	NULL,
404};
405
406const struct attribute_group tegra_soc_attr_group = {
407	.attrs = tegra_soc_attr,
408};
409
410#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
411    IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
412    IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC)
413static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
414			     char *buf)
415{
416	/*
417	 * Displays the value in the 'pre_si_platform' field of the HIDREV
418	 * register for Tegra194 devices. A value of 0 indicates that the
419	 * platform type is silicon and all other non-zero values indicate
420	 * the type of simulation platform is being used.
421	 */
422	return sprintf(buf, "%d\n", tegra_get_platform());
423}
424
425static DEVICE_ATTR_RO(platform);
426
427static struct attribute *tegra194_soc_attr[] = {
428	&dev_attr_major.attr,
429	&dev_attr_minor.attr,
430	&dev_attr_platform.attr,
431	NULL,
432};
433
434const struct attribute_group tegra194_soc_attr_group = {
435	.attrs = tegra194_soc_attr,
436};
437#endif
438
439struct device *tegra_soc_device_register(void)
440{
441	struct soc_device_attribute *attr;
442	struct soc_device *dev;
443
444	attr = kzalloc(sizeof(*attr), GFP_KERNEL);
445	if (!attr)
446		return NULL;
447
448	attr->family = kasprintf(GFP_KERNEL, "Tegra");
449	if (tegra_is_silicon())
450		attr->revision = kasprintf(GFP_KERNEL, "%s %s",
451					   tegra_platform_name[tegra_sku_info.platform],
452					   tegra_revision_name[tegra_sku_info.revision]);
453	else
454		attr->revision = kasprintf(GFP_KERNEL, "%s",
455					   tegra_platform_name[tegra_sku_info.platform]);
456	attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
457	attr->custom_attr_group = fuse->soc->soc_attr_group;
458
459	dev = soc_device_register(attr);
460	if (IS_ERR(dev)) {
461		kfree(attr->soc_id);
462		kfree(attr->revision);
463		kfree(attr->family);
464		kfree(attr);
465		return ERR_CAST(dev);
466	}
467
468	return soc_device_to_device(dev);
469}
470
471static int __init tegra_init_fuse(void)
472{
473	const struct of_device_id *match;
474	struct device_node *np;
475	struct resource regs;
476	int err;
477
478	tegra_init_apbmisc();
479
480	np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
481	if (!np) {
482		/*
483		 * Fall back to legacy initialization for 32-bit ARM only. All
484		 * 64-bit ARM device tree files for Tegra are required to have
485		 * a FUSE node.
486		 *
487		 * This is for backwards-compatibility with old device trees
488		 * that didn't contain a FUSE node.
489		 */
490		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
491			u8 chip = tegra_get_chip_id();
492
493			regs.start = 0x7000f800;
494			regs.end = 0x7000fbff;
495			regs.flags = IORESOURCE_MEM;
496
497			switch (chip) {
498#ifdef CONFIG_ARCH_TEGRA_2x_SOC
499			case TEGRA20:
500				fuse->soc = &tegra20_fuse_soc;
501				break;
502#endif
503
504#ifdef CONFIG_ARCH_TEGRA_3x_SOC
505			case TEGRA30:
506				fuse->soc = &tegra30_fuse_soc;
507				break;
508#endif
509
510#ifdef CONFIG_ARCH_TEGRA_114_SOC
511			case TEGRA114:
512				fuse->soc = &tegra114_fuse_soc;
513				break;
514#endif
515
516#ifdef CONFIG_ARCH_TEGRA_124_SOC
517			case TEGRA124:
518				fuse->soc = &tegra124_fuse_soc;
519				break;
520#endif
521
522			default:
523				pr_warn("Unsupported SoC: %02x\n", chip);
524				break;
525			}
526		} else {
527			/*
528			 * At this point we're not running on Tegra, so play
529			 * nice with multi-platform kernels.
530			 */
531			return 0;
532		}
533	} else {
534		/*
535		 * Extract information from the device tree if we've found a
536		 * matching node.
537		 */
538		if (of_address_to_resource(np, 0, &regs) < 0) {
539			pr_err("failed to get FUSE register\n");
540			return -ENXIO;
541		}
542
543		fuse->soc = match->data;
544	}
545
546	np = of_find_matching_node(NULL, car_match);
547	if (np) {
548		void __iomem *base = of_iomap(np, 0);
549		of_node_put(np);
550		if (base) {
551			tegra_enable_fuse_clk(base);
552			iounmap(base);
553		} else {
554			pr_err("failed to map clock registers\n");
555			return -ENXIO;
556		}
557	}
558
559	fuse->base = ioremap(regs.start, resource_size(&regs));
560	if (!fuse->base) {
561		pr_err("failed to map FUSE registers\n");
562		return -ENXIO;
563	}
564
565	fuse->soc->init(fuse);
566
567	tegra_fuse_print_sku_info(&tegra_sku_info);
568
569	err = tegra_fuse_add_lookups(fuse);
570	if (err)
571		pr_err("failed to add FUSE lookups\n");
572
573	return err;
574}
575early_initcall(tegra_init_fuse);
576
577#ifdef CONFIG_ARM64
578static int __init tegra_init_soc(void)
579{
580	struct device_node *np;
581	struct device *soc;
582
583	/* make sure we're running on Tegra */
584	np = of_find_matching_node(NULL, tegra_fuse_match);
585	if (!np)
586		return 0;
587
588	of_node_put(np);
589
590	soc = tegra_soc_device_register();
591	if (IS_ERR(soc)) {
592		pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
593		return PTR_ERR(soc);
594	}
595
596	return 0;
597}
598device_initcall(tegra_init_soc);
599#endif