rcar-rst.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
  4 *
  5 * Copyright (C) 2016 Glider bvba
  6 */
  7
  8#include <linux/err.h>
  9#include <linux/io.h>
 10#include <linux/of_address.h>
 11#include <linux/soc/renesas/rcar-rst.h>
 12
 13#define WDTRSTCR_RESET		0xA55A0002
 14#define WDTRSTCR		0x0054
 15#define GEN4_WDTRSTCR_RESET	0xA55A8002
 16#define GEN4_WDTRSTCR		0x0010
 17
 18#define CR7BAR			0x0070
 19#define CR7BAREN		BIT(4)
 20#define CR7BAR_MASK		0xFFFC0000
 21
 22static void __iomem *rcar_rst_base;
 23static u32 saved_mode __initdata;
 24static int (*rcar_rst_set_rproc_boot_addr_func)(u64 boot_addr);
 25
 26static int rcar_rst_enable_wdt_reset(void __iomem *base)
 27{
 28	iowrite32(WDTRSTCR_RESET, base + WDTRSTCR);
 29	return 0;
 30}
 31
 32static int rcar_rst_v3u_enable_wdt_reset(void __iomem *base)
 33{
 34	iowrite32(GEN4_WDTRSTCR_RESET, base + GEN4_WDTRSTCR);
 35	return 0;
 36}
 37
 38/*
 39 * Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
 40 * Firmware boot address has to be set in CR7BAR before
 41 * starting the realtime core.
 42 * Boot address must be aligned on a 256k boundary.
 43 */
 44static int rcar_rst_set_gen3_rproc_boot_addr(u64 boot_addr)
 45{
 46	if (boot_addr & ~(u64)CR7BAR_MASK) {
 47		pr_err("Invalid boot address got %llx\n", boot_addr);
 48		return -EINVAL;
 49	}
 50
 51	iowrite32(boot_addr, rcar_rst_base + CR7BAR);
 52	iowrite32(boot_addr | CR7BAREN, rcar_rst_base + CR7BAR);
 53
 54	return 0;
 55}
 56
 57struct rst_config {
 58	unsigned int modemr;		/* Mode Monitoring Register Offset */
 59	int (*configure)(void __iomem *base);	/* Platform specific config */
 60	int (*set_rproc_boot_addr)(u64 boot_addr);
 61};
 62
 63static const struct rst_config rcar_rst_gen1 __initconst = {
 64	.modemr = 0x20,
 65};
 66
 67static const struct rst_config rcar_rst_gen2 __initconst = {
 68	.modemr = 0x60,
 69	.configure = rcar_rst_enable_wdt_reset,
 70};
 71
 72static const struct rst_config rcar_rst_gen3 __initconst = {
 73	.modemr = 0x60,
 74	.set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr,
 75};
 76
 77/* V3U firmware doesn't enable WDT reset and there won't be updates anymore */
 78static const struct rst_config rcar_rst_v3u __initconst = {
 79	.modemr = 0x00,		/* MODEMR0 and it has CPG related bits */
 80	.configure = rcar_rst_v3u_enable_wdt_reset,
 81};
 82
 83static const struct rst_config rcar_rst_gen4 __initconst = {
 84	.modemr = 0x00,		/* MODEMR0 and it has CPG related bits */
 85};
 86
 87static const struct of_device_id rcar_rst_matches[] __initconst = {
 88	/* RZ/G1 is handled like R-Car Gen2 */
 89	{ .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
 90	{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
 91	{ .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
 92	{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
 93	{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
 94	/* RZ/G2 is handled like R-Car Gen3 */
 95	{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
 96	{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
 97	{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
 98	{ .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
 99	/* R-Car Gen1 */
100	{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
101	{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
102	/* R-Car Gen2 */
103	{ .compatible = "renesas,r8a7790-rst", .data = &rcar_rst_gen2 },
104	{ .compatible = "renesas,r8a7791-rst", .data = &rcar_rst_gen2 },
105	{ .compatible = "renesas,r8a7792-rst", .data = &rcar_rst_gen2 },
106	{ .compatible = "renesas,r8a7793-rst", .data = &rcar_rst_gen2 },
107	{ .compatible = "renesas,r8a7794-rst", .data = &rcar_rst_gen2 },
108	/* R-Car Gen3 */
109	{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
110	{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
111	{ .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
112	{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
113	{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
114	{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
115	{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
116	{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
117	/* R-Car Gen4 */
118	{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_v3u },
119	{ .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
120	{ .compatible = "renesas,r8a779g0-rst", .data = &rcar_rst_gen4 },
121	{ .compatible = "renesas,r8a779h0-rst", .data = &rcar_rst_gen4 },
122	{ /* sentinel */ }
123};
124
125static int __init rcar_rst_init(void)
126{
127	const struct of_device_id *match;
128	const struct rst_config *cfg;
129	struct device_node *np;
130	void __iomem *base;
131	int error = 0;
132
133	np = of_find_matching_node_and_match(NULL, rcar_rst_matches, &match);
134	if (!np)
135		return -ENODEV;
136
137	base = of_iomap(np, 0);
138	if (!base) {
139		pr_warn("%pOF: Cannot map regs\n", np);
140		error = -ENOMEM;
141		goto out_put;
142	}
143
144	rcar_rst_base = base;
145	cfg = match->data;
146	rcar_rst_set_rproc_boot_addr_func = cfg->set_rproc_boot_addr;
147
148	saved_mode = ioread32(base + cfg->modemr);
149	if (cfg->configure) {
150		error = cfg->configure(base);
151		if (error) {
152			pr_warn("%pOF: Cannot run SoC specific configuration\n",
153				np);
154			goto out_put;
155		}
156	}
157
158	pr_debug("%pOF: MODE = 0x%08x\n", np, saved_mode);
159
160out_put:
161	of_node_put(np);
162	return error;
163}
164
165int __init rcar_rst_read_mode_pins(u32 *mode)
166{
167	int error;
168
169	if (!rcar_rst_base) {
170		error = rcar_rst_init();
171		if (error)
172			return error;
173	}
174
175	*mode = saved_mode;
176	return 0;
177}
178
179int rcar_rst_set_rproc_boot_addr(u64 boot_addr)
180{
181	if (!rcar_rst_set_rproc_boot_addr_func)
182		return -EIO;
183
184	return rcar_rst_set_rproc_boot_addr_func(boot_addr);
185}
186EXPORT_SYMBOL_GPL(rcar_rst_set_rproc_boot_addr);